ALSC AS4C64M16D1 Programmable burst Datasheet

AS4C64M16D1
Revision History AS4C64M16D1 – 66-pin TSOP II package
Revision
Rev 1.0
Rev 2
Confidential
Details
Preliminary datasheet
Speed grade option changed -5(400MHz) to -6(333MHz)
1
Date
Sep 2014
Oct 2014
Rev. 2.0
Oct. /2014
AS4C64M16D1
64M x 16 bit DDR1 Synchronous DRAM (SDRAM)
Confidential
Advanced (Rev. 2.0, Oct. /2014)
Features
High speed data transfer rates with system
frequency up to 200MHz
- Data Mask for Write Control
- Four Banks controlled by BA0 & BA1
- Programmable CAS Latency: 2, 2.5, 3
- Programmable
Wrap
Sequence:
Sequential or Interleave
- Programmable Burst
Length: 2, 4, 8 for
Sequential Type 2, 4, 8
for Interleave Type
- Automatic and Controlled Precharge Command
- Power Down Mode
- Auto Refresh and Self Refresh
- Refresh Interval: 8192 cycles/64 ms
- Available in 66 Pin TSOP II
- SSTL-2 Compatible I/Os
- Double Data Rate (DDR)
- Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
- On-Chip DLL aligns DQ and DQs transitions with
CK transitions
CK
- VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V
VDD = 2.6V ± 0.1V, VDDQ = 2.6V ± 0.1V
(DDR400)
- tRAS lockout supported
- Concurrent auto precharge option is supported
Description
The AS4C64M16D1 is a four bank DDR DRAM
organized as 4 banks x 16Mbit x 16. The
AS4C64M16D1 achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock.
All of the controls, address, circuits are
synchronized with the positive edge of an externally
supplied clock. I/O transactions are occurring on
both edges of DQS.
Operating the four memory banks in an
interleaved fashion allows random access operation
to occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
-6
DDR333
Clock Cycle Time (tCK2)
7.5ns
Clock Cycle Time (tCK2.5)
6ns
Clock Cycle Time (tCK3)
6ns
System Frequency (fCK max)
166 MHz
All parts are ROHS compliant
Table 1. Speed Grade Information
Speed Grade
DDR1-333
Clock Frequency
CAS Latency
tRCD (ns)
tRP (ns)
166 MHz
3
18
18
Table 2. Ordering Information
Product part No
Org
Temperature
Package
AS4C64M16D1-6TCN
64M x 16
66-pin TSOP II
AS4C64M16D1-6TIN
64M x 16
Commercial
0°C to 70°C
Industrial
-40°C to 85°C
Confidential
2
66-pin TSOP II
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
3
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
4
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
5
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
6
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
7
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
8
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
9
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
10
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
11
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
12
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
13
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
14
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
15
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
16
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
17
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
18
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
19
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
20
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
21
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
22
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
23
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
24
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
25
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
26
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
27
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
28
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
29
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
30
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
31
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
32
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
33
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
34
Rev. 2.0
Oct. /2014
AS4C64M16D1
IDD Max Specifications and Conditions
( VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V )
Version
Conditions
Symbol
-6
Unit
Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=tCKmin;
DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per
clock cycle
IDD0
85
mA
Operating current - One bank operation; One bank open, BL=2
IDD1
105
mA
Precharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=tCKmin; Vin = Vref for DQ,DQS and DM
IDD2P
6
mA
Precharge Floating standby current; CS# > =VIH(min); All banks idle;
CKE > = VIH(min); tCK=tCKmin; Address and other control inputs changing once per clock cycle; Vin =
Vref for DQ, DQS and DM
IDD2F
30
mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=tCKmin; Address and other control inputs stable with keeping
>= VIH(min) or =<VIL(max); Vin = Vref for DQ, DQS and DM
IDD2Q
25
mA
Active power - down standby current; one bank active; power-down mode;
CKE=< VIL (max); tCK=tCKmin; Vin = Vref for DQ, DQS and DM
IDD3P
15
mA
IDD3N
35
mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address
and control inputs changing once per clock cycle; tCK=tCKmin; 50% of data changing at every burst;
lout = 0 m A
IDD4R
115
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address
and control inputs changing once per clock cycle; tCK=tCKmin; DQ, DM and DQS
inputs changing twice per clock cycle, 50% of input data changing at every burst
IDD4W
145
mA
IDD5
185
mA
IDD5A
9
mA
Self-refresh current; CKE =< 0.2V; External clock should be on; tCK=tCKmin.
IDD6
3
mA
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
230
mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge;
tRC=tRASmax; tCK=tCKmin; DQ, DQS and DM inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
Auto refresh current; tRC = tRFCmin; tCK=tCKmin; burst refresh; address and
control inputs changing once per clock cycle; data bus inputs are stable
tREFC=tRFC (MIN)
tREFC=7.8ms
Confidential
35
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
36
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
37
Rev. 2.0
Oct. /2014
AS4C64M16D1
ELECTRICAL CHARACTERISTICS AND AC TIMING -Absolute Specifications
( VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V, for DDR400 VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V )
AC CHARACTERISTICS
-6
PARAMETER
SYMBOL
t
Access window of DQs from CK/CK
CH
t
CL
CK high-level width
CK low-level width
Clock cycle time
CL = 3
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
t
CK (3)
t
CK (2.5)
t
CK (2)
t
DH
t
DS
AUTO Precharge write recovery
+ precharge time
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid,
per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK
Data-out low-impedance window from CK/CK
Confidential
AC
t
t
MIN
MAX UNITS NOTES
-0.7
0.7
0.45
HP
t
HZ
t
LZ
30
ns
52
6
12
ns
52
7.5
12
ns
52
0.45
ns
26,31
0.45
ns
26,31
CK
54
ns
31
-0.6
t
0.6
ns
t
0.35
t
0.35
DQSQ
t
CK
12
1.75
DQSS
t
DSS
t
DSH
30
6
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
CK
0.55
-
t
t
0.45
DAL
t
0.55
ns
t
0.40
0.75
1.25
t
0.2
t
CH,
t
CL
CK
ns
t
t
0.2
CK
25,26
CK
CK
CK
ns
34
-0.7
+0.7
ns
18
-0.7
+0.7
ns
18
38
Rev. 2.0
Oct. /2014
AS4C64M16D1
AC CHARACTERISTICS
PARAMETER
-6
SYMBOL MIN
t
IH
Address and control input hold time
(fast slew rate)
t
LOAD MODE REGISTER command cycle time
t
ISS
t
IPW
t
MRD
ACTIVE to READ with Auto precharge
command
t
QH
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Confidential
0.75
ns
14
0.80
ns
14
0.80
ns
14
ns
53
2.2
t
2
HP
t
- QHS
t
QHS
t
RAS
CK
25, 26
ns
70,000
ns
35
18
ns
46
RC
60
ns
RFC
120
ns
RCD
t
RP
18
ns
t
RAP
t
t
t
ns
0.55
ACTIVE to ACTIVE/AUTO REFRESH
command period
AUTO REFRESH command period
14
t
per access
ACTIVE to PRECHARGE command
ns
S
DQ-DQS hold, DQS to first DQ to go non-valid,
Data hold skew factor
ISF
t
IH
Address and control input hold time
(slow slew rate)
Control & Address input width (for each input)
0.75
F
Address and control input setup time
(fast slew rate)
Address and control input setup time
(slow slew rate)
MAX UNITS NOTES
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
na
t
REFI
t
VTD
t
XSNR
t
XSRD
42
18
0.9
0.4
ns
1.1
0.6
t
t
12
0
0.6
t
15
t
CK
ns
20, 21
CK
19
CK
ns
7.8
25
us
0
ns
75
39
42
CK
ns
1
t
t
QH - DQSQ
200
CK
ns
t
0.25
0.4
50
ns
t
CK
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
40
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
41
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
42
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
43
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
44
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
45
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
46
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
47
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
48
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
49
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
50
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
51
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
52
Rev. 2.0
Oct. /2014
AS4C64M16D1
* = Device must be in the "All banks idle" state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK)
are required before a READ command can be applied.
Confidential
53
Rev. 2.0
Oct. /2014
AS4C64M16D1
Figure 42 - READ - WITHOUT AUTO PRECHARGE
tCH
tCK
tCL
/CK
CK
tIS
tIH
tIS
tIH
tIH
CKE
COMMAND
NOP
Start!Autoprecharge
READ
tIS
x4:A0-A9,A11,A12
x8:A0-A9, A11
x16:A0-A9
x8:A12
x16:A11, A12
NOP
PRE
NOP
NOP
ACT
VALID
VALID
NOP
NOP
NOP
tIH
Col n
RA
RA
tIS
tIH
ALL BANKS
A10
RA
DIS AP
tIS
BA0, BA1
VALID
ONE BANK
tIH
Bank x
*Bank x
Bank x
tRP
CL = 2
DM
Case 1:
tAC/tDQSCK = min
t DQSCK
min
tRPST
tRPRE
DQS
DQ
tLZ
min
tHZ
min
DO
n
tLZ
min
tAC
min
Case 2:
tAC/tDQSCK = max
t DQSCK
max
tRPRE
tRPST
DQS
DQ
tLZ
max
tHZ
max
DO
n
tLZ
max
t AC
max
DON'T CARE
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Confidential
54
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
55
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
56
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
57
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
58
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
59
Rev. 2.0
Oct. /2014
AS4C64M16D1
Confidential
60
Rev. 2.0
Oct. /2014
AS4C64M16D1
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
Confidential
61
Rev. 2.0
Oct. /2014