Fairchild ML4841 Variable feedforward pfc/pwm controller combo Datasheet

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ML4841
Variable Feedforward PFC/PWM Controller Combo
Features
General Description
• Internally synchronized PFC and PWM in one IC
• Low total harmonic distortion
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Average current, continuous mode, boost type, leading
edge PFC
• High efficiency trailing edge PWM can be configured for
current mode or voltage mode operation
• Average line voltage compensation with brown-out
control
• PFC overvoltage comparator eliminates output
“runaway” due to load removal
• Current fed multiplier for improved noise immunity
• Overvoltage protection, UVLO, and soft start
The ML4841 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-2-3 specifications. The ML4841 includes circuits
for the implementation of a leading edge, average current,
“boost” type power factor correction, and a trailing edge,
pulse width modulator (PWM).
The PFC frequency of the ML4841 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the optimum
operating frequency for the PFC. An over-voltage comparator shuts down the PFC section in the event of a sudden
decrease in load. The PFC section also includes peak current
limiting and input voltage brown-out protection.
Block Diagram
16
VFB
15
VEA
-
13
1
IEAO
VEAO
POWER FACTOR CORRECTOR
OVP
+
IEA
3.5kΩ
-
2.5V
VCC
VCCZ
+
+
2.7V
-
-1V
+
13.5V
+
IAC
-
2
8V
GAIN
MODULATOR
VRMS
4
-
S
Q
R
Q
S
Q
R
Q
S
Q
R
Q
VREF
14
PFC OUT
3.5kΩ
ISENSE
7.5V
REFERENCE
PFC ILIMIT
12
3
RAMP 1
8
RTCT
÷2
OSCILLATOR
7
RAMP 2
DUTY CYCLE
LIMIT
9
8V
VDC
6
1.25V
+
VCC
SS
-
PWM OUT
-
50µA
5
+
VFB
-
2.5V
+
VIN OK
+
1V
8V
PULSE WIDTH MODULATOR
-
11
DC ILIMIT
VCCZ
UVLO
REV. 1.0.3 6/13/01
ML4841
PRODUCT SPECIFICATION
Pin Configuration
ML4841
16-Pin PDIP (P16)
IEAO 1
IAC 2
ISENSE 3
VRMS 4
SS 5
VDC 6
RT/CT 7
RAMP 1 8
16 VEAO
15 VFB
14 VREF
13 VCC
12 PFC OUT
11 PWM OUT
10 GND
9
RAMP 2
TOP VIEW
Pin Description
2
PIN
NAME
1
IEAO
FUNCTION
PFC transconductance current error amplifier output
PFC gain control reference input
2
IAC
3
ISENSE
4
VRMS
5
SS
6
VDC
PWM voltage feedback input
7
RTCT
Connection for oscillator frequency setting components
8
RAMP 1
PFC ramp input
9
RAMP 2
PWM ramp current sense input
10
GND
11
PWM OUT
PWM driver output
12
PFC OUT
PFC driver output
13
VCC
Positive supply (connected to an internal shunt regulator).
14
VREF
Buffered output for the internal 7.5V reference
15
VFB
16
VEAO
Current sense input to the PFC current limit comparator
Input for PFC RMS line voltage compensation
Connection point for the PWM soft start capacitor
Ground
PFC transconductance voltage error amplifier input
PFC transconductance voltage error amplifier output
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
Min.
Max.
Units
55
mA
-3
5
V
GND - 0.3
VCCZ + 0.3
V
IREF
20
mA
IAC Input Current
10
mA
Peak PFC OUT Current, Source or Sink
500
mA
Peak PWM OUT Current, Source or Sink
500
mA
PFC OUT, PWM OUT Energy Per Cycle
1.5
mJ
150
°C
150
°C
Lead Temperature (Soldering, 10 sec)
260
°C
Thermal Resistance (θJA)
Plastic DIP
80
°C/W
VCC Shunt Regulator Current
ISENSE Voltage
Voltage on Any Other Pin
Junction Temperature
Storage Temperature Range
–65
Operating Conditions
Temperature Range
Parameter
Min.
Max.
Units
ML4841CP
0
70
°C
Electrical Characteristics
Unless otherwise specified, ICC = 25mA, RT = 23kΩ, RRAMP1 = 28.7kΩ, CT = 400pF, CRAMP1 = 270pF, TA =
Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
40
70
100
µ
2.4
2.5
2.6
V
-0.5
-1.0
µA
Voltage Error Amplifier
Transconductance
0
VNON INV = VINV, VEAO = 3.75V
Feedback Reference Voltage
Input Bias Current
Note 2
Output High Voltage
6.0
Output Low Voltage
7
6.7
0.65
V
Ω
Input Voltage Range
V
1.0
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-90
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
90
µA
60
75
dB
60
75
dB
Open Loop Gain
PSRR
VCCZ - 3V < VCC < VCCZ - 0.5V
Current Error Amplifier
Transconductance
Input Offset Voltage
REV. 1.0.3 6/13/01
-1.5
VNON INV = VINV, VEAO = 3.75V
130
2
V
Ω
Input Voltage Range
195
310
µ
±3
±15
mV
3
ML4841
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
Unless otherwise specified, ICC = 25mA, RT = 23kΩ, RRAMP1 = 28.7kΩ, CT = 400pF, CRAMP1 = 270pF, TA =
Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Input Bias Current
Output High Voltage
6.0
Output Low Voltage
Typ.
Max.
Units
-0.5
-1.0
µA
6.7
0.65
V
1.0
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-90
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
90
µA
60
75
dB
60
75
dB
Threshold Voltage
2.6
2.7
2.8
V
Hysteresis
70
95
125
mV
Threshold Voltage
-0.8
-1.0
-1.15
V
∆(PFC ILIMIT VTH - Gain
Modulator Output)
100
190
Open Loop Gain
PSRR
VCCZ - 3V < VCC < VCCZ - 0.5V
OVP Comparator
PFC ILIMIT Comparator
Delay to Output
mV
150
300
ns
1.0
1.1
V
Input Bias Current
±0.3
±1
µA
Delay to Output
150
300
ns
DC ILIMIT Comparator
Threshold Voltage
0.9
VIN OK Comparator
Threshold Voltage
2.4
2.5
2.6
V
Hysteresis
0.8
1.0
1.2
V
Gain Modulator
Gain (Note 3)
IAC = 100µA, VRMS = VFB = 0V
0.35
0.50
0.65
IAC = 50µA, VRMS = 1.2V, VFB = 0V
1.15
1.65
2.15
IAC = 50µA, VRMS = 1.8V, VFB = 0V
0.52
0.74
0.96
IAC = 100µA, VRMS = 3.3V, VFB = 0V
0.14
0.20
0.26
Bandwidth
IAC = 100µA
10
MHz
Output Voltage
IAC = 250µA, VRMS = 1.15V,
VFB = 0V
0.74
0.82
0.90
V
Initial Accuracy
TA = 25°C
188
200
212
kHz
Voltage Stability
VCCZ - 3V < VCC < VCCZ - 0.5V
Oscillator
1
Temperature Stability
Total Variation
2
Line, Temp
182
Ramp Valley to Peak Voltage
4
%
%
218
kHz
2.5
V
ns
Dead Time
PFC Only
260
400
CT Discharge Current
VRAMP 2 = 0V, VRAMP 1 = 2.5V
4.5
7.5
9.5
mA
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Electrical Characteristics (continued)
Unless otherwise specified, ICC = 25mA, RT = 23kΩ, RRAMP1 = 28.7kΩ, CT = 400pF, CRAMP1 = 270pF, TA =
Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
7.4
7.5
7.6
V
2
10
mV
2
15
mV
Reference
Output Voltage
TA = 25°C, I(VREF) = 1mA
Line Regulation
VCCZ - 3V < VCC < VCCZ - 0.5V
Load Regulation
1mA < I(VREF) < 20mA
Temperature Stability
0.4
Total Variation
Line, Load, Temp
Long Term Stability
TJ = 125°C, 1000 Hours
7.25
5
%
7.65
V
25
mV
0
%
PFC
Minimum Duty Cycle
VIEAO > 6.7V
Maximum Duty Cycle
VIEAO < 1.2V
Output Low Voltage
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = 10mA, VCC = 8V
0.8
1.5
V
Output High Voltage
Rise/Fall Time
90
95
%
IOUT = 20mA
10
10.5
V
IOUT = 100mA
9.5
10
V
50
ns
CL = 1000pF
PWM
DC
Duty Cycle Range
VOL
Output Low Voltage
VOH
Output High Voltage
Rise/Fall Time
0-44
0-47
0-50
%
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = 10mA, VCC = 8V
0.8
1.5
V
IOUT = 20mA
10
10.5
V
IOUT = 100mA
9.5
10
V
50
ns
CL = 1000pF
Supply
VCCZ
Shunt Regulator Voltage
12.8
13.5
14.2
V
±100
±200
mV
14.6
V
VCCZ Load Regulation
25mA < ICC < 55mA
VCCZ Total Variation
Load, Temp
Start-up Current
VCC = 11.2V, CL = 0
0.7
1.0
mA
Operating Current
VCC < VCCZ - 0.5V, CL = 0
17
21
mA
Undervoltage Lockout
Threshold
Undervoltage Lockout
Hysteresis
12.4
VCCZ - VCCZ - VCCZ 1.0
0.7
0.4
2.7
3.0
3.3
V
V
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Includes all bias currents to other circuits connected to the VFB pin.
3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
REV. 1.0.3 6/13/01
5
ML4841
PRODUCT SPECIFICATION
250
200
200
Ω
Transconductance (µ )
250
Ω
Transconductance (µ )
Typical Performance Characteristics
150
100
50
150
100
50
0
1
0
2
4
3
0
-500
5
0
VFB (V)
500
IEA Input Voltage (mV)
Voltage Error Amplifier (VEA) Transconductance (gm)
Current Error Amplifier (IEA) Transconductance (gm)
Variable Gain Block Constant - K
400
300
200
100
0
0
1
2
3
4
5
VRMS (mV)
Variable Gain Control Transfer Characteristic
16
VFB
15
VEA
-
13
1
VCC
IEAO
VEAO
OVP
+
IEA
3.5kΩ
-
2.5V
+
+
ISENSE
-
-1V
+
-
2
4
2.7V
13.5V
+
IAC
VRMS
VCCZ
8V
GAIN
MODULATOR
-
7.5V
REFERENCE
S
Q
R
Q
S
Q
R
Q
VREF
14
PFC OUT
3.5kΩ
PFC ILIMIT
12
3
RAMP 1
8
RTCT
7
OSCILLATOR
÷2
VCCZ
UVLO
Figure 1. PFC Section Block Diagram.
6
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
Functional Description
The ML4841 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM section uses current mode control. The PWM
stage uses conventional trailing-edge duty cycle modulation,
while the PFC uses leading-edge modulation. This patented
leading/trailing edge modulation technique results in a
higher useable PFC error amplifier bandwidth, and can
significantly reduce the size of the PFC DC buss capacitor.
The synchronization of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the ML4841 runs at twice the frequency of the
PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the
PFC stage power components.
In addition to power factor correction, a number of protection features have been built into the ML4841. These include
soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and undervoltage lockout.
Power Factor Correction
Power factor correction makes a non-linear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with and proportional to the line
voltage, so the power factor is unity (one). A common class
of non-linear load is the input of a most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect which occurs on the
input filter capacitor in such a supply causes brief highamplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less
than one (another way to state this is that it causes significant
current harmonics to appear at its input). If the input current
drawn by such a supply (or any other non-linear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the ML4841 uses a boost-mode
DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No
filtering is applied following the bridge rectifier, so the input
voltage to the boost converter ranges, at twice line frequency,
from zero volts to the peak value of the AC input and back to
zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current
which the converter draws from the power line agrees with
the instantaneous line voltage. One of these conditions is that
REV. 1.0.3 6/13/01
ML4841
the output voltage of the boost converter must be set higher
than the peak value of the line voltage. A commonly used
value is 385VDC, to allow for a high line of 270VAC.
The other condition is that the current which the converter is
allowed to draw from the line at any given instant must be
proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control
loop for the converter, which in turn drives a current error
amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation
causes the current error amplifier to command a power stage
current which varies directly with the input voltage. In order
to prevent ripple which will necessarily appear at the output
of the boost circuit (typically about 10VAC on a 385V DC
level) from introducing distortion back through the voltage
error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain
of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies.
Since the boost converter topology in the ML4841 PFC is of
the current-averaging type, no slope compensation is
required.
PFC Section
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4841. The gain modulator is the heart of the PFC, as it is
this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the
gain modulator. These are:
1.
A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain
modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.
2.
A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at VRMS. The gain modulator’s output is
inversely proportional to VRMS2 (except at unusually low
values of VRMS where special gain contouring takes over
to limit power dissipation of the circuit components
under heavy brownout conditions). The relationship
between VRMS and gain is designated as K, and is
illustrated in the Typical Performance Characteristics.
3.
The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
7
ML4841
PRODUCT SPECIFICATION
The output of the gain modulator is a current signal, in
the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC from the power line. The general form for the
output of the gain modulator is:
I AC × VEAO
× 1V
I GAINMOD ≅ -------------------------------2
V RMS
VREF
PFC
OUTPUT
16
VFB
15
VEA
-
2.5V
More exactly, the output current of the gain modulator is
given by:
(1)
where K is in units of V-1.
Note that the output current of the gain modulator is limited
to ≅ 200µA.
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a linear
function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain modulator is summed with a current which results from a negative
voltage being impressed upon the ISENSE pin (current into
ISENSE ≅ VSENSE/3.5kΩ). The negative voltage on ISENSE
represents the sum of all currents flowing in the PFC circuit,
and is typically derived from a current sense resistor in series
with the negative terminal of the input bridge rectifier. In
higher power applications, two current transformers are
sometimes used, one to monitor the ID of the boost
MOSFET(s) and one to monitor the IF of the boost diode.
As stated above, the inverting input of the current error
amplifier is a virtual ground. Given this fact, and the
arrangement of the duty cycle modulator polarities internal
to the PFC, an increase in positive current from the gain
modulator will cause the output stage to increase its duty
cycle until the voltage on ISENSE is adequately negative to
cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to
achieve a less negative voltage on the ISENSE pin.
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop perturbations.
However, the boost inductor will usually be the dominant
factor in overall current loop response. Therefore, this
contouring is significantly less marked than that of the
voltage error amplifier. This is illustrated in the Typical
Performance Characteristics.
8
IEA
+
+
+
IAC
I GAINMOD ≅ K × ( VEAO – 1.5V ) × I AC
1
IEAO
VEAO
-
2
VRMS
4
GAIN
MODULATOR
ISENSE
3
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
Cycle-By-Cycle Current Limiter
The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this
pin ever be more negative than -1V, the output of the PFC
will be disabled until the protection flip-flop is reset by the
clock pulse at the start of the next PFC power cycle.
Overvoltage Protection
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load should
suddenly change. A resistor divider from the high voltage
DC output of the PFC is fed to VFB. When the voltage on
VFB exceeds 2.7V, the PFC output driver is shut down.
The PWM section will continue to operate. The OVP
comparator has 125mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.58V. The VFB
should be set at a level where the active and passive external
power components and the ML4841 are within their safe
operating voltages, but not so low as to interfere with the
boost voltage regulation loop.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative
resistor; an increase in input voltage to the PWM causes a
decrease in the input current. This response dictates the
proper compensation of the two transconductance error
amplifiers. Figure 2 shows the types of compensation
networks most commonly used for the voltage and current
error amplifiers, along with their respective return points.
The current loop compensation is returned to VREF to
produce a soft-start characteristic on the PFC: as the
reference voltage comes up from zero volts, it creates a
differentiated voltage on IEAO which prevents the PFC from
immediately demanding a full duty cycle on its boost
converter.
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient response.
Optimizing interaction between transient response and
stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or
23Hz for a 47Hz line (lowest anticipated international power
frequency). The gain vs. input voltage of the ML4841’s
voltage error amplifier has a specially shaped nonlinearity
such that under steady-state operating conditions the
transconductance of the error amplifier is at a local
minimum. Rapid perturbations in line or load conditions
will cause the input to the voltage error amplifier (VFB) to
deviate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will increase
significantly, as shown in the Typical Performance Characteristics. This increases the gain-bandwidth product of the
voltage loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a
conventional linear gain characteristic.
Solving for RT x CT yields 1 x 10-5. Selecting standard components values, CT = 390pF, and RT = 24.9kΩ.
The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplifier should be at least 10 times that of the voltage
amplifier, to prevent interaction with the voltage loop. It
should also be limited to less than 1/6th that of the switching
frequency, e.g. 16.7kHz for a 100kHz switching frequency.
The ramp voltage should be limited to no more than the output high voltage (6V) of the current error amplifier. The timing resistor value should be selected such that the capacitor
will not charge past this point before being reset. In order to
ensure the linearity of the PFC loop’s transfer function and
improve noise immunity, the charging resistor should be
connected to the 13.5V VCC rather than the 7.5V reference.
This will keep the charging voltage across the timing cap in
the "linear" region of the charging curve.
For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the
design of this class of PFC.
Oscillator (RT/CT)
The oscillator frequency is determined by the values Of RT
and CT, which determine the ramp and off-time of the
oscillator output clock:
1
f OSC = ------------------------------------------------------t RAMP + t DISCHARGE
(2)
The ramp-charge time of the oscillator is derived from the
following equation:
V REF – 1.25
t RAMP = C T × R T × In  --------------------------------
 V REF – 3.75
(3)
at VREF = 7.5V:
The discharge time of the oscillator may be determined
using:
(4)
The deadtime is so small (tRAMP >> tDEADTIME) that the
operating frequency can typically be approximated by:
1
f OSC = ---------------t RAMP
REV. 1.0.3 6/13/01
t RAMP = 0.51 × R T × C T = 5 × 10
–6
RAMP 1
The ramp voltage on this pin serves as a reference to which
the PFC’s current error amp output is compared in order to
set the duty cycle of the PFC switch. The external ramp voltage is derived from a RC network similar to the oscillator’s.
The PWM’s oscillator sends a synchronous pulse every other
cycle to reset this ramp.
The component value selection is similar to oscillator RC
component selection.
1
f OSC = -------------------------------------------------------------t CHARGE + t DISCHARGE
(5)
(6)
The charge time of Ramp 1 is derived from the following
equations:
2
t CHARGE = -----------f OSC
(7)
V CC – Ramp Valley
t CHARGE = C T × R T × In  ---------------------------------------------------
 V CC – Ramp Peak 
(8)
At VCC = 13.5V and assuming Ramp Peak = 5V to allow for
component tolerances:
t CHARGE = 0.463 × R T × C T
t RAMP = C T × R T × 0.51
2.5V
t DISCHARGE = ------------------ × C T = 490 × C T
5.1mA
1
f OSC = 200kHz = ---------------t RAMP
(9)
The capacitor value should remain small to keep the discharge energy and the resulting discharge current through the
part small. A good value to use is the same value used in the
PWM timing circuit (CT).
For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields RT:
–5
1 × 10
R T = -------------------------------------------------------- = 56.2kΩ
– 12
( 0.463 ) ( 390 × 10 )
(10)
9
ML4841
PRODUCT SPECIFICATION
PWM SECTION
Solving for the minimum value of CSS:
Pulse Width Modulator
The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In applications
utilizing current mode control, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and is
thereby representative of the current flowing in the converter’s output stage. The DC ILIMIT comparator provides
cycle-by-cycle current limiting and is connected to RAMP 2
internally. If the current sense signal exceeds the 1V threshold, the PWM switch is disabled until the protection flip-flop
is rest by the clock pulse at the start of the next PWM power
cycle.
50µA
C SS = 5ms × ---------------- = 200nF
1.25V
VBIAS
VCC
ML4841
10nF
ceramic
1µF
ceramic
GND
PWM Current Limit
The DC ILIMIT comparator is a cycle-by-cycle current lim-
iter for the PWM section. Should the input voltage at this pin
ever exceed 1V, the output of the PWM will be disabled until
the output flip-flop is reset by the clock pulse at the start of
the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than its
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start commences.
PWM Control (RAMP 2)
The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:
50µA
C SS = t DELAY × ---------------1.25V
(11)
Figure 3. External Component Connections to VCC
Generating VCC
The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying it. This can be easily done with a single resistor in
series with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet the
operating current requirement of the ML4841 itself (19mA
max) plus the current required by the two gate driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC limit of 14.6V (max) and
driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
I GATEDRIVE = ( 100kHz × 45nC ) + ( 200kHz × 52nC ) = 15mA (12)
20V – 14.6V
R BIAS = --------------------------------------- = 160Ω
19mA + 15mA
(13)
To check the maximum dissipation in the ML4841, check the
current at the minimum VCC (12.4V):
where CSS is the required soft start capacitance, and tDELAY
is the desired start-up delay.
20V – 12.4V
I CC = --------------------------------- = 47.5mA
160Ω
It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
The maximum allowable ICC is 55mA, so this is an acceptable design.
10
(14)
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
The ML4841 should be locally bypassed with a 10nF and a
1µF ceramic capacitor. In most applications, an electrolytic
capacitor of between 100µF and 330µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
SW2
L1
I2
I1
+
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
I3
I4
VIN
RL
SW1
DC
C1
RAMP
REF
U3
+
–EA
VEAO
DFF
RAMP
OSC
U4
CLK
+
–
U1
R
Q
D U2
Q
CLK
TIME
VSW1
TIME
Figure 4. Typical Trailing Edge Control Scheme
REV. 1.0.3 6/13/01
11
ML4841
PRODUCT SPECIFICATION
SW2
L1
I2
I1
+
I3
I4
VIN
RL
SW1
DC
C1
RAMP
REF
U3
+
–EA
RAMP
OSC
U4
CLK
VEAO
VEAO
+
–
CMP
U1
DFF
R
Q
D U2
Q
CLK
TIME
VSW1
TIME
Figure 5. Leading/Trailing Edge Control Scheme
12
REV. 1.0.3 6/13/01
PRODUCT SPECIFICATION
ML4841
Typical Applications
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology suggested in Application Note
33.
AC INPUT
85 TO 265VAC
F1
3.15A
C1
680nF
L1
3.1mH
D1
8A, 600V
Q1
IRF840
C4
10nF
R2A
453kΩ
Q2
R17 IRF830
33Ω
C5
100µF
C25
100nF
T1
BR1
4A, 600V
R1A
499kΩ
R21
22Ω
R2B
453kΩ
D13
1A, 50V
R1B
499kΩ
C30
330µF
C12
10µF
D3
50V
RTN
R14
33Ω
C22
4.7µF
Q3
IRF830
R23
1.5kΩ
C7
220pF
VREF
VRMS
VCC
R7B
178kΩ
C23
100nF
R25
2.26kΩ
C15
10nF
C16
1µF
C13
100nF
C14
1µF
R8
2.37kΩ
C31
1nF
R11
750kΩ
C9
8.2nF
C8
82nF
PWM OUT
D8
1A, 20V
GND
RAMP 1
RAMP 2 DC I LIMIT
C18
390pF
R22
8.66kΩ
TL431
PFC OUT
SS
390pF
R26
10kΩ
VFB
I SENSE
VDC
R18
220Ω
VEAO
I AC
C19
1µF
R20
1.1Ω
R19
220Ω
C6
1nF
R12
27kΩ
12VDC
R24
1.2kΩ
R7A
178kΩ
R4
13kΩ
C24
1µF
C21
1800µF
C20
1µF
R3
75kΩ
IEAO
R5
300mΩ
1W
L2
D11
MBR2545CT 33µH
D6
600V
56.2kΩ
C2
470nF
T2
R15
3Ω
R28
160Ω
D12
1A, 50V
D7
15V
R30
4.7kΩ
R27
22kΩ
C3
100nF
D5
600V
D10
1A, 20V
ML4841
R6
24.9kΩ
R10
6.2kΩ
C17
220pF
C11
10nF
Figure 6. 100W Power Factor Corrected Power Supply.
REV. 1.0.3 6/13/01
13
ML4841
PRODUCT SPECIFICATION
Mechanical Dimensions inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
0.02 MIN
(0.50 MIN)
(4 PLACES)
1
0.055 - 0.065
(1.40 - 1.65)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
14
0.100 BSC
(2.54 BSC)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0° - 15°
0.008 - 0.012
(0.20 - 0.31)
REV. 1.0.3 6/13/01
ML4841
PRODUCT SPECIFICATION
Ordering Information
Part Number
ML4841CP
Temperature Range
Package
0°C to 70°C
16-Pin Plastic DIP (P16)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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