AD AD8202YR High common-mode voltage, single-supply difference amplifier Datasheet

High Common-Mode Voltage,
Single-Supply Difference Amplifier
AD8202
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
NC
A1
A2
+VS
7
3
4
6
AD8202
100kΩ
G = ×10
G = ×2
+IN
A1
–IN
+IN 8
–IN 1
+IN
A2
–IN
5
200kΩ
200kΩ
2
NC = NO CONNECT
GND
Figure 1. SOIC (R) Package Die Form
INDUCTIVE
LOAD
CLAMP
DIODE
BATTERY
4-TERM
SHUNT
+VS OUT
AD8202
–IN
GND
A1
A2
NC = NO CONNECT
COMMON
04981-002
POWER
DEVICE
The AD8202 is available in die and packaged form. The MSOP
and SOIC packages are specified over a wide temperature range,
from −40°C to +125°C, making the AD8202 well-suited for use
in many automotive platforms.
The AD8202 features an externally accessible 100 kΩ resistor
at the output of the Preamp A1 that can be used for low-pass
filter applications and for establishing gains other than 20.
NC
14V
The AD8202 is a single-supply difference amplifier for amplifying
and low-pass filtering small differential voltages in the presence of a
large common-mode voltage (CMV). The input CMV range
extends from −8 V to +28 V at a typical supply voltage of 5 V.
Automotive platforms demand precision components for
better system control. The AD8202 provides excellent ac and
dc performance keeping errors to a minimum in the user’s
system. Typical offset and gain drift in the SOIC package are
0.3 μV/°C and 1 ppm/°C, respectively. Typical offset and gain
drift in the MSOP package are 2 μV/°C and 1 ppm/°C, respectively. The device also delivers a minimum CMRR of 80 dB
from dc to 10 kHz.
5V
OUTPUT
+IN
GENERAL DESCRIPTION
04981-001
10kΩ
APPLICATIONS
Transmission control
Diesel injection control
Engine management
Adaptive suspension control
Vehicle dynamics control
OUT
10kΩ
Figure 2. High Line Current Sensor
POWER
DEVICE
5V
OUTPUT
+IN
BATTERY
NC
+VS OUT
14V
4-TERM
SHUNT
AD8202
–IN
CLAMP
DIODE
COMMON
GND
A1
A2
INDUCTIVE
LOAD
NC = NO CONNECT
04981-003
High common-mode voltage range
−8 V to +28 V at a 5 V supply voltage
Operating temperature range: −40°C to +125°C
Supply voltage range: 3.5 V to 12 V
Low-pass filter (1-pole or 2-pole)
Excellent ac and dc performance
±1 mV voltage offset
±1 ppm/°C typical gain drift
80 dB CMRR min dc to 10 kHz
Figure 3. Low Line Current Sensor
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8202
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Applications....................................................................................... 1
Applications..................................................................................... 14
General Description ......................................................................... 1
Current Sensing .......................................................................... 14
Functional Block Diagrams............................................................. 1
Gain Adjustment ........................................................................ 14
Specifications..................................................................................... 3
Gain Trim .................................................................................... 15
Single Supply ................................................................................. 3
Low-Pass Filtering...................................................................... 15
Absolute Maximum Ratings............................................................ 4
High Line Current Sensing with LPF and Gain Adjustment 16
ESD Caution.................................................................................. 4
Driving Charge Redistribution ADCs..................................... 16
Pin Configuration and Function Descriptions............................. 5
Outline Dimensions ....................................................................... 17
Typical Performance Characteristics ............................................. 6
Ordering Guide .......................................................................... 17
REVISION HISTORY
11/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Typical Performance Characteristics ........................ 6
Added Figure 18................................................................................ 8
Added Figure 25 to Figure 27.......................................................... 9
Added Figure 32.............................................................................. 10
Added Figure 37 to Figure 39........................................................ 11
Changes to Theory of Operation.................................................. 12
Added Figure 41.............................................................................. 13
2/05—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Figure 14........................................................................ 8
Changes to Figure 22........................................................................ 9
11/04—Rev. 0 to Rev. A
Changes to the Features....................................................................1
Changes to the General Description...............................................1
Changes to Specifications (Table 1) ................................................3
Changes to Absolute Maximum Ratings (Table 2) .......................4
Changes to Pin Function Descriptions (Table 3) ..........................5
Changes to Figure 5...........................................................................5
Changes to Figure 9 and Figure 10..................................................6
Updated Outline Dimensions....................................................... 12
Changes to the Ordering Guide ................................................... 12
7/04—Revision 0: Initial Version
1/05—Rev. A to Rev. B
Changes to the General Description.............................................. 1
Changes to Specifications ................................................................ 3
Added Figure 14 to Figure 33.......................................................... 8
Changes to Figure 38...................................................................... 14
Changes to Figure 40 and Figure 41............................................. 15
Changes to Ordering Guide .......................................................... 16
Rev. D | Page 2 of 20
AD8202
SPECIFICATIONS
SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted.
Table 1.
Parameter
SYSTEM GAIN
Initial
Error
vs. Temperature
VOLTAGE OFFSET
Input Offset (RTI)
vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
CMV
CMRR1
PREAMPLIFIER
Gain
Gain Error
Output Voltage Range
Output Resistance
OUTPUT BUFFER
Gain
Gain Error
Output Voltage Range
Input Bias Current
Output Resistance
DYNAMIC RESPONSE
System Bandwidth
Slew Rate
NOISE
0.1 Hz to 10 Hz
Spectral Density, 1 kHz (RTI)
POWER SUPPLY
Operating Range
Quiescent Current vs.
Temperature
PSRR
TEMPERATURE RANGE
For Specified Performance
1
2
Conditions
AD8202 SOIC
Min Typ Max
0.02 ≤ VOUT ≤ 4.8 V dc @ 25°C
−0.3
AD8202 MSOP
Min Typ Max
20
VCM = 0.15 V; 25°C
−40°C to +125°C
−40°C to +150°C
Continuous
VCM = −8 V to +28 V
f = dc
f = 1 kHz
f = 10 kHz 2
−1
−10
260
135
−8
20
1
+0.3
20
+0.3
+1
+10
−2
−20
390
205
+28
260
135
−8
325
170
82
82
80
100
−0.3
0.02
30
−0.3
0.02
97
+0.3
4.8
−0.3
0.02
0.25
75
+2
+20
−1
−10
−15
390
205
+28
260
135
−8
325
170
30
83
−40
100
−0.3
0.02
97
+0.3
4.8
−0.3
0.02
50
0.28
3.5
0.25
75
+125
+0.3
+5
+1
+10
+15
mV
μV/°C
μV/°C
390
205
+28
kΩ
kΩ
V
−40
325
170
dB
dB
dB
100
+0.3
4.8
103
2
30
10
275
12
1.0
1
V/V
%
ppm/°C
10
+0.3
4.8
103
12
1.0
83
+125
40
2
50
0.28
kHz
V/μs
10
275
μV p-p
nV/√Hz
0.25
−40
V/V
%
V
kΩ
V/V
%
V
nA
Ω
+0.3
4.8
3.5
75
Unit
+0.3
30
82
82
80
40
2
50
0.28
3.5
VS = 3.5 V to 12 V
+2
2
10
275
VO = 0.1 V dc
25
10
+0.3
4.8
103
40
2
VIN = 0.1 V p-p; VOUT = 2.0 V p-p
VIN = 0.2 V dc; VOUT = 4 V step
1
82
82
80
2
0.02 ≤ VOUT ≤ 4.8 V dc
20
−0.3
10
−0.3
0.02
97
AD8202 Die
Min Typ Max
12
1.0
83
V
mA
dB
+150
°C
Source imbalance <2 Ω.
The AD8202 preamplifier exceeds 80 dB CMRR at 10 kHz. However, because the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-topin capacitance between Pin 1, Pin 8 and Pin 3, Pin 4 might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of
pin-to-pin coupling can be neglected in all applications by using filter capacitors at Node 3.
Rev. D | Page 3 of 20
AD8202
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Transient Input Voltage (400 ms)
Continuous Input Voltage (Common Mode)
Reversed Supply Voltage Protection
Operating Temperature Range
Die
SOIC
MSOP
Storage Temperature
Output Short-Circuit Duration
Lead Temperature Range (Soldering, 10 sec)
Rating
12.5 V
44 V
35 V
0.3 V
−40°C to +150°C
−40°C to +125°C
−40°C to +125°C
−65°C to +150°C
Indefinite
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 4 of 20
AD8202
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN 1
GND 2
AD8202
8
+IN
7
NC
6 +VS
TOP VIEW
A2 4 (Not to Scale) 5 OUT
NC = NO CONNECT
04981-004
A1 3
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Mnemonic
−IN
GND
A1
A2
OUT
+VS
NC
+IN
1036μm
X
−409.0
−244.6
+229.4
+410.0
+410.0
+121.0
NA
−409.0
Y
−205.2
−413.0
−413.0
−308.6
+272.4
+417.0
NA
+205.2
+VS
OUT
+IN
1048μm
–IN
A2
GND
A1
Figure 5. Metallization Photograph
Rev. D | Page 5 of 20
04981-005
Pin No.
1
2
3
4
5
6
7
8
AD8202
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, VCM = 0 V, RL = 10 kΩ, unless otherwise noted.
90
0
80
PSRR (dB)
60
50
40
30
20
0
10
100
1k
FREQUENCY (Hz)
10k
–40°C
–15
+25°C
–20
–25
+125°C
–30
04981-006
10
–55°C
–10
+150°C
04981-009
COMMON-MODE VOLTAGE (V)
–5
70
–35
100k
3
Figure 6. Power Supply Rejection Ratio vs.
Frequency Valid for CM Range −8 V to +28 V
4
5
6
7
8
9
10
POWER SUPPLY (V)
11
12
13
Figure 9. Negative Common-Mode Voltage vs. Voltage Supply
30
40
35
COMMON-MODE VOLTAGE (V)
25
OUTPUT (dB)
20
15
10
30
–55°C
25
+150°C
20
+125°C
15
–40°C
10
+25°C
5
1k
10k
FREQUENCY (Hz)
100k
04981-010
04981-007
0
100
5
0
1M
3
Figure 7. Bandwidth
4
5
6
7
8
9
10
POWER SUPPLY (V)
11
12
13
Figure 10. Positive Common-Mode Voltage vs. Voltage Supply
100
5.0
4.5
95
OUTPUT SWING (V)
4.0
85
80
3.0
2.5
2.0
1.5
100
1k
FREQUENCY (Hz)
10k
04981-011
70
10
3.5
1.0
75
04981-008
CMRR (dB)
90
0.5
0
10
100k
Figure 8. Common-Mode Rejection Ratio vs. Frequency
Valid for Common-Mode Range −8 V to +28 V
100
1k
LOAD RESISTANCE (Ω)
Figure 11. Output Swing vs. Load Resistance
Rev. D | Page 6 of 20
10k
AD8202
18
0
TEMPERATURE = 25°C
16
OUTPUT MINUS SUPPLY (mV)
–10
14
NO LOAD
–20
12
HITS
–30
–40
10k LOAD
10
8
6
–50
04981-012
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
11
2
0
13
12
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
–70
04981-043
4
–60
CMRR (μV/V)
Figure 12. Output Minus Supply vs. Supply Voltage
Figure 15. CMRR Distribution, −8 V to +28 V Common Mode
8
OUTPUT
7
VSUPPLY = 5V
TEMPERATURE RANGE =
–40°C TO +25°C
6
HITS
5
3
INPUT
1
4
2
0
CH1 500mVΩ CH2 50mVΩ M 20μs 2.5MS/s 400NS/PT
A CH1 1.73V
04981-034
2
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
04981-013
1
VOS DRIFT (μV/°C)
Figure 13. Pulse Response
Figure 16. Offset Drift Distribution, MSOP,
Temperature Range = −40°C to +25°C
12
1000
800
10
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 125°C
600
8
HITS
200
–40°C
0
6
–200
–400
+25°C
4
+85°C
–600
–5
0
5
10
15
20
COMMON-MODE VOLTAGE (V)
25
0
30
04981-036
–1000
–10
2
+125°C
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
–800
04981-044
VOS (μV)
400
VOS DRIFT (μV/°C)
Figure 17. Offset Drift Distribution, MSOP,
Temperature Range = 25°C to 125°C
Figure 14. VOS vs. Common-Mode Voltage
Rev. D | Page 7 of 20
AD8202
10
9
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 85°C
9
TEMPERATURE = –40°C
8
8
7
7
6
HITS
HITS
6
5
5
4
4
3
3
04981-052
0
VOS DRIFT (μV/°C)
–2200
–2000
–1800
–1600
–1400
–1200
–1000
–800
–600
–400
–200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
1
16.0
14.0
12.0
8.0
10.0
6.0
4.0
0
2.0
–2.0
–4.0
–6.0
–8.0
–10.0
–12.0
–14.0
0
–16.0
1
04981-039
2
2
VOS (μV)
Figure 18. Offset Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
Figure 21. VOS Distribution, MSOP, Temperature = −40°C
14
14
10
10
8
8
6
4
4
2
2
0
04981-037
6
0
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
12
HITS
12
04981-040
TEMPERATURE = 25°C
–2200
–2000
–1800
–1600
–1400
–1200
–1000
–800
–600
–400
–200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
HITS
TEMPERATURE = 25°C
ERROR (%)
VOS (μV)
Figure 19. VOS Distribution, MSOP, Temperature = 25°C
Figure 22. MSOP Gain Accuracy, Temperature = 25°C
10
14
TEMPERATURE = 125°C
TEMPERATURE = 125°C
9
12
8
10
7
HITS
5
8
6
4
3
4
2
VOS (μV)
04981-041
0
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0
2
04981-038
1
–2200
–2000
–1800
–1600
–1400
–1200
–1000
–800
–600
–400
–200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
HITS
6
ERROR (%)
Figure 20. VOS Distribution, MSOP, Temperature = 125°C
Figure 23. MSOP Gain Accuracy, Temperature = 125°C
Rev. D | Page 8 of 20
AD8202
14
10
TEMPERATURE = –40°C
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 125°C
9
12
8
7
6
8
HITS
HITS
10
6
5
4
3
4
04981-042
ERROR (%)
18
16
14
12
8
10
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
0
–18
1
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0
04981-050
2
2
GAIN DRIFT (PPM/°C)
Figure 24. MSOP Gain Accuracy, Temperature = −40°C
Figure 27. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 125°C
40
9
TEMPERATURE = 25°C
VSUPPLY = 5V
TEMPERATURE RANGE =
+25°C TO –40°C
8
35
7
30
6
HITS
HITS
25
5
4
20
15
3
10
2
04981-028
0
–1500
–1400
–1300
–1200
–1100
–1000
–900
–800
–700
–600
–500
–400
–300
–200
–100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
04981-048
5
18
16
14
12
8
10
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
0
–18
1
VOS (μV)
GAIN DRIFT (PPM/°C)
Figure 25. Gain Drift Distribution, MSOP,
Temperature Range = +25°C to −40°C
Figure 28. VOS Distribution, SOIC, Temperature = 25°C
30
9
TEMPERATURE = 125°C
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 85°C
8
25
7
20
HITS
5
4
15
10
3
2
04981-030
0
18
16
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
0
–1500
–1400
–1300
–1200
–1100
–1000
–900
–800
–700
–600
–500
–400
–300
–200
–100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
04981-049
5
1
–18
HITS
6
VOS (μV)
GAIN DRIFT (PPM/°C)
Figure 29. VOS Distribution, SOIC, Temperature = 125°C
Figure 26. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
Rev. D | Page 9 of 20
AD8202
35
30
TEMPERATURE = –40°C
30
25
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 125°C
25
HITS
HITS
20
20
15
15
10
10
–10.0
–9.0
–8.0
–7.0
–6.0
–5.0
–4.0
–3.0
–2.0
–1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
04981-029
0
–1500
–1400
–1300
–1200
–1100
–1000
–900
–800
–700
–600
–500
–400
–300
–200
–100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
0
04981-027
5
5
VOS DRIFT (μV/°C)
VOS (μV)
Figure 30. VOS Distribution, SOIC, Temperature = −40°C
Figure 33. Offset Drift Distribution, SOIC,
Temperature Range = 25°C to 125°C
25
40
VSUPPLY = 5V
TEMPERATURE RANGE =
–40°C TO +25°C
TEMPERATURE = 25°C
35
20
30
25
HITS
HITS
15
10
20
15
10
5
VOS DRIFT (μV/°C)
04981-031
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
04981-025
0
8.0
9.0
10.0
3.0
4.0
5.0
6.0
7.0
–2.0
–1.0
0
1.0
2.0
–10.0
–9.0
–8.0
–7.0
–6.0
–5.0
–4.0
–3.0
0
5
ERROR (%)
Figure 31. Offset Drift Distribution, SOIC,
Temperature Range = −40°C to +25°C
Figure 34. Gain Accuracy, SOIC, Temperature = 25°C
45
25
TEMPERATURE = 125°C
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 85°C
40
20
35
30
HITS
HITS
15
25
20
10
15
04981-051
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
5
–15.0
–14.0
–13.0
–12.0
–11.0
–10.0
–9.0
–8.0
–7.0
–6.0
–5.0
–4.0
–3.0
–2.0
–1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
0
04981-032
10
5
ERROR (%)
VOS DRIFT (μV/°C)
Figure 32. Offset Drift Distribution, SOIC,
Temperature Range = 25°C to 85°C
Figure 35. Gain Accuracy, SOIC, Temperature = 125°C
Rev. D | Page 10 of 20
AD8202
50
25
TEMPERATURE = –40°C
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 85°C
45
20
40
35
15
HITS
HITS
30
25
10
20
15
0
ERROR (%)
GAIN DRIFT (PPM/°C)
Figure 36. Gain Accuracy, SOIC, Temperature = −40°C
Figure 38. Gain Drift Distribution, SOIC,
Temperature Range = 25°C to 85°C
45
40
35
–25
–23
–21
–19
–17
–15
–13
–11
–9
–7
–5
–3
–1
1
3
5
7
9
11
13
15
17
19
21
23
25
04981-033
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
5
04981-046
5
10
VSUPPLY = 5V
TEMPERATURE RANGE =
+25°C TO –40°C
40
VSUPPLY = 5V
TEMPERATURE RANGE =
25°C TO 125°C
35
30
30
HITS
20
25
20
15
15
10
04981-045
5
0
–25
–23
–21
–19
–17
–15
–13
–11
–9
–7
–5
–3
–1
1
3
5
7
9
11
13
15
17
19
21
23
25
0
04981-047
10
5
–25
–23
–21
–19
–17
–15
–13
–11
–9
–7
–5
–3
–1
1
3
5
7
9
11
13
15
17
19
21
23
25
HITS
25
GAIN DRIFT (PPM/°C)
GAIN DRIFT (PPM/°C)
Figure 39. Gain Drift Distribution, SOIC,
Temperature Range = 25°C to 125°C
Figure 37. Gain Drift Distribution, SOIC,
Temperature Range = +25°C to −40°C
Rev. D | Page 11 of 20
AD8202
THEORY OF OPERATION
The AD8202 consists of a preamp and buffer arranged as shown
in Figure 40. Like-named resistors have equal values.
The preamp uses a dynamic bridge (subtractor) circuit.
Identical networks (within the shaded areas), consisting of RA,
RB, RC, and RG, attenuate input signals applied to Pin 1 and
Pin 8. When equal amplitude signals are asserted at Input 1 and
Input 8, and the output of A1 is equal to the common potential
(that is, 0), the two attenuators form a balanced-bridge network.
When the bridge is balanced, the differential input voltage at
A1, and thus its output, is 0.
Any common-mode voltage applied to both inputs keeps the
bridge balanced and the A1 output at 0. Because the resistor
networks are carefully matched, the common-mode signal
rejection approaches this ideal state.
However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive RB, by way of RG, to adjust the voltage at its inverting
input until it matches the voltage at its noninverting input.
By attenuating voltages at Pin 1 and Pin 8, the amplifier inputs
are held within the power supply range, even if Pin 1 and Pin 8
input levels exceed the supply or fall below common (ground).
The input network also attenuates normal (differential) mode
voltages. RC and RG form an attenuator that scales A1 feedback,
forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at 10.
Because the differential input signal is attenuated and then
amplified to yield an overall gain of 10, Amplifier A1 operates
at a higher noise gain, multiplying deficiencies such as input
offset voltage and noise with respect to Pin 1 and Pin 8.
+IN
–IN
8
1
RA
RA
100kΩ
A1
3
4
(TRIMMED)
RCM
RB
RB
RC
RC
A2
5
RF
RCM
A3
RF
RG
Amplifier A3 detects the common-mode signal applied to A1
and adjusts the voltage on the matched RCM resistors to reduce
the common-mode voltage range at the A1 inputs. By adjusting
the common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.
The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio-trimmed for high accuracy.
The output of the preamp drives a gain-of-2 buffer amplifier,
A2, implemented with carefully matched feedback resistors (RF).
The 2-stage system architecture of the AD8202 enables the user
to incorporate a low-pass filter prior to the output buffer. By
separating the gain into two stages, a full-scale, rail-to-rail
signal from the preamp can be filtered at Pin 3, and a half-scale
signal, resulting from filtering, can be restored to full scale by
the output buffer amp. The source resistance seen by the
inverting input of A2 is approximately 100 kΩ to minimize the
effects of the input bias current of A2. However, this current is
quite small, and errors resulting from applications that mismatch
the resistance are correspondingly small.
The A2 input bias current has a typical value of 40 nA, however,
this can increase under certain conditions. For example, if the
input signal to the A2 amplifier is VCC/2, the output attempts to
go to VCC due to the gain of 2. However, the output saturates
because the maximum specified voltage for correct operation is
200 mV below VCC. Under these conditions the total input bias
current increases (see Figure 41 for more information).
AD8202
04981-014
RG
To minimize these errors while extending the common-mode
range, a dedicated feedback loop is used to reduce the range of
common-mode voltage applied to A1 for a given overall range at
the inputs. By offsetting the voltage range applied to the compensator, the input common-mode range is also offset to include
voltages more negative than the power supply.
2
COM
Figure 40. Simplified Schematic
Rev. D | Page 12 of 20
AD8202
–140
VSUPPLY = 5V
TEMPERATURE RANGE =
+125°C TO –40°C
A2 INPUT BIAS CURRENT (nA)
–120
•
The total error at the input of A2, 24 mV, multiplied by the
buffer gain generates a resulting error of 48 mV at the
output of the buffer. This is AD8202 system output low
saturation potential.
•
The high output voltage range of the AD8202 is specified
as 4.8 V. Therefore, assuming a typical A2 input bias
current, the output voltage range for the AD8202 is 48 mV
to 4.8 V.
–100
–80
–60
–40
04981-053
–20
0
0
0.5
1.0
1.5
2.0
2.5
DIFFERENTIAL-MODE VOLTAGE (V)
Figure 41. A2 Input Bias Current vs. Input Voltage and Temperature. The
Shaded Area is the Bias Current from +125°C to −40°C.
For an example of the effect of changes in A2 input bias current
vs. applied input potentials, see Figure 41. The change in bias
current causes a change in error voltage at the input of the
buffer amplifier. This results in a change in overall error
potential at the output of the buffer amplifier.
An increase in the A2 bias current, in addition to the output
saturation voltage of A1, directly affects the output voltage of
the AD8202 system (Pin 3 and Pin 4 shorted). An example of
how to calculate the correct output voltage swing of the
AD8202, by taking all variables into account, follows:
•
Amplifier A1 output saturation potential can drop as low
as 20 mV at its output.
•
A2 typical input bias current of 40 nA multiplied by the
100 kΩ preamplifier output resistor produces
40 nA × 100 kΩ = 4 mV at the A2 input
•
Total voltage at the A2 input equals the output saturation
voltage of A1 combined with the voltage error generated
by the input bias current
20 mV + 4 mV = 24 mV
Rev. D | Page 13 of 20
AD8202
APPLICATIONS
+VS
The AD8202 difference amplifier is intended for applications that
require extracting a small differential signal in the presence of
large common-mode voltages. The differential input resistance
is nominally 325 kΩ, and the device can tolerate common-mode
voltages higher than the supply voltage and lower than ground.
The open collector output stage sources current to within
20 mV of ground and to within 200 mV of VS.
OUT
+IN
VDIFF
2
+VS
NC
10kΩ
OUT
10kΩ
GAIN =
AD8202
VCM
VDIFF
REXT = 100kΩ
100kΩ
2
–IN
20REXT
REXT + 100kΩ
GND
A1
GAIN
20 – GAIN
A2
CURRENT SENSING
High Line, High Current Sensing
Basic automotive applications using the large common-mode
range are shown in Figure 2 and Figure 3. The capability of the
device to operate as an amplifier in primary battery supply
circuits is shown in Figure 2; Figure 3 illustrates the ability
of the device to withstand voltages below system ground.
Low Current Sensing
The AD8202 is also used in low current sensing applications,
such as the 4 to 20 mA current loop shown in Figure 42. In such
applications, the relatively large shunt resistor can degrade the
common-mode rejection. Adding a resistor of equal value on the
low impedance side of the input corrects for this error.
NC = NO CONNECT
Figure 43. Adjusting for Gains Less than 20
The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due
to the imbalance in source resistances at the input to the buffer.
This can often be ignored, but if desired, it can be nulled by
inserting a resistor equal to 100 kΩ minus the parallel sum of REXT
and 100 kΩ, in series with Pin 4. For example, with REXT = 100 kΩ
(yielding a composite gain of ×10), the optional offset nulling
resistor is 50 kΩ.
Gains Greater Than 20
5V
Connecting a resistor from the output of the buffer amplifier
to its noninverting input, as shown in Figure 44, increases the
gain. The gain is multiplied by the factor REXT/(REXT − 100 kΩ);
for example, the gain is doubled for REXT = 200 kΩ. Overall
gains as high as 50 are achievable in this way. The accuracy of
the gain becomes critically dependent on the resistor value at
high gains. Also, the effective input offset voltage at Pin 1 and
Pin 8 (about six times the actual offset of A1) limits the part’s
use in high gain, dc-coupled applications.
OUTPUT
+IN
10Ω
1%
NC
+VS
OUT
AD8202
GND
A1
A2
NC = NO CONNECT
04981-015
–IN
+VS
OUT
Figure 42. 4 to 20 mA Current Loop Receiver
+IN
VDIFF
2
GAIN ADJUSTMENT
The default gain of the preamplifier and buffer are ×10 and ×2,
respectively, resulting in a composite gain of ×20. With the
addition of external resistor(s) or trimmer(s), the gain can be
lowered, raised, or finely calibrated.
NC
10kΩ
+VS
OUT
10kΩ
GAIN =
AD8202
VCM
Gains Less than 20
VDIFF
2
REXT
REXT = 100kΩ
100kΩ
–IN
GND
A1
Rev. D | Page 14 of 20
GAIN
GAIN – 20
A2
NC = NO CONNECT
Because the preamplifier has an output resistance of 100 kΩ,
an external resistor connected from Pin 3 and Pin 4 to GND
decreases the gain by a factor REXT/(100 kΩ + REXT) as shown
in Figure 43.
20REXT
REXT – 100kΩ
Figure 44. Adjusting for Gains > 20
04981-017
10Ω
1%
+
04981-016
REXT
AD8202
GAIN TRIM
Figure 45 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor, REXT.
The following approximation is useful for small gain ranges:
ΔG ≈ (10 MΩ/REXT)%
Thus, the adjustment range is ±2% for REXT = 5 MΩ; ±10% for
REXT = 1 MΩ, and so on.
Low-pass filters can be implemented in several ways by using the
AD8202. In the simplest case, a single-pole filter (20 dB/decade)
is formed when the output of A1 is connected to the input of
A2 via the internal 100 kΩ resistor by tying Pin 3 and Pin 4
and adding a capacitor from this node to ground, as shown in
Figure 46. If a resistor is added across the capacitor to lower the
gain, the corner frequency increases; it should be calculated using
the parallel sum of the resistor and 100 kΩ.
5V
OUTPUT
5V
OUT
+IN
NC
+IN
+VS OUT
VDIFF
2
+VS OUT
VDIFF
2
fC =
AD8202
AD8202
VCM
VDIFF
2
VDIFF
2
A1
GND
A1
A2
A2
REXT
NC = NO CONNECT
GAIN TRIM
20kΩ MIN
C
04981-019
GND
1
2πC105
C IN FARADS
–IN
–IN
04981-018
VCM
NC
NC = NO CONNECT
Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor
Figure 45. Incremental Gain Trim
Internal Signal Overload Considerations
When configuring gain for values other than 20, the maximum input voltage with respect to the supply voltage and
ground must be considered because either the preamplifier
or the output buffer reaches its full-scale output (approximately
VS − 0.2 V) with large differential input voltages. The input of
the AD8202 is limited to (VS − 0.2)/10 for overall gains ≤ 10
because the preamplifier, with its fixed gain of ×10, reaches its fullscale output before the output buffer. For gains greater than 10, the
swing at the buffer output reaches its full scale first and limits the
AD8202 input to (VS − 0.2)/G, where G is the overall gain.
If the gain is raised using a resistor, as shown in Figure 44, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz/μF
(0.039 μF for a 20 Hz corner frequency).
5V
OUT
+IN
NC
+VS OUT
VDIFF
2
AD8202
VCM
C
VDIFF
2
–IN
GND
A1
A2
LOW-PASS FILTERING
255kΩ
When implementing a filter, the PAR should be considered
so that the output of the AD8202 preamplifier (A1) does not
clip before A2 because this nonlinearity would be averaged
and appear as an error at the output. To avoid this error,
both amplifiers should clip at the same time. This condition
is achieved when the PAR is no greater than the gain of the
second amplifier (2 for the default configuration). For example,
if a PAR of 5 is expected, the gain of A2 should be increased to 5.
C
fC(Hz) = 1/C(μF)
NC = NO CONNECT
04981-020
In many transducer applications, it is necessary to filter
the signal to remove spurious high frequency components
including noise, or to extract the mean value of a fluctuating
signal with a peak-to-average ratio (PAR) greater than unity.
For example, a full-wave rectified sinusoid has a PAR of 1.57,
a raised cosine has a PAR of 2, and a half-wave sinusoid has a
PAR of 3.14. Signals having large spikes can have PARs of 10
or more.
Figure 47. 2-Pole, Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be
implemented using the connections shown in Figure 47. This is a
Sallen-Key form based on a ×2 amplifier. It is useful to remember
that a 2-pole filter with a corner frequency f2 and a 1-pole filter
with a corner at f1 have the same attenuation at the frequency
(f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is
illustrated in Figure 48. Using the standard resistor value shown
and equal capacitors (see Figure 47), the corner frequency is
conveniently scaled at 1 Hz/μF (0.05 μF for a 20 Hz corner).
A maximally flat response occurs when the resistor is lowered to
196 kΩ and the scaling is then 1.145 Hz/μF. The output offset
is raised by approximately 5 mV (equivalent to 250 μV at the
input pins).
Rev. D | Page 15 of 20
AD8202
FREQUENCY
by a 1-pole low-pass filter, set with a corner frequency of 3.6 Hz,
providing about 30 dB of attenuation at 100 Hz. A higher rate of
attenuation can be obtained using a 2-pole filter with fC = 20 Hz,
as shown in Figure 50. Although this circuit uses two separate
capacitors, the total capacitance is less than half that needed for
the 1-pole filter.
20dB/DECADE
INDUCTIVE
LOAD
40LOG (f2/f1)
CLAMP
DIODE
OUTPUT
NC
+IN
A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f2, HAVE
THE SAME ATTENUATION –40LOG (f2/f1)
AT FREQUENCY f22/f1
04981-021
4-TERM
SHUNT
NC
BATTERY
C
NC = NO CONNECT
OUT
4V/AMP
+VS OUT
20kΩ
A1
A2
POWER
DEVICE
VOS/IB
NULL
COMMON
5% CALIBRATION RANGE
fC(Hz) = 0.796Hz/C(μF)
(0.22μF FOR fC = 3.6Hz)
Figure 49. High Line Current Sensor Interface;
Gain = ×40, Single-Pole, Low-Pass Filter
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends
on the inductance of the load and the control frequency. The
common-mode voltage, conversely, extends from roughly 1 V
above ground for the on condition to about 1.5 V above the
battery voltage in the off condition. The conduction of the
clamping diode regulates the common-mode potential applied
to the device. For example, a battery spike of 20 V can result
in an applied common-mode potential of 21.5 V to the input
of the devices.
04981-022
C
NC = NO CONNECT
COMMON
fC(Hz) = 1/C(μF)
(0.05μF FOR fC = 20Hz)
Figure 50. 2-Pole Low-Pass Filter
191kΩ
GND
A2
127kΩ
AD8202
–IN
A1
DRIVING CHARGE REDISTRIBUTION ADCS
5V
14V
4-TERM
SHUNT
GND
POWER
DEVICE
Figure 49 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.
+IN
C
50kΩ
HIGH LINE CURRENT SENSING WITH LPF AND
GAIN ADJUSTMENT
CLAMP
DIODE
AD8202
–IN
Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
INDUCTIVE
LOAD
432kΩ
14V
f22/f1
f2
+VS OUT
04981-023
f1
BATTERY
5V
When driving CMOS ADCs, such as those embedded in
popular microcontrollers, the charge injection (ΔQ) can cause
a significant deflection in the output voltage of the AD8202.
Though generally of short duration, this deflection can persist
until after the sample period of the ADC expires due to the
relatively high open-loop output impedance (typically 21 kΩ)
of the AD8202. Including an R-C network in the output can
significantly reduce the effect. The capacitor helps to absorb the
transient charge, effectively lowering the high frequency output
impedance of the AD8202. For these applications, the output
signal should be taken from the midpoint of the RLAG − CLAG
combination, as shown in Figure 51.
Because the perturbations from the analog-to-digital converter
are small, the output impedance of the AD8202 appears to be low.
The transient response, therefore, has a time constant governed
by the product of the two LAG components, CLAG × RLAG. For the
values shown in Figure 51, this time constant is programmed at
approximately 10 μs. Therefore, if samples are taken at several
tenths of microseconds or more, there is negligible charge
stack-up.
To produce a full-scale output of 4 V, a gain ×40 is used,
adjustable by ±5% to absorb the tolerance in the shunt.
Sufficient headroom allows 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
Rev. D | Page 16 of 20
5V
4
6
+IN
AD8202
RLAG
1kΩ
A2
5
–IN
10kΩ
CLAG
0.01μF
MICROPROCESSOR
A/D
10kΩ
2
Figure 51. Recommended Circuit for Driving CMOS A/D
04981-024
ATTENUATION
40dB/DECADE
AD8202
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
8
3.20
3.00
2.80
0.50 (0.0196)
× 45°
0.25 (0.0099)
1
5.15
4.90
4.65
5
4
PIN 1
0.65 BSC
0.95
0.85
0.75
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
1.10 MAX
0.15
0.00
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.80
0.60
0.40
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8202YR
AD8202YR-REEL
AD8202YR-REEL7
AD8202YRZ 1
AD8202YRZ-RL1
AD8202YRZ-R71
AD8202YRMZ1
AD8202YRMZ-RL1
AD8202YRMZ-R71
AD8202YCSURF
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8 Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8 Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Die
Z = Pb-free part.
Rev. D | Page 17 of 20
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
Branding
JWY
JWY
JWY
AD8202
NOTES
Rev. D | Page 18 of 20
AD8202
NOTES
Rev. D | Page 19 of 20
AD8202
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04981-0-11/05(D)
Rev. D | Page 20 of 20