Revised January 1999 MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset General Description Features The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement transistors. Each flip-flop has independent J, K, clock and clear inputs and Q and Q outputs. The MM74C76 flip flops also include preset inputs and are supplied in 16 pin packages. This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input. ■ Supply voltage range: 3V to 15V ■ Tenth power TTL compatible: ■ High noise immunity: Drive 2 LPTTL loads 0.45 VCC (typ.) ■ Low power: 50 nW (typ.) ■ Medium speed operation: 10 MHz (typ.) Applications • Automotive • Data terminals • Instrumentation • Medical electronics • Alarm systems • Industrial electronics • Remote metering • Computers Ordering Code: Order Number Package Number Package Description MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C76M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams MM74C76 MM74C73 Note: A logic “0” on clear sets Q to a logic “0”. Note: A logic “0” on preset sets Q to a logic “1”. Top View Note: A logic “0” on clear sets Q to logic “0”. Top View © 1999 Fairchild Semiconductor Corporation DS005884.prf www.fairchildsemi.com MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset October 1987 MM74C73 • MM74C76 Truth Tables tn tn+1 J K Q 0 0 Qn 0 1 0 1 0 1 1 1 Qn tn = bit time before clock pulse tn+1 = bit time after clock pulse Clear Qn Qn 0 0 0 0 0 1 1 0 1 0 0 1 1 1 Qn (Note 1) Qn (Note 1) Note 1: No change in output from previous state Logic Diagrams MM74C73 MM74C76 Transmission Gate www.fairchildsemi.com Preset 2 −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range −40°C to +85°C −65°C to +150°C Storage Temperature Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation. Lead Temperature (Soldering, 10 seconds) 260°C +3V to 15V Operating VCC Range VCC (Max) 18V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage VCC = 5V 3.5 VCC = 10V 8 V V VIN(0) Logical “0” Input Voltage VCC = 5V VOUT(1) Logical “1” Output Voltage VCC = 5V 4.5 VCC = 10V 9 VOUT(0) Logical “0” Output Voltage VCC = 5V 0.5 VCC = 10V 1 V IIN(1) Logical “1” Input Current VCC = 15V 1 µA IIN(0) Logical “0” Input Current VCC = 15V ICC Supply Current VCC = 15V 1.5 VCC = 10V 2 V V V V −1 V µA 0.050 60 µA 0.8 V LOW POWER TTL TO CMOS INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current VCC = 5V, VIN(0) = 0V −1.75 mA −8 mA 1.75 mA 8 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current VCC = 10V, VIN(0) = 0V TA = 25°C, VOUT = 0V ISINK Output Sink Current VCC = 5V, VIN(1) = 5V TA = 25°C, VOUT = VCC ISINK Output Sink Current VCC = 10V, VIN(1) = 10V TA = 25°C, VOUT = VCC 3 www.fairchildsemi.com MM74C73 • MM74C76 Absolute Maximum Ratings(Note 2) MM74C73 • MM74C76 AC Electrical Characteristics (Note 3) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CIN Input Capacitance Any Input 5 tpd0, tpd1 Propagation Delay Time to a VCC = 5V 180 300 pF ns Logical “0” or Logical “1” from VCC = 10V 70 110 ns Propagation Delay Time to a VCC = 5V 200 300 ns Logical “0” from Preset or Clear VCC = 10V 80 130 ns Propagation Delay Time to a VCC = 5V 200 300 ns Logical “1” from Preset or Clear VCC = 10V 80 130 ns Time Prior to Clock Pulse that VCC = 5V 110 175 ns Data must be Present VCC = 10V 45 70 ns Clock to Q or Q tpd0 tpd tS tH tPW tPW tMAX tr, tf Time after Clock Pulse that J VCC = 5V −40 0 ns and K must be Held VCC = 10V −20 0 ns Minimum Clock Pulse Width VCC = 5V 120 190 ns tWL = tWH VCC = 10V 50 80 ns Minimum Preset and Clear VCC = 5V 90 130 ns Pulse Width VCC = 10V 40 60 ns Maximum Toggle Frequency VCC = 5V 2.5 4 VCC = 10V 7 11 Clock Pulse Rise and Fall Time MHz VCC = 5V 15 µs VCC = 10V 5 µs Note 3: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com MHz 4 Switching Time Waveforms CMOS to CMOS tr = tf = 20 ns Typical Applications Ripple Binary Counters Shift Registers 74C Compatibility Guaranteed Noise Margin as a Function of VCC 5 www.fairchildsemi.com MM74C73 • MM74C76 AC Test Circuit MM74C73 • MM74C76 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset Physical Dimensions inches (millimeters) unless otherwise noted (Continued)