AD ADF4360-5 300 mhz to 1000 mhz quadrature modulator Datasheet

300 MHz to 1000 MHz
Quadrature Modulator
ADL5370
FEATURES
Output frequency range: 300 MHz to 1000 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 11 dBm @ 450 MHz
Noise floor: −160 dBm/Hz
Sideband suppression: −41 dBc @ 450 MHz
Carrier feedthrough: −50 dBm @ 450 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP_VQ package
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
LOIP
LOIN
QUADRATURE
PHASE
SPLITTER
VOUT
Cellular communication systems at 450 MHz
CDMA2000/GSM
WiMAX/broadband wireless access systems
Cable communication equipment
Satellite modems
06117-001
QBBN
APPLICATIONS
QBBP
Figure 1.
GENERAL DESCRIPTION
The ADL5370 is the first in the fixed-gain quadrature modulator
(F-MOD) family designed for use from 300 MHz to 1000 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.
The ADL5370 provides a greater than 500 MHz, 3 dB baseband
bandwidth, making it ideally suited for use in broadband zero
IF or low IF-to-RF applications and in broadband digital
predistortion transmitters.
The ADL5370 accepts two differential baseband inputs and
a single-ended LO and generates a single-ended 50 Ω output.
The ADL5370 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in
a 24-lead, exposed-paddle, Pb-free, LFCSP_VQ package. Performance is specified over a −40°C to +85°C temperature range.
A Pb-free evaluation board is available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADL5370
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 13
Applications....................................................................................... 1
DAC Modulator Interfacing ..................................................... 13
Functional Block Diagram .............................................................. 1
Limiting the AC Swing .............................................................. 13
General Description ......................................................................... 1
Filtering........................................................................................ 13
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Using the AD9779 Auxiliary DAC for Carrier Feedthrough
Nulling ......................................................................................... 14
Absolute Maximum Ratings............................................................ 4
GSM Operation .......................................................................... 14
ESD Caution.................................................................................. 4
LO Generation Using PLLs ....................................................... 15
Pin Configuration and Function Descriptions............................. 5
Evaluation Board ............................................................................ 16
Theory of Operation ...................................................................... 10
Characterization Setup .................................................................. 17
Circuit Description..................................................................... 10
Outline Dimensions ....................................................................... 19
Basic Connections .......................................................................... 11
Ordering Guide .......................................................................... 19
Optimization ............................................................................... 12
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADL5370
SPECIFICATIONS
VS = 5 V; TA = 25°C; LO = 0 dBm 1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
Table 1.
Parameter
ADL5370
Operating Frequency Range
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
GSM
LO INPUTS
LO Drive Level1
Input Return Loss
BASEBAND INPUTS
I and Q Input Bias Level
Input Bias Current
Input Offset Current
Differential Input Impedance
Bandwidth (0.1 dB)
Bandwidth (1 dB)
POWER SUPPLIES
Voltage
Supply Current
1
2
Conditions
LO = 450 MHz
Range over which uncompensated sideband suppression < −30 dBc
Low frequency
High frequency
VIQ = 1.4 V p-p differential
Min
POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm
POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −2 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
6 MHz carrier offset, POUT = 6 dBm, PLO = 6 dBm
Characterization performed at typical level
See Figure 9 for a plot of return loss vs. frequency
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
−7
Typ
LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
Pin VPS1 and Pin VPS2
MHz
MHz
dBm
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
−157
dBc/Hz
0
6
4.75
+7
dBm
dB
mV
μA
μA
kΩ
MHz
MHz
5.25
205
Rev. 0 | Page 3 of 20
Unit
300
1000
6.2
11
−50
−41
0.76
0.03
−65
−54
60
24
−160
500
45
0.1
2900
70
350
Current sourcing from each baseband input with a bias of 500 mV dc 2
High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
See V-to-I converter discussion in the Circuit Description section for architecture information.
Max
V
mA
ADL5370
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPOS
IBBP, IBBN, QBBP, QBBN
LOIP and LOIN
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
0 V to 2 V
13 dBm
1375 mW
54°C/W
159°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 4 of 20
ADL5370
24
23
22
21
20
19
QBBP
QBBN
COM4
COM4
IBBN
IBBP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5370
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
VPS5
VPS4
VPS3
VPS2
VPS2
VOUT
06117-002
1
2
3
4
5
6
COM2 7
LOIP 8
LOIN 9
COM2 10
COM3 11
COM3 12
COM1
COM1
VPS1
VPS1
VPS1
VPS1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2, 7, 10 to 12,
21, 22
3 to 6, 14 to 18
Mnemonic
COM1, COM2,
COM3, COM4
VPS1, VPS2, VPS3,
VPS4, VPS5
19, 20, 23, 24
IBBP, IBBN, QBBN,
QBBP
8, 9
LOIP, LOIN
13
VOUT
Exposed Paddle
Description
Input Common Pins. Connect to ground plane via a low impedance path.
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground. Adjacent
power supply pins of the same name can share one capacitor (see Figure 25).
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to 500 mV dc, and must be driven from a low impedance source. Nominal characterized
ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a
500 mV dc bias. These inputs are not self-biased and must be externally biased.
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled. AC-couple
LOIN to ground and drive LO through LOIP.
Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the load.
Connect to ground plane via a low impedance path.
Rev. 0 | Page 5 of 20
ADL5370
TYPICAL PERFORMANCE CHARACTERISTICS
8
14
7
12
TA = –40°C
5
TA = +25°C
4
TA = +85°C
3
2
0
250
450
650
850
1050
1250
10
TA = +25°C
TA = +85°C
8
6
4
2
06117-003
1
TA = –40°C
0
250
1450
06117-006
6
OUTPUT P1dB (dBm)
450
LO FREQUENCY (MHz)
7
12
VS = 5.25V
OUTPUT P1dB (dBm)
VS = 5V
4
VS = 4.75V
3
2
650
850
1050
1250
VS = 5.25V
10
VS = 5V
VS = 4.75V
8
6
4
0
250
1450
450
LO FREQUENCY (MHz)
650
850
1050
1250
1450
LO FREQUENCY (MHz)
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Supply
Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Supply
90
5
60
120
150
30
1450MHz
S22 OF OUTPUT
1450MHz
0
180
0
250MHz
S11 OF LOIP
330
210
–5
06117-035
OUTPUT POWER VARIANCE (dB)
1450
2
06117-004
1
450
1250
06117-007
SSB OUTPUT POWER (dBm)
14
0
250
1050
Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. fLO and Temperature
8
5
850
LO FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Temperature
6
650
1
10
100
250MHz
240
1000
300
BASEBAND FREQUENCY (MHz)
270
Figure 5. I and Q Input Bandwidth Normalized to Gain @ 1 MHz
(fLO = 500 MHz)
Figure 8. Smith Chart of LOIP S11 and VOUT S22 .
(fLO from 250 MHz to 1450 MHz)
Rev. 0 | Page 6 of 20
06117-008
SSB OUTPUT POWER (dBm)
VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
ADL5370
0
0
SIDEBAND SUPPRESSION (dBc)
–10
–10
–15
–20
TA = +85°C
–30
TA = –40°C
–40
–50
–60
–70
TA = +25°C
850
1050
1250
–90
250
1450
450
650
LO FREQUENCY (MHz)
0
–10
–10
SIDEBAND SUPPRESSION (dBc)
CARRIER FEEDTHROUGH (dBm)
0
–20
–30
–40
–50
–60
–70
650
850
1050
1250
TA = +85°C
–40
–50
–60
–70
TA = +25°C
–90
250
1450
450
650
1050
1250
–20
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–10
–20
–30
–40
–50
–60
–70
06117-011
–80
650
850
1050
1450
Figure 13. Sideband Suppression vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
0
CARRIER FEEDTHROUGH (dBm)
850
LO FREQUENCY (MHz)
Figure 10. Carrier Feedthrough vs. fLO and Temperature
Multiple Devices Shown
450
1450
TA = –40°C
–30
LO FREQUENCY (MHz)
–90
250
1250
–20
–80
06117-010
–80
450
1050
Figure 12. Sideband Suppression vs. fLO and Temperature
Multiple Devices Shown
Figure 9. Return Loss (S11) of LOIP
–90
250
850
LO FREQUENCY (MHz)
06117-013
650
1250
–30
10
THIRD ORDER (dBc)
–40
5
CARRIER
FEEDTHROUGH
(dBm)
–50
SIDEBAND
SUPPRESSION (dBc)
–60
0
–5
SECOND ORDER (dBc)
–70
–80
0.2
1450
15
SSB OUTPUT POWER
0.6
1.0
1.4
1.8
2.2
SSB OUTPUT POWER (dBm)
450
06117-012
–80
06117-009
–25
250
–20
–10
2.6
3.0
–15
3.4
06117-014
RETURN LOSS (dB)
–5
BASEBAND INPUT VOLTAGE (V p-p)
LO FREQUENCY (MHz)
Figure 11. Carrier Feedthrough vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 450 MHz)
Rev. 0 | Page 7 of 20
ADL5370
15
30
CARRIER
FEEDTHROUGH
(dBm)
SSB OUTPUT POWER
–40
SIDEBAND
SUPPRESSION (dBc)
–50
5
0
SECOND ORDER (dBc) –5
–60
–70
SSB OUTPUT POWER (dBm)
10
–10
–80
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
–15
3.4
TA = –40°C
25
TA = +25°C
20
15
10
5
0
250
450
650
–20
THIRD
ORDER = –40°C
–50
SECOND ORDER = –40°C
–60
–70
SECOND ORDER = +85°C
–80
250
SECOND ORDER = +25°C
450
650
850
1050
1250
TA = +25°C
50
TA = +85°C
40
30
20
10
0
250
1450
450
650
Figure 16. Second- and Third-Order Distortion vs. fLO and Temperature
(Baseband I/Q Amplitude = 1.4 V p-p differential)
3
2
–70
SECOND ORDER (dBc)
1
–80
10
0
100
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
THIRD ORDER (dBc)
4
SSB OUTPUT POWER (dBm)
CARRIER FEEDTHROUGH (dBm)
5
06117-034
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
6
SIDEBAND SUPPRESSION (dBc)
1250
1450
–20
SSB OUTPUT POWER
–30
1050
Figure 19. OIP2 vs. Frequency and Temperature
7
–20
850
LO FREQUENCY (MHz)
LO FREQUENCY (Hz)
–30
15
SIDEBAND
SUPPRESSION (dBc)
–40
5
CARRIER
FEEDTHROUGH (dBm)
–50
–60
0
THIRD ORDER (dBc)
–70
–5
–10
SECOND ORDER (dBc)
–80
–90
–7
BASEBAND FREQUENCY (Hz)
10
SSB OUTPUT POWER
–15
–5
–3
–1
1
3
5
7
–20
LO AMPLITUDE (dBm)
Figure 17. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. fBB and Temperature (fLO = 450 MHz)
Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 450 MHz)
Rev. 0 | Page 8 of 20
SSB OUTPUT POWER (dBm)
THIRD
ORDER = +85°C
TA = –40°C
60
06117-018
THIRD
ORDER = +25°C
1
1450
06117-024
OUTPUT SECOND ORDER INTERCEPT (dBm)
–40
–90
1250
70
–30
–60
1050
Figure 18. OIP3 vs. Frequency and Temperature
06117-016
SECOND AND THIRD ORDER DISTORTION (dBc)
Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 900 MHz)
–50
850
LO FREQUENCY (MHz)
BASEBAND INPUT VOLTAGE (V p-p)
–40
TA = +85°C
06117-023
–30
OUTPUT THIRD ORDER INTERCEPT (dBm)
THIRD ORDER (dBc)
06117-015
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–20
ADL5370
16
12
–5
–3
–1
1
3
5
7
–20
06117-036
–158.6
–90
–7
0
–158.8
–15
–159.0
–80
2
–159.2
–10
–159.4
–70
4
–159.6
SECOND ORDER (dBc)
6
–159.8
–5
–160.0
SIDEBAND SUPPRESSION (dBc)
–160.2
THIRD ORDER (dBc)
–60
8
–160.4
0
10
–160.6
5
CARRIER FEEDTHROUGH (dBm)
–160.8
–50
SSB OUTPUT POWER (dBm)
SSB OUTPUT POWER
–40
–161.0
10
–161.2
–30
–161.4
15
QUANTITY
–20
06117-019
SECOND ORDER DISTORTION, THIRD ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
FLO = 450MHz
14
NOISE (dBm/Hz) AT 20MHz OFFSET
LO AMPLITUDE (dBm)
Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 900 MHz)
0.23
0.22
VS = 5V
0.20
VS = 4.75V
0.19
0.18
0.17
0.16
0.15
–40
06117-020
SUPPLY CURRENT (A)
VS = 5.25V
0.21
25
TEMPERATURE (°C)
85
Figure 22. Power Supply Current vs. Temperature
Rev. 0 | Page 9 of 20
Figure 23. 20 MHz Offset Noise Floor Distribution at fLO = 450 MHz
(I/Q Amplitude = 0 mV p-p with 500 mV dc bias)
ADL5370
THEORY OF OPERATION
CIRCUIT DESCRIPTION
V-to-I Converter
Overview
The differential baseband inputs (QBBP, QBBN, IBBN, IBBP)
consist of the bases of PNP transistors, which present a high
impedance. The voltages applied to these pins drive the V-to-I
stage that converts baseband voltages into currents. The differential
output currents of the V-to-I stages feed each of their respective
Gilbert-cell mixers. The dc common-mode voltage at the baseband
inputs sets the currents in the two mixer cores. Varying the
baseband common-mode voltage varies the current in the mixer
and affects overall modulator performance. The recommended
dc voltage for the baseband common-mode voltage is 500 mV dc.
The ADL5370 can be divided into five circuit blocks: the local
oscillator (LO) interface, the baseband voltage-to-current(V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 24.
LOIP
LOIN
PHASE
SPLITTER
Mixers
The ADL5370 has two double-balanced mixers: one for the inphase channel (I channel) and one for the quadrature channel
(Q channel). Both mixers are based on the Gilbert-cell design of
four cross-connected transistors. The output currents from the
two mixers sum together into a load. The signal developed
across this load is used to drive the D-to-S amplifier.
IBBP
IBBN
OUT
06117-032
Σ
QBBP
QBBN
Figure 24. Block Diagram
The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I and Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the differential-to-single-ended amplifier, which
provides a 50 Ω output interface. The bias cell generates
reference currents for the V-to-I stage and the D-to-S amplifier.
LO Interface
The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. The LO can be driven either single-ended or
differentially. When driven single-ended, the LOIN pin should
be ac-grounded via a capacitor. Each quadrature LO signal then
passes through a limiting amplifier that provides the mixer with
a limited drive signal.
D-to-S Amplifier
The output D-to-S amplifier consists of a totem pole output
stage. The 50 Ω output impedance is established by an on-chip
resistor. The D-to-S output is internally dc-biased and should be
ac-coupled at its output (VOUT).
Bias Circuit
An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage and a temperature independent current for
the D-to-S output stage.
Rev. 0 | Page 10 of 20
ADL5370
BASIC CONNECTIONS
Baseband Inputs
Figure 25 shows the basic connections for the ADL5370.
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
IBBP
The dc common-mode bias level for the baseband inputs may
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5370 input range and on the top end by the output compliance
range on most digital-to-analog converters (DAC) from Analog
Devices.
IBBP
C16
0.1µF
19
COM4
IBBN
20
COM4
IBBN
21
22
23
24
QBBN
QBBN
QBBP
QBBP
1
COM1
2
VPS1
3
VPS1
4
VPS1
5
VPS1
18
Z1
ADL5370
17
16
VPS5
VPS4
VPS2
15
VPS2
14
EXPOSED PADDLE
6
C12
0.1µF
13
VOUT
VPOS
GND
CLOP
100pF
C11
OPEN
VOUT
12
C13
0.1µF
COM3
11
COM3
9
8
10
COM2
LOIN
LOIP
COM2
7
COUT
100pF
LO Input
C14
0.1µF
VPS3
06117-033
VPOS
C15
0.1µF
COM1
CLON
100pF
LO
Figure 25. Basic Connections for the ADL5370
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Analog Devices AN-772 application note
discusses the thermal and electrical grounding of the
LFCSP_VQ in greater detail.
A single-ended LO signal should be applied to the LOIP pin
through an ac-coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 7 dBm
to realize an improvement in the noise performance of the
modulator. This improvement is tempered by degradation in
the sideband suppression performance (see Figure 20) and,
therefore, should be used judiciously. If the LO source cannot
provide the 0 dBm level, then operation at a reduced power
below 0 dBm is acceptable. Reduced LO drive results in slightly
increased modulator noise. The effect of LO power on sideband
suppression and carrier feedthrough is shown in Figure 20. The
effect of LO power on GSM noise is shown in Figure 35.
RF Output
The RF output is available at the VOUT pin (Pin 13). This pin
must also be ac-coupled. The VOUT pin has a nominal
broadband impedance of 50 Ω and does not need further
external matching.
Rev. 0 | Page 11 of 20
ADL5370
OPTIMIZATION
The carrier feedthrough and sideband suppression performance
of the ADL5370 can be improved through the use of optimization techniques.
It is often desirable to perform a one-time carrier null calibration. This is usually performed at a single frequency. Figure 27
shows how carrier feedthrough varies with LO frequency over a
range of ±50 MHz on either side of a null at 450 MHz.
–25
Carrier Feedthrough Nulling
–60
–35
–40
–45
–50
–55
–60
–65
–70
–75
06117-028
CARRIER FEEDTHROUGH (dBm)
–30
Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN) are
equal to zero, and this results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero; and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5370 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (VIOPP − VIOPN)
and (VQOPP − VQOPN) offsets. The I-channel offset is held constant
while the Q-channel offset is varied, until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant while the offset on the Ichannel is adjusted, until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 26 shows the relationship of carrier feedthrough vs. dc
offset as null.
–80
–85
400
410
420
430
440
450
460
470
480
490
500
LO FREQUENCY (MHz)
Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 450 MHz
Sideband Suppression Optimization
Sideband suppression results from relative gain and relative
phase offsets between the I and Q channels and can be
suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by the
gain and phase imbalances.
0
–10
–72
–76
–80
–88
–300 –240 –180 –120
06117-027
–84
–60
0
60
120
180
240
300
The same applies to the Q channel.
–70
0dB
0.1
1
10
100
PHASE ERROR (Degrees)
Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied
VIOPP = 500 mV + VIOS/2, and
VIOPN = 500 mV − VIOS/2, such that
VIOPP − VIOPN = VIOS
–50 0.05dB
0.025dB
–60 0.0125dB
–90
0.01
Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz
When an offset of +VIOS is applied to the I-channel inputs
–30 0.5dB
0.25dB
–40 0.125dB
–80
VP –VN OFFSET (µV)
VIOPP = VIOPN = 500 mV, or
VIOPP − VIOPN = VIOS = 0 V
2.5dB
–20 1.25dB
06117-026
–68
SIDEBAND SUPPRESSION (dBc)
CARRIER FEEDTHROUGH (dBm)
–64
Figure 28. Sideband Suppression vs. Quadrature Phase Error for Various
Quadrature Amplitude Offsets
Figure 28 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.
The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.
Rev. 0 | Page 12 of 20
ADL5370
APPLICATIONS INFORMATION
AD9779
OUT1_P
The ADL5370 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.
AD9779
OUT1_N
ADL5370
19
IBBP
RBIP
50Ω
OUT2_N
OUT2_P
RBIN
50Ω
84
RBQN
50Ω
RBQP
50Ω
83
RSLI
100Ω
RBIN
50Ω
20
84
23
RBQN
50Ω
RBQP
50Ω
83
IBBN
QBBN
RSLQ
100Ω
24
QBBP
Figure 30. AC Voltage Swing Reduction Through the Introduction
of a Shunt Resistor Between Differential Pair
The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing. Figure 31 shows the
relationship between the swing-limiting resistor and the peakto-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.
2.0
20
23
24
1.8
IBBN
QBBN
QBBP
06117-029
OUT1_N
92
OUT2_P
92
IBBP
Figure 29. Interface Between the AD9779 and ADL5370 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5370 Baseband Inputs
The AD9779 output currents have a swing that ranges from 0 mA
to 20 mA. With the 50 Ω resistors in place, the ac voltage swing
going into the ADL5370 baseband inputs ranges from 0 V to 1 V.
A full-scale sine wave out of the AD9779 can be described as a
1 V p-p single-ended (or 2 V p-p differential) sine wave with a
500 mV dc bias.
LIMITING THE AC SWING
There are situations in which it is desirable to reduce the ac
voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the interface.
This resistor is placed in shunt between each side of the
differential pair, as shown in Figure 30. It has the effect of
reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
06117-025
93
OUT2_N
DIFFERENTIAL SWING (V p-p)
OUT1_P
19
RBIP
50Ω
Driving the ADL5370 with an Analog Devices TxDAC®
An example of the interface using the AD9779 TxDAC is shown
in Figure 31. The baseband inputs of the ADL5370 require a dc
bias of 500 mV. The average output current on each of the
outputs of the AD9779 is 10 mA. Therefore, a single 50 Ω
resistor to ground from each of the DAC outputs results in an
average current of 10 mA flowing through each of the resistors,
thus producing the desired 500 mV dc bias for the inputs to the
ADL5370.
ADL5370
93
06117-030
DAC MODULATOR INTERFACING
0.2
0
10
100
1000
10000
RL (Ω)
Figure 31. Relationship Between the AC Swing-Limiting Resistor and the
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
FILTERING
It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing that was discussed in the Limiting the
AC Swing section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting
resistors and the ac swing-limiting resistor. Doing so establishes
the input and output impedances for the filter.
An example is shown in Figure 32 with a third-order elliptical
filter with a 3 dB frequency of 3 MHz. Matching input and output
impedances makes the filter design easier, so the shunt resistor
chosen is 100 Ω, producing an ac swing of 1 V p-p differential.
Rev. 0 | Page 13 of 20
ADL5370
LNQ
2.7nH
84
RBQP
83 50Ω
1.1nF
C1Q
1.1nF
C2Q
23
–35
IBBN
QBBN
RSLQ
100Ω
24
LPQ
2.7nH
QBBP
Figure 32. DAC Modulator Interface with 3 MHz Third-Order Low-Pass Filter
USING THE AD9779 AUXILIARY DAC FOR CARRIER
FEEDTHROUGH NULLING
The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator. Figure 33 shows the interface required
to utilize the auxiliary DACs. This adds four resistors to the
interface.
AD9779
OUT1_P
OUT1_N
90
500Ω
RBIN
92 50Ω
1.1nF
C1I
1.1nF
C2I
19
IBBP
RSLI
100Ω
LNI
2.7nH
IBBN
500Ω
87
AUX2_N
84
RBQN
50Ω
OUT2_P
AUX2_P
250Ω
RBQP
83 50Ω
86
1.1nF
C1Q
LNQ
2.7nH
1.1nF
C2Q
23
–56
EVMPK (%)
–63
1.0
400kHz
–70
–77
0.5
1200kHz
–84
–91
0
1
2
3
600kHz
4
5
6
7
OUTPUT POWER (dBm)
Figure 35 shows the GSM EVM, spectral mask performance
and 6 MHz offset noise vs. LO amplitude at 450 MHz with an
output power of 6 dBm. Increasing the LO drive level improves
the noise performance but degrades EVM performance.
3.1
LPQ
2.7nH
–49
2.9
EVMPK (%)
250kHz
2.7
–56
2.5
–63
2.3
400kHz
–70
2.1
–77
1.9
600kHz
–84
1.7
–91
1.5
EVMRMS (%)
1200kHz
–98
1.3
–105
–112
–6
RSLQ
100Ω
1.1
6 MHz OFFSET NOISE
–4
–2
0
2
4
6
0.9
LO AMPLITUDE (dBm)
24
250Ω
0
Figure 34. GSM EVM and Spectral Performance vs. Channel Power at
450 MHz vs. Output Power; LO Power = 0 dBm
QBBN
Figure 35. GSM EVM, Spectral Performance, and 6 MHz Noise Floor vs.
LO Power at 450 MHz; Output Power = 6 dBm
QBBP
500Ω
Figure 33. DAC Modulator Interface with Auxiliary DAC Resistors
06117-041
OUT2_N
1.5
–42
89
500Ω
–49
ADL5370
LPI
2.7nH
20
250Ω
AUX1_N
EVMRMS (%)
–35
250Ω
93
RBIP
50Ω
–42
6MHz NOISE (dBc/100kHz)
250kHz, 400kHz, 600kHz AND 1200kHz
SPECTRAL MASK (dBc/30kHz)
AUX1_P
2.0
250kHz
RMS AND PEAK EVM (%)
20
LNI
2.7nH
RBQN
50Ω
OUT2_P
1.1nF
C2I
06117-039
OUT2_N
1.1nF
C1I
RMS AND PEAK EVM (%)
OUT1_N
RBIN
92 50Ω
Figure 34 shows the GSM EVM and spectral mask performance
vs. output power for the ADL5370 at 450 MHz. For a given LO
amplitude, the performance is independent of output power.
IBBP
RSLI
100Ω
Figure 35 illustrates that an LO amplitude of 0 dBm provides
the ideal operating point for noise and EVM for a GSM signal
at 450 MHz.
Rev. 0 | Page 14 of 20
06117-040
RBIP
50Ω
19
250kHz, 400kHz, 600kHz, AND 1200kHz
SPECTRAL MASK (dBc/30KHz)
OUT1_P
GSM OPERATION
ADL5370
LPI
2.7nH
93
06117-031
AD9779
ADL5370
LO GENERATION USING PLLS
TRANSMIT DAC OPTIONS
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with
their maximum frequency and phase noise performance.
The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
ADL5370. There are other appropriate DACs, depending on the
level of performance required. Table 6 lists the dual Tx-DACs
offered by Analog Devices.
Table 4. ADI PLL Selection Table
Part
ADF4110
ADF4111
ADF4112
ADF4113
ADF4116
ADF4117
ADF4118
Frequency FIN (MHz)
550
1200
3000
4000
550
1200
3000
Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)
−91 @ 540 MHz
−87@ 900 MHz
−90 @ 900 MHz
−91 @ 900 MHz
−89 @ 540 MHz
−87 @ 900 MHz
−90 @ 900 MHz
The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One is chosen, depending on the local
oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5370, it can be a cheaper alternative
to a separate PLL and VCO solution. Table 5 shows the options
available.
Table 5. ADF4360 Family Operating Frequencies
Part
ADF4360-0
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
ADF4360-8
Output Frequency Range (MHz)
2400 to 2725
2050 to 2450
1850 to 2150
1600 to 1950
1450 to 1750
1200 to 1400
1050 to 1250
350 to 1800
65 to 400
Table 6. Analog Devices Dual Tx—DAC Selection Table
Part
AD9709
AD9761
AD9763
AD9765
AD9767
AD9773
AD9775
AD9777
AD9776
AD9778
AD9779
Resolution (Bits)
8
10
10
12
14
12
14
16
12
14
16
Update Rate (MSPS Min)
125
40
125
125
125
160
160
160
1000
1000
1000
All DACs listed have nominal bias levels of 0.5 V and use the same
simple DAC-modulator interface that is shown in Figure 31.
MODULATOR/DEMODULATOR OPTIONS
Table 7 lists other Analog Devices modulators and demodulators.
Table 7. Modulator/Demodulator Options
Part
AD8345
AD8346
AD8349
ADL5390
ADL5385
ADL5371
ADL5372
ADL5373
ADL5374
AD8347
AD8348
AD8340
AD8341
Rev. 0 | Page 15 of 20
Mod/Demod
Mod
Mod
Mod
Mod
Mod
Mod
Mod
Mod
Mod
Demod
Demod
Vector mod
Vector mod
Frequency
Range (MHz)
140 to 1000
800 to 2500
700 to 2700
20 to 2400
50 to 2200
700 to 1300
1600 to 2400
2300 to 3000
3000 to 4000
800 to 2700
50 to 1000
700 to 1000
1500 to 2400
Comments
External quadrature
ADL5370
EVALUATION BOARD
Populated RoHS-compliant evaluation boards are available for
evaluation of the ADL5370. The ADL5370 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the Power Supply and Grounding
discussion in the Basic Connections section). The evaluation
board is designed without any components on the underside
so heat can be applied to the underside for easy removal and
replacement of the ADL5370.
IBBN
RFPQ RFNQ CFNQ CFNI
0Ω
0Ω OPEN OPEN
2
VPS1
3
VPS1
4
VPS1
5
VPS1
CFPI
OPEN
IBBP
C16
0.1µF
L12
0Ω
19
COM4
COM4
IBBN
20
21
22
QBBN
23
1
COM1
RFPI
0Ω
18
C15
0.1µF
L11
0Ω
VPS5
VPS4
17
VPS3
16
Z1
ADL5370
C14
0.1µF
VPS2
15
VPS2
14
EXPOSED PADDLE
6
C12
0.1µF
13
VOUT
C11
OPEN
VOUT
12
C13
0.1µF
COM3
COM3
11
10
9
LOIN
8
LOIP
CLOP
100pF
COM2
GND
COM2
7
COUT
100pF
Figure 37. Evaluation Board Layout, Top Layer.
06117-021
VPOS
COM1
RFNI
0Ω
RTI
OPEN
24
QBBP
RTQ
CFPQ OPEN
OPEN
IBBP
06117-022
QBBN
VPOS
QBBP
CLON
100pF
LO
Figure 36. ADL5370 Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component
VPOS, GND
RFPI, RFNI, RFPQ, RFNQ, CFPI,
CFNI, CFPQ, CFNQ, RTQ, RTI
Description
Power Supply and Ground Clip Leads.
Baseband Input Filters. These components can be used
to implement a low-pass filter for the baseband signals.
See the Filtering discussion in the Applications
Information section.
Rev. 0 | Page 16 of 20
Default Condition
Not applicable
RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = Open (0402)
RTQ, RTI = Open (0402)
ADL5370
CHARACTERIZATION SETUP
AEROFLEX IFR 3416
250kHz TO 6GHz SIGNAL GENERATOR
R AND S SPECTRUM ANALYZER
FSU 20Hz TO 8GHz
RF
OUT
FREQ 4MHz LEVEL 0dBm
BIAS 0.5V GAIN 0.7V
BIAS 0.5V GAIN 0.7V
LO
CONNECT TO BACK OF UNIT
I OUT I/AM Q OUT Q/FM
90°
I
+6dBm
RF
IN
0°
Q
AGILENT 34401A
MULTIMETER
FMOD TEST SETUP
0.175 ADC
IP
VPOS +5V
LO
IN
QP
AGILENT E3631A
POWER SUPPLY
–
OUTPUT
VPOS GND
0.175A
6V
OUT
QN
±25V
+ COM –
06117-037
5.000
+
FMOD
Figure 38. Characterization Bench Setup
The primary setup used to characterize the ADL5370 is shown
in Figure 38. This setup was used to evaluate the product as a
single-sideband modulator. The Aeroflex signal generator supplied
the local oscillator (LO) and differential I and Q baseband
signals to the device under test, DUT. The typical LO drive was
0 dBm. The I channel is driven by a sine wave, and the Q channel
is driven by a cosine wave. The lower sideband is the single
sideband (SSB) output.
The majority of characterization for the ADL5370 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the VIOS1 and VQOS
offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT.
1
See the Carrier Feedthrough Nulling section for the definitions of VIOS
and VQOS.
Rev. 0 | Page 17 of 20
ADL5370
CH1 1MHz
AMPL 700mV p-p
PHASE 0°
CH2 1MHz
AMPL 700mV p-p
PHASE 90°
0°
R AND S SMT 06
SIGNAL GENERATOR
CH2 OUTPUT
CH1 OUTPUT
TEKTRONIX AFG3252
DUAL FUNCTION
ARBITRARY FUNCTION GENERATOR
I Q
RF
OUT
FREQ 4MHz TO 4GHz
LEVEL 0dBm
LO
90°
SINGLE TO DIFFERENTIAL
CIRCUIT BOARD
AGILENT E3631A
POWER SUPPLY
FMOD TEST RACK
5.000
0.350A
Q IN AC
±25V
6V
VPOS ++5V–
+5V
VPOS +5V
FMOD
CHAR BD
Q IN DCCM
+ COM –
IP
IP
VPOSB VPOSA IN
IN
TSEN
–5V
GND
AGND IN1
IN1
VN1
VP1
I IN DCCM
I IN AC
QP
QP
OUTPUT
OUT
QN
GND
VPOS
QN
AGILENT E3631A
POWER SUPPLY
0.500
LO
R AND S FSEA 30
SPECTRUM ANALYZER
0.010A
+
6V
RF
IN
±25V
–
+ COM –
100MHz TO 4GHz
+6dBm
VCM = 0.5V
06117-038
AGILENT 34401A
MULTIMETER
0.200 ADC
Figure 39. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling
The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5370 is shown in Figure 39.
The interface board has circuitry that converts the single-ended
I and Q inputs from the arbitrary function generator to differential I and Q baseband signals with a dc bias of 500 mV.
Undesired sideband nulling was achieved through an iterative
process of adjusting amplitude and phase on the Q channel.
See Sideband Suppression Optimization in the Optimization
section for a more detailed discussion on sideband nulling.
Rev. 0 | Page 18 of 20
ADL5370
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
0.50
BSC
3.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
PIN 1
INDICATOR
19
18
24 1
*2.45
EXPOSED
PAD
2.30 SQ
2.15
(BOTTOMVIEW)
13
12
7
6
0.23 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5370ACPZ-R21
ADL5370ACPZ-R7 1
ADL5370ACPZ-WP1
ADL5370-EVALZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead LFCSP_VQ, 7” Tape and Reel
24-Lead LFCSP_VQ, 7” Tape and Reel
24-Lead LFCSP_VQ, Waffle Pack
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 19 of 20
Package Option
CP-24-2
CP-24-2
CP-24-2
Ordering Quantity
250
1,500
64
ADL5370
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06117-0-10/06(0)
Rev. 0 | Page 20 of 20