a AC ’97 SoundMAX Codec AD1888 ® FEATURES AC ’97 2.3 COMPATIBLE FEATURES 6 DAC Channels for 5.1 Surround 90 dB Dynamic Range 20-Bit PCM DACs S/PDIF Output Integrated Stereo Headphone Amplifiers Phone, Aux, and Line-In High Quality CD Input Selectable MIC Input Mono Output External Amplifier Power-Down Control Double Rate Audio (fS = 96 kHz) Power Management Modes 48-Lead LQFP and 48-Lead LFCSP Packages ENHANCED FEATURES Selectable Front and Rear MIC Inputs with Preamp Integrated PLL for System Clocking Crystal-Free Operation Variable Sample Rate 7 kHz to 96 kHz Jack Sense (Auto Topology Switching) Software Controlled VREF_OUT for MIC Bias Software Enabled Outputs for Jack Sharing Auto Down-Mix and Channel Spreading Modes FUNCTIONAL BLOCK DIAGRAM XTAL_IN AD1888 MIC1 MIC2 G XTAL_OUT PHONE_IN PLL CD_L DIFF AMP CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R G G M 16-BIT ⌺-⌬ ADC M 16-BIT ⌺-⌬ ADC ADC SLOT LOGIC ID0 GA M GA MONO_OUT M A M LINE_OUT_L MZ LINE_OUT_R MZ GA GA M GA M GA M AC '97 CONTROL REGISTERS GA GA GA M M M DAC SLOT LOGIC M GA 20-BIT ⌺-⌬ DAC M GA 20-BIT ⌺-⌬ DAC M GA 20-BIT ⌺-⌬ DAC M GA 20-BIT ⌺-⌬ DAC A M MZ A LFE_OUT MZ A SURR_L/ HP_OUT_L HP M A SURR_R/ HP_OUT_R HP M A M M M M RESET SYNC BIT_CLK SDATA_OUT M A CENTER_OUT AC '97 INTERFACE ID1 M G = GAIN A = ATTENUATION M = MUTE Z = HIGH-Z SDATA_IN SPDIF TX SPDIF_OUT EAPD EAPD JACK SENSE LOGIC VOLTAGE REFERENCE M GA 20-BIT ⌺-⌬ DAC M GA 20-BIT ⌺-⌬ DAC JS0 JS1 VREF VREFOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD1888–SPECIFICATIONS STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (fS) Input Signal Analog Output Pass Band DAC Test Conditions Calibrated –3 dB Attenuation Relative to Full Scale 0 dB Input 10 kΩ Output Load LINE_OUT, MONO_OUT, CENTER_OUT, and LFE_OUT 32 Ω Output Load (HP_OUT) 25°C 3.3 V 5.0 V 48 kHz 1 kHz 20 Hz to 20 kHz ADC Test Conditions Calibrated 0 dB Gain Input –3.0 dB Relative to Full Scale Parameter Min ANALOG INPUT Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, CD, AUX, PHONE_IN Typ 1 2.83 0.032 0.089 0.1 0.283 0.316 0.894 1 2.83 20 5 MIC_IN with 30 dB Preamp MIC_IN with 20 dB Preamp MIC_IN with 10 dB Preamp MIC_IN with 0 dB Gain Input Impedance* Input Capacitance* MASTER VOLUME Step Size (Line Out, Mono Out, Surround Out, Center, LFE) Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental* Max Unit 7.5 V rms V p-p V rms V p-p V rms V p-p V rms V p-p V rms V p-p kΩ pF 80 dB dB dB 1.5 46.5 PROGRAMMABLE GAIN AMPLIFIER—ADC Step Size (0 dB to 22.5 dB) PGA Gain Range Span 1.5 22.5 dB dB ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT LINE, AUX, or PHONE to LINE_OUT* MIC1 or MIC2 (Note: MIC Gain of 0 dB) to LINE_OUT* Step Size All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs 90 90 90 1.5 46.5 dB dB dB dB dB DIGITAL DECIMATION AND INTERPOLATION FILTERS* Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band –2– 0.4 fS ± 0.09 0.6 fS 0 0.4 fS 0.6 fS –74 16/fS 0 Hz dB Hz Hz dB sec µs REV. 0 AD1888 Parameter Min ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) AVDD = 5.0 V Dynamic Range (–60 dB Input THD + N Referenced to FS, A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error* (0 dB Gain, HPF On) DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD), LINE_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), HP_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), CENTER/LFE, AVDD = 5.0 V Dynamic Range (–60 dB Input THD + N Referenced to FS A-Weighted) AVDD = 5.0 V, All Outputs Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Read LINE_OUT_R; Input R, Zero L, Read LINE_OUT_L, 10 kΩ Load)* Total Audible Out-of-Band Energy* (Measured from 0.6 fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT/MONO_OUT, CENTER_OUT, LFE_OUT Output Impedance* External Load Impedance* (LINE_OUT, CENTER_OUT/LFE_OUT, MONO_OUT) Output Capacitance* External Load Capacitance* Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance*; HP_OUT VREF VREF_OUT (VREFH = 0) VREF_OUT (VREFH = 1) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current 80 84 dB dB –85 –85 ± 10 ± 0.5 ± 10 dB dB % dB mV 20 –80 –70 –80 Bits dB dB dB 90 88 ± 10 ± 0.7 –80 dB dB % dB dB –40 dB 1 2.83 300 V rms V p-p Ω 10 15 100 1 32 2.05 –3– Unit Bits dB 2.25 2.25 3.65 2.45 5 ±5 0.35 DVDD 0.9 DVDD *Guaranteed but not tested. Specifications subject to change without notice. Max 16 –78 0.65 DVDD POWER SUPPLY Power Supply Range, Analog (AVDD) Power Supply Range, Digital (DVDD) Power Dissipation 5 V/3.3 V Analog Supply Current 5 V (AVDD) Digital Supply Current 3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) REV. 0 Typ –10 –10 0.1 DVDD +10 +10 4.75 3.15 5.25 3.45 kΩ pF pF V rms Ω V V V mA mV V V V V µA µA 563 70 53 V V mW mA mA –40 dB AD1888 Parameter PR[K:I]1 PR[6:0]1 DVDD Typ AVDD Typ Unit 000 000 000 010 101 111 000 000 111 111 111 000 000 0000 000 0001 000 0010 000 0000 000 0000 000 0011 000 0100 000 0101 000 0110 000 0111 011 1111 100 0000 53 44 46 46 46 12 52 45 31 12 0 52 70 66 61 61 61 33 44 39 14 8 0 65 mA mA mA mA mA mA mA mA mA mA mA mA 2 POWER-DOWN STATES Fully Active ADC FRONT DAC SURROUND DAC CENTER/LFE DAC ADC + ALL DACs Mixer ADC + Mixer ALL DACs + Mixer ADC + ALL DACs + Mixer Standby Headphone Standby NOTES 1 PR bits are controlled in Reg. 2Ah and 26h 2 Values presented with V REFOUT loaded. Specifications subject to change without notice. Parameter CLOCK SPECIFICATIONS* Input Clock Frequency (XTAL Mode or Clock Oscillator) Input Clock Frequency (Reference Clock Mode) Input Clock Frequency (USB Clock Mode) Recommended Clock Duty Cycle Min Typ 40 24.576 14.31818 48.000 50 Max Unit 60 MHz MHz MHz % *Guaranteed but not tested. Specifications subject to change without notice. TIMING PARAMETERS (Guaranteed over Operating Temperature Range) Parameter Symbol RESET Active Low Pulse Width RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulse Width SYNC Low Pulse Width SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2 BIT_CLK High Pulse Width BIT_CLK Low Pulse Width SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to RESET Inactive (SYNC, SDATA_OUT) Rising Edge of RESET to Hi-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from BIT_CLK Rising tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK Min Typ 1.0 162.8 400,000 1.3 19.5 162.8 12.288 tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF 1.0 81.4 750 tCLK_PERIOD tCLK_HIGH tCLK_LOW Max 40 39.7 41.7 41.4 48.0 20.8 4 3 2 2 2 2 2 2 2 2 0 15 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 1.0 25 15 50 15 Unit µs ns µs µs ns MHz ppm ns ps ns ns kHz µs ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns NOTES 1 Guaranteed but not tested. 2 Output jitter directly dependent on crystal input jitter. Specifications subject to change without notice. –4– REV. 0 AD1888 tRST2CLK tRST_LOW RESET tTRI2ACTV BIT_CLK tTRI2ACTV SDATA_IN Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal) tSYNC_HIGH tSYNC2CLK SYNC BIT_CLK Figure 2. Warm Reset Timing tCLK_LOW SLOT 1 SLOT 2 WRITE TO 0x26 DATA PR4 SYNC BIT_CLK tCLK_HIGH BIT_CLK tCLK_PERIOD SDATA_OUT tSYNC_LOW tS2_PDOWN SDATA_IN SYNC BIT_CLK NOT TO SCALE tSYNC_HIGH tSYNC_PERIOD Figure 5. AC-Link Low Power Mode Timing Figure 3. Clock Timing tCO tSETUP BIT_CLK tRISECLK tFALLCLK BIT_CLK SYNC VIH VIL SDATA_OUT tRISESYNC VOH SDATA_IN tFALLSYNC VOL SYNC tHOLD SDATA_IN tRISEDIN Figure 6. AC-Link Low Power Mode Timing tFALLDIN RESET SDATA_OUT tRISEDOUT tFALLDOUT SDATA_OUT tSETUP2RST Figure 4. Signal Rise and Fall Times SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O Hi-Z tOFF Figure 7. ATE Test Mode REV. 0 –5– AD1888 ENVIRONMENTAL CONDITIONS* ABSOLUTE MAXIMUM RATINGS* Parameter Power Supplies Digital (DVDD) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min Max Unit –0.3 –0.3 +3.6 +6.0 ± 10.0 AVDD + 0.3 DVDD + 0.3 +70 +150 V V mA V V °C °C –0.3 –0.3 0 –65 Ambient Temperature Rating TCASE = Case Temperature in °C PD = Power Dissipation in W JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package θJA θJC LQFP LFCSP 50.1°C/W 50°C/W 17.8°C/W 25.88°C/W *All measurements per EIA/JESD51 with 2S2P test board per EIA/JESD51-7. ORDERING GUIDE Model Temperature Range Package Description Package Option AD1888JST AD1888JST-REEL AD1888JSTZ* AD1888JSTZ-REEL* AD1888JCP AD1888JCP-REEL 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 48-Lead LQFP, Tray Version 48-Lead LQFP, Reel Version 48-Lead LQFP, Tray Version 48-Lead LQFP, Reel Version 48-Lead LFCSP, Tray Version 48-Lead LFCSP, Reel Version ST-48 ST-48 ST-48 ST-48 CP-48 CP-48 *Z = Lead Free CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1888 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. 0 AD1888 DVDD1 SPDIF EAPD ID1 ID0 AVSS3 AVDD3 NC SURR_OUT_R/HP_OUT_R AVSS2 SURR_OUT_L/HP_OUT_L AVDD2 MONO_OUT PIN CONFIGURATION 48-Lead LQFP 48 47 46 45 44 43 42 41 40 39 38 37 1 36 LINE_OUT_R (FRONT_R) XTL_IN 2 35 LINE_OUT_L (FRONT_L) XTL_OUT 3 34 AVDD4 DVSS1 4 33 AVSS4 SDATA_OUT 5 BIT_CLK 6 AD1888 DVSS2 7 TOP VIEW (Not to Scale) 32 LFE_OUT 31 CENTER_OUT 30 AFILT2 SDATA_IN 8 DVDD2 29 AFILT1 28 VREFOUT 9 27 VREF SYNC 10 14 15 16 17 18 19 20 21 22 23 24 JS0 CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R PHONE_IN 13 NC = NO CONNECT JS1 25 AVDD1 AUX_R 26 AVSS1 NC 12 AUX_L RESET 11 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic I/O Function DIGITAL INPUT/OUTPUT 2 XTL_IN I 3 5 6 XTL_OUT SDATA_OUT BIT_CLK O I O/I 8 10 11 48 SDATA_IN SYNC RESET SPDIF O I I O Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz, or 48000 MHz). Crystal Output. AC-Link Serial Data Output. AD1888 input stream. AC-Link Bit Clock. 12.288 MHz serial data clock. (Input pin for Secondary mode only.) AC-Link Serial Data Input. AD1888 output stream. AC-Link Frame Sync. AC-Link Reset. AD1888 master H/W reset. SPDIF Output. I I Chip Select Input 0 (Active Low). Chip Select Input 1 (Active Low). O I I EAPD Output. Jack Sense 0 Input. Jack Sense 1 Input. CHIP SELECTS/CLOCK STRAPPING 45 46 ID0 ID1 JACK SENSE AND EAPD 47 17 16 REV. 0 EAPD JS0 JS1 –7– AD1888 Pin Number Mnemonic I/O Function PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R CENTER_OUT LFE_OUT LINE_OUT_L LINE_OUT_R MONO_OUT SURR_OUT_L/HP_OUT_L SURR_OUT_R/HP_OUT_R I I I I I I I I I I O O O O O O O Monaural Line-Level Input. Auxiliary Input, Left Channel. Auxiliary Input, Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Rear Panel MIC Input. Front Panel MIC Input. Line-In Left Channel. Line-In Right Channel. Center Channel Output. Low Frequency Enhanced Output. Line Out (Front) Left Channel. Line Out (Front) Right Channel. Monaural Output to Telephone Subsystem Speakerphone. Surround Front Headphone Left Channel Output. Surround Front Headphone Right Channel Output. VREF VREFOUT AFILT1 AFILT2 O O O O Voltage Reference Filter. Voltage Reference Output 5 mA Drive (intended for MIC bias). Antialiasing Filter Capacitor—ADC Right Channel. Antialiasing Filter Capacitor—ADC Left Channel. I I I I I I I I I I I I Digital VDD 3.3 V. Digital GND. Digital GND. Digital VDD 3.3 V. Analog VDD 5.0 V. Analog GND. Analog GND. Analog VDD 5.0 V. Analog VDD 5.0 V. Analog GND. Analog VDD 5.0 V. Analog GND. ANALOG INPUT/OUTPUT 13 14 15 18 19 20 21 22 23 24 31 32 35 36 37 39 41 FILTER/REFERENCE 27 28 29 30 POWER AND GROUND SIGNALS 1 DVDD1 4 DVSS1 7 DVSS2 9 DVDD2 25 AVDD1 26 AVSS1 33 AVSS4 34 AVDD4 38 AVDD2 40 AVSS2 43 AVDD3 44 AVSS3 NO CONNECTS 12 42 NC NC No Connect. No Connect. –8– REV. 0 AD1888 Indexed Control Registers Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h 02h Master Volume MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM* X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h 04h Headphone Volume HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 HPRM* X RHV5 RHV4 RHV3 RHV2 RHV1 8000h 06h Mono Volume MVM X X X X X X X X X MV5 MV4 MV2 MV2 MV1 MV0 8000h 0Ch Phone Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 8008h 0Eh MIC Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h 10h Line-In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 LVRM* X X RLV4 8808h RLV3 RLV2 RLV1 RHV0 RLV0 12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 CDRM* X X RCV4 RCV3 RCV2 RCV1 RCV0 8808h 16h AUX Volume AVM X X LAV4 LAV3 LAV2 LAV1 LAV0 AVRM* X X RAV4 RAV3 RAV2 RAV1 RAV0 8808h 18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOV1 LOV0 OMRM* X X ROV4 ROV3 ROV2 ROV1 ROV0 8808h 1Ah Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h 1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 IMRM* X X X RIM3 RIM2 RIM1 RIM0 8000h 20h General-Purpose X X X X DRSS1 DRSS0 X MS LPBK X X X X X X X 0000h 24h Audio Int. and Paging I4 X X X I0 X X X X X X X PG3 PG2 PG1 PG0 xxxxh 26h Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC NA 28h Ext’d Audio ID ID1 ID0 X X REV1 REV0 AMAP LDAC SDAC CDAC DSA1 DSA0 X SPDIF DRA VRA 2Ah Ext’d Audio Stat/Ctrl VFORCE X PRK PRJ PRI SPCV X ELDAC ESDAC ECDAC SPSA1 SPSA0 X ESPDIF EDRA EVRA 0xx0h 2Ch PCM Front DAC Rate SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h 2Eh PCM Surr DAC Rate SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 BB80h 30h PCM C/LFE DAC Rate SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 BB80h 32h PCM L/R ADC Rate SRA15 SRA14 SRA13 SRA13 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 BB80h 36h Center/LFE Volume LM X LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 CM X CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 38h Surround Volume MUTE_L X LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 MUTE_R X RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 8080h 3Ah SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h 72h JACK SENSE JS1 SPRD JS1 DMX JS0 DMX JS MT2 JS MT1 JS MT0 X X JS1 TMR JS0 TMR JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0000h 74h Serial Configuration SLOT 16 REGM2 REGM1 REGM0 REGM3 DRF X CHEN X LBKS1 LBKS0 INTS X SPAL SPDZ SPLNK 1001h 76h Misc Control Bits DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD X LOSEL SRU VREFH VREFD MBG1 MBG0 0000h 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5368h SRA4 SRA3 SRA2 SRA1 SRA0 NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written to. Zeros should be written to reserved bits. *For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. REV. 0 –9– x3C7h 8080h AD1888 Reset Register (Index 00h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h NOTES All registers not shown and bits containing an X are assumed to be reserved. Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following: Bit = 1 Function AD1888 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Dedicated Mic PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution 0 0 0 0 1 0 0 1 0 0 SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.) Master Volume Register (Index 02h) Reg No. 02h Name D15 Master MM Volume D14 D131 X D12 D11 D10 D9 D8 D6 D51 D7 2 LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM X D4 D3 D2 D1 D0 Default RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h NOTES 1 Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1. 2 For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: For AC97NC = 0, the register controls the Line_out output Attenuators only. For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators. RMV[5:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. MMRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM bit. Otherwise this bit will always read 0 and will have no effect when set to 1. LMV[5:0] Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. MM Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1. –10– REV. 0 AD1888 Headphones Volume Register (Index 04h) Reg No. Name D15 D14 D13 04h HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 HPRM* X Headphones Volume D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 RHV5 RHV4 RHV3 RHV2 D1 D0 Default RHV1 RHV0 8000h *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. Table I. Volume Settings for Master and Headphone Control Bits Master Volume (02h) and Headphone Volume (04h) Reg. 76h Left Channel Volume D[13:8] Right Channel Volume D[5:0] MSPLT* D15 WRITE READBACK Function D7* WRITE READBACK Function 0 0 00 0000 00 0000 0 dB Gain x 00 0000 00 0000 0 dB Gain 0 0 00 1111 00 1111 –22.5 dB Gain x 00 1111 00 1111 –22.5 dB Gain 0 0 01 1111 01 1111 –46.5 dB Gain x 01 1111 01 1111 –46.5 dB Gain 0 0 1x xxxx 01 1111 –46.5 dB Gain x 1x xxxx 01 1111 –46.5 dB Gain 0 1 xx xxxx xx xxxx – dB Gain, Muted x xx xxxx xx xxxx – dB Gain, Muted 1 0 1x xxxx 01 1111 –46.5 dB Gain 1 xx xxxx xx xxxx – dB Gain, only Right Muted 1 1 xx xxxx xx xxxx – dB Gain, Left only Muted 0 xx xxxx xx xxxx –46.5 dB Gain 1 1 xx xxxx xx xxxx – dB Gain, Left Muted 1 xx xxxx xx xxxx – dB Gain, Right Muted *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. x in the above table is “don’t care.” Mono Volume Register (Index 06h) Reg No. Name 06h D15 Mono Volume MVM D14 D13 D12 D11 D10 D9 D8 D7 D6 D5* D4 D3 D2 D1 D0 Default X X X X X X X X MV5 MV4 MV3 MV2 MV1 MV0 8000h X *Refer to Table II for examples. This register controls the Mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1. All registers not shown and bits containing an X are assumed to be reserved. MV[5:0] Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. MVM Mono Volume Mute. When this bit is set to 1, the channel is muted. Table II. Volume Settings for Mono Control Bits D[4:0] for Mono (06h) D15 WRITE READBACK Function 0 0 0 1 0 0000 0 1111 1 1111 x xxxx 0 0000 0 1111 1 1111 x xxxx 0 dB Gain –22.5 dB Gain –46.5 dB Gain – dB Gain, Muted x in the above table is a wild card and has no effect on the value. REV. 0 –11– AD1888 Phone_in Volume Register (Index 0Ch) Reg No. Name D15 D14 D13 0Ch Phone_in Volume PHM X X D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 Default 8008h All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples. PHV[4:0] Phone Volume. Allows setting the Phone Volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute bit enabled. PHM Phone Mute. When this bit is set to 1, the Phone channel is muted. MIC Volume Register (Index 0Eh) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0Eh MIC Volume MCM X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h X D0 Default All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples. MCV[4:0] MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with mute enabled. M20 MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB; however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 dB or 30 dB, if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1) MCM MIC Mute. When this bit is set to 1, the channel is muted. Table III. Volume Settings for Phone and MIC Control Bits D[4:0] Phone (0Ch) and MIC (0Eh) D15 WRITE READBACK Function 0 0 0 1 0 0000 0 1000 1 1111 x xxxx 0 0000 0 1000 1 1111 x xxxx 12 dB Gain 0 dB Gain –34.5 dB Gain – dB Gain, Muted x in the above table is a wild card, and has no effect on the value. –12– REV. 0 AD1888 Line-In Volume Register (Index 10h) Reg No. Name D15 10h Line-In Volume LVM D14 D13 D12 X X D11 LLV4 LLV3 D10 D9 D8 LLV2 LLV1 LLV0 D7 D6 D5 D4 LVRM* X X D3 RLV4 RLV3 D2 D1 D0 Default RLV2 RLV1 RLV0 8808h *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RLV[4:0] Right Line-In Volume. Allows setting the Line-In Right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to –34.d dB. The default value is 0 dB, mute enabled. LVRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the LIM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. LLV[4:0] Left Line-In Volume. Allows setting the Line-In left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LVM Line-In Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will only affect the left channel. CD Volume Register (Index 12h) Reg No. Name D15 12h CD Volume CVM X D14 D13 D12 X D11 D10 D9 D8 D7 D6 D5 D4 LCV4 LCV3 LCV2 LCV1 LCV0 CDRM* X X D3 RCV4 RCV3 D2 D1 D0 Default RCV2 RCV1 RCV0 8808h *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RCV[4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. CDRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the Right channel separately from the CVM bit. Otherwise this bit will always read 0 and will have no effect when set to 1. LCV[4:0] Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to –24.5 dB. The default value is 0 dB, mute enabled. CVM CD Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel. AUX Volume Register (Index 16h) Reg No. Name D15 D14 D13 D12 16h AUX Volume AVM X X D11 D10 LAV4 LAV3 LAV2 D9 D8 D7 D6 LAV1 LAV0 AVRM* X D5 D4 D3 D2 D1 D0 Default X RAV4 RAV3 RAV2 RAV1 RAV0 8808h *For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RAV[4:0] Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. AVRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. LAV[4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. AVM PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel. REV. 0 –13– AD1888 PCM-Out Volume Register (Index 18h) Reg No. Name D15 D14 D13 D12 18h PCM Out Volume OM X X D11 D10 LOV4 LOV3 LOV2 D9 D8 D7 D6 D5 D4 LOV1 LOV0 OMRM* X X ROV4 D3 D2 D1 D0 Default ROV3 ROV2 ROV1 ROV0 8808h *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality: For AC97NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators. For AC97NC = 1, the register controls the PCM Out Volume only. ROV[4:0] Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. OMRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. LOV[4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. OM PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel. Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out Control Bits Line-In (10h), CD (12h), AUX (16h) and PCM-Out (18h) Reg. 76h Left Channel Volume D[12:8] Right Channel Volume D[4:0] MSPLT* D15 WRITE READBACK Function D7* WRITE READBACK Function 0 0 0 0 1 0 0 0 1 0 0 0000 0 1000 1 1111 x xxxx 1 1111 0 0000 0 1000 1 1111 x xxxx 1 1111 12 dB Gain 0 dB Gain –34.5 dB Gain – dB Gain, Muted –34.5 dB Gain x x x x 1 0 0000 0 1000 1 1111 x xxxx x xxxx 0 0000 0 1000 1 1111 x xxxx x xxxx 1 1 x xxxx x xxxx 1 1111 1 1111 1 1 x xxxx x xxxx – dB Gain, 0 Left Only Muted – dB Gain, Left Muted 1 12 dB Gain 0 dB Gain –34.5 dB Gain – dB Gain, Muted – dB Gain, Right Only Muted –34.5 dB Gain x xxxx x xxxx – dB Gain, Right Muted *For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM Bit has no effect. x in the above table is “don’t care.” Record Select Control Register (Index 1Ah) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1Ah Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h All registers not shown and bits containing an X are assumed to be reserved. Refer to Table V for examples. Used to select the record source independently for the right and left channels. For MIC recording, see MS bit (Register 20h) for MIC1 and MIC2 input selection. RS [2:0] Right Record Select LS [2:0] Left Record Select –14– REV. 0 AD1888 Table V. Settings for Record Select Control LS [10:8] Left Record Source RS [2:0] Right Record Source 000 001 010 011 100 101 110 111 MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN 000 001 010 011 100 101 110 111 MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN Record Gain Register (Index 1Ch) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 IMRM* X D7 D6 D5 D4 D3 D2 X X RIM2 RIM1 RIM0 8000h RIM3 D1 D0 Default *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VI for examples. RIM[3:0] Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. IMRM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. LIM[3:0] Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. IM Input Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel. Table VI. Settings for Record Gain Register Control Bits Record Gain (1Ch) Reg. 76h Left Channel Input Mixer D[11:8] Right Channel Input Mixer D[3:0] MSPLT* D15 WRITE READBACK Function D7* WRITE READBACK Function 0 0 1111 1111 22.5 dB Gain x 1111 1111 22.5 dB Gain 0 0 0000 0000 0 dB Gain x 0000 0000 0 dB Gain 0 1 xxxx xxxx – dB Gain, Muted x xxxx xxxx – dB Gain, Muted 1 0 1111 1111 22.5 dB Gain 1 xxxx xxxx – dB Gain, Right Only Muted 1 1 xxxx xxxx – dB Gain, Left Only Muted 0 1111 1111 22.5 dB Gain 1 1 xxxx xxxx – dB Gain, Left Muted 1 xxxx xxxx – dB Gain, Right Muted *For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. x is “don’t care.” REV. 0 –15– AD1888 General-Purpose Register (Index 20h) Reg No. Name 20h D15 General-Purpose X D14 D13 D12 D11 X X X D10 DRSS1 DRSS0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X MS LPBK X X X X X X X 0000h This register should be read before writing to generate a mask only for the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed to be reserved. LPBK Loopback Control. This bit enables the digital internal loopback from the ADC to the front DAC. This feature is normally used for test and troubleshooting. 0 = No Loopback (Default) 1 = Loopback PCM digital data from ADC output to DAC See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center/LFE DACs. MS MIC Select. Selects Mono MIC input. 0 = Select MIC1, from rear panel MIC jack 1 = Select MIC2, from front panel MIC jack DRSS [1:0] Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R (n + 1) data are by default provided in output slots 10 and 11. 00: PCM L, R n + 1 Data is on Slots 10, 11 (reset default) 01: PCM L, R n + 1 Data is on Slots 7, 8 10: Reserved 11: Reserved Audio Interrupt and Paging Mechanism Register (Index 24h) Reg No. Name 24h Audio Interrupt and Paging D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I4 X X I0 X X X X X X X PG3 PG2 PG1 PG0 xxxxh X Default This register controls the audio interrupt and paging mechanism. All registers not shown and bits containing an X are assumed to be reserved. PG[3:0] Page Selector (Read Only). This register is used to describe page selector capability for extended features. Reading these bits returns 0h, which describes page selection as vendor specific only. I0 INTERRUPT ENABLE (R/W). This enables interrupt generation. 0 = Interrupt Generation is Masked (Default) 1 = Interrupt Generation is Unmasked The S/W should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with modem slot 12 GPI functionality. AC ’97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, S/W could poll the interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an interrupting event has occurred. I4 INTERRUPT STATUS (R/W). This bit provides interrupt status and clear capability. 0 = Interrupt is Clear 1 = Interrupt was Generated Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the ac link will follow this bit change when interrupt enable (I0) is unmasked. –16– REV. 0 AD1888 Power-Down Control/Status Register (Index 26h) Reg No. Name 26h Power-Down Control/Status D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC NA The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1888 subsections. If the bit is a 1, then that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved. ADC ADC Sections Ready to Transmit Data DAC DAC Sections Ready to Transmit Data ANL Analog Amplifiers, Attenuators, and Mixers Ready REF Voltage References, VREF and VREFOUT, up to Nominal Level PR[6:0] Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. EAPD External Audio Power-Down Control. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset defaults). EAPD = 1 sets the EAPD pin high, shutting off the external power amplifier. REV. 0 –17– AD1888 PR0 = 1 PR1 = 1 ADCs OFF PR0 NORMAL PR2 = 1 ANALOG OFF PR2 OR PR3 DACs OFF PR1 PR1 = 0 AND DAC = 1 PR0 = 0 AND ADC = 1 PR4 = 1 PR2 = 0 AND ANL = 1 DIGITAL I/F OFF PR4 SHUT OFF AC-LINK WARM RESET COLD RESET READY = 1 DEFAULT Figure 8. One Example of AC ‘97 Power-Down/Power-Up Flow Extended Audio ID Register (Index 28h) Reg No. Name D15 D14 D13 D12 D11 28h Ext’d Audio ID ID1 ID0 X X D10 D9 D8 D7 D6 REV1 REV0 AMAP LDAC SDAC CDAC D5 D4 D3 D2 DSA1 DSA0 X D1 D0 Default SPDIF DRA VRA x3C7h The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one or more of the extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved. VRA Variable Rate PCM Audio Support (Read Only). This bit returns a 1 when read to indicate that the Variable Rate PCM Audio is supported. DRA Double Rate Audio (Read Only). This bit returns a 1 when read to indicate that the optional Double Rate RCM Audio is supported for PCM L and PCM R. SPDIF SPDIF Support (Read Only). This bit returns a 1 when read to indicate that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DSA[1,0] DAC Slot Assignments (Read/Write) (Reset Default = 00) 00 DACs 1, 2 = 3 and 4 DACs 3, 4 = 7 and 8 DACs 5, 6 = 6 and 9 01 DACs 1, 2 = 7 and 8 DACs 3, 4 = 6 and 9 DACs 5, 6 = disabled 10 DACs 1, 2 = 6 and 9 DACs 3, 4 = disabled DACs 5, 6 = disabled 11 Reserved CDAC PCM CENTER DAC Support (Read Only). This bit returns a 1 when read to indicate that PCM center DAC is supported. SDAC PCM Surround DAC Support (Read Only). This bit returns a 1 when read to indicate that PCM surround left and right DACs are supported. LDAC PCM LFE DAC Support (Read Only), This bit returns a 1 when read to indicate that PCM LFE DAC is supported. AMAP Slot DAC Mappings Based on Codec ID (Read Only). This bit returns a 1 when read to indicate that slot/DAC mappings based on codec ID are supported. REV[1,0] REV[1,0] = 01 indicates codec is AC ’97 revision 2.2 compliant (Read Only). ID[1:0] Indicates Codec Configuration (Read Only). 00 = Primary 01, 10, 11 = Secondary –18– REV. 0 AD1888 Extended Audio Status and Control Register (Index 2Ah) Reg No. Name D15 D14 D13 D12 D11 D10 2Ah Extended Audio VFORCE X Stat/Ctrl PRK PRJ D9 D8 PRI SPCV X D7 D6 D5 D4 D3 D2 ELDAC ESDAC ECDAC SPSA1 SPSA0 X D1 D0 Default ESPDIF EDRA EVRA 0xx0h The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers not shown and bits containing an X are assumed to be reserved. EVRA Variable Rate Audio (Read/Write). EVRA = 0, sets fixed sample rate audio at 48 kHz (Reset Default). EVRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). EDRA Double Rate Audio. EDRA = 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used in conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other DACs (surround, center, and LFE) are automatically powered down. Note that EDRA can be used without VRA; in that case, the converter rates are forced to 96 kHz if EDRA = 1. ESPDIF SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write). ESPDIF = 1 enables the SPDIF transmitter. ESPDIF = 0 disables the SPDIF transmitter (default). SPSA[1,0] SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. See the following table. ECDAC Center DAC Status (Read Only). ECDAC = 1 indicates the PCM center DAC is ready. ESDAC Surround DAC status (Read Only). ESDAC = 1 indicates the PCM surround DACs are ready. ELDAC LFE DAC status (Read Only). ELDAC = 1 indicates the PCM LFE DAC is ready. SPCV SPDIF Configuration Valid (Read Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported). PRI Center DAC Power-Down (Read/Write). PRI = 1 turns off the PCM Center DAC. PRJ Surround DACs Power-Down (Read/Write). PRJ = 1 turns off the PCM surround DACs. PRK LFE DAC Power-Down (Read/Write). PRK = 1 turns off the PCM LFE DAC. VFORCE Validity Force Bit (Reset Default = 0). When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the V bit (D15) in Register 3Ah (SPDIF control register). VFORCE = 0 and V = 0; the Validity Bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid. VFORCE = 1 and V = 0; the Validity Bit is forced low, indicating subframe data is valid. VFORCE = 1 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid. REV. 0 –19– AD1888 AC ’97 2.2 AMAP Compliant Default SPDIF Slot Assignments Codec ID Function SPSA = 00 SPSA = 01 SPSA = 10 SPSA = 11 00 00 00 01 01 10 10 11 2-Ch Primary w/SPDIF 4-Ch Primary w/SPDIF 6-Ch Primary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 7 and 8 [default] 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9 10 and 11 10 and 11 10 and 11[default] 10 and 11[default] 10 and 11[default] 10 and 11[default] PCM Front DAC Rate Register (Index 2Ch) Reg No. Name 2Ch PCM Front DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz. SRF[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz. PCM Surround DAC Rate Register (Index 2Eh) Reg No. Name 2Eh PCM Surr DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 BB80h This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the surround DAC. This register’s reset default is to be locked to the PCM front DAC sample rate register (2-Ch). To unlock this register, Bit SRU in Register 76h must be asserted. SRS[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to the EVRA bit, the sample rate is reset to 48 kHz. PCM LFE (and CENTER) DAC Rate Register (Index 30h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 30h PCM LFE/ SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 BB80h C DAC Rate This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the LFE DAC and Center DAC. This register’s reset default is to be locked to the PCM Front DAC sample rate register (2-Ch) . To unlock the register bit, SRU in Register 76h must be asserted. SRCL[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz. PCM ADC Rate Register (Index 32h) Reg No. Name 32h PCM L/R ADC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. SRA[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz. –20– REV. 0 AD1888 CENTER/LFE Volume Control Register (Index 36h) Reg No. Name D15 D14 36h Center/LFE LM Volume D13* X D12 D11 LFE5 LFE4 D10 LFE3 LFE2 D9 D8 D7 LFE1 LFE0 CM D6 D5* X D4 D3 D2 D1 D0 Default CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 8080h All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples. This register controls the LFE output volume and mute bit. The volume registers contain five bits, generating 32 volume levels with 31 steps of 1.5 dB each. If MSPLT is not set, Bit D7 has no effect. *Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1. Note that depending on the state of the AC97NC bit in Register 76h, this register operates as follows: For AC97NC = 0, the register controls the center and LFE output pin attenuators. Range is 0 dB to –46.5 dB. For AC97NC = 1, the register controls the center and LFE DAC gain/attenuators. Range is +12 dB to –34.5 dB. CNT[5:0] Center Volume Control CM Center Volume Mute. When this bit is set to 1, the channel is muted. LFE[5:0] LFE Volume Control LM LFE Volume Mute. When this bit is set to 1, the channel is muted. Table VII. Settings for Center/LFE Register Control Bits CENTER and LFE Volume (36h) D15/D7 CENTER D[5:0] and LFE D[13:8] WRITE READBACK Function with AC97NC = 0 Function with AC97NC = 1 0 0 0 0 1 00 0000 00 1111 01 1111 1x xxxx xx xxxx 0 dB Gain –22 dB Gain –46.5 dB Gain –46.5 dB Gain Muted 12 dB Gain –10.5 dB Gain –34.5 dB Gain Not Applicable Muted 00 0000 00 1111 01 1111 01 1111 xx xxxx Surround Volume Control Register (Index 38h) Reg No. 38h Name D15 D14 D13* D12 Surround Volume MUTE_L X D11 D10 D9 D8 D7 D6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 MUTE_R X D5* D4 D3 D2 RSR5 RSR4 RSR3 RSR2 D1 D0 Default RSR1 RSR0 8080h *Refer to Table VIII for examples. This register controls the surround volume controls for both stereo channels and mute bits. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 Bit is set to 1, its respective lower five volume bits are automatically set to 1 by the coded logic. On readback , all lower five bits will read 1s whenever these bits are set to 1. Note that depending on the state of the AC97NC bit in Register 76h, this register operates as follows: For AC97NC = 0, the register controls the surround output pin attenuators. Range is 0 dB to –46.5 dB. For AC97NC = 1, the register controls the surround DAC gain/attenuators. Range is +12 dB to –34.5 dB. RSR[5:0] Right Surround Volume Control MUTE_R Right Surround Volume Mute. When this bit is set to 1, the right channel is muted. LSR[5:0] Left Surround Volume Control MUTE_L Left Surround Volume Mute. When this bit is set to 1, the left channel is muted. REV. 0 –21– AD1888 Table VIII. Settings for Surround Register Control Bits Surround Volume (38h) D15/D7 0 0 0 0 1 Left Surround D[13:8] Right Surround D[5:0] WRITE READBACK 00 0000 00 0000 00 1111 00 1111 01 1111 01 1111 1x xxxx 01 1111 xx xxxx xx xxxx Function with AC97NC = 0 Function with AC97NC = 1 0 dB Gain –22 dB Gain –46.5 dB Gain –46.5 dB Gain Muted 12 dB Gain –10.5 dB Gain –34.5 dB Gain Not Applicable Muted SPDIF Control Register (Index 3Ah) Reg No. Name 3Ah SPDIF Control D15 D14 D13 D12 D11 D10 D9 D8 V X SPSR1 SPSR0 L CC6 CC5 CC4 D7 D6 D5 D4 D3 D2 D1 D0 Default CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h All registers not shown and bits containing an X are assumed to be reserved. Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF Bit in Register 2Ah is 0). This ensures that control and status information starts up correctly at the beginning of SPDIF transmission. PRO Professional. 1 indicates professional use of channel status, 0 indicates consumer. /AUD Non-Audio. 1 indicates data is non PCM format, 0 indicates data is PCM. COPY Copyright. 1 indicates copyright is asserted, 1 indicates copyright is not asserted. PRE Pre-emphasis. 1 indicates filter pre-emphasis is 50 µs/15 µs, 0 indicates pre-emphasis is none. CC[6-0] Category Code. Programmed according to IEC standards, or as appropriate. L Generation Level. Programmed according to IEC standards, or as appropriate. SPSR[1,0] SPDIF Transmit Sample Rate: SPSR[1:0] = 00 Transmit Sample Rate = 44.1 kHz SPSR[1:0] = 01 Reserved SPSR[1:0] = 10 Transmit Sample Rate = 48 kHz (default) SPSR[1:0] = 11 Not supported. V Validity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid. –22– REV. 0 AD1888 Jack Sense/Audio Interrupt Status Register (Index 72h) Reg No. Name D15 72h Jack Sense JS1 JS1 JS0 JS SPRD DMX DMX MT2 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default JS MT1 JS MT0 X X JS1 TMR JS0 TMR JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0000h All register bits are read/write except for JS0ST and JS1ST, which are read only. JS0INT Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR should clear this bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also, note that the actual interrupt implementation is selected by the INTS bit (Register 76h). It is also possible to generate a software system interrupt by writing a 1 to this bit. JS1INT Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description for additional details. JS0ST JS0 STATE. This bit always reports the logic state of the JS0 pin. JS1ST JS1 STATE. This bit always reports the logic state of the JS1 pin. JS0MD JS0 Mode. This bit selects the operation mode for the JS0 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS1MD JS1 Mode. This bit selects the operation mode for the JS1 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS0TMR JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized. JS1TMR JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized. JSMT[2,0] JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table IX). JS0DMX JS0 Down Mix Control Enable. This bit enables JS0 to control the down-mix function. This function allows a digital mix of six channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_OUT or HP_OUT jacks. When this bit is set to 1, JS0 = 1 will activate the down-mix conversion. See the DMIX description in Register 76h. The DMIX bits select the down-mix implementation type and can also force the function to be activated. JS1DMX JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active (logic state 1). Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit’s description in Register 76h for a better understanding of the spread function. JS1SPRD JS Spread Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active (logic state 1). Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit’s description in Register 76h for a better understanding of the spread function. REV. 0 –23– AD1888 Table IX. Jack Sense Mute Select (JSMT [2:0]) JS1 JS0 JSMT2 JSMT1 JSMT0 HP OUT LINE OUT C/LFE OUT MONO OUT NOTES NA NA 0 0 0 ACTIVE ACTIVE ACTIVE ACTIVE JS0 and JS1 ignored. OUT OUT IN IN (0) (0) (1) (1) OUT IN OUT IN (0) (1) (0) (1) 0 0 0 0 0 0 0 0 1 1 1 1 ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE JS0 no mute action, JS1 mutes mono and enables LINE_OUT and C/LFE. Standard 6-channel config. OUT OUT IN IN (0) (0) (1) (1) OUT IN OUT IN (0) (1) (0) (1) 1 1 1 1 0 0 0 0 0 0 0 0 ACTIVE ACTIVE ACTIVE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE ACTIVE FMUTE FMUTE ACTIVE FMUTE FMUTE FMUTE JS0 = 0 and JS1 = 0 enables mono. JS1 = 1 enables front only. JS0 = 1 enables all rear. 6-chan config with front jack wrapback. OUT OUT IN IN (0) (0) (1) (1) OUT IN OUT IN (0) (1) (0) (1) 1 1 1 1 0 0 0 0 1 1 1 1 FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ACTIVE FMUTE FMUTE FMUTE JS0 no mute action, JS1 mutes mono and enables LINE_OUT + HP_OUT + C/LFE. Standard 6-channel config. 1 1 0 1 1 1 0 1 1 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** NA NA NA NA NA NA Reserved Reserved Reserved FMUTE = Output is forced to mute independent of the respective Volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective Volume register setting. OUT = Nothing plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is 1 (via the codec JS internal pull-up). –24– REV. 0 AD1888 Serial Configuration Register (Index 74h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 74h Serial SLOT16 REGM2 REGM1 REGM0 REGM3 DRF X Configuration D7 D6 CHEN X D5 D4 D3 D2 LBKS1 LBKS0 INTS X D1 D0 Default SPAL SPDZ SPLNK 1001h All registers not shown and bits containing an X are assumed to be reserved. Note that this register is not reset when Register 00h (Reset Register) is written to (soft reset). SPLNK SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the same data requests (reset default). SPDZ SPDIF DACZ. 0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO underruns. SPAL SPDIF ADC Loop-Around. 0 = SPDIF transmitter is connected to the AC-Link stream (reset default). 1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link. INTS Interrupt Mode Select. This bit selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (modem interrupt) (reset default). 1 = Slot 6 Valid Bit (MIC ADC interrupt). LBKS[1:0] Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h) 00 = Loop-back through the front DACs (reset default). 01 = Loop-back through the surround DACs. 10 = Reserved 11 = Loop-back through the center and LFE DACs (center DAC loops back from the ADC left channel, the LFE DAC from the ADC right channel). CHEN Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin. DRF DAC Request Force. This allows the AD1888 to synchronize DAC requests with the AD1981A/B. 0 = Normal DAC requesting sequence (reset default). 1 = Synchronize to AD1981A/B DAC requests. REGM3 Slave 3 Codec Register Mask REGM0 Master Codec Register Mask REGM1 Slave 1 Codec Register Mask REGM2 Slave 2 Codec Register Mask SLOT16 Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing. REV. 0 –25– AD1888 Miscellaneous Control Bit Register (Index 76h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 76h Misc DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD X Control Bits D5 D4 D3 D2 D1 D0 Default LOSEL SRU VREFH VREFD MBG1MBG0 0000h MBG[1:0] MIC Boost Gain Select Register. These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Both MIC1/MIC2 and MIC2 preamps will be set to the same selected gain. Note that this gain takes effect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise, the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default) 01 = 10 dB gain 10 = 30 dB gain 11 = reserved VREFD VREFOUT Disable. Disables VREFOUT, placing it into High-Z out mode. Note that this bit overrides the VREFH bit selection (see below). 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into High-Z out mode. VREFH VREFOUT High. Changes VREFOUT from 2.25 V to 3.70 V for PC2001 compliant MIC bias applications. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 3.70 V output. SRU Sample Rate Unlock. Controls DAC sample rate locking. 0 = All DAC sample rates are locked to the front sample rate (reset default). 1 = DAC sample rates can be set independently for front, surround, and LFE. LOSEL LINE_OUT Amplifiers Input Select. This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is to allow swapping of the front and surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit should normally be used in tandem with the HPSEL bit (see below). 0 = LINE_OUT amplifiers are driven by the mixer outputs (reset default). 1 = LINE_OUT amplifiers are driven by the surround DAC outputs. SPRD SPREAD Enable. This bit enables spreading of 2-channel media to all six output channels. This function is implemented in the analog section by using the output selector controls line for the center/LFE, surround, and Line_out output channels. Note that the Jack Sense pins can also be set up to control (gate) this function, depending on the JSSPRD bit (see Register 72h). 0 = No spreading occurs unless activated by the Jack Senses and JSSPRD bits (reset default). 1 = The SPRD selector drives the center and LFE outputs from the MONO_OUT, the HPSEL selector drives the SURR/HP_OUT outputs from the mixer outputs, and the LOSEL selector drives the LINE_OUT outputs also from the mixer outputs. Note that the SPRD bit overrides the current output selector control lines set up by bits LOSEL and HPSEL as follows: LOSEL = 0 and HPSEL = 1. –26– REV. 0 AD1888 DMIX[1:0] Down Mix Mode Select. Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. Note that the Jack Sense pins can also be set up to control (gate) this function depending on the JS0DMX and JS1DMX Bits (see Register 72h). The upper bit allows forcing the down-mix function: DMIX[1] = 0, no down-mix unless activated by the Jack Sense and JSxDMX bits (default). DMIX[1] = 1, forces down-mix function. The lower bit selects the down-mix type: DMIX[0] = 0, selects 6-to-4 down-mix. The center and LFE channels are summed equally into the mixer left and right channels (default). DMIX[0] = 1, selects 6-to-2 down-mix. The surround left and right channels are summed into the mixer left and right channels. Default for DMIX[1:0] is 00. HPSEL Headphone Amplifier Input Select. This bit allows the headphone power amps to be driven from the surround DACs or from the mixer outputs. There are two reasons for this: one is to allow 2-channel media to use the higher power headphone amplifiers available on the SURR/HP_OUT outputs; the other is to allow spreading of 2-channel media to the surround outputs. Together with the LOSEL bit (see above), this bit also provides for analog swapping of the mixer (front) and surround outputs. 0 = SURR_OUT/HP_OUToutputs are driven by the surround DACs (reset default). 1 = SURR_OUT/HP_OUToutputs are driven by the mixer outputs. CLDIS Center and LFE Disable. Disables the center and LFE output pins, placing them into High-Z mode so that the assigned output audio jack(s) can be shared for MIC inputs or other functions. 0 = Center and LFE output pins have normal audio drive capability (reset default). 1 = Center and LFE output pins are placed into High-Z mode. LODIS Line_out Disable. Disables the Line_out pins (L/R), placing them into High-Z mode so that the assigned output audio jack can be shared for Line Input function. 0 = Line_out pins have normal audio drive capability (reset default). 1 = Line_out pins are placed into High-Z mode. MSPLT Mute Split. Allows separate mute control bits for master, HP, Line_in, CD, PCM OUT, and record volume/gain control registers. 0 = Both left and right channel mutes are controlled by Bit D15 in the respective registers (reset default). 1 = Bit D15 affects only the left channel mute and Bit D7 affects only the right channel mute. AC97NC AC ’97 No Compatibility Mode. This bit allows the surround, center, and LFE volume control registers and output attenuators to operate in a more functional mode than defined by the AC97 2.2 spec. This is called ADI compatibility mode. In AC ’97 compatibility mode, the DAC gain/attenuators for the surround, center, and LFE are controlled by Register 18h (PCM volume). The output pin attenuators for the surround are controlled by Register 38h, and the output pin attenuators for the center and LFE are controlled by Register 36h. In ADI compatibility mode, the Surround DAC gain/attenuators are controlled by Register 38h, and the Center/LFE DACs are controlled by Register 36h. The output pin attenuators for Center/LFE are controlled by Register 02h (Master Volume), and the output pin attenuators for Surround are controlled by Register 04h. 0 = AC97 compatibility mode (reset default). 1 = ADI compatibility mode. DACZ DAC Zero-Fill. Determines DAC data fill under starved condition. 0 = DAC data is repeated when DACs are starved for data (reset default). 1 = DAC data is zero-filled when DACs are starved for data. REV. 0 –27– AD1888 Vendor ID Register (Index 7Ch–7Eh) Reg No. Name D15 7Ch Vendor ID1 F7 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default F6 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 F5 S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D. Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 D6 D5 D4 D3 D2 S1 D1 S0 D0 4144h Default T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5368h T[7:0] This register is ASCII encoded to S. REV[7:0] This register is set to 68h identifying the AD1888. Codec ID and Clock Selection Table XTL_IN ID1# ID0# Codec ID Codec Clocking Source GND GND GND XTAL into XTL_IN CLK INPUT CLK INPUT CLK INPUT 0 0 1 1 0 1 0 1 SECONDARY, ID = 3 SECONDARY, ID = 2 SECONDARY, ID = 1 PRIMARY, ID = 0 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 24.576 MHz Local XTAL or External CLK 0 0 1 0 1 X PRIMARY, ID = 0 PRIMARY, ID = 0 RESERVED 14.3181 MHz (External into XTL_IN) 48.00 MHz (External into XTL_IN) RESERVED Note that internally, the ID pins have weak pull-ups and are inverted. –28– REV. 0 AD1888 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 10 6 2 1.45 1.40 1.35 0.15 0.05 SEATING PLANE PIN 1 SEATING PLANE 7.00 BSC SQ TOP VIEW 0.20 0.09 (PINS DOWN) VIEW A 7 3.5 0 0.08 MAX COPLANARITY 25 12 13 24 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.75 BSC SQ TOP VIEW 0.20 REF 12 MAX 1 25 24 0.25 MIN 5.50 REF 1.00 MAX 0.65 NOM 0.50 BSC COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 REV. 0 5.25 5.10 SQ 4.95 12 13 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR 48 BOTTOM VIEW 0.50 0.40 0.30 1.00 0.90 0.80 0.30 0.23 0.18 –29– –30– –31– –32– C04294–0–10/03(0)