ICST MK3724GL Vcxo plus audio clock for stb Datasheet

MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Description
Features
The MK3724 is a low cost, low jitter, high performance
VCXO and PLL clock synthesizer designed to replace
expensive discrete VCXOs and multipliers. The
patented on-chip Voltage Controlled Crystal Oscillator
accepts a 0 to 3.3 V input voltage to cause the output
clocks to vary by ±115 ppm. Using ICS’ analog/digital
Phase-Locked Loop (PLL) techniques, the device uses
an inexpensive 27 MHz pullable crystal input to
produce a reference output and a selectable audio
clock.
•
•
•
•
•
•
•
Packaged in 16-pin TSSOP
ICS manufactures the largest variety of VCXO based
timing devices for all applications. Consult ICS to
eliminate VCXOs, crystals, and oscillators from your
board.
•
•
•
•
VCXO tuning voltage of 0 to 3.3 V
The frequency of the on-chip VCXO is adjusted by an
external control voltage connected to VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit.
Available in Pb free packaging
Replaces a VCXO and oscillator
Operating voltage of 3.3 V
Provides output of 27 MHz plus audio clock
Uses an inexpensive 27 MHz pullable crystal
On-chip patented VCXO with pull range of 230 ppm
(minimum)
Advanced, low power, sub-micron CMOS process
Industrial temperature range available
For other standard audio frequencies see the
MK3722
Block Diagram
VDD
3
PLL/Clock
Synthesis
Circuitry
3
S2:S0
VIN
X1
27 MHz
Pullable
Crystal
X2
ACLK
Voltage
Controlled
Crystal
Oscillator
27MHz
3
GND
1
MDS 3724 C
I n t e gra te d C i r c u i t S y s t e m s
PDTS
●
525 Race Stre et, San Jo se, CA 9 5126
Revision 121904
●
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Pin Assignment
Audio Clock Select Table
S2
S1
S0
ACLK (MHz)
0
0
0
3.072
0
0
1
4.096
0
1
0
6.144
0
1
1
8.192
27M
1
0
0
12.288
11
GND
1
0
1
24.576
7
10
ACLK
1
1
0
33.8688
8
9
S2
1
1
1
73.728
X2
1
16
S1
X1
2
15
NC
VDD
3
14
VDD
VDD
4
13
S0
VIN
5
12
GND
6
GND
PDTS
16-pin TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
X2
Output
Crystal connection. Connect to a 27 MHz fundamental mode
pullable crystal.
2
X1
Input
Crystal connection. Connect to a 27 MHz fundamental mode
pullable crystal.
3
VDD
Power
Connect to +3.3 V.
4
VDD
Power
Connect to +3.3 V.
5
VIN
Input
Voltage input to VCXO. Changing the voltage between 0 to 3.3 V
controls the VCXO frequency.
6
GND
Power
Connect to ground.
7
GND
Power
Connect to ground.
8
PDTS
Power
Power Down Tri-state. This pin powers down entire chip and
tri-states the outputs when low. Internal pull-up resistor.
9
S2
Input
Select input S2. Selects ACLK per table above. Internal pull-up
resistor.
10
ACLK
Output
Audio clock output per table above.
11
GND
Power
Connect to ground.
12
27M
Output
27 MHz reference clock output.
13
S0
Input
Select input S0. Selects ACLK per table above. Internal pull-up
resistor.
2
MDS 3724 C
In te grated Circuit Systems
Pin Description
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Pin
Number
Pin
Name
Pin
Type
14
VDD
Power
15
NC
--
16
S1
Input
Connect to +3.3 V.
No connect. Do not connect anything to this pin.
Select input S1. Selects ACLK per table above. Internal pull-up
resistor.
3
MDS 3724 C
In te grated Circuit Systems
Pin Description
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
External Component Selection
Crystal Tuning Load Capacitors
The MK3724 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01 µF should be connected
between VDD and GND on pins 3 and 4, pins 6 and 7,
and pins 11 and 14 as close to the MK3724 as
possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and samples of the crystals which you plan to use in
production. You will also need measured initial
accuracy for each crystal at the specified crystal load
capacitance (CL).
When the PCB traces between the clock outputs and
the loads are over 1 inch, series termination should be
used. To series terminate a 50 Ω trace (a commonly
used trace impedance), place a 33 Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20 Ω.
To determine the value of the crystal capacitors:
Quartz Crystal
2. Adjust the voltage on pin 5 to 3.3 V. Measure and
record the frequency of the same output.
The MK3724 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device meeting ICS’
recommended parameters must be used, and the
layout guidelines discussed in the following section
must be followed.
To calculate the centering error:
See Application Note MAN05 for a full list of crystal
parameters.
ftarget = nominal crystal frequency
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3724 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3724 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3724. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal.
6 ( f 3.3 ( 3.0 )V – f t arg et ) + ( f 0V – f t arg et )
Error = 10 x ---------------------------------------------------------------------------------------- – error xtal
f t arg et
Where:
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
4
MDS 3724 C
In te grated Circuit Systems
1. Connect VDD to 3.3 V. Connect pin 5 to the second
power supply. Adjust the voltage on pin 5 to 0V.
Measure and record the frequency of the CLK output.
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25 ppm).
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3724. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial
0 to +70°C
Ambient Operating Temperature, Industrial
-40 to +85°C
Storage Temperature
-65 to +150°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
-40
+85
°C
+3.135
+3.465
V
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Power Supply Voltage (measured in respect to GND)
Typ.
Reference crystal parameters
Refer to page 3
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature -40 to +85°C, unless stated otherwise
Parameter
Symbol
Conditions
Operating Voltage
VDD
Output High Voltage
VOH
IOH = -12 mA
Output Low Voltage
VOL
IOL = 12 mA
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
Output Low Voltage (CMOS
Level)
VOL
IOH = +4 mA
Typ.
3.135
●
525 Ra ce Street, San Jose, CA 9512 6
Max.
Units
3.465
V
2.4
V
0.4
VDD-0.4
V
V
0.375
5
MDS 3724 C
In te grated Circuit Systems
Min.
V
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input High Voltage (S1:S0)
VIH
2.0
V
Input High Voltage (S2)
VIH
2.5
V
Input Low Voltage (S1:S0)
VIL
0.8
V
Input Low Voltage (S2)
VIL
0.5
V
Input High Current
IIH
at 3.3V, Sx, PDTS
0.1
µA
Input Low Current
IIL
at 0V, Sx, PDTS
-8.5
µA
11
mA
±50
mA
Operating Supply Current
IDD
Short Circuit Current
IOS
VIN, VCXO Control Voltage
VIA
On Chip Pull-up Resistor,
inputs
RPU
Input selects
360
kΩ
Input Capacitance
CIN
Input selects
5
pF
20
Ω
Nominal Output Impedance
No load
0
3.3
ZOUT
V
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Crystal Pullability
fP
VCXO Gain
Conditions
Min.
Typ.
+ 100
+ 150
ppm
VIN = VDD/2 + 1 V, Note 1
150
ppm/V
0V< VIN < 3.3 V, Note 1
Max. Units
Output Rise Time
tOR
20% to 80%, CL=15 pF
1.2
2.0
ns
Output Fall Time
tOF
80% to 20%, CL=15 pF
1.2
2.0
ns
Output Clock Duty Cycle
tD
Measured at 1.65 V, CL=15
pF
50
60
%
Maximum Output Jitter,
short term
tJ
CL=15 pF
40
+150
ps
Changing Frequency
Setting Time
Power-up time
1
ms
PLL lock time from power-up
up to ±1% of final frequency
10
ms
PDTS goes high until stable
CLK output up to 1% of final
frequency
2
ms
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
6
MDS 3724 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Thermal Characteristics
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Min.
Typ.
Max. Units
θJA
Still air
78
°C/W
θJA
1 m/s air flow
70
°C/W
θJA
3 m/s air flow
68
°C/W
37
°C/W
θJC
Marking Diagram
Notes:
16
1. ###### is the lot code.
9
2. YYWW is the last two digits of the year, and the week
number that the part was assembled.
MK3724G
######
YYWW
1
3. “L” designates Pb (lead) free.
4. Bottom mark denotes country of origin if not USA.
8
Non Lead-Free
16
9
MK3724GL
######
YYWW
1
8
Lead-Free
16
9
MK3724IL
######
YYWW
1
8
Industrial Temp., Lead-Free
7
MDS 3724 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95Ordering Information
Millimeters
16
Symbol
E1
E
INDEX
AREA
1 2
D
A
2
Min
A
A1
A2
b
C
D
E
E1
e
L
α
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
A
A
1
c
-Ce
SEATING
PLANE
b
L
.10 (.004)
C
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
MK3724G
MK3724GTR
MK3724GLF
MK3724GLFTR
MK3724GILF
MK3724GILFTR
MK3724G
MK3724G
MK3724GL
MK3724GL
MK3724IL
MK3724IL
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
8
MDS 3724 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 121904
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
Similar pages