TI1 LP8861-Q1 Low-emi, high-performance four-channel led driver Datasheet

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LP8861-Q1
SNVSA50A – AUGUST 2015 – REVISED NOVEMBER 2015
LP8861-Q1 Low-EMI, High-Performance Four-Channel LED Driver for Automotive Lighting
1 Features
3 Description
•
•
The LP8861-Q1 is an automotive high-efficiency, lowEMI, easy-to-use LED driver with integrated
boost/SEPIC converter. It has four high-precision
current sinks that can provide high dimming ratio
brightness control with a PWM input signal.
1
•
•
•
•
•
•
Qualified for Automotive Applications
AECQ100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage Operating Range 4.5 V to 40 V
Four High-Precision Current Sinks
– Current Matching 1% (typical)
– LED String Current up to 100 mA/Channel
– Dimming Ratio 10 000:1 at 200 Hz
Integrated Boost/SEPIC for LED String Power
– Output Voltage up to 45 V
– Switching Frequency 300 kHz to 2.2 MHz
– Boost/SEPIC Synchronization Input
– Spread Spectrum
Power-Line FET Control for Inrush Current
Protection and Standby Energy Saving
Extensive Fault Detection and Tolerance Features
– Fault Output
– Input Voltage OVP, UVLO, and OCP
– Open and Shorted LED Fault Detection
– Automatic LED Current Reduction With
External Temperature Sensor
– Thermal Shutdown
Minimum Number of External Components
The boost/SEPIC converter has adaptive output
voltage control based on the LED current sink
headroom voltages. This feature minimizes the power
consumption by adjusting the voltage to lowest
sufficient level in all conditions. Boost/SEPIC
controller supports spread spectrum for switching
frequency and an external synchronization with
dedicated pin. The high switching frequency allows
the LP8861-Q1 to avoid disturbance for AM radio
band.
The LP8861-Q1 has option to drive an external pFET to disconnect the input supply from the system in
the event of a fault and reduce inrush current and
standby power consumption. The device has ability to
reduce LED current based on temperature measured
with external NTC sensor to protect LED from
overheating and extend LED life time.
The input voltage range for the LP8861-Q1 is from
4.5 V to 40 V to support automotive stop/start and
load dump condition. The device supports PWM
brightness dimming ratio 10 000:1 for input PWM
frequency
200 Hz. The LP8861-Q1 integrates extensive fault
detection and protection features.
Device Information(1)
2 Applications
Automotive Infotainment, Instrument Clusters, and
Backlighting Systems
PART NUMBER
LP8861-Q1
PACKAGE
BODY SIZE (NOM)
TSSOP (20)
6.50 × 4.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
4.5...40 V
RISENSE
D1
L1
Q1
System Efficiency
100
Up to 45 V
95
System efficiency (%)
COUT
CIN BOOST
RGS
R2
SW
CIN
CLDO
SD
VSENSE_N
VIN
FB
CFB
Up to 100 mA/string
LDO
VLDO
LP8861-Q1
RFSET
BRIGHTNESS
EN
R1
OUT1
OUT2
FSET
OUT3
SYNC
OUT4
PWM
VLDO
R4
R3
90
85
80
VIN=5V
75
VIN=8V
70
VIN=12V
65
VIN=16V
TSET
TSENSE
VDDIO/EN
R7
RTº
ISET
FAULT
PGND
GND
R6
R5
PAD
NTC
60
0
20
40
60
Brightness (%)
80
100
C010
RISET
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8861-Q1
SNVSA50A – AUGUST 2015 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
5
5
5
6
6
6
6
7
7
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Internal LDO Electrical Characteristics .....................
Protection Electrical Characteristics .........................
Power Line FET Control Electrical Characteristics ...
Current Sinks Electrical Characteristics....................
PWM Brightness Control Electrical Characteristics
Boost/SEPIC Converter Characteristics .................
Logic Interface Characteristics................................
Typical Characteristics ............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
13
22
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Applications ................................................ 24
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2015) to Revision A
Page
•
Changed maximum Tstg from 160°C to 150°C ...................................................................................................................... 5
•
Added last 2 sentences to end of Internal LDO subsection ................................................................................................. 15
•
Changed Equation 3 ............................................................................................................................................................ 15
•
Changed Figure 29 to update VIN and VSENSE_N pin connections; removed RISENSE row from sub-section
8.2.2.1 Design Requirements ............................................................................................................................................... 27
2
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SNVSA50A – AUGUST 2015 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
20-Pin TSSOP with Exposed Thermal Pad
Top View
VIN
1
20
VSENSE_N
LDO
2
19
SD
FSET
3
18
SW
VDDIO/EN
4
17
PGND
FAULT
5
16
FB
SYNC
6
15
OUT1
PWM
7
14
OUT2
TSENSE
8
13
OUT3
TSET
9
12
OUT4
ISET
10
11
GND
EP*
*EXPOSED PAD
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Pin Functions
PIN
NUMBER
NAME
TYPE (1)
DESCRIPTION
1
VIN
P
Input power pin as well as the positive input for an optional current sense resistor.
2
LDO
A
Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free
ground.
3
FSET
A
Boost/SEPIC switching frequency setting resistor.
4
VDDIO/EN
I
Enable input for the device as well as supply input (VDDIO) for digital pins
5
FAULT
OD
6
SYNC
I
Input for synchronizing boost/SEPIC.
In synchronization is not used, connect this pin to GND to disable spread spectrum or to
VDDIO/EN to enable spread spectrum.
7
PWM
I
PWM dimming input.
8
TSENSE
A
Input for NTC bridge.
If unused, the pin may be left floating.
9
TSET
A
Input for NTC bridge.
This pin must be connected to GND if not used.
10
ISET
A
LED current setting resistor
11
GND
G
Ground.
12
OUT4
A
Current sink output.
This pin must be connected to GND if not used.
13
OUT3
A
Current sink output.
This pin must be connected to GND if not used.
14
OUT2
A
Current sink output.
This pin must be connected to GND if not used.
15
OUT1
A
Current sink output.
This pin must be connected to GND if not used.
Fault signal output.
If unused, the pin may be left floating.
16
FB
A
Boost/SEPIC feedback input.
17
PGND
G
Boost/SEPIC power ground.
18
SW
A
Boost/SEPIC switch pin.
19
SD
A
Power-line FET control.
If unused, the pin may be left floating.
20
VSENSE_N
A
Input current sense pin. Connect to VIN pin when optional input current sense resistor is not
used.
(1)
4
A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
Over operating free-air temperature range (unless otherwise noted)
Voltage on pins
MIN
MAX
VIN, VSENSE_N, SD, SW, FB
–0.3
50
OUT1…OUT4
–0.3
45
LDO, SYNC, FSET, ISET, TSENSE, TSET, PWM, VDDIO/EN, FAULT
–0.3
5.5
Continuous power dissipation (3)
UNIT
V
Internally Limited
(4)
–40
125
ºC
Junction temperature range, TJ (4)
–40
150
ºC
See (5)
ºC
150
°C
Ambient temperature range, TA
Maximum lead temperature (soldering)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pins.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and
disengages at TJ = 145°C (typical).
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
For detailed soldering specifications and information, refer to the PowerPAD™ Thermally Enhanced Package Application Note
(SLMA002).
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
Other pins
±500
Corner pins (1,10,11,20)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
Over operating free-air temperature range (unless otherwise noted) .
VIN
Voltage on pins
(1)
MIN
MAX
4.5
45
VSENSE_N, SD, SW
0
45
OUT1…OUT4
0
40
FB, FSET, LDO, ISET, TSENSE, TSET, VDDIO/EN, FAULT
0
5.25
SYNC, PWM
0
VDDIO/EN
UNIT
V
All voltages are with respect to the potential at the GND pins.
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6.4 Thermal Information
LP8861-Q1
THERMAL METRIC (1)
PWP (TSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance (2)
44.2
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
26.5
°C/W
RθJB
Junction-to-board thermal resistance
22.4
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
22.2
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
2.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
6.5 Electrical Characteristics (1) (2)
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TYP
MAX
Standby supply current
Device disabled, VVDDIO/EN = 0 V,
VIN = 12 V
4.5
20
μA
Active supply current
VIN = 12 V, VBOOST=26 V, output
current 80 mA/channel, ƒSW= 300
kHz
5
12
mA
VPOR_R
Power-on reset rising threshold
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
2.7
V
VPOR_F
Power-on reset falling threshold
LDO pin voltage. Output of the
internal LDO or an external supply
input (VDD).
TTSD
Thermal shutdown threshold
TTSD_THR
Thermal shutdown hysteresis
IQ
(1)
(2)
TEST CONDITIONS
MIN
1.5
150
UNIT
V
165
175
20
°C
°C
All voltages are with respect to the potential at the GND pins.
Min and Max limits are specified by design, test, or statistical analysis.
6.6 Internal LDO Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
MIN
TYP
MAX
UNIT
VLDO
Output voltage
PARAMETER
VIN = 12 V
TEST CONDITIONS
4.15
4.3
4.45
V
VDR
Dropout voltage
External current load 5mA
120
220
430
mV
ISHORT
Short circuit current
IEXT_MAX
Maximum current for external load
50
mA
5
mA
6.7 Protection Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
41
42
44
UNIT
V
2.7
3.2
3.7
A
VOVP
VIN OVP threshold voltage
IOCP
VIN OCP current
VUVLO
VIN UVLO
4.0
V
VUVLO_HYST
VIN UVLO hysteresis
100
mV
RSENSE = 50 mΩ
LED short detection threshold
6
5.6
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7
V
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6.8 Power Line FET Control Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSENSE_N pin leakage current
VVSENSE_N = 45 V
0.1
3
µA
SD leakage current
VSD = 45 V
0.1
3
µA
230
283
µA
SD pulldown current
185
6.9 Current Sinks Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
TYP
MAX
ILEAKAGE
Leakage current
PARAMETER
Outputs OUT1 to OUT4, VOUTx = 45 V
0.1
5
IMAX
Maximum current
OUT1 to OUT4
100
IOUT
Output current accuracy
IOUT = 100 mA
IMATCH
Output current matching (1)
IOUT = 100 mA, PWM duty =100%
1%
3.5%
VSAT
Saturation voltage (2)
IOUT = 100 mA, VLDO = 4.3 V
0.4
0.7
(1)
(2)
TEST CONDITIONS
MIN
−5%
UNIT
µA
mA
5%
V
Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are
determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).
Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all
parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.
6.10 PWM Brightness Control Electrical Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
ƒPWM
Recommended PWM input
frequency
tON/OFF
Minimum on/off time
TEST CONDITIONS
MIN
TYP
MAX
100
IOUT = 100 mA. No external load
from LDO
UNIT
20 000
Hz
0.5
µs
6.11 Boost/SEPIC Converter Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
Unless otherwise specified: VIN = 12 V, VVDDIO/EN = 3.3 V, L = 22 μH, CIN = 2 × 10-μF ceramic and 33-μF electrolytic, COUT = 2
× 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒSW = 300 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
4.5
40
V
VOUT
Output voltage
10
45
V
ƒSW_MIN
Minimum switching frequency
(central frequency if spread
spectrum is enabled)
300
kHz
2200
kHz
Defined by RFSET resistor
ƒSW_MAX
Maximum switching frequency
(central frequency if spread
spectrum is enabled)
VOUT/VIN
Conversion ratio
TOFF
Minimum switch OFF time
ISW_MAX
SW current limit
RDSon
FET RDSon
ƒSYNC
External SYNC frequency
tSYNC_ON_MIN
External SYNC minimum on time
150
ns
tSYNC_OFF_MIN
External SYNC minimum off time
150
ns
10
ƒSW ≥ 1.15 MHz
55
1.8
Pin-to-pin
2
2.2
A
240
400
mΩ
2200
kHz
300
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6.12 Logic Interface Characteristics
TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT VDDIO/EN
VIL
Input low level
VIH
Input high level
II
Input current
0.4
V
30
µA
1.65
−1
V
5
LOGIC INPUTS SYNC, PWM
VIL
Input low level
VIH
Input high level
II
Input current
0.2 × VVDDIO/EN
0.8 × VVDDIO/EN
−1
V
1
μA
0.5
V
1
μA
LOGIC OUTPUT FAULT
VOL
Output low level
Pullup current 3 mA
ILEAKAGE
Output leakage current
V = 5.5 V
8
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6.13 Typical Characteristics
1000
1000
900
900
Boost Output Current (mA)
Boost Output Crurrent (mA)
Unless otherwise specified: D = NRVB460MFS, T = 25°C.
800
700
600
500
Vboost = 22 V
400
Vboost = 30 V
300
800
700
600
500
Vboost = 22 V
400
Vboost = 30V
300
Vboost = 37 V
Vboost = 37 V
200
200
5
10
15
20
25
30
Input Voltage (V)
5
ƒSW = 300 kHz
L = 33 μH
DC Load (PWM = 100%)
CIN and COUT = 33 µF + 2 × 10 µF (ceramic)
900
Boodt Output Current (mA)
900
800
700
600
500
30
C002
DC Load (PWM = 100%)
Vboost = 22 V
Vboost = 30 V
800
700
600
500
Vboost = 22 V
400
Vboost = 30 V
300
Vboost = 37 V
Vboost = 37 V
200
200
5
10
15
20
25
30
Input Voltage (V)
ƒSW = 1.5 MHz
L = 8.2 μH
CIN and COUT = 2 × 10 µF (ceramic)
5
10
15
20
ƒSW = 2.2 MHz
L = 4.7 μH
CIN and COUT = 2 × 10 µF (ceramic)
DC Load (PWM = 100%)
25
30
Input Voltage (V)
C003
Figure 3. Maximum Boost Output Current
C004
DC Load (PWM = 100%)
Figure 4. Maximum Boost Output Current
100
2200
80
1800
60
1400
fSW (kHz)
IOUT (mA)
25
Figure 2. Maximum Boost Output Current
1000
300
20
ƒSW = 800 kHz
L = 15 μH
CIN and COUT = 2 × 10 µF (ceramic)
1000
400
15
Input Voltage (V)
Figure 1. Maximum Boost Output Current
Boost Output Current (mA)
10
C001
40
20
1000
600
0
200
20
40
60
80
100
120
140
RISET (k )
160
20
Figure 5. LED Current vs RISET
60
100
140
180
RFSET (k )
C005
220
C009
Figure 6. Boost Switching Frequency ƒSW vs RFSET
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Typical Characteristics (continued)
6
120
5
100
4
80
Current (mA)
Output current mismatch (%)
Unless otherwise specified: D = NRVB460MFS, T = 25°C.
3
2
60
40
20
1
0
0
40
50
60
70
80
90
Output current (mA)
100
0.0
0.1
0.2
0.3
0.4
0.5
Voltage (V)
C013
0.6
C014
RISET = 24 kΩ
Figure 7. LED Current Sink Matching
10
Figure 8. LED Current Sink Saturation Voltage
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7 Detailed Description
7.1 Overview
The LP8861-Q1 is a highly integrated LED driver for automotive infotainment, lighting systems, and mediumsized LCD backlight applications. It includes a boost/SEPIC converter with an integrated FET, an internal LDO,
and four LED current sinks. A VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs)
and at the same time enables the device.
The switching frequency on the boost/SEPIC regulator is set by a resistor connected to the FSET pin. The
maximum voltage is set by a resistive divider connected to the FB pin. For the best efficiency the voltage is
adapted automatically to the minimum necessary level needed to drive the LED strings. This is done by
monitoring LED output voltage in real time. For EMI reduction and control two optional features are available:
• Spread spectrum, which reduces EMI noise spikes at the switching frequency and its harmonic frequencies.
• Boost/SEPIC can be synchronized to an external clock frequency connected to the SYNC pin.
The four constant current sinks for driving the LEDs provide current up to 100 mA per sink and can be tied
together to get a higher current. Value for the current value is set with a resistor connected to the ISET pin.
Current sinks that are not used must be connected to the ground. Grounded current sinks are disabled and
excluded from the adaptive voltage and open/short LED fault detection loop.
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED
output PWM follows the input PWM so the output frequency is equal to the input frequency.
The LP8861-Q1 has extensive fault detection features:
• Open-string and shorted LED detections
– LED fault detection prevents system overheating in case of open or short in some of the LED strings
• VIN input-overvoltage protection
– Threshold sensing from VIN pin
• VIN input undervoltage protection
– Threshold sensing from VIN pin
• VIN input overcurrent protection
– Threshold sensing across RISENSE resistor
• Thermal shutdown in case of die overtemperature
• LED thermal protection with a external NTC (optional feature)
Fault condition is indicated with the FAULT output pin. Additionally, the LP8861-Q1 supports control for an
optional power-line FET allowing further protection in boost/SEPIC overcurrent state by disconnecting the device
from power-line in fault condition. With the power-line FET control it is possible to protect device, boost
components, and LEDs in case of shorted VBOOST and too-high VIN voltage. Power-line FET control also features
soft-start which reduces the peak current from the power line during start-up.
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7.2 Functional Block Diagram
RISENSE
VIN
L
Q
RGS
CIN
CIN BOOST
VIN
VSENSE_N
D
COUT
SD
POWER-LINE FET CONTROL
LDO
LDO
CLDO
SW
SYNC
RFSET
FSET
PGND
BOOST
CONTROLLER
FB
RISET
4 x LED
CURRENT
SINK
ISET
TSET
CURRENT
SETTING
OUT2
NTC
TSENSE
OUT3
PWM
OUT4
tº
VDDIO/
EN
FAULT
VDDIO
OUT1
GND
DIGITAL BLOCKS
(FSM, ADAPTIVE VOLTAGE
CONTROL, SAFETY LOGIC
etc.)
ANALOG BLOCKS
(CLOCK GENERATOR, VREF,
TSD etc.)
EXPOSED PAD
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7.3 Feature Description
7.3.1 Integrated Boost/SEPIC Converter
The LP8861-Q1 boost/SEPIC DC-DC converter generates supply voltage for the LEDs. The maximum output
voltage VMAX BOOST is defined by an external resistive divider (R1, R2).
Maximum voltage must be chosen based on the maximum voltage required for LED strings. Recommended VMAX
BOOST is about 30% higher than maximum LED string voltage. Initial DC-DC voltage is about 88% of VMAX BOOST.
DC-DC output voltage is adjusted automatically based on LED current sink headroom voltage. Maximum voltage
can be calculated with Equation 1:
§V
·
VMAX BOOST ¨ BG 0.0387 ¸ u R1 VBG
© R2
¹
where
•
•
•
VBG = 1.2 V
R2 recommended value is 130 kΩ
Resistors values are in kΩ
(1)
45
Maximum Converter Output Voltage (V)
40
35
30
25
20
15
10
200
300
400
500
600
700
800
900
1000
R1 (k )
C008
Figure 9. Maximum Converter Output Voltage vs R1 Resistance
The converter is a current mode DC-DC converter, where the inductor current is measured and controlled with
the feedback. Switching frequency is adjustable between 300 kHz and 2.2 MHz with RFSET resistor as Equation 2
in Equation 2:
ƒSW = 67600/ (RFSET + 6.4)
where
•
•
ƒSW is switching frequency, kHz
RFSET is frequency setting resistor, kΩ
(2)
In most cases lower frequency has higher system efficiency. Boost parameters are chosen automatically during
start-up according to the selected switching frequency (see Table 2). In boost mode a 15-pF capacitor CFB must
be placed across resistor R1 when operating in 300 kHz ... 500 kHz range (see Figure 24). When operating in
the 1.8-MHz...2.2-MHz range, CFB = 4.7 pF (see Figure 29).
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Feature Description (continued)
D
VIN
VBOOST
CIN
COUT
R1
SW
OCP
ADAPTIVE
VOLTAGE
CONTROL
RC
filter
FB
R2
LIGHT
LOAD
GM
S R
R
+
CURRENT
SENSE
OVP
R
R
PGND
SYNC
FSET
GM
FSET
CTRL
BOOST
OSCILLATOR
RFSET
OFF/BLANK
TIME
PULSE
GENERATOR
BLANK
TIME
CURRENT
RAMP
GENERATOR
Figure 10. Boost Block Diagram
Boost clock can be driven by an external SYNC signal between 300 kHz…2.2 MHz. If the external
synchronization input disappears, boost continues operation at the frequency defined by RFSET resistor. When
external frequency disappears and SYNC pin level is low, boost continues operation without spread spectrum
immediately. If SYNC remains high, boost continues switching with spread spectrum enabled after 256 µs.
External SYNC frequency must be 1.2…1.5 times higher than the frequency defined by the RFSET resistor.
Minimum frequency setting with RFSET is 250 kHz to support minimum switching frequency with external clock
frequency 300 kHz.
The optional spread-spectrum feature (±3% from central frequency, 1-kHz modulation frequency) reduces EMI
noise spikes at the switching frequency and its harmonic frequencies. When external synchronization is used,
spread spectrum is not available.
Table 1. Boost Synchronization Mode
SYNC PIN STATUS
Spread spectrum disabled
High
Spread spectrum enabled
300...2200 kHz frequency
14
MODE
Low
Spread spectrum disabled, external synchronization mode
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Table 2. Boost Parameters (1)
(1)
(2)
RANGE
FREQUENCY
(kHz)
TYPICAL
INDUCTANCE
(µH)
TYPICAL BOOST
INPUT
AND OUTPUT
CAPACITORS (µF)
MIN SWITCH
OFF TIME (ns) (2)
BLANK
TIME (ns)
CURRENT
RAMP (A/s)
CURRENT RAMP
DELAY (ns)
1
300...480
33
2 × 10 (cer.) + 33
(electr.)
150
95
24
550
2
480...1150
15
10 (cer.) +33 (electr.)
60
95
43
300
3
1150...1650
10
3 × 10 (cer.)
40
95
79
0
4
1650...2200
4.7
3 × 10 (cer.)
40
70
145
0
Parameters are for reference only.
Due to current sensing comparator delay the actual minimum off time is 6ns (typ.) longer than in the table.
Boost SW pin DC current is limited to 2 A (typical). To support warm start transient condition the current limit is
automatically increased to 2.5 A for a short period of 1.5 seconds when a 2-A limit is reached.
NOTE
Application condition where the 2-A limit is exceeded continuously is not allowed. In this
case the current limit would be 2 A for 1.5 seconds followed by 2.5-A limit for 1.5 seconds,
and this 3-second period repeats.
7.3.2 Internal LDO
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage. The LDO regulator
supplies internal and external circuitry. The maximum external load is 5 mA. Connect LDO output with a
minimum of 1-µF ceramic capacitor to ground as close to the LDO pin as possible. If an external voltage higher
than 4.5 V is connected to LDO pin, the internal LDO is disabled, and the internal circuitry is powered from the
external power supply. VIN and VSENSE_N pins must be connected to the same external voltage as LDO pin.
See Figure 29 for application schematic example.
7.3.3 LED Current Sinks
7.3.3.1 Current Sink Configuration
The LP8861-Q1 detects LED current sinks configuration during start-up. Any sink connected to the ground is
disabled and excluded from the adaptive boost control and fault detection.
7.3.3.2 Current Setting
Maximum current for the LED current sinks is controlled with external RISET resistor. RISET value for target
maximum current can be calculated using Equation 3:
RISET = 2342 / (IOUT ± 2.5)
where
•
•
RISET is current setting resistor, kΩ
IOUT is output current per output, mA
(3)
7.3.3.3 Brightness Control
The LP8861-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the
input PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz. Dimming ratio is calculated as ratio
between the input PWM period and minimum on/off time (0.5 μs).
7.3.4 Power Line FET Control
The LP8861-Q1 has a control pin (SD) for driving the gate of an external power-line FET. Power-line FET is an
optional feature; an example schematic is shown in Figure 24. Power-line FET limits inrush current by turning on
gradually when the device is enabled (VDDIO/EN = high, VIN > VGS). Inrush current is controlled by increasing
sink current for the FET gradually to 230 μA.
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In shutdown the LP8861-Q1 turns off the power-line FET and prevents the possible boost and LEDs leakage.
The power switch also turns off in case of any fault which causes the device to enter FAULT RECOVERY state.
7.3.5 LED Current Dimming with External Temperature Sensor
The LP8861-Q1 has an optional feature to decrease automatically LED current when LED overheating is
detected with an external NTC sensor. An example of the behavior is shown in Figure 11. When the NTC
temperature reaches T1, the LP8861-Q1 starts to decrease the LED current. When the LED current has reduced
to 17.5% of the nominal value, current turns off until temperature returns to the operation range. When TSET pin
is grounded this feature is disabled. Temperature T1 and de-rate slope are defined by external resistors as
explained below.
LED CURRENT
100%
17.5%
T1
T2
AMBIENT TEMPERATURE
Figure 11. Temperature-Based LED Current Dimming Functionality
VBG
ISET_SCALED
1:2000
ISET
+
LED OUT
RISET
VDD
ILED
R1
ITSENSE
R2
LED DRIVER
TSET
TSENSE
RT
R5
R3
R4
ITSENSE
NTC
Figure 12. Temperature-Based LED Current Dimming Implementation
When the TSET pin is grounded LED current is set by RISET resistor:
RISET = 2342 / (IOUT ± 2.5)
(4)
When external NTC is connected, the TSENSE pin current decreases LED output current. The following steps
describe how to calculate LED output current.
Parallel resistance of the NTC sensor RT and resistor R4 is calculated by formula:
RT u R4
RII
RT R4
16
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TSET voltage can be calculated with Equation 6:
R3
VTSET VDD u
R2 R3
(6)
TSENSE pin current is calculated by Equation 7:
RII
VTSET VDD u
RII R1
ITSENSE
RII2
RII R5
RII R1
(7)
ISET pin current defined by RISET is:
VBG
ISET _ SCALED
RISET
(8)
For Equation 9, ITSENSE current must be limited between 0 and ISET_SCALED. If ITSENSE > ISET_SCALED then set
ITSENSE = ISET_SCALED. If ITSENSE < 0 then set ITSENSE = 0.
LED driver output current is:
ILED = (ISET_SCALED – ITSENSE ) x 2 000
(9)
When current is lower than 17.5% of the nominal value, the current is set to 0 (so called cut-off point).
120
0.06
100
0.05
80
0.04
60
0.03
40
0.02
LED current
20
TSENSE Current (mA)
LED Current (mA)
An Excel® calculator is available for calculating the component values for a specific NTC and target thermal
profile (contact your local TI representative). Figure 13 shows an example thermal profile implementation.
0.01
TSENSE current
0.00
0
60
70
80
90
100
110
120
Temperature (ž&
C006
NTC – 10 kΩ at 25ºC
RISET = 24 kΩ
R2 = 10 kΩ
R4 = 100 kΩ
VDD = 4.3V
R1 = 10 kΩ
R3 = 2 kΩ
R5 = 7.5 kΩ
Figure 13. Calculation Example
7.3.6 Protection and Fault Detection
The LP8861-Q1 has fault detection for LED open and short, VIN input overvoltage (VIN_OVP), VIN undervoltage
lockout (VIN_UVLO), power line overcurrent (VIN_OCP), and thermal shutdown (TSD).
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7.3.6.1 Adaptive Boost Control and Functionality of LED Fault Comparators
Adaptive boost control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED
current sink operation. The output with highest VF LED string is detected and boost output voltage adjusted
accordingly. Boost adaptive control voltage step size is defined by maximum boost voltage settings, VSTEP =
(VMAX BOOST - VMIN BOOST) / 256. Periodic down pressure is applied to the target boost voltage to achieve better
system efficiency.
Every LED current sink has 3 comparators for an adaptive boost control and fault detection. Comparator outputs
are filtered, filtering time is 1 µs.
OUT#
SHORT STRING
DETECTION LEVEL
HIGH_COMP
VOLTAGE THRESHOLD
MID_COMP
LOWEST VOLTAGE
LOW_COMP
CURRENT/PWM
CONTROL
Figure 14. Comparators for Adaptive Voltage Control and LED Fault Detection
Figure 15 illustrates different cases which cause boost voltage increase, decrease, or generate faults. In normal
operation, voltage at all the OUT# pins is between LOW_COMP and MID_COMP levels and boost voltage stays
constant. LOW_COMP level is the minimum for proper LED current sink operation, 1.1 × VSAT + 0.2 V (typical).
MID_COMP level is 1.1 × VSAT + 1.2 V (typical) — that is, typical headroom window is 1 V.
When voltage at all the OUT# pins increases above MID_COMP level, boost voltage adapts downwards.
When voltage at any of the OUT# pins falls below LOW_COMP threshold, boost voltage adapts upwards. In the
condition where boost voltage reaches the maximum and there are one or more outputs still below LOW_COMP
level, an open LED fault is detected.
VOUT VOLTAGE
HIGH_COMP level, 6 V typical, is the threshold for shorted LED detection. When the voltage of one or more of
the OUT# pins increases above HIGH_COMP level and at least one of the other outputs is within the normal
headroom window, shorted LED fault is detected.
No actions
Boost
decreases
voltage
No actions
All outputs are
above headroom
window
HIGH_COMP
Shorted LED fault (at
least one output should
Open LED fault when
be between LOW_COMP
VBOOST = VSET BOOST MAX
and MID_COMP)
Boost
increases
voltage
Minimum
headroom
level reached
Shorted
LED fault
Open LED
fault
MID_COMP
HEADROOM
WINDOW
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
OUT4
OUT3
OUT1
OUT2
LOW_COMP
Figure 15. Boost Adaptation and LED Protection Algorithms
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7.3.6.2 Overview of the Fault/Protection Schemes
The LP8861-Q1 fault detection behavior is described in Table 3. Detected faults (excluding LED faults) cause the
device to enter FAULT_RECOVERY state. In FAULT_RECOVERY the boost and LED outputs of LP8861-Q1 are
disabled, power-line FET is turned off, and the FAULT pin is pulled low. Device recovers automatically and
enters normal operating mode (ACTIVE) after a recovery time of 100 ms if the fault condition has disappeared.
When recovery is successful, the FAULT pin is released.
In case a LED fault is detected, device continues normal operation and only the faulty string is disabled. Fault is
indicated via FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2…20 µs.
LEDs are turned off for this period but device stays in ACTIVE mode. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
Table 3. Fault/Protection Schemes
FAULT/
PROTECTION
FAULT_
RECOVERY
STATE
ACTION
Yes
Yes
1. Overvoltage is monitored from the beginning of soft start. Fault is
detected if the duration of overvoltage condition is 100 µs minimum.
2. Overvoltage is monitored from the beginning of normal operation
(ACTIVE mode). Fault is detected if overvoltage condition duration is
560 ms minimum (tfilter). After the first fault detection filter time is
reduced to 50 ms for following recovery cycles. When device
recovers and has been in ACTIVE mode for 160 ms, filter is
increased back to 560 ms.
Falling 3.9 V
Rising 4 V
Yes
Yes
Detects undervoltage condition at VIN pin. Sensed from the
beginning of soft start. Fault is detected if undervoltage condition
duration is 100 µs minimum.
3 A (50-mΩ current sensor
resistor)
Yes
Yes
Detects overcurrent by measuring voltage of the SENSE resistor
connected between VIN and VSENSE_N pins. Sensed from the
beginning of soft start. Fault is detected if undervoltage condition
duration is 10 µs minimum.
No
Detected if one or more outputs are below threshold level, and boost
adaptive control has reached maximum voltage. Open string(s) is
removed from voltage control loop and PWM is disabled.
Fault pin is cleaned by toggling VDDIO/EN pin. If VDDIO/EN is low
for a short period of 2…20 µs, LEDs are turned off for this period but
device stays ACTIVE. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
CONNECTED TO
FAULT PIN
FAULT NAME
THRESHOLD
VIN overvoltage
protection
VIN_OVP
1. VIN > 42 V
2. VBOOST > VSET_BOOST + (6...10)
V
VSET_BOOST is voltage value
defined by logic during
adaptation
VIN undervoltage
lockout
VIN_UVLO
VIN overcurrent
protection
VIN_OCP
Open LED fault
Shorted LED fault
Thermal
protection
OPEN_LED
LOW_COMP threshold
Yes
SHORT_LED
Shorted string detection level 6 V
Yes
No
Detected if one or more outputs voltages are above shorted string
detection level and at least one LED output voltage is within
headroom window. Shorted string(s) are removed from the boost
voltage control loop and outputs PWM(s) are disabled.
Fault pin is cleaned by toggling VDDIO/EN pin. If VDDIO/EN is low
for a short period of 2…20 µs, LEDs are turned off for this period but
device stays ACTIVE. If VDDIO/EN is low longer, device goes to
STANDBY and restarts when EN goes high again.
TSD
165ºC
Thermal Shutdown Hysteresis
20ºC
Yes
Yes
Thermal shutdown is monitored from the beginning of soft start. Die
temperature must decrease by 20ºC for device to recover.
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Time is not enough to
discharge COUT
VIN OVERVOLTAGE
VIN OK
VIN
VBOOST
VSET_BOOST +6...10 V
Powerline
FET state
ON
OFF
tFILTER = 560 ms
tRECOVERY =
100 ms
ON
OFF
tFILTER =
50 ms
tRECOVERY =
100 ms
OFF
ON
ON
IOUT
FAULT
tSOFTSTART +
tBOOST START
tSOFTSTART + tFILTER =
tRECOVERY =
tBOOST START 40 - 50 ms
100 ms
tSOFTSTART + tFILTER =
tBOOST START 50 ms
Figure 16. VIN Overvoltage Protection (Boost OVP)
VIN OVP threshold
VIN
BOOST OVP threshold
FB
Powerline
FET state
ON
OFF
FAULT
ttRECOVERY = 100 mst
ON
ttSOFTSTART +t
ttBOOST STARTUPt
ttRECOVERY = 100 mst
Figure 17. VIN Overvoltage Protection (VIN OVP)
UVLO falling threshold
UVLO rising threshold
VIN
FB
Powerline
FET state
ON
FAULT
OFF
ttRECOVERY = 100 mst
ON
ttRECOVERY = 100 mst
ttSOFTSTART +t
ttBOOST STARTUPt
Figure 18. VIN Undervoltage Lockout
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3 A @ 50 m
IIN
FB
Powerline
FET state
ON
OFF
ON
ttRECOVERY = 100 mst
OFF
ttSOFTSTART +t
ttBOOST STARTUPt
ttRECOVERY = 100 mst
FAULT
Figure 19. Input Voltage Overcurrent Protection
VBOOST SET MAX LEVEL
VBOOST
VOUT
OTHER LEDs
VOUT
OPEN LED
LOW_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 20. LED Open Fault
MID_COMP level
VOUT OTHER
LOW_COMP level
VOUT
SHORTED LED
HIGH_COMP level
t = 2...20 µs
VDDIO/EN
FAULT
Figure 21. LED Short Fault
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7.4 Device Functional Modes
7.4.1 Device States
The LP8861-Q1 enters STANDBY mode when the internal LDO output rises above the power-on reset level,
VLDO > VPOR_R. In STANDBY mode device is able to detect the VDDIO/EN signal. When VDDIO/EN is pulled
high, device powers up. During soft start the external power line FET is opened gradually to limit inrush current.
Soft start is followed by boost start, during which time boost voltage is ramped to the initial value. After boost
start LED outputs are sensed to detect grounded current sinks. Grounded current sinks are disabled and
excluded from the boost voltage control loop.
If a fault condition is detected, the LP8861-Q1 enters FAULT_RECOVERY state. In this state power line FET is
switched off and both the boost and LED current sinks are disabled. Fault that cause the device to enter
FAULT_RECOVERY are listed in Figure 22. When LED open or short is detected, faulty string is disabled but
LP8861-Q1 stays in ACTIVE mode.
POR = 1
STANDBY
VDDIO / EN = 1
100 ms
VIN_OCP
VIN_OVP
VIN_UVLO
TSD
SOFT START
65 ms
BOOST START
50 ms
FAULT RECOVERY
FAULTS
VDDIO / EN = 0
FAULT
RECOVERY?
FAULTS:
- VIN_OCP
- VIN_OVP
- VIN_UVLO
- TSD
NO
FAULTS
LED OUTPUT
CONFIGURATION
DETECTION
YES
ACTIVE
BOOST, LED CURRENT SINKS
AND POWER LINE FET ARE
DISABLED IN FAULT RECOVERY
STATE
VDDIO / EN = 0
SHUTDOWN
Figure 22. State Diagram
22
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Device Functional Modes (continued)
T = 50 s
t > 500 s
VIN
LDO
VDDIO/EN
SYNC
PL pFET drain
Headroom adaptation
VOUT = VIN level ± diode drop
VBOOST
PWM OUT
IQ
Active mode
SOFT
tSTARTt
tBOOSTt
START
Figure 23. Timing Diagram for the Typical Start-Up and Shutdown
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8861-Q1 is designed for automotive applications, and an input voltage VIN is intended to be connected to
the car battery. Device circuitry is powered from the internal LDO which, alternatively, can be used as external
VDD voltage — in that case, external voltage must be in the 4.5-V to 5.5-V range.
The LP8861-Q1 uses a simple four-wire control:
• VDDIO/EN for enable
• PWM input for brightness control
• SYNC pin for boost synchronisation (optional)
• FAULT output to indicate fault condition (optional)
8.2 Typical Applications
8.2.1 Typical Application for 4 LED Strings
Figure 24 shows the typical application for LP8861-Q1 which supports 4 LED strings with maximum current 100
mA and boost switching frequency of 300 kHz.
VIN
4.5...28 V RISENSE
Q1
L1
D1
CIN BOOST
Up to 37 V
COUT
RGS
R2
SW
R1
SD
VSENSE_N
FB
VIN
CIN
CLDO
CFB
Up to 100 mA/string
LDO
OUT1
LP8861-Q1
OUT2
RFSET
BRIGHTNESS
EN
FSET
OUT3
SYNC
OUT4
PWM
TSET
VDDIO/EN
FAULT
TSENSE
FAULT
R3
PGND
ISET
GND
PAD
RISET
VDDIO
Figure 24. Typical Application for Four Strings 100 mA/String Configuration
24
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Typical Applications (continued)
8.2.1.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…28 V
LED string
4 x 8 LEDs (30 V)
LED string current
100 mA
Max boost voltage
37 V
Boost switching frequency
300 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
33 μH
CIN
10 µF 50 V
CIN BOOST
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
COUT
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
CLDO
1 µF 10 V
CFB
15 pF
RISET
24 kΩ
RFSET
210 kΩ
RISENSE
50 mΩ
R1
750 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.
The saturation current must be greater than the sum of the maximum load current and the worst-case average to
peak inductor current. Equation 10 shows the worst-case conditions:
IOUTMAX
+ IRIPPLE For Boost
'¶
(VOUT - VIN) VIN
x
Where IRIPPLE =
(2 x L x f)
VOUT
ISAT >
Where D =
•
•
•
•
•
•
•
•
(VOUT ± VIN)
(VOUT)
DQG '¶ = (1 - D)
IRIPPLE - peak inductor current
IOUTMAX - maximum load current
VIN - minimum input voltage in application
L - min inductor value including worst case tolerances
ƒ - minimum switching frequency
VOUT - output voltage
D - Duty Cycle for CCM Operation
VOUT - Output Voltage
(10)
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As a result the inductor should be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A
saturation current rating at least 3 A is recommended for most applications. See Table 2 for inductance
recommendation for the different switch frequency ranges. The inductor’s resistance should be less than 300 mΩ
for good efficiency.
See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies (SLVA061).
Power Stage Designer™ Tools can be used for the boost calculation: http://www.ti.com/tool/powerstagedesigner.
8.2.1.2.2 Output Capacitor Selection
A ceramic and electrolytic capacitors should have sufficient voltage rating. The DC-bias effect in ceramic
capacitors can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendation for different switching frequency range is shown in Table 2. To
minimize audible of noise ceramic capacitors their geometric size is usually minimized.
8.2.1.2.3 Input Capacitor Selection
A ceramic and electrolytic capacitors should have sufficient voltage rating. The DC-bias effect in ceramic
capacitors can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Capacitance recommendation for different switching frequency range is shown in Table 2. To
minimize audible of noise ceramic capacitors their geometric size is usually minimized.
8.2.1.2.4 LDO Output Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The
DC-bias effect in ceramic capacitors can reduce the effective capacitance by up to 80%, which needs to be
considered in capacitance value selection. Typically a 1-µF capacitor is sufficient.
8.2.1.2.5 Diode
A Schottky diode should be used for the boost output diode. Ordinary rectifier diodes should not be used,
because slow switching speeds and long recovery times degrade the efficiency and the load regulation. Diode
rating for peak repetitive current should be greater than inductor peak current (up to 3 A) to ensure reliable
operation. Average current rating should be greater than the maximum output current. Schottky diodes with a low
forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage
of the Schottky diode significantly larger than the output voltage.
8.2.1.2.6 Power Line Transistor
A pFET transistor with necessary voltage rating (VDS at least 5 V higher than max input voltage) should be used.
Current rating for the FET should be the same as input peak current or greater. Transfer characteristic is very
important for pFET. VGS for open transistor should be less then VIN. A 20-kΩ resistor between pFET gate and
source is sufficient.
8.2.1.2.7 Input Current Sense Resistor
A high-power 50-mΩ resistor should be used for sensing the boost input current. Power rating can be calculated
from the input current and sense resistor resistance value. Increasing RISENSE decreases VIN OCP current
proportionally.
26
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8.2.1.3 Application Curves
SD 2V/div
VBOOST 10V/div
IBOOST 200mA/div
VDDIO/EN 5 V/div
20ms/div
40ms/div
OUT1/OUT2/BOOST 10V/div
FAULT 2V/div
ƒSW = 300 kHz
VIN = 10 V
Brightness PWM 50% 100 Hz
Figure 26. Open LED Fault
100
100
95
95
System efficiency (%)
Boost efficiency (%)
Figure 25. Typical Start-up
90
85
80
VIN=5V
75
VIN=8V
70
VIN=12V
90
85
80
VIN=5V
75
VIN=8V
70
VIN=12V
VIN=16V
VIN=16V
65
65
0
20
40
60
80
100
Brightness (%)
Load 4 strings, 8 LED per string
I = 100 mA/string for VIN = 12 V and 16 V
I = 60 mA/sting for VIN = 8 V
I = 50 mA/string for VIN = 5 V
0
40
60
80
100
Brightness (%)
C011
ƒSW= 300 kHz
20
C012
Load 4 strings, 8 LED per string
ƒSW = 300 kHz
I = 100 mA/string for VIN = 12 V and VIN = 16 V
I = 60 mA/sting for VIN = 8 V
I = 50 mA/string for VIN = 5 V
Figure 27. Boost Efficiency
Figure 28. System Efficiency
8.2.2 High Output Current Application
The LP8861-Q1 current sinks can be tied together to drive LED with higher current. To drive 200 mA per string 2
outputs can be connected together. All 4 outputs connected together can drive an up to 400-mA LED string.
Device circuitry is powered from external VDD voltage.
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VIN
4.5...28 V
L1
Q1
D1
CIN BOOST
CIN
Up to 37 V
COUT
R2
SW
R1
SD
VSENSE_N
FB
VIN
CFB
Up to 200 mA/string
VDD 5 V
LDO
CLDO
OUT1
LP8861-Q1
OUT2
RFSET
BRIGHTNESS
EN
FSET
OUT3
SYNC
OUT4
TSET
PWM
TSENSE
VDDIO/EN
FAULT
FAULT
R3
PGND
ISET
GND
RISET
PAD
VDDIO
Figure 29. Two Strings 200 mA/String Configuration
8.2.2.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…28 V
LED string
2 x 8 LEDs (30 V)
LED string current
200 mA
Max boost voltage
37 V
Boost switching frequency
2.2 MHz
External boost sync
not used
Boost spread spectrum
disabled
L1
4.7 μH
CIN
10 µF 50 V
CIN BOOST
2 × 10-µF, 50-V ceramic
COUT
3 × 10-µF, 50-V ceramic
CLDO
1 µF 10 V
CFB
4.7 pF
RISET
24 kΩ
RFSET
24 kΩ
R1
750 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
8.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
8.2.2.3 Application Curves
See Application Curves.
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8.2.3 SEPIC Mode Application
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. The SW pin
voltage is equal to the sum of the input voltage and output voltage in SEPIC mode — this fact limits the
maximum input voltage in this mode. LED current sinks not used should be connected to ground. External
frequency can be used to synchronize boost/SEPIC switching frequency, and external frequency can be
modulated to spread switching frequency spectrum.
RISENSE
VIN
D1
Q1
L1
CIN SEPIC
C1
COUT
RGS
R2
SW
R1
SD
VSENSE_N
FB
VIN
CIN
CLDO
Up to 100 mA/string
LDO
OUT1
LP8861-Q1
RFSET
OUT2
FSET
BOOST SYNC
BRIGHTNESS
EN
OUT3
SYNC
OUT4
PWM
TSET
VDDIO/EN
FAULT
TSENSE
FAULT
R3
PGND
ISET
GND
PAD
RISET
VDDIO
Figure 30. SEPIC Mode, 4 Strings 100 mA/String Configuration
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8.2.3.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…30 V
LED string
4 x 4 LEDs (14.5 V)
LED string current
100 mA
Max boost voltage
17.5 V
Boost switching frequency
300 kHz
External boost sync
used
Boost spread spectrum
not available with external sync
L1
33 μH
CIN
10 µF 50 V
CIN SEPIC
2 × 10-µF, 50-V ceramic + 33-µF 50-V electrolytic
C1
10-µF 50-V ceramic
COUT
2 × 10-µF, 50-V ceramic +33-µF 50-V electrolytic
CLDO
1 µF 10 V
RISET
24 kΩ
RFSET
210 kΩ
RISENSE
50 mΩ
R1
390 kΩ
R2
130 kΩ
R3
10 kΩ
RGS
20 kΩ
8.2.3.2 Detailed Design Procedure
See Detailed Design Procedure for external component recommendations. The Power Stage Designer™ Tools
can be use for defining SEPIC component current and voltage ratings according to application:
http://www.ti.com/tool/powerstage-designer
8.2.3.2.1 Diode
A Schottky diode with a low forward drop and fast switching speed should be used for the SEPIC output diode.
Do not use ordinary rectifier diodes, because slow switching speeds and long recovery times degrade the
efficiency and load regulation. The diode must be able to handle peak repetitive current greater than the
integrated FET peak current (SW pin limit), thus 3 A or higher must be used to ensure reliable operation.
Average current rating should be greater than the maximum output current. Choose a diode with reverse
breakdown larger than the sum of input voltage and output voltage.
8.2.3.2.2 Inductor
Coupled or uncoupled inductors can be used in SEPIC mode. Coupled inductor typically provides better
efficiency. Power Stage Designer™ Tools can be used for the SEPIC inductance calculation:
http://www.ti.com/tool/powerstage-designer.
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8.2.3.3 Application Curves
100
100
95
95
VIN=12V
90
VIN=14V
System efficiency (%)
SECIC efficiency (%)
VIN=8V
90
85
80
VIN=8V
75
VIN=12V
70
VIN=14V
40
60
80
0
100
Brightness (%)
Load 4 strings, 4 LED per string
I = 100 mA/string
75
65
65
20
80
70
VIN=18V
0
VIN=18V
85
20
40
60
80
100
Brightness (%)
C015
C016
Load 4 strings, 4 LED per string
I = 100 mA/string
ƒSW= 300 kHz
ƒSW= 300 kHz
Figure 32. System Efficiency
Figure 31. SEPIC Efficiency
8.2.4 Application with Temperature Based LED Current De-rating
The LP8881-Q1 is able to protect connected LED strings from overheating. LED current versus temperature
behavior can be adjusted with external resistor as described in LED Current Dimming with External Temperature
Sensor.
VIN
4.5...30 V RISENSE
Q1
L1
D1
CIN BOOST
Up to 43 V
COUT
RGS
R2
SW
R1
SD
VSENSE_N
CIN
FB
VIN
VLDO
CLDO
CFB
Up to 50 mA/string
LDO
OUT1
LP8861-Q1
OUT2
RFSET
BRIGHTNESS
EN
FSET
OUT3
VLDO
SYNC
OUT4
R4
PWM
TSET
TSENSE
VDDIO/EN
FAULT
FAULT
R8
PGND
R3
R7
RTº
ISET
GND
PAD
R6
R5
RISET
NTC
VDDIO
Figure 33. Temperature Based LED Current De-rating
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8.2.4.1 Design Requirements
DESIGN PARAMETER
VALUE
VIN voltage range
4.5…30 V
LED string
4 x 9 LEDs (33 V)
LED string current
50 mA
Max boost voltage
43 V
Boost switching frequency
400 kHz
External boost sync
not used
Boost spread spectrum
enabled
L1
33 μH
CIN
10-µF 50-V ceramic
CIN BOOST
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
COUT
2 × 10-µF, 50-V ceramic + 33-µF, 50-V electrolytic
CLDO
1 µF 10 V
CFB
15 pF
RISET
48 kΩ
RFSET
160 kΩ
RISENSE
50 mΩ
R1
866 kΩ
R2
130 kΩ
R3
12 kΩ
R4
10 kΩ
R5
1.8 kΩ
R6
82 kΩ
R7
16 kΩ
R8
10 kΩ
RT
10 kΩ @ 25ºC
RGS
20 kΩ
8.2.4.2 Detailed Design Procedure
See Detailed Design Procedure.
8.2.4.3 Application Curve
60
LED Current (mA)
50
40
30
20
10
0
60
65
70
75
80
85
90
95
100
105
110
Temperature (ž&
C007
Figure 34. LED Current vs Temperature
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9 Power Supply Recommendations
The LP8861-Q1 device is designed to operate from a car battery. The device should be protected from reverse
voltage polarity and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that
the input current transient does not cause too high drop at the LP8861-Q1 VIN pin. If the input supply is
connected by using long wires additional bulk capacitance may be required in addition to the ceramic bypass
capacitors in the VIN line.
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10 Layout
10.1 Layout Guidelines
Figure 35 is a layout recommendation for the LP8861-Q1 used to demonstrate the principles of good layout. This
layout can be adapted to the actual application layout if or where possible. It is important that all boost
components are close to the chip, and the high current traces must be wide enough. By placing boost
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This
way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must as
close as possible to the device.
Here are some main points to help the PCB layout work:
• Current loops need to be minimized:
– For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to the SW and PGND pins. Input and output capacitor grounds need to be close to each other to
minimize current loop size
– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High-frequency return currents try to find route with minimum impedance, which
is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the “positive” current route in the ground plane, if the ground plane is intact
under the route
• GND plane needs to be intact under the high current boost traces to provide shortest possible return path and
smallest possible current loops for high frequencies.
• Current loops when the boost switch is conducting and not conducting need to be on the same direction in
optimal case.
• Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating
inductor 180° changes current direction.
• Use separate power and noise-free grounds. Power ground is used for boost converter return current and
noise-free ground for more sensitive signals, like LDO bypass capacitor grounding as well as grounding the
GND pin of the device itself.
• Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the
diode cathode.
• Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
• Input and output capacitors need strong grounding (wide traces, many vias to GND plane).
• If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.
• Output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to
become unstable on some loads; this increases EMI. DC bias characteristics need to be obtained from the
component manufacturer; DC bias is not taken into account on component tolerance. X5R/X7R capacitors are
recommended.
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10.2 Layout Example
RISENSE
VIN
RGS
LDO
1
VIN
VSENSE_N
20
2
LDO
SD
19
3
FSET
SW
18
RFSET
4
PGND
17
FAULT
5
FB
16
SYNC
6
OUT1
15
PWM
7
OUT2
14
TSENSE
8
OUT3
13
TSET
9
OUT4
12
GND
11
RISET
10
ISET
VBOOST
LED STRINGS
VDDIO/EN
Figure 35. LP8861-Q1 Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For additional information, see the following:
• Using the LP8861-Q1EVM Evaluation Module (SNVU456)
• PowerPAD™ Thermally Enhanced Package Application Note (SLMA002)
• TI Application Note Understanding Boost Power Stages in Switch Mode Power Supplies (SLVA061)
• Power Stage Designer™ Tools, http://www.ti.com/tool/powerstage-designer
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LP8861QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
20
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
LP8861Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LP8861QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
20
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP8861QPWPRQ1
HTSSOP
PWP
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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