SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 !" # $ % FEATURES ANALOG FEATURES D 24 Bits No Missing Codes D 22 Bits Effective Resolution at 10Hz − Low Noise: 75nV D PGA From 1 to 128 D Precision On-Chip Voltage Reference D D D D D D D D − Accuracy: 0.2% − Drift: 5ppm/°C 8 Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.1ppm/°C Gain Drift: 0.5ppm/°C On-Chip Temperature Sensor Selectable Buffer Input Burnout Detect 16-Bit Monotonic Voltage DACS: − Quad Voltage DACs (MSC1211, MSC1212) − Dual Voltage DACs (MSC1213, MSC1214) DIGITAL FEATURES Microcontroller Core D 8051-Compatible D High-Speed Core − 4 Clocks per Instruction Cycle D DC to 40MHz at +85C D Single Instruction 100ns D Dual Data Pointer Memory D Up To 32kB Flash Memory D Flash Memory Partitioning D Endurance 1M Erase/Write Cycles, 100-Year Data Retention D In-System Serially Programmable D External Program/Data Memory (64kB) D 1,280 Bytes Data SRAM D Flash Memory Security D 2kB Boot ROM D Programmable Wait State Control Peripheral Features D 34 I/O Pins D Additional 32-Bit Accumulator D Three 16-Bit Timer/Counters D System Timers D Programmable Watchdog Timer D Full-Duplex Dual USARTs D Master/Slave SPI with DMA D Multi-master I2C (MSC1211 and MSC1213) D 16-Bit PWM D Power Management Control D Internal Clock Divider D Idle Mode Current < 200µA D Stop Mode Current < 100nA D Programmable Brownout Reset D Programmable Low-Voltage Detect D 24 Interrupt Sources D Two Hardware Breakpoints GENERAL FEATURES D D D D D Pin-Compatible with MSC1210 Package: TQFP-64 Low Power: 4mW Industrial Temperature Range: −40°C to +125°C Power Supply: 2.7V to 5.25V APPLICATIONS D D D D D D D D D D D Industrial Process Control Instrumentation Liquid/Gas Chromatography Blood Analysis Smart Transmitters Portable Instruments Weigh Scales Pressure Transducers Intelligent Sensors Portable Applications DAS Systems Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips corporation. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. Copyright 2004−2007, Texas Instruments Incorporated &'()*'+ ) , $ - , .-/ 0 - , $ . , . $ , ) 1 * -$ %0 - . % - , . $ 0 www.ti.com www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PACKAGE/ORDERING INFORMATION(1) PRODUCT FLASH MEMORY 16-BIT DACS I2C PACKAGE MARKING MSC1211Y2 4k 4 Y MSC1211Y2 MSC1211Y3 8k 4 Y MSC1211Y3 MSC1211Y4 16k 4 Y MSC1211Y4 MSC1211Y5 32k 4 Y MSC1211Y5 MSC1212Y2 4k 4 N MSC1212Y2 MSC1212Y3 8k 4 N MSC1212Y3 MSC1212Y4 16k 4 N MSC1212Y4 MSC1212Y5 32k 4 N MSC1212Y4 MSC1213Y2 4k 2 Y MSC1213Y2 MSC1213Y3 8k 2 Y MSC1213Y3 MSC1213Y4 16k 2 Y MSC1213Y4 MSC1213Y5 32k 2 Y MSC1213Y5 MSC1214Y2 4k 2 N MSC1214Y2 MSC1214Y3 8k 2 N MSC1214Y3 MSC1214Y4 16k 2 N MSC1214Y4 MSC1214Y5 32k 2 N MSC1214Y5 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our web site at www.ti.com. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) MSC1211/12/13/14 UNITS Momentary 100 mA Continuous 10 mA AGND − 0.3 to AVDD + 0.3 V DVDD to DGND −0.3 to +6 V AVDD to AGND −0.3 to +6 V AGND to DGND −0.3 to +0.3 V VREF to AGND −0.3 to AVDD + 0.3 V Digital input voltage to DGND −0.3 to DVDD + 0.3 V Digital output voltage to DGND −0.3 to DVDD + 0.3 V +150 °C Operating temperature range −40 to +125 °C Storage temperature range −65 to +150 °C High K (2s 2p) 48.9 °C/W Low K (1s) 72.9 °C/W 12.2 °C/W Analog Inputs Input current Input voltage Power Supply Maximum junction temperature (TJ Max) Thermal resistance Junction to ambient (qJA) Junction to case (qJC) Package power dissipation (TJ Max − TAMBIENT)/qJA W Output current, all pins 200 mA Output pin short-circuit 10 s Digital Outputs Output current 100 mA I/O source/sink current Continuous 100 mA Power pin maximum 300 mA (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 MSC121xYX FAMILY FEATURES FEATURES(1) MSC121xY2(2) MSC121xY3(2) MSC121xY4(2) MSC121xY5(2) Flash Program Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Flash Data Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Internal Scratchpad SRAM (Bytes) 256 256 256 256 Internal MOVX RAM (Bytes) 1024 1024 1024 1024 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data Externally Accessible Memory (Bytes) (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2N)kBytes. ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS AGND − 0.1 AVDD + 0.1 V AGND + 50mV AVDD − 1.5 ±VREF/PGA V V MΩ nA Analog Inputs (AIN0−AIN7, AINCOM) Buffer OFF Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Fast Settling Filter Bandwidth Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Buffer ON (AIN+) − (AIN−) Buffer OFF Buffer ON −3dB 7/PGA(1) 0.5 0.469 • fDATA 0.318 • fDATA −3dB −3dB User-Selectable Gain Range Buffer ON Multiplexer Channel OFF, T = +25°C Buffer ON 0.262 • fDATA 1 128 9 0.5 ±2 pF pA µA ±VREF/(2 • PGA) V Bits % of Range ppm/°C ADC Offset DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift Bipolar Mode 8 ±1.5 1 System Performance Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(2) Gain Error(3) Gain Error Drift(2) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection Normal-Mode Rejection Power-Supply Rejection (1) (2) (3) (4) (5) (6) (7) (8) 24 See Typical Characteristics Sinc3 Filter, Decimation > 360 End Point Fit, Bipolar Mode After Calibration Before Calibration After Calibration Before Calibration Bits Bits 22 See Typical Characteristics 24 At DC 115 Bits %FSR ppm of FS ppm of FS/°C % ppm/°C % of FS % of FS dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50HZ, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz At DC, dB = −20log(∆VOUT/∆VDD)(4) 100 92 dB dB 0.0003 ±3.5 0.1 −0.002 0.5 80 −50 ±0.0015 120 50 The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 3 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS AVDD(3) V Voltage Reference Inputs Reference Input Range REF IN+, REF IN− VREF VREF ≡ (REF IN+) − (REF IN−) VREF Common-Mode Rejection At DC Input Current(5) DAC Reference Input Resistance AGND 0.1 2.5 AVDD V 110 dB VREF = 2.5V, ADC Only 1 µA For Each DAC, PGA = 1 20 kΩ On-Chip Voltage Reference Output Voltage VREFH = 1 at +25°C, REFCLK = 250kHz 2.495 2.5 2.505 V 1.25 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 2.6 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration VREFH = 0 at +25°C, REFCLK = 250kHz Sink or Source Indefinite Drift 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power ON CREFOUT = 0.1µF 8 ms Temperature Sensor Voltage Buffer ON, T = +25°C 115 mV Temperature Sensor Coefficient Buffer ON 375 µV/°C Voltage DAC Static Performance(6) Resolution 16 Relative Accuracy Differential Nonlinearity Ensured Monotonic by Design Zero Code Error All 0s Loaded to DAC Register Full-Scale Error All 1s Loaded to DAC Register Gain Error −1.25 −1.25 Bits ±0.05 ±0.146 %FSR ±1 LSB +13 +35 0 0 mV % of FSR +1.25 % of FSR Zero Code Error Drift ±20 µV/°C Gain Temperature Coefficient ±5 ppm of FSR/°C Voltage DAC Output Characteristics(7) Output Voltage Range REF IN+ = AVDD Output Voltage Settling Time To ±0.003% FSR, 0200h to FD00h AGND AVDD V 8 µs Slew Rate 1 V/µs DC Output Impedance 7 Ω 20 mA 25 mA Short-Circuit Current All 1s Loaded to DAC Register IDAC Output Characteristics Full-Scale Output Current Maximum VREF = 2.5V Maximum Short-Circuit Current Duration Indefinite Compliance Voltage Relative Accuracy AVDD − 1.5 V 0.185 % of FSR Zero Code Error All 0s Loaded to DAC Register 0.5 µA Full-Scale Error All 1s Loaded to DAC Register −0.4 % of FSR −0.6 % of FSR Gain Error (1) (2) (3) (4) (5) (6) (7) (8) 4 The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +5V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX 5 5.25 UNITS Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Off Current(8) (1) (2) (3) (4) (5) (6) (7) (8) 4.75 V Analog OFF, PDCON = 48h <1 nA PGA = 1, Buffer OFF 200 µA PGA = 128, Buffer OFF 500 µA PGA = 1, Buffer ON 240 µA PGA = 128, Buffer ON 850 µA VDAC Current (IVDAC) Excluding Load Current, External Reference 250 µA VREF Supply Current (IVREF) ADC ON, VDAC OFF 250 µA ADC Current (IADC) Analog Power-Supply Current AVDD The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Inputs (AIN0−AIN7, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (AIN+) − (AIN−) Differential Input Impedance Buffer OFF Input Current Buffer ON Bandwidth ±VREF/PGA V 7/PGA(1) MΩ 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Sinc2 Filter −3dB 0.318 • fDATA Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range Input Capacitance Buffer ON Input Leakage Current Multiplexer Channel OFF, T = +25°C 0.5 pA Burnout Current Sources Sensor Input Open Circuit ±2 µA (1) (2) (3) (4) (5) (6) (7) (8) 1 128 9 pF The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 5 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS ADC Offset DAC Offset DAC Range ±VREF/(2•PGA) Bipolar Mode Offset DAC Monotonicity V 8 Bits Offset DAC Gain Error Offset DAC Gain Error Drift ±1.5 % of Range 1 ppm/°C System Performance Resolution 24 Bits ENOB 22 Output Noise Bits See Typical Characteristics No Missing Codes Sinc3 Filter Integral Nonlinearity End Point Fit, Bipolar Mode Offset Error After Calibration ±3.5 ppm of FS Offset Drift(2) Before Calibration 0.1 ppm of FS/°C Gain Error(3) After Calibration Gain Error Drift(2) Before Calibration 24 Bits 0.0003 ±0.0015 %FSR −0.002 % 1.0 ppm/°C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS Common-Mode Rejection Normal Mode Rejection Power-Supply Rejection At DC 115 dB fCM = 60Hz, fDATA = 10Hz 130 dB fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB fSIG = 50Hz, fDATA = 50Hz 100 dB fSIG = 60Hz, fDATA = 60Hz 100 dB At DC, dB = −20log(∆VOUT/∆VDD)(4) 92 dB Voltage Reference Inputs Reference Input Range REF IN+, REF IN− VREF VREF ≡ (REF IN+) − (REF IN−) VREF Common-Mode Rejection At DC Input Current(5) DAC Reference Input Resistance AVDD(3) AGND 0.1 1.25 AVDD V V 110 dB VREF = 1.25V, ADC Only 3 µA For Each DAC, PGA = 1 20 kΩ On-Chip Voltage Reference Output Voltage VREFH = 0 at +25°C, REFCLK = 250kHz 1.245 1.25 1.255 V Power-Supply Rejection Ratio 65 dB Short-Circuit Current Source 2.6 mA Short-Circuit Current Sink 50 µA Short-Circuit Duration Sink or Source Drift Indefinite 5 ppm/°C Output Impedance Sourcing 100µA 3 Ω Startup Time from Power ON CREFOUT = 0.1µF 8 ms Temperature Sensor Voltage Buffer ON, T = +25°C 115 mV Temperature Sensor Coefficient Buffer ON 375 µV/°C (1) (2) (3) (4) (5) (6) (7) (8) 6 The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, AVDD = +3V, fMOD = 15.625kHz, PGA = 1, filter = Sinc3, Buffer ON, fDATA = 10Hz, Bipolar, fCLK = 8MHz, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1211/12/13/14 PARAMETER CONDITIONS MIN TYP MAX UNITS ±0.05 ±0.146 % of FSR ±1 LSB +13 +35 Voltage DAC Static Performance(6) Resolution 16 Relative Accuracy Differential Nonlinearity Ensured Monotonic by Design Zero Code Error All 0s Loaded to DAC Register Full-Scale Error All 1s Loaded to DAC Register Gain Error −1.25 −1.25 Bits 0 0 mV % of FSR ±1.25 % of FSR Zero Code Error Drift ±20 µV/°C Gain Temperature Coefficient ±5 ppm of FSR/°C Voltage DAC Output Characteristics(7) Output Voltage Range AGND V µs Slew Rate 1 V/µs DC Output Impedance 7 Ω 16 mA 25 mA Short-Circuit Current To ±0.003% FSR, 0200h to FD00h AVDD 8 Output Voltage Settling Time All 1s Loaded to DAC Register IDAC Output Characteristics Full-Scale Output Current Maximum VREF = 1.25V Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD − 1.5 V 0.185 % of FSR Zero Code Error 0.5 % of FSR Full-Scale Error −0.4 % of FSR Gain Error −0.6 % of FSR Relative Accuracy Over Full Range Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Off Current(8) Analog Power-Supply Current (1) (2) (3) (4) (5) (6) (7) (8) AVDD 2.7 3.0 3.6 V Analog OFF, PDCON = 47h <1 nA PGA = 1, Buffer OFF 200 µA PGA = 128, Buffer OFF 500 µA PGA = 1, Buffer ON 240 µA PGA = 128, Buffer ON 850 µA VDAC Current (IVDAC) Excluding Load Current, External Reference 250 µA VREF Supply Current (IVDAC) ADC ON, VDAC OFF 250 µA ADC Current (IADC) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. ∆VOUT is change in digital result. 9pF switched capacitor at fSAMP clock frequency (see Figure 14). Linearity calculated using a reduced code range of 512 to 65024; output unloaded. Ensured by design and characterization; not production tested. Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1). 7 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, FMCON = 10h, all digital outputs high, PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), PSEN and ALE enabled (all peripherals ON) or PSEN and ALE disabled (all peripherals OFF), unless otherwise specified. MSC1211/12/13/14 PARAMETER MIN CONDITIONS TYP MAX 3 3.6 UNITS Digital Power-Supply Requirements DVDD 2.7 Digital Power-Supply Current 0.9 mA Normal Mode, fOSC = 1MHz, peripherals ON 1.1 mA Normal Mode, fOSC = 8MHz, peripherals OFF 5.7 mA Normal Mode, fOSC = 8MHz, peripherals ON 7.5 mA Crystal Operation Stop Mode(1) 100 DVDD 4.75 Digital Power-Supply Current V Normal Mode, fOSC = 1MHz, peripherals OFF nA 5 5.25 V Normal Mode, fOSC = 1MHz, peripherals OFF 1.7 mA Normal Mode, fOSC = 1MHz, peripherals ON 2.4 mA Normal Mode, fOSC = 8MHz, peripherals OFF 11 mA Normal Mode, fOSC = 8MHz, peripherals ON 14.8 mA Crystal Operation Stop Mode(1) 100 nA DIGITAL INPUT/OUTPUT (CMOS) Logic Level VIH (except XIN pin) 0.6 • DVDD DVDD VIL (except XIN pin) DGND 0.2 • DVDD I/O Pin Hysteresis Ports 0−3, Input Leakage Current, Input Mode VIH = DVDD or VIH = 0V Pins EA, RST Input Leakage Current VOL, ALE, PSEN, Ports 0−3, All Output Modes VOH, ALE, PSEN, Ports 0−3, Strong Drive Output mV <1 pA pA DGND 0.4 IOL = −30mA (5V), −20mA (3V) V 1.5 IOH = 1mA DVDD − 0.4 IOH = 30mA (5V), 20mA (5V) V DVDD − 0.1 DVDD V DVDD − 1.5 V 9 kΩ 9 kΩ Ports 0−3, Pull-Up Resistors Pins ALE, PSEN, Pull-Up Resistors During Reset V 700 <1 IOL = −1mA V Flash Programming Mode Only OSCILLATOR/CLOCK INPUT/OUTPUT External Oscillator/Clock VIH (except XIN pin) XOUT must be unconnected 0.6 • DVDD DVDD V VIL (except XIN pin) XOUT must be unconnected DGND 0.2 • DVDD V (1) Digital Brownout Detect disabled (HCR1.2 = 1), Low Voltage Detect disabled (LVDCON.3 = 1). Ports configured for CMOS output low. FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V MSC1211/12/13/14 PARAMETER CONDITIONS Flash Memory Endurance Flash Memory Data Retention MIN TYP 100,000 1,000,000 Set with FER in FTCON 10 Flash Memory Write Time Set with FWR in FTCON 30 Years ms 40 µs DVDD = 3.0V 10 mA DVDD = 5.0V 25 mA (1) Peak current during Mass and Page Erase Time and Memory Write Time. 8 UNITS Cycles 100 Mass and Page Erase Time Flash Programming Current(1) MAX www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V 2.7V to 3.6V 4.75V to 5.25V FIGURE PARAMETER MIN MAX MIN MAX UNITS fOSC(3) 4 1/tOSC(3) 4 External Crystal Frequency (fOSC) External Clock Frequency (fOSC) at +85°C 1 0 24 24 1 0 33 40 MHz MHz fOSC(3) 4 External Clock Frequency (fOSC) at +125°C External Ceramic Resonator Frequency (fOSC) 0 1 22 12 0 1 36 12 MHz MHz 1 1 1 1 1 1 1 1 1 1 1 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float 1.5tCLK − 5 0.5tCLK − 10 0.5tCLK RD Pulse Width (tMCS = 0)(4) RD Pulse Width (tMCS > 0)(4) WR Pulse Width (tMCS = 0)(4) WR Pulse Width (tMCS > 0)(4) RD Low to Valid Data In (tMCS = 0)(4) RD Low to Valid Data In (tMCS > 0)(4) Data Hold After Read Data Float After Read (tMCS = 0)(4) Data Float After Read (tMCS > 0)(4) ALE Low to Valid Data In (tMCS = 0)(4) ALE Low to Valid Data In (tMCS > 0)(4) Address to Valid Data In (tMCS = 0)(4) Address to Valid Data In (tMCS > 0)(4) ALE Low to RD or WR Low (tMCS = 0)(4) ALE Low to RD or WR Low (tMCS > 0)(4) Address to RD or WR Low (tMCS = 0)(4) Address to RD or WR Low (tMCS > 0)(4) Data Valid to WR Transition Data Hold After WR RD Low to Address Float RD or WR High to ALE High (tMCS = 0)(4) RD or WR High to ALE High (tMCS > 0)(4) 2tCLK − 5 tMCS − 5 2tCLK − 5 tMCS − 5 SYMBOL System Clock Program Memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ 1.5tCLK − 5 0.5tCLK − 7 0.5tCLK 2.5tCLK − 35 0.5tCLK 2tCLK − 5 2.5tCLK − 25 0.5tCLK 2tCLK − 5 2tCLK − 40 5 2tCLK − 30 −5 tCLK − 5 3tCLK − 40 0 tCLK 3tCLK − 25 0 ns ns ns ns ns ns ns ns ns ns ns Data Memory tRLRH 2 tWLWH 3 tRLDV 2 tRHDX 2 tRHDZ 2 tLLDV 2 tAVDV 2 tLLWL 2, 3 tAVWL 2, 3 tQVWX tWHQX tRLAZ 3 3 2 tWHLH 2, 3 2tCLK − 5 tMCS − 5 2tCLK − 5 tMCS − 5 −0.5tCLK − 5 5 tCLK + 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 ns ns ns ns 2tCLK − 40 tMCS − 40 −5 2tCLK − 30 tMCS − 30 −5 tCLK 2tCLK 2.5tCLK − 40 tCLK + tMCS − 40 3tCLK − 40 tCLK 2tCLK 2.5tCLK − 25 tCLK + tMCS − 25 3tCLK − 25 1.5tCLK +tMCS −40 0.5tCLK − 5 tCLK − 5 tCLK − 5 2tCLK − 5 −8 tCLK − 8 0.5tCLK + 5 tCLK + 5 −0.5tCLK − 5 5 tCLK + 5 −5 tCLK − 5 1.5tCLK + tMCS −25 0.5tCLK − 5 tCLK − 5 tCLK − 5 2tCLK − 5 −5 tCLK − 5 −5 tCLK − 5 0.5tCLK + 5 tCLK + 5 External Clock tHIGH tLOW tR tF (1) (2) (3) (4) (5) High Time(5) Low Time(5) Rise Time(5) Fall Time(5) 4 4 4 4 15 15 10 10 5 5 Parameters are valid over operating temperature range, unless otherwise specified. Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF. tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection: These values are characterized, but not 100% production tested. MD2 MD1 MD0 MOVX DURATION 0 0 0 2 Machine Cycles tMCS 0 0 0 1 3 Machine Cycles (default) 4tCLK 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 4 Machine Cycles 5 Machine Cycles 6 Machine Cycles 7 Machine Cycles 8 Machine Cycles 9 Machine Cycles 8tCLK 12tCLK 16tCLK 20tCLK 24tCLK 28tCLK 9 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 EXPLANATION OF THE AC SYMBOLS Each Timing Symbol has five characters. The first character is always ’t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designators are: RRD Signal AAddress CClock tTime DInput Data VValid HLogic Level High WWR Signal IInstruction (program memory contents) XNo Longer a Valid Logic Level LLogic Level Low, or ALE ZFloat PPSEN Examples: (1) tAVLL = Time for address valid to ALE Low. QOutput Data (2) tLLPL = Time for ALE Low to PSEN Low. tLHLL ALE tAVLL t PLPH tLLPL tLLIV tPLIV PSEN tPXIZ t LLAX tPLAZ A0−A7 PORT 0 tPXIX INSTR IN A0−A7 tAVIV A8−A15 PORT 2 A8−A15 Figure 1. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL t LLAX tRLAZ PORT 0 tRHDZ tRLDV A0−A7 from RI or DPL t RHDX DATA IN A0−A7 from PCL t AVWL tAVDV PORT 2 P2.0−P2.7 or A8−A15 from DPH Figure 2. External Data Memory Read Cycle 10 A8−A15 from PCH INSTR IN www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ALE tWHLH PSEN tLLWL tWLWH WR tAVLL tLLAX tQ V W X tWHQX t DW PORT 0 A0−A7 from RI or DPL DATA OUT A0−A7 from PCL INSTR IN tAVWL PORT 2 P2.0−P2.7 or A8−A15 from DPH A8−A15 from PCH Figure 3. External Data Memory Write Cycle t HIGH VIH1 0.8V tr VIH1 0.8V VIH1 tLOW tf VIH1 0.8V 0.8V t OSC Figure 4. External Clock Drive CLK 11 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 RESET AND POWER-ON TIMING tRW RST tRRD tRFD tRRD tRFD PSEN ALE tRS tRH EA NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high. Figure 5. Reset Timing, User Application Mode tRW RST tRFD tRRD PSEN tRS tRRD tRH ALE NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high. Figure 6. Parallel Flash Programming Power-On Timing (EA is ignored) tRW RST tRS tRRD tRH PSEN t RFD t RRD ALE NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high. Figure 7. Serial Flash Programming Power-On Timing (EA is ignored) Table 1. Serial/Parallel Flash Programming Timing SYMBOL 12 PARAMETER tRW tRRD RST width tRFD tRS RST falling to PSEN and ALE start tRH RST falling to input signal hold time RST rise to PSEN ALE internal pull high Input signal to RST falling setup time MIN MAX 2tOSC — — UNIT — 5 µs — (217 + 512)tOSC — tOSC (217 + 512)tOSC — — — — www.ti.com P0.3/AD3 P0.4/AD4 P0.5/AD5 58 P0.2/AD2 59 P0.1/AD1 P1.2/RxD1 60 P0.0/AD0 P1.3/TxD1 61 P1.0/T2 P1.4/INT2/SS 62 P1.1/T2EX P1.5/INT3/MOSI 63 DGND P1.6/INT4/MISO/SDA(1) 64 DVDD P1.7/INT5/SCK/SCL(1) SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 57 56 55 54 53 52 51 50 49 XOUT 1 48 EA XIN 2 47 P0.6/AD6 P3.0/RxD0 3 46 P0.7/AD7 P3.1/TxD0 4 45 ALE P3.2/INT0 5 44 PSEN/OSCCLK/MODCLK P3.3/INT1/TONE/PWM 6 43 P2.7/A15 P3.4/T0 7 P3.5/T1 8 P3.6/WR 9 42 DVDD MSC1211 MSC1212 MSC1213 MSC1214 P3.7/RD 10 41 DGND 40 P2.6/A14 39 P2.5/A13 DVDD 11 38 P2.4/A12 DGND 12 37 P2.3/A11 RST 13 36 P2.2/A10 DVDD 14 35 P2.1/A09 DVDD 15 34 P2.0/A08 33 NC(3) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AIN0/IDAC0 AIN1/IDAC1 AIN2/VDAC2(2) (2) AIN4 AIN5 AIN6/EXTD AIN7/EXTA AINCOM AGND AVDD REF IN− REFOUT/REF IN+ VDAC1 RDAC1 AIN3/VDAC3 17 VDAC0 RDAC0 16 NOTES: (1) SCL and SDA are only available on the MSC1211 and MSC1213. (2) VDAC2 and VDAC3 are only available on the MSC1211 and MSC1212. (3) NC pin should be left unconnected. 13 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN 3-10 P3.0-P3.7 The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. Refer to P3DDR, SFR B3h−B4h. Port Alternate Name(s) Alternate Use P3.0 RxD0 Serial port 0 input P3.1 TxD0 Serial port 1 input P3.2 INT0 External interrupt 0 P3.3 INT1/TONE/PWM External interrupt 1/TONE/PWM output P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External memory data write strobe P3.7 RD External memory data read strobe 11, 14, 15, 42, 58 DVDD Digital Power Supply 12, 41, 57 DGND Digital Ground 13 RST 16 RDAC0 IDAC0 Reference Resistor Pin 17 VDAC0 VDAC0 Output 27 AGND Analog Ground 18 AIN0/IDAC0 Analog Input Channel 0 / IDAC0 Output 19 AIN1/IDAC1 Analog Input Channel 1 / IDAC1 Output 20 AIN2/VDAC2 Analog Input Channel 2 / VDAC2 Output (MSC1211 and MSC1212 only) 21 AIN3V/DAC3 Analog Input Channel 3 / VDAC3 Output (MSC1211 and MSC1212 only) 22 AIN4 Analog Input Channel 4 23 AIN5 Analog Input Channel 5 24 AIN6/EXTD Analog Input Channel 6 / LVD Comparator Input, Generates DLVD Interrupt 25 AIN7/EXTA Analog Input Channel 7 / LVD Comparator Input, Generates ALVD Interrupt 26 AINCOM 28 AVDD Holding the reset input high for two tOSC periods will reset the device. Analog Common; can be used like any analog input except during Offset − Inputs shorted to this pin. Analog Power Supply 29 REF IN− 30 REFOUT/REF IN+ Voltage Reference Negative Input (must be tied to AGND for internal VREF use) 31 VDAC1 VDAC1 Output 32 RDAC1 IDAC1 Reference Resistor Pin 33 NC 34-40, 43 P2.0-P2.7 Internal Voltage Reference Output / Voltage Reference Positive Input No Connection; leave unconnected. Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Refer to P2DDR, SFR B1h−B2h. Port Alternate Name Alternate Use P2.0 A8 Address bit 8 P2.1 A9 Address bit 9 P2.2 A10 Address bit 10 P2.3 A11 Address bit 11 P2.4 A12 Address bit 12 P2.5 A13 Address bit 13 P2.6 A14 Address bit 14 P2.7 A15 Address bit 15 (1) SDA and SCL are only available on the MSC1213. 14 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PIN DESCRIPTIONS (continued) PIN # NAME 44 PSEN OSCCLK MODCLK DESCRIPTION Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held high for parallel programming and held low for serial programming. This pin can also be selected (when not using external memory) to output the Oscillator clock, Modulator clock, high, or low. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. ALE PSEN Program Mode Selection During Reset NC NC Normal operation (User Application mode) 0 NC Parallel programming NC 0 Serial programming 0 0 Reserved 45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define serial or parallel programming mode. ALE is held high for serial programming and held low for parallel programming. This pin can also be selected (when not using external memory) to output high or low. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. 48 EA External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations starting with 0000h. No internal pull-up on this pin. 46, 47, 49-54 P0.0-P0.7 55, 56, 59-64 P1.0-P1.7 Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Port Alternate Name Alternate Use P0.0 AD0 Address/Data bit 0 P0.1 AD1 Address/Data bit 1 P0.2 AD2 Address/Data bit 2 P0.3 AD3 Address/Data bit 3 P0.4 AD4 Address/Data bit 4 P0.5 AD5 Address/Data bit 5 P0.6 AD6 Address/Data bit 6 P0.7 AD7 Address/Data bit 7 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEh−AFh. Port Alternate Name(s) Alternate Use P1.0 T2 T2 input P1.1 T2EX T2 external input P1.2 RxD1 Serial port input P1.3 TxD1 Serial port output P1.4 INT2/SS External Interrupt / Slave Select P1.5 INT3/MOSI External Interrupt / Master Out-Slave In P1.6 INT4/MISO/SDA(1) External Interrupt / Master In-Slave Out / SDA P1.7 INT5/SCK/SCL(1) External Interrupt / Serial Clock (1) SDA and SCL are only available on the MSC1213. 15 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22 PGA2 PGA1 PGA1 PGA8 21 PGA32 PGA64 20 PGA4 PGA8 19 PGA128 ENOB (rms) ENOB (rms) EFFECTIVE NUMBER OF BITS vs DATA RATE 18 PGA16 17 PGA32 PGA64 16 15 14 Sinc3 Filter, Buffer OFF Sinc3 Filter, Buffer OFF 13 12 1 10 100 Data Rate (SPS) 1000 0 500 1000 1500 20 20 19 19 18 17 PGA128 PGA64 PGA32 16 PGA16 PGA8 PGA4 18 17 PGA16 PGA32 PGA128 PGA64 16 15 15 14 14 Sinc3 Filter, Buffer ON AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF 13 13 12 12 0 500 1000 1500 Decimation Ratio = 0 2000 500 f MOD 1000 1500 Decimation Ratio = fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 2000 f MOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 21 PGA4 PGA2 PGA8 21 PGA1 20 20 19 19 ENOB (rms) ENOB (rms) PGA2 PGA1 21 PGA1 ENOB (rms) ENOB (rms) 21 22 PGA8 PGA4 PGA2 fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 2000 fMOD Decimation Ratio = 18 17 16 PGA16 15 PGA32 PGA128 PGA64 PGA4 18 17 PGA32 PGA16 PGA64 PGA128 16 14 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON 13 PGA8 PGA1 15 14 Sinc2 Filter 13 12 12 0 500 1000 Decimation Ratio = 16 PGA128 1500 fMOD fDATA 2000 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 25 20 19 fMOD = 203kHz Gain 1 20 18 Gain 16 16 ENOB (rms) ENOB 17 15 14 Gain 128 13 fMOD = 15.6kHz fMOD = 110kHz 15 fMOD = 31.25kHz 10 5 12 fMOD = 62.5kHz 11 0 10 0 500 1500 1000 1 2000 10 100 1k Data Rate (SPS) 10k 100k Decimation Value EFFECTIVE NUMBER OF BITS vs INPUT SIGNAL (Internal and External VREF) EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION, PGA = 1 25 DEC = 2020 22.0 DEC = 500 20 21.0 DEC = 255 15 DEC = 50 Internal ENOB (rms) ENOB (rms) External 21.5 DEC = 20 10 20.5 20.0 19.5 19.0 5 DEC = 10 18.5 18.0 0 10 100 1k Data Rate (SPS) 10k − 2.5 100k − 1.5 − 0.5 NOISE vs INPUT SIGNAL 1.5 2.5 INL ERROR vs PGA 100 0.8 90 0.7 80 0.6 INL (ppm of FS) Noise (rms, ppm of FS) 0.5 VIN (V) 0.5 0.4 0.3 0.2 60 50 40 30 20 0.1 0 −2.5 70 10 0 −1.5 −0.5 0.5 VIN (V) 1.5 2.5 1 2 4 8 16 32 64 128 PGA Setting 17 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INL (ppm of FS) 10 15 AVDD = 5V VREF = 2.5V Buffer ON +85_C 5 0 +125_C +25_C −5 −40_ C −10 −15 −2.5 30 −2 −1.5 −1 −0.5 0 5 0 +85_ C 0.5 1 1.5 2 2.5 −55_C ADC INTEGRAL NONLINEARITY vs INPUT SIGNAL ADC INTEGRAL NONLINEARITY vs VREF 5.5 AVDD = 3V 25 20 AVDD = 5V 15 10 5 0 VIN = −VREF 0 0 VIN = +VREF 0.5 1.0 1.5 2.0 PGA = 128, ADC ON, Brownout Detect ON, All VDACs ON = FFFFh, VDACs REF = AVDD 2.5 3.0 3.5 4.0 4.5 VREF (V) ANALOG SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE ADC CURRENT vs PGA 900 +125_C AVDD = 5V, Buffer = ON 800 +85_ C Buffer = OFF 700 600 2.2 +25_C 2.1 2.0 −40_C 1.9 IADC (µA) Analog Supply Current (mA) 5.0 Buffer OFF VIN (V) 500 AVDD = 3V, Buffer = ON 400 Buffer = OFF 300 1.8 200 1.7 100 1.6 1.5 2.5 3.0 3.5 4.0 4.5 Analog Supply Voltage (V) 18 2.5 30 −20 2.3 2.0 35 VREF = AVDD Buffer OFF −10 2.4 1.5 VIN (V) 0 2.5 1.0 VIN (V) 10 2.6 +125_ C −5 −40_C −15 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 ADC INL (ppm of FS) ADC INL (ppm of FS) +25_C −10 20 −30 AVDD = 5V VREF = 2.5V Buffer OFF 10 ADC INL (ppm of FS) 15 5.0 5.5 0 0 1 2 4 8 16 PGA Setting 32 64 128 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. PGA SUPPLY CURRENT NORMALIZED GAIN vs PGA 101 AVDD = DVDD fCLK = 8MHz VIN = 0V 250 100 AVDD = 5.0V 200 Buffer OFF Normalized Gain (%) PGA Supply Current (µA) 300 150 100 AVDD = 3.0V 99 98 Buffer ON 97 50 96 0 1 2 4 8 32 16 64 128 1 2 4 8 16 32 64 128 125 150 PGA Setting PGA Gain HISTOGRAM OF TEMPERATURE SENSOR VALUES ADC OFFSET vs TEMPERATURE (Offset Calibration at +25_C Only) 200 10 6 150 ADC Offset (ppm) Number of Occurrences 8 100 50 4 2 0 −2 −4 −6 −8 −10 −50 117.0 116.5 116.0 115.5 115.0 114.5 114.0 113.5 113.0 112.5 112.0 111.5 111.0 0 −25 0 25 50 75 100 Temperature (_C) Temperature Sensor Value (mV) OFFSET DAC: GAIN vs TEMPERATURE 1.00008 15 1.00006 10 1.00004 Normalized Gain Offset (ppm of FSR) OFFSET DAC: OFFSET vs TEMPERATURE 20 5 0 −5 1.00002 1 0.99998 −10 0.99996 −15 0.99994 −20 −40 0.99992 +25 Temperature (_C) +125 −40 +25 +125 Temperature (_C) 19 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. VREFOUT vs LOAD CURRENT 2.510 4000 2.508 3500 2.506 3000 2.504 VREFOUT (V) Number of Occurrences HISTOGRAM OF OUTPUT DATA 4500 2500 2000 1500 2.502 2.500 2.498 2.496 1000 2.494 500 2.492 0 −2 −1.5 −1 2.490 −0.5 0 0.5 1 1.5 2 0 0.4 ppm of FS DIGITAL SUPPLY CURRENT vs FREQUENCY 1.2 1.6 2.0 2.4 DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER 100 100 IMIN, DVDD = 5V Digital Supply Current (mA) Digital Supply Current (mA) 0.8 VREFOUT Current Load (mA) IMAX, DVDD = 5V IMAX, DVDD = 3V IMIN, DVDD = 3V 10 IMAX IDLE, DVDD = 5V IMIN IDLE, DVDD = 3V Divider Values OFF 2 4 10 8 16 32 1024 2048 1 4096 IMIN: PDCON = FFh, PSEN and ALE disabled, LVDCON = FFh IMAX: PDCON = 00h, PSEN and ALE enabled, LVDCON = 00h 1 1 10 Clock Frequency (MHz) 0.1 1 100 10 Clock Frequency (MHz) DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE CMOS DIGITAL OUTPUT 15 5.0 +125_C +25_ C −40_C 10 5V Low Output 4.0 Output Voltage (V) Digital Supply Current (mA) 4.5 3.5 3V Low Output 3.0 2.5 2.0 1.5 5V 1.0 0.5 5 3V 0 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 20 100 5.0 5.5 0 10 20 30 40 Output Current (mA) 50 60 70 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDAC DIFFERENTIAL NONLINEARITY vs CODE VDAC INTEGRAL NONLINEARITY vs CODE 1.0 40 +125_C 20 0.8 0.6 +85_ C DNL (LSB) INL (LSB) 0.4 0 0 −0.2 −0.4 +25_ C −20 0.2 −0.6 −0.8 −40_ C −40 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh −1.0 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh DAC Code DAC Code VDAC SOURCE CURRENT CAPABILITY VDAC SINK CURRENT CAPABILITY 5.0 0.6 DAC = All 0s DAC = All 1s 0.5 VDAC Output (V) 4.8 4.7 4.6 0.4 0.3 0.2 0.1 4.5 0 0 2 4 6 8 10 12 14 16 0 2 4 6 ISOURCE (mA) 8 10 12 14 16 ISINK (mA) VDAC FULL−SCALE ERROR vs LOAD RESISTOR 1 0 Error (% of FS) VDAC Output (V) 4.9 −1 −2 −3 −4 −5 0.5 1 10 100 1k 10k Load Resistor (kΩ) 21 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS: VDACs (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, filter = Sinc3, Buffer ON, and VREF ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise specified. For VDAC: VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF unless otherwise noted. VDAC FULL−SCALE SETTLING TIME Scope Trigger (5.0V/div) VDAC FULL−SCALE SETTLING TIME Scope Trigger (5.0V/div) Full−Scale Code Change 0200H to FFFFH Output Loaded with 10kΩ and 200pF to GND Large−Signal Output (1.0V/div) Full−Scale Code Change FFFFH to 0200H Output Loaded with 10kΩ and 200pF to GND Large−Signal Output (1.0V/div) Time (1µs/div) Time (1µs/div) VDAC HALF−SCALE SETTLING TIME VDAC HALF−SCALE SETTLING TIME Scope Trigger (5.0V/div) Half−Scale Code Change 4000H to C000H Output Loaded with 10kΩ and 200pF to GND Large−Signal Output (1.0V/div) Scope Trigger (5.0V/div) Half−Scale Code Change C000H to 4000H Output Loaded with 10kΩ and 200pF to GND Large−Signal Output (1.0V/div) Time (1µs/div) 22 Time (1µs/div) www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DESCRIPTION The MSC1211/12/13/14 are completely integrated families of mixed-signal devices incorporating a high-resolution delta-sigma (∆Σ) ADC, 16-bit DACs, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, Programmable Gain Amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 8. On-chip peripherals include an additional 32-bit accumulator, an SPI-compatible serial port with FIFO, dual USARTs, multiple digital input/output ports, a watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, breakpoints, brownout reset, three timer/counters, and a system clock divider. The MSC1211 and MSC1213 also contain a hardware I2C peripheral. The devices accept low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a Sinc3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution, single-cycle conversion. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. This design makes it possible to run the devices at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. The MSC1211/12/13/14 allow users to uniquely configure the Flash and SRAM memory maps to meet the needs of their applications. The Flash is programmable down to 2.7V using both serial and parallel programming methods. The Flash endurance is 100k Erase/Write cycles. In addition, 1280 bytes of RAM are incorporated on-chip. The parts have separate analog and digital supplies, which can be independently powered from 2.7V to +5.25V. At +3V operation, the power dissipation for each part is typically less than 4mW. The MSC1211/12/13/14 are all available in a TQFP-64 package. The MSC1211/12/13/14 are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. REFOUT/REF IN+ REF IN− (1) AVDD AGND DVDD DGND AVDD Burnout Detect VREF LVD Timers/ Counters PSEN BOR 8−Bit Offset DAC Temperature Sensor AIN0/IDAC0 AIN1/IDAC1 EA ALE WDT Alternate Functions AIN2/VDAC2(3) AIN3/VDAC3(3) AIN4 BUFFER MUX Digital Filter Modulator PGA AIN5 Up to 32K FLASH AIN6/EXTD AIN7/EXTA V/I Converter AINCOM IDAC0/ AIN1 Burnout Detect 32−Bit Accumulator VDAC0 V/I Converter IDAC1/ AIN1 VDAC1 AIN2 VDAC2(3) 1.2K SRAM PORT0 8 ADDR DATA PORT1 8 T2 SPI/EXT/I2C(2) USART1 PORT2 8 ADDR PORT3 8 8051 SFR SPI FIFO AIN3 VDAC3(3) POR SYS Clock Divider Clock Generator USART0 EXT T0 T1 PWM RW RST AGND RDAC0 RDAC1 VDAC0 VDAC1 XIN XOUT NOTES: (1) REF IN− must be tied to AGND when using internal VREF. (2) I 2C only available on the MSC1213. (3) VDAC2 and VDAC3 only available on MSC1211 and MSC1212. Figure 8. Block Diagram 23 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ENHANCED 8051 CORE The MSC1211/12/13/14 also provide dual data pointers (DPTRs) to speed block Data Memory moves. Additionally, both devices can stretch the number of memory cycles to access external Data Memory from between two and nine instruction cycles in order to accommodate different speeds of memory or devices, as shown in Table 2. The MSC1211/12/13/14 provide an external memory interface with a 16-bit address bus (P0 and P2). The 16-bit address bus makes it necessary to multiplex the low address byte through the P0 port. To enhance P0 and P2 for high-speed memory access, hardware configuration control is provided to configure the ports for external memory/peripheral interface or general-purpose I/O. MSC1211/12/13/14 Timing Single-Byte, Single-Cycle Instruction ALE PSEN AD0−AD7 PORT 2 4 Cycles CLK 12 Cycles Standard 8051 Timing All instructions in the MSC1211/12/13/14 families perform exactly the same functions as they would in a standard 8051. The effects on bits, flags, and registers is the same; however, the timing is different. The MSC1211/12/13/14 families utilize an efficient 8051 core which results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 9). This efficiency translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. Therefore, a device frequency of 40MHz for the MSC1211/12/13/14 actually performs at an equivalent execution speed of 100MHz compared to the standard 8051 core. This increased performance allows the the device to be run at slower external clock speeds, which reduces system noise and power consumption, but provides greater throughput. This performance difference can be seen in Figure 10. The timing of software loops will be faster with the MSC1211/12/13/14. However, the timer/counter operation of the MSC1211/12/13/14 may be maintained at 12 clocks per increment, or optionally run at 4 clocks per increment. ALE PSEN AD0−AD7 PORT 2 Single-Byte, Single-Cycle Instruction Figure 10. Comparison of MSC1211/12/13/14 Timing to Standard 8051 Timing CKCON (8Eh) MD2:MD0 INSTRUCTION CYCLES (for MOVX) RD or WR STROBE WIDTH (SYS CLKs) RD or WR STROBE WIDTH (µs) AT 12MHz 000 001 010 011 100 101 110 111 2 3 (default) 4 5 6 7 8 9 2 4 8 12 16 20 24 28 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333 Table 2. Memory Cycle Stretching (stretching of MOVX timing as defined by MD2, MD1, and MD0 bits in CKCON register at address 8Eh). CLK instr_cycle cpu_cycle n+1 C1 C2 n+2 C3 C4 C1 C2 Figure 9. Instruction Timing Cycle 24 C3 C4 C1 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency. For instance, the SPI interface uses a FIFO, which allows the SPI interface to transmit and receive data with minimum overhead needed from the core. Also, a 32-bit accumulator was added to significantly reduce the processing overhead for multiple byte data from the ADC or other sources. This allows for 32-bit addition, subtraction and shifting to be accomplished in a few instruction cycles, compared to hundreds of instruction cycles executed through software implementation. This gives the user the ability to add or subtract software functions and to freely migrate between family members. Thus, the MSC1211/12/13/14 can become a standard device used across several application platforms. Family Development Tools The MSC1211/12/13/14 are fully compatible with the standard 8051 instruction set. This compatibility means that users can develop software for the MSC1211/12/13/14 with their existing 8051 development tools. Additionally, a complete, integrated development environment is provided with each demo board, and third-party developers also provide support. Family Device Compatibility Power-Down Modes The hardware functionality and pin configuration across the MSC1211/12/13/14 families are fully compatible. To the user, the only differences between family members are the memory configuration, the number of DACs, and the availability of I2C for the MSC1211 and MSC1213. This design makes migration between family members simple. fOSC STOP The MSC1211/12/13/14 can each power several of the on-chip peripherals and put the CPU into Idle mode. This is accomplished by shutting off the clocks to those sections, as shown in Figure 11. fSYS SYSCLK C7 fCLK SPICON/ I2CCON(1) 9A f CLK SCL/SCK PDCON.0 PWMHI A3 PDCON.4 µs USEC ms PWM Clock Flash Write FTCON [3:0] EF Timing FB MSECH MSECL FD FC PWMLOW A2 Flash Erase FTCON (5ms to 11ms) [7:4] EF Timing milliseconds interrupt MSINT REFCLK SEL DC divide by 4 (30µs to 40µs) FA REF CLOCK PDCON.1 100ms HMSEC FE fACLK seconds interrupt SECINT F9 watchdog WDTCON interrupt FF PDCON.2 ACLK F6 divide by 64 Analog Power Down ADC Output Rate ADCON3 ADCON2 DF DE Decimation Ratio ADCON0 DC PDCON.3 fDATA f SAMP (see Figure 14) f MOD Timers 0/1/2 IDLE CPUClock USART 0/1 NOTE: (1) I2CCON only available on the MSC1211 and MSC1213. Figure 11. MSC1211/12/13/14 Timing Chain and Clock Control 25 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 OVERVIEW TEMPERATURE SENSOR The MSC1211/12/13/14 ADC structure is shown in Figure 12. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. On-chip diodes provide temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diodes are connected to the inputs of the ADC. All other channels are open. ADC INPUT MULTIPLEXER BURNOUT DETECT The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 13. For example, if AIN0 is selected as the positive differential input channel, then any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels with common connections between them. It is also possible to switch the polarity of the differential input pair to negate any offset voltages. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins. When the Burnout Detect (BOD) bit is set in the ADC control configuration register (ADCON0 DCh), two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. The current sources allow for the detection of an open circuit (full-scale reading) or short circuit (small differential reading) on the selected input differential pair. The buffer should be on for sensor burnout detection. AVDD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM REFOUT/ REFIN+ Burnout Detect fSAMP Input Multiplexer In+ Sample and Hold Buffer In− Σ PGA Temperature Sensor Burnout Detect D7h ADMUX REFOUT/ REFIN+ fMOD Offset DAC REFIN− AGND DCh ADC0N0 F6h fDATA ACLK E6h ODAC A4h AIPOL.5 A4h AIPOL.6 A6h AIE.5 A6h AIE.6 A7h AISTAT.5 A7h AISTAT.6 FAST VIN ∆Σ ADC Modulator SINC2 SINC3 AUTO REFIN− Σ X Offset Calibration Register Gain Calibration Register ADC Result Register Summation Block Σ DDh ADCON1 OCR GCR ADRES DEh ADCON2 D3h D2h D1h D6h D5h D4h DBh DAh D9h DFh ADCON3 SUMR E5h E4h E3h E2h E1h Figure 12. MSC1211/12/13/14 ADC Structure 26 SSCON www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC ANALOG INPUT When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6h) and gain (PGA). The relationship is: AIN0 AIN1 Impedance (W) + AVDD AIN Impedance (W) + Burnout Detect (2µA) AIN2 1 f SAMP @ CS 10 Ǔ ǒACLK1 Frequency Ǔ @ ǒ7MW PGA 6 where ACLK frequency (f ACLK) + AIN3 In+ and modclk + f MOD + Buffer AIN4 In− AIN7 f ACLK . 64 NOTE: The input impedance for PGA = 128 is the same as that for PGA = 64 ( that is, 7MW). 64 AIN5 AIN6 f CLK ACLK ) 1 Burnout Detect (2µA) Temperature Sensor AVDD AVDD AGND 80 • I I Figure 14 shows the basic input structure of the MSC1211/12/13/14. The sampling frequency varies according to the PGA settings, as shown in the table in Figure 14. AINCOM RSWITCH (3k typical) High Impedance > 1GΩ AIN CS (9pF typical) Figure 13. Input Multiplexer Configuration Sampling Frequency = f SAMP AGND ADC INPUT BUFFER The analog input impedance is always high, regardless of PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always preferred. The input impedance of the MSC1211/12/13/14 without the buffer is 7MΩ/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0 DCh). PGA 1 2 4 to 128 PGA 1 2 4 8 16 32 64 128 NOTE: BIPOLAR MODE FULL-SCALE RANGE ±VREF ±VREF/2 ±VREF/4 ±VREF/8 ±VREF/16 ±VREF/32 ±VREF/64 ±VREF/128 UNIPOLAR MODE FULL-SCALE RANGE +VREF +VREF/2 +VREF/4 +VREF/8 +VREF/16 +VREF/32 +VREF/64 +VREF/128 CS 9pF 18pF 36pF fSAMP fMOD fMOD fMOD fMOD S 2 fMOD S 4 fMOD S 8 fMOD S 16 fMOD S 16 fMOD = ACLK frequency/64 Figure 14. Analog Input Structure 27 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range (FSR), the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV FSR, the ADC can resolve to 75nV, as shown in Table 3. Table 3. Sampling Frequency versus PGA Setting PGA SETTING BIPOLAR MODE FULL-SCALE RANGE (V) ENOB(1) AT 10HZ RMS INPUT-REFERRED NOISE (nV) 1 2 4 8 16 32 64 128 ±2.5V ±1.25 ±0.625 ±0.313 ±0.156 ±0.0781 ±0.039 ±0.019 21.7 21.5 21.4 21.2 20.8 20.4 20 19 1468 843 452 259 171 113 74.5 74.5 (1) ENOB = Log2(FSR/RMS Noise) = Log2(224) − Log2(σCODES) = 24 − Log2(σCODES) ADC OFFSET DAC For system calibration, the appropriate signal must be applied to the inputs. The system offset calibration requires a zero input signal. It then computes an offset that will nullify offset in the system. The system gain calibration requires a positive full-scale input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. Calibration should be performed after power on. It should also be done after a change in temperature, decimation ratio, buffer, Power Supply, voltage reference, or PGA. The Offset DAC wil affect offset calibration; therefore, the value of the Offset DAC should be zero until prior to performing a calibration. At the completion of calibration, the ADC Interrupt bit goes high, which indicates the calibration is finished and valid data is available. ADC DIGITAL FILTER The Digital Filter can use either the Fast Settling, Sinc2, or Sinc3 filter, as shown in Figure 15. In addition, the Auto mode changes the Sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter for the next two conversions, the first of which should be discarded. The analog input to the PGA can be offset (in bipolar mode) by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6h). The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, using the ODAC does not reduce the range of the ADC. The modulator is a single-loop, 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from the CLK using the value in the Analog Clock (ACLK) register (SFR F6h). The data output rate is: where f MOD + f MOD Decimation Ratio f CLK f + ACLK 64 (ACLK ) 1) @ 64 and Decimation Ratio is set in [ADCON3:ADCON2]. ADC CALIBRATION The offset and gain errors in the MSC1211/12/13/14, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDh), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. 28 Sinc3 Modulator ADC MODULATOR Data Rate + f DATA + Adjustable Digital Filter Sinc2 Data Out Fast Settling FILTER SETTLING TIME SETTLING TIME FILTER (Conversion Cycles)(1) Sinc3 3 Sinc2 2 Fast 1 NOTE: (1) MUX change may add one cycle. AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 2 3 Fast Fast Sinc2 4 Sinc3 Figure 15. Filter Step Responses www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 It will then use the Sinc2 followed by the Sinc3 filter to improve noise performance. This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 16. The internal voltage reference can be selected as either 1.25V or 2.5V. The analog power supply (AVDD) must be within the specified range for the selected internal voltage reference. The valid ranges are: VREF = 2.5 internal (AVDD = 3.3V to 5.25V) and VREF = 1.25 internal (AVDD = 2.7V to 5.25V). If the internal VREF is selected, then AGND must be connected to REF IN−. The REFOUT/REF IN+ pin should also have a 0.1µF capacitor connected to AGND as close as possible to the pin. If the internal VREF is not used, then VREF should be disabled in ADCON0. If the external voltage reference is selected, it can be used as either a single-ended input or differential input, for ratiometric measures. When using an external reference, it is important to note that the input current will increase for VREF with higher PGA settings and with a higher modulator frequency. The external voltage reference can be used over the input range specified in the Electrical Characteristics section. For applications requiring higher performance than that obtainable from the internal reference, use an external precision reference such as the REF50xx. The internal reference performance can be observed in the noise (and ENOB) versus input signal graphs in the Typical Characteristics section. All of the other ENOB plots are obtained with the inputs shorted together. By shorting the inputs, the inherent noise performance of only the ADC can be determined and displayed. When the inputs are not shorted, the extra noise comes from the reference. As can be seen in the ENOB vs Input Signal graph, the external reference adds about 0.7 bits of noise, whereas the internal reference adds about 2.3 bits of noise. This ENOB performance of 19.4 represents 21.16 bits of noise. With an LSB of 298nV, that translates to 6.3µV or a peak-to-peak noise of almost 42µV. The internal reference is initialized each time power is applied. That initialization can cause a shift in the output that is within the specified accuracy. An external reference provides the best noise, drift, and repeatability performance for high-precision applications. −20 Gain (dB) −40 −60 −80 −100 −120 0 1 2 3 4 5 4 5 fDATA SINC 2 FILTER RESPONSE (−3dB = 0.318 • fDATA) 0 −20 −40 Gain (dB) The MSC1211/12/13/14 can use either an internal or external voltage reference. The voltage reference selection is controlled via ADC Control Register 0 (ADCON0, SFR DCh). The default power-up configuration for the voltage reference is 2.5V internal. 0 −60 −80 −100 −120 0 1 2 3 fDATA FAST SETTLING FILTER RESPONSE (−3dB = 0.469 • fDATA ) 0 −20 −40 Gain (dB) VOLTAGE REFERENCE SINC3 FILTER RESPONSE (−3dB = 0.262 • f DATA) −60 −80 −100 −120 0 1 2 3 4 5 fDATA NOTE: fDATA = Normalized Data Output Rate = 1/tDATA Figure 16. Filter Frequency Responses 29 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 VDAC DAC OUTPUT AMPLIFIER The architecture of the MSC1211/12/13/14 consists of a string DAC followed by an output buffer amplifier. Figure 17 shows a block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which provides an output range of AGND to AVDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1V/µs with a full-scale settling time of 8µs. The input coding to the DAC is straight binary, so the ideal output voltage is given by: VDAC + VREF @ D Ǔ ǒ65536 DAC REFERENCE where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. Each DAC can be selected to use the REFOUT/REF IN+ pin voltage or the supply voltage AVDD as the reference for the DAC. DAC RESISTOR STRING DAC LOADING The DAC selects the voltage from a string of resistors from the reference to AGND. It is essentially a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because of the design architecture. The DAC can be selected to be turned off with a 1kΩ, 100kΩ, or open circuit on the DAC outputs. DAC3 21 AIN3/VDAC3 DAC2 20 AIN2/VDAC2 DAC1 31 VDAC1 19 AIN1/IDAC1 Sink AVDD 28 REFOUT/ REF IN+ Source Current Mirror DAC0 32 17 RDAC1 VDAC0 30 Sink 0.1µF REF 2.5V/1.25V 18 Source Current Mirror Figure 17. DAC Architecture 30 16 AIN0/IDAC0 RDAC0 DAC Sink Connection www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 BIPOLAR OPERATION USING THE DAC ANALOG/DIGITAL LOW-VOLTAGE DETECT The DAC can be used for a bipolar output range, as shown in Figure 18; the circuit illustrates an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. The MSC1211/12/13/14 contain an analog or digital low-voltage detect. When the analog or digital supply drops below the value programmed in LVDCON (SFR E7h), an interrupt is generated (one for each supply). RESET R2 100kΩ The device can be reset from the following sources: +6V R1 100kΩ DACREF OPA703 VREF VDAC ±(DACREF) −6V Figure 18. Bipolar Operation with the DAC The output voltage for any input code can be calculated as follows: VO + ƪ DAC REF @ R 1)R 2 D Ǔ ǒ65536 Ǔ * DACREF @ ǒRR1Ǔƫ @ǒ R 1 2 where D represents the input code in decimal (0 to 65535). With DACREF = 5V, R1 = R2: VO + @ DǓ ǒ10 * 5V 65536 This is an output voltage range of ±5V with 0000h corresponding to a –5V output and FFFFh corresponding to a +5V output. Similarly, using DACREF = 2.5V, a ±2.5V output voltage can be achieved. IDAC The IDAC can source current and sink current (through an external transistor). The compliance specification of the IDAC output defines the maximum output voltage to achieve the expected current. IDAC OUT ȡ4 R@ V ȧ + ȥV ȧR Ȣ Power-on reset External reset Software reset Watchdog timer reset Brownout reset An external reset is accomplished by taking the RST pin high for two tOSC periods, followed by taking the RST pin low. A software reset is accomplished through the System Reset register (SRTST, 0F7h). A watchdog timer reset is enabled and controlled through Hardware Configuration Register 0 (HCR0) and the Watchdog Timer register (WDTCON, 0FFh). A brownout reset is enabled through Hardware Configuration Register 1 (HCR1). External reset, software reset, and watchdog timer reset complete after 217 clock cycles. A brownout reset completes after 215 clock cycles. All sources of reset cause the digital pins to be pulled high from the initiation of the reset. For an external reset, taking the RST pin high stops device operation (crystal oscillation, internal oscillator, or PLL circuit operation) and causes all digital pins to be pulled high from that point. Taking the RST pin low initiates the reset procedure. A recommended external reset circuit is shown in Figure 19. The serial 10kΩ resistor is recommended for any external reset circuit configuration. DVDD DAC MSC1211/12/13/14 for Source mode 0.1µF DAC DAC D D D D D 10kΩ for Sink mode 13 RST DAC 1MΩ with VDAC < (AVDD − 2V) for maximum code. Refer to Figure 17 for the IDAC structure. Figure 19. Typical Reset Circuit 31 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 POWER ON RESET The on-chip Power On Reset (POR) circuitry releases the device from reset when DVDD ≈ 2.0V. The power supply ramp rate does not affect the POR. If the power supply falls below 1.0V for more than 200ms, then the POR will execute. If the power supply falls below 1.0V for less than 200ms, unexpected operation may occur. If these conditions are not met, the POR will not execute. For example, a negative spike on the DVDD supply that does not remain below 1.0V for at least 200ms, will not initiate a POR. If the Analog/Digital Brownout Reset circuit is on, the POR has no effect. BROWNOUT RESET The Brownout Reset (BOR) is enabled through HCR1. If the conditions for proper POR are not met, or the device encounters a brownout condition that does not generate a POR, the BOR can be used to ensure proper device operation. The BOR will hold the state of the device when the power supply drops below the threshold level programmed in HCR1, and then generate a reset when the supply rises above the threshold level. Note that, as the device is released from reset and program execution begins, the device current consumption may increase, which can result in a power supply voltage drop, which may initiate another brownout condition. The BOR level should be chosen to match closely with the application. That is, with a high external clock frequency, the BOR level should match the minimum operating voltage range for the device or improper operation may still occur. The BOR voltage is not calibrated until the end of the reset cycle; therefore, the actual BOR voltage will be approxiamtely 25% higher than the selected voltage. This can create a condition where the reset never ends (for example, when selecting a 4.5V BOR voltage for a 5V power supply). IDLE MODE Idle mode is entered by setting the IDLE bit in the Power Control register (PCON, 087h). In Idle mode, the CPU, Timer0, Timer1, and USARTs are stopped, but all other peripherals and digital pins remain active. The device can be returned to active mode via an active internal or external interrupt. This mode is typically used for reducing power consumption between ADC samples. By configuring the device prior to entering Idle mode, further power reductions can be achieved (while in Idle mode). These reductions include powering down 32 peripherals not in use in the PDCON register (0F1h) and reducing the system clock frequency by using the System Clock Divider register (SYSCLK, 0C7h). STOP MODE Stop mode is entered by setting the STOP bit in the Power Control register (PCON, 087h). In STOP mode, all internal clocks are halted. This mode has the lowest power consumption. The device can be returned to active mode only via an external or power-on reset (not brownout reset). By configuring the device prior to entering Stop mode, further power reductions can be achieved (while in Stop mode). These power reductions include halting the external clock into the device, configuring all digital I/O pins as open drain with low output drive, disabling the ADC buffer, disabling the internal VREF, disabling the DACs, and setting PDCON to 0FFh to power down all peripherals. In Stop mode, all digital pins retain their values. If the BOR is enabled before entering Stop mode, the BOR circuit will continue to draw approximately 25µA of current from the power supply during Stop mode. To minimize power consumption, disable the BOR circuit before entering Stop mode. POWER CONSUMPTION CONSIDERATIONS The following suggestions will reduce current consumption in the MSC1211/12/13/14 devices: 1. Use the lowest supply voltage that will work in the application for both AVDD and DVDD. 2. Use the lowest clock frequency that will work in the application. 3. Use Idle mode and the system clock divider whenever possible. Note that the system clock divider also affects the ADC clock. 4. Avoid using 8051-compatible I/O mode on the I/O ports. The internal pull-up resistors will draw current when the outputs are low. 5. Use the delay line for Flash Memory control by setting the FRCM bit in the FMCON register (SFR EEh) 6. Power down peripherals when they are not needed. Refer to SFR PDCON, LVDCON, ADCON0, and DACCONx. For more information about power cunsumption considerations, refer to application report SBAA139, Minimizing Power Consumption on the MSC12xx, available for download at www.ti.com. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 MEMORY MAP FLASH MEMORY The MSC1211/12/13/14 contain on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM, and SRAM. The SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1211/12/13/14 are controlled through the SFR. Reading from an undefined SFR will return zero; writing to an undefined SFR is not recommended, and will have indeterminate effects. The page size for Flash memory is 128 bytes. The respective page must be erased before it can be written to, regardless of whether it is mapped to Program or Data Memory space. The MSC1211/12/13/14 use a memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area is 64kB beginning at address 0000h and ending at FFFFh, as shown in Figure 20. The program and data segments can overlap since they are accessed in different ways. Program Memory is fetched by the microcontroller automatically. There is one instruction (MOVC) that is used to explicitly read the program area. This instruction is commonly used to read lookup tables. The Data Memory area is accessed explicitly using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is also used to access the 64kB of Data Memory. The address and data range of devices with on-chip Program and Data Memory overlap the 64kB memory space. When on-chip memory is enabled, accessing memory in the on-chip range will cause the device to access internal memory. Memory accesses beyond the internal range will be addressed externally via Ports 0 and 2. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memory. The partition size is set through hardware configuration bits, which are programmed through either the parallel or serial programming methods. Both Program and Data Flash Memory are erasable and writable (programmable) in User Application mode (UAM). However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be activated through the hardware configuration bits, which disables erase and writes to 4kB of Program Flash Memory or the entire Program Flash Memory in UAM. The MSC1211/12/13/14 include 1kB of SRAM on-chip. SRAM starts at address 0 and is accessed through the MOVX instruction. This SRAM can also be located to start at 8400h and can be accessed as both Program and Data Memory. 2k Internal Boot ROM FFFFh FFFFh F800h External Program Memory Select in MCON Data Memory 1k RAM or External External Memory On−Chip Flash Mapped to Both Memory Spaces (von Neumann) 8800h 8400h 7FFFh, 32k (Y5) 3FFFh, 16k (Y4) 1FFFh, 8k (Y3) External Data Memory 1k RAM or External Select in MCON Select in HCR0 Program Memory The MSC1211/12/13/14 have two hardware configuration registers (HCR0 and HCR1) that are programmable only during Flash Memory Programming mode. On−Chip Flash Configuration Memory 8800h 83FFh, 33k (Y5) 43FFh, 17k (Y4) 23FFh, 9k (Y3) 13FFh, 5k (Y2) 0FFFh, 4k (Y2) 0000h, 0k 1k RAM or External 03FFh, 1k UAM: Read Only FPM: Read/Write User Flash Programming Application Mode Mode Address Address(1) 807Fh 7Fh 8079h 79h 8070h 70h 8000h 00h UAM: Read Only FPM: Read Only UAM: Read Only FPM: Read/Write NOTE: (1) Can be accessed using CADDR or the faddr_data_read Boot ROM routine. Figure 20. Memory Map 33 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 The MSC1211/12/13/14 allow the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1213Y5 contains 32kB of Flash Memory on-chip. Through the hardware configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Table 4 and Table 5. The MSC1211/12/13/14 families offer four memory configurations. Table 4. MSC1211/12/13/14 Flash Partitioning HCR0 MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5 DFSEL PM DM PM DM PM DM PM DM 000 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB 001 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB 010 0kB 4kB 0kB 8kB 0kB 16kB 16kB 16kB 011 0kB 4kB 0kB 8kB 8kB 8kB 24kB 8kB 100 0kB 4kB 4kB 4kB 12kB 4kB 28kB 4kB 101 2kB 2kB 6kB 2kB 14kB 2kB 30kB 2kB 110 3kB 1kB 7kB 1kB 15kB 1kB 31kB 1kB 111 (default) 4kB 0kB 8kB 0kB 16kB 0kB 32kB 0kB NOTE: When a 0kB Program Memory configuration is selected, program execution is external. Table 5. MSC1211/12/13/14 Flash Memory Partitioning HCR0 MSC121xY2 MSC121xY3 MSC121xY4 The effect of memory mapping on Program and Data Memory is straightforward. The Program Memory is decreased in size from the top of internal Program Memory. Therefore, for example, if the MSC1213Y5 is partitioned with 31kB of Flash Program Memory and 1kB of Flash Data Memory, external Program Memory execution will begin at 7C00h (versus 8000h for 32kB). The Flash Data Memory is added on top of the SRAM memory. Thus, access to Data Memory (through MOVX) will access SRAM for addresses 0000h−03FFh and access Flash Memory for addresses 0400h−07FFh. MSC121xY5 DFSEL PM DM PM DM PM DM PM DM 000 0000 040013FF 0000 040023FF 0000 040043FF 0000 040083FF 001 0000 040013FF 0000 040023FF 0000 040043FF 0000 040083FF 010 0000 040013FF 0000 040023FF 0000 040043FF 00003FFF 040043FF 011 0000 040013FF 0000 040023FF 00001FFF 040023FF 00005FFF 040023FF 100 0000 040013FF 00000FFF 040013FF 00002FFF 040013FF 00006FFF 040013FF 101 000007FF 04000BFF 000017FF 04000BFF 000037FF 04000BFF 000077FF 04000BFF 110 00000BFF 040007FF 00001BFF 040007FF 00003BFF 040007FF 00007BFF 040007FF 111 (default) 00000FFF −− 00001FFF −− 00003FFF −− 00007FFF −− NOTE: Program Memory accesses above the highest listed address will access external Program Memory. 34 It is important to note that the Flash Memory is readable and writable by the user through the MOVX instruction when configured as either Program or Data Memory (via the MXWS bit in the MWS SFR 8Fh). This flexibility means that the device can be partitioned for maximum Flash Program Memory size (no Flash Data Memory) and Flash Program Memory can be used as Flash Data Memory. However, this configuration may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning prohibits execution of code from Data Flash Memory. Additionally, the Program Memory erase/write can be disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) to Data Flash Memory. Data Memory The MSC1211/12/13/14 can address 64kB of Data Memory. Scratchpad Memory provides 256 bytes in addition to the 64kB of Data Memory. The MOVX instruction is used to access the Data SRAM Memory. This includes 1024 bytes of on-chip Data SRAM Memory. The data bus values do not appear on Port 0 (during data bus timing) for internal memory access. The MSC1211/12/13/14 also have on-chip Flash Data Memory which is readable and writable (depending on Memory Write Select register) during normal operation (full VDD range). This memory is mapped into the external Data Memory space directly above the SRAM. The MOVX instruction is used to write to Flash Memory. Flash Memory must be erased before it can be written. Flash Memory is erased in 128 byte pages. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 CONFIGURATION MEMORY The MSC121x Configuration Memory consists of 128 bytes. In UAM, all Configuration Memory is readable using the faddr_data_read Boot ROM routine, and the CADDR and CDATA registers. In UAM, however, none of the Configuration Memory is writable. In serial or parallel programming mode, all Configuration Memory is readable. Most locations are also writable, except for addresses 8070h through 8079h, which are read-only. The two hardware configuration registers reside in configuration memory at 807Eh (HCR1) and 807Fh (HCR0). Figure 21 shows the configuration register mapping for programming mode and UAM. Note that reading/writing configuration memory in Flash Programming mode (FPM) requires 16-bit addressing; whereas, reading configuration memory in User Application mode (UAM) requires only 8-bit addressing. User Application Mode (Read−Only) Flash Programming Mode 0807Fh 0807Eh HCR0 HCR1 08079h Read−Only in Both FPM and UAM 7Fh 7Fh 79h 08070h 70h 08000h 00h UAM Address NOTE: All Configuration Memory is R/W in programming mode, except addresses 8070h−8079h, which are read−only. All Configuration Memory is read−only in UAM. Figure 21. Configuration Memory Mapping for Programming Mode and UAM REGISTER MAP Figure 22 illustrates the Register Map. It is entirely separate from the Program and Data Memory areas discussed previously. A separate class of instructions is used to access the registers. There are 256 potential register locations. In practice, the MSC1211/12/13/14 have 256 bytes of Scratchpad RAM and up to 128 SFRs. This is possible, since the upper 128 Scratchpad RAM locations can only be accessed indirectly. Thus, a direct reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0 to 127). 255 FFh 255 Indirect RAM 128 127 80h 128 7Fh Direct RAM 0 FFh Direct Special Function Registers 80h SFR Registers 00h Scratchpad RAM Figure 22. Register Map SFRs are accessed directly between 80h and FFh (128 to 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data contents are small. When off-chip RAM is needed, the Scratchpad area will still provide the fastest general-purpose access. Within the 256 bytes of RAM, there are several special-purpose areas. Bit Addressable Locations In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20h to 2Fh are bit addressable. This provides 128 (16 • 8) individual bits available to software. A bit access is distinguished from a full-register access by the type of instruction. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 23 shows details of the on-chip RAM addressing including the locations of individual RAM bits. Working Registers As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 23. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0—R7. This design allows software to change context by simply switching banks. Bank access is controlled via the Program Status Word register (PSW; 0D0h) in the SFR area described below. Registers R0 and R1 also allow their contents to be used for indirect addressing of the upper 128 bytes of RAM. 35 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Thus, an instruction can designate the value stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the these registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions. FFh Indirect RAM 7Fh Stack 2Fh 7F 7E 7D 7C 7B 7A 79 78 2Eh 77 76 75 74 73 72 71 70 2Dh 6F 6E 6D 6C 6B 6A 69 68 2Ch 67 66 65 64 63 62 61 60 2Bh 5F 5E 5D 5C 5B 5A 59 58 2Ah 57 56 55 54 53 52 51 50 29h 4F 4E 4D 4C 4B 4A 49 48 28h 47 46 45 44 43 42 41 40 27h 3F 3E 3D 3C 3B 3A 39 38 26h 37 36 35 34 33 32 31 30 25h 2F 2E 2D 2C 2B 2A 29 28 24h 27 26 25 24 23 22 21 20 23h 1F 1E 1D 1C 1B 1A 19 18 22h 17 16 15 14 13 12 11 10 21h 0F 0E 0D 0C 0B 0A 09 08 20h 07 06 05 04 03 02 01 00 Bit-Addressable Direct RAM Program Memory After reset, the CPU begins execution from Program Memory location 0000h. The selection of where Program Memory execution begins is made by tying the EA pin to DVDD for internal access, or DGND for external access. When EA is tied to DVDD, any PC fetches outside the internal Program Memory address occur from external memory. If EA is tied to DGND, then all PC fetches address external memory. Table 6 shows the standard internal Program Memory size for MSC1211/12/13/14 family members. If enabled the Boot ROM will appear from address F800h to FFFFh. 1Fh Bank 3 18h 17h Bank 2 10h Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack Pointer (SP; 81h) SFR. Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack. The Stack Pointer will default to 07h on reset. The user can then move it as needed. A convenient location would be the upper RAM area (> 7Fh) since this is only available indirectly. The SP will point to the last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment the SP by the appropriate value. Each POP or RET will decrement as well. 0Fh Table 6. MSC1211/12/13/14 Maximum Internal Program Memory Sizes Bank 1 08h 07h Bank 0 0000h MSB LSB Figure 23. Scratchpad Register Addressing 36 MODEL NUMBER STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES) MSC121xY5 32k MSC121xY4 16k MSC121xY3 8k MSC121xY2 4k www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ACCESSING EXTERNAL MEMORY If external memory is used, P0 and P2 must be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the hardware configuration register (HCR0, HCR1). To enable access to external memory, bits 0 and 1 of the HCR1 register must be set to ‘0’. When these bits are enabled all memory accesses for both internal and external memory will appear on Ports 0 and 2. During the data portion of the cycle for internal memory, Port 0 will be zero for security purposes. Accesses to external memory are of two types: to external Program Memory and to external Data Memory. Accesses to external Program Memory use signal PSEN (program store enable) as the read strobe. Accesses to external Data Memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory. If desired, External Program Memory and external Data Memory may be combined by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data Memory. A program fetch from external Program Memory uses a 16-bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @RI). If Port 2 is selected for external memory use (HCR1, bit 0), it cannot be used as general-purpose I/O. This bit (or Bit 1 of HCR1) also forces bits P3.6 and P3.7 to be used for WR and RD instead of I/O. Port 2, P3.6, and P3.7 should all be written to ‘1.’ If an 8-bit address is being used (MOVX @RI), the contents of the MPAGE (92h) SFR remain at the Port 2 pins throughout the external memory cycle, which facilitates paging. In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The ADDR/DATA signals use CMOS drivers in the Port 0, Port 2, WR, and RD output buffers. Thus, in this application, the Port 0 pins are not open-drain outputs, and do not require external pull-ups for high-speed access. Signal ALE (Address Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated. The functions of Port 0 and Port 2 are selected in HCR1. (Hardware configuration registers can only be changed during Flash Programming mode.) The default state is for Port 0 and Port 2 to be used as general-purpose I/O. If an external memory access is attempted when they are configured as general-purpose I/O, the values of Port 0 and Port 2 will not be affected. External Program Memory is accessed under two conditions: 1. 2. Whenever signal EA is low during reset, then all future code and data accesses are external; or Whenever the Program Counter (PC) contains a number that is outside of the internal Program Memory address range, if the ports are enabled. If Port 0 and Port 2 are selected for external memory, all 8 bits of Port 0 and Port 2, as well as P3.6 and P3.7, are dedicated to an output function and may not be used for general-purpose I/O. During external program fetches, Port 2 outputs the high byte of the PC. Programming Flash Memory There are four sections of Flash Memory for programming: 1. 128 configuration bytes. 2. Reset sector (4kB) (not to be confused with the 2kB Boot ROM). 3. Program Memory. 4. Data Memory. Boot ROM There is a 2kB Boot ROM that controls operation during serial or parallel programming. Additionally, the Boot ROM routines can be accessed during the user mode if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800h−FFFFh during user mode. In program mode the Boot ROM is located in the first 2kB of Program Memory. For additional information, refer to Application Note SBAA085, available for download from the TI web site (www.ti.com). The MSC1211/12/13/14 are shipped with Flash Memory erased (all 1s). Parallel programming methods typically involve a third-party programmer. Serial programming methods typically involve in-system programming. UAM allows Code Program and Data Memory programming. The actual code for Flash programming cannot execute from Flash. That code must execute from the Boot ROM or internal (von Neumann) RAM. 37 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Flash Programming Mode There are two programming modes: parallel and serial. The programming mode is selected by the state of the ALE and PSEN signals during reset (BOR, WDT, software, or POR). Serial programming mode is selected with PSEN = 0 and ALE = 1. Parallel programming mode is selected with PSEN = 1 and ALE = 0, as shown in Figure 24. If they are both high, the MSC1211/12/13/14 will operate in User Application mode. For both signals, low is a reserved mode and is not defined. Programming mode is exited with a reset and the normal mode selected. HOST MSC1211/12/13/14 PSEL P2[7] AddrHi[6:0] NC Flash Programmer P2[6:0] PSEN AddrLo[7:0] P1[7:0] Data[7:0] ALE P0[7:0] Cmd[2:0] P3[7:5] Req P3[4] Figure 25 shows the serial programming conection. P3[3] Serial programming mode works through USART0, and has special protocols. Table 7 describes these protocols, which are discussed at length in Application Note SBAA076 (available for download at www.ti.com). The serial programming mode works at a maximum baud rate determined by fOSC. P3[2] RST XIN Ack Pass RST CLK Figure 24. Parallel Programming Configuration MSC121x Reset Circuit (or VDD) RST DVDD P3.1 TXD PSEN Not Connected Clock Source Serial Port 0 P3.0 RXD RS232 Transceiver Host PC or Serial Terminal ALE XIN NOTE: Serial programming is selected with PSEN = 0 and ALE = 1 or open. Figure 25. Serial Programming Connection 38 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 7. MSC121x Boot ROM Routines ADDRESS ROUTINE C DECLARATIONS FFD5 put_string void put_string (char code *string); DESCRIPTION Output string FFD7 page_erase char page_erase (int faddr, char fdata, char fdm); Erase flash page FFD9 write_flash Assembly only; DPTR = address, R5 = data Fast flash write FFDB write_flash_chk char write_flash_chk (int faddr, char fdata, char fdm); Write flash byte, verify FFDD write_flash_byte char write_flash_byte (int faddr, char fdata, char fdm); Write flash byte FFDF faddr_data_read char faddr_data_read (char faddr); Read HW config byte from addr FFE1 data_x_c_read char data_x_c_read (int faddr, char fdm); Read xdata or code byte FFE3 tx_byte void tx_byte (char); Send byte to USART0 FFE5 tx_hex void tx_hex (char); Send hex value to USART0 FFE7 putok void putok (void); Send “OK” to USART0 FFE9 rx_byte char rx_byte (void); Read byte from USART0 FFEB rx_byte_echo char rx_byte_echo (void); Read and echo byte on USART0 FFED rx_hex_echo int rx_hex_echo (void); Read and echo hex on USART0 FFEF rx_hex_int_echo int rx_hex_int_echo (void); Read int as hex and echo: USART0 FFF1 rx_hex_rev_echo int rx_hex_rev_echo (void); Read int reversed as hex and echo: USART0 FFF3 autobaud void autobaud (void); Set baud with received CR FFF5 putspace4 void putspace4 (void); Output 4 spaces to USART0 FFF7 putspace3 void putspace3 (void); Output 3 spaces to USART0 FFF9 putspace2 void putspace2 (void); Output 2 spaces to USART0 FFFB putspace1 void putspace1 (void); Output 1 space to USART0 FFFB F97D(1) FD3B(1) putcr void putcr (void); Output CR, LF to USART0 cmd_parse void cmd_parser (void); See SBAA076 monitor_isr void monitor_isr ( ) interrupt 6 (1) These addresses only relate to version 1.0 of the MSC1211/12/13/14 Boot ROM. Push registers and call cmd_parser 39 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 INTERRUPTS The MSC1211/12/13/14 use a three-priority interrupt system. As shown in Table 8, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family. All of the standard interrupts are available. Table 8. Interrupt Summary INTERRUPT PRIORITY CONTROL ADDR NUM PRIORITY FLAG ENABLE DVDD Low Voltage/HW Breakpoint 33h 6 High EDLVB (AIE.0 or AIPOL.0)(1)(2) EBP (BPCON.7)(1) EDLVB (AIE.0)(1) EBP (BPCON.0)(1) N/A AVDD Low Voltage SPI Receive / I2C(3) 33h 6 0 EALV (AIE.1 or AIPOL.1)(1)(2) EALV (AIE.1)(1) N/A 33h 6 0 ESPIR/EI2C (AIE.2 or AIPOL.2)(1)(2) ESPIR/EI2C (AIE.2)(1) N/A INTERRUPT/EVENT SPI Transmit 33h 6 0 Milliseconds Timer 33h 6 0 ADC 33h 6 0 ESPIT (AIE.3 or AIPOL.3)(1)(2) EMSEC (AIE.4 or AIPOL.4)(1)(2) EADC (AIE.5 or AIPOL.5)(1)(2) AIPOL.6)(1)(2) Summation Register 33h 6 0 ESUM (AIE.6 or Seconds Timer 33h 6 0 ESEC (AIE.7 or AIPOL.7)(1)(2) (TCON.1)(4) ESPIT (AIE.3)(1) EMSEC (AIE.4)(1) N/A N/A EADC (AIE.5)(1) N/A ESUM (AIE.6)(1) N/A ESEC (AIE.7)(1) N/A EX0 External Interrupt 0 03h 0 1 IE0 Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)(5) ET1 (IE.1)(6) PT0 (IP.1) External Interrupt 1 13h 2 3 IE1 (TCON.3)(4) EX1 (IE.2)(6) PX1 (IP.2) (TCON.7)(5) (IE.3)(6) PT1 (IP.3) ET1 (IE.0)(6) PX0 (IP.0) Timer 1 Overflow 0Bh 3 4 TF1 Serial Port 0 23h 4 5 RI_0 (SCON0.0) TI_0 (SCON0.1) ES0 (IE.4)(6) PS0 (IP.4) Timer 2 Overflow 2Bh 5 6 TF2 (T2CON.7) ET2 (IE.5)(6) PT2 (IP.5) Serial Port 1 3Bh 7 7 RI_1 (SCON1.0) TI_1 (SCON1.1) ES1 (IE.6)(6) PS1 (IP.6) External Interrupt 2 43h 8 8 IE2 (EXIF.4)(4) EX2 (EIE.0)(6) PX2 (EIP.0) (EXIF.5)(4) (EIE.1)(6) PX3 (EIP.1) External Interrupt 3 4Bh 9 9 IE3 External Interrupt 4 53h 10 10 IE4 (EXIF.6)(4) EX4 (EIE.2)(6) PX4 (EIP.2) External Interrupt 5 5Bh 11 11 IE5 (EXIF.7)(4) EX5 (EIE.3)(6) PX5 (EIP.3) Watchdog 63h 12 12 Low WDTI (EICON.3) EX3 EWDI (EIE.4)(6) PWDI (EIP.4) (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) For AIPOL.RDSEL = 1, reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of AIE register contents. For AIPOL.RDSEL = 0, Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary interrupts before masking. (3) I2C is only available on the MSC1211 and MSC1213. (4) If edge-triggered, cleared automatically by hardware on interrupt service routine vector. For EX0 or EX1, if level-triggered, the flag follows the state of the pin. (5) Cleared automatically by hardware when interrupt vector occurs. (6) Globally enabled by EA (IE.7). 40 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. CADDR 7Fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. EPMA bit 7 Enable Programming Memory Access (Security Bit). 0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done. 1: Fully Accessible (default) PML bit 6 Program Memory Lock (PML has priority over RSL). 0: Enable writing to Program Memory in UAM. 1: Disable writing to Program Memory in UAM (default). RSL bit 5 Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming, which allows Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read-Only Mode for Reset Sector (4kB) (default) EBR bit 4 Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR bit 3 Enable Watchdog Reset. 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1−0 Data Flash Memory Size (see Table 4 and Table 5). bits 2−0 000: Reserved 001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory 010: 16kB, 8kB, or 4kB Data Flash Memory 011: 8kB or 4kB Data Flash Memory 100: 4kB Data Flash Memory 101: 2kB Data Flash Memory 110: 1kB Data Flash Memory 111: No Data Flash Memory (default) 41 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Configuration Register 1 (HCR1) CADDR 7Eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine. DBLSEL bits 7−6 Digital Supply Brownout Level Select 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) ABLSEL bits 5−4 Analog Supply Brownout Level Select 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) DAB bit 3 Disable Analog Power-Supply Brownout Reset 0: Enable Analog Brownout Reset 1: Disable Analog Brownout Reset (default) DDB bit 2 Disable Digital Power-Supply Brownout Reset 0: Enable Digital Brownout Reset 1: Disable Digital Brownout Reset (default) EGP0 bit 1 Enable General-Purpose I/O for Port 0 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 0 is Used as General-Purpose I/O (default) EGP23 bit 0 Enable General-Purpose I/O for Ports 2 and 3 0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR and RD. 1: Port 2 and Port3 are Used as General-Purpose I/O (default) Configuration Memory Programming Hardware Configuration Memory can be changed only in Serial Flash Programming mode or Parallel Programming mode. 42 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE 80h P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh 81h SP 07h 82h DPL0 00h 83h DPH0 00h 84h DPL1 00h 85h DPH1 86h DPS 0 0 0 0 0 0 0 SEL 00h 87h PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 30h 88h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h 89h TMOD 8Ah TL0 00h 8Bh TL1 00h 8Ch TH0 00h 8Dh TH1 8Eh CKCON 0 0 T2M T1M T0M MD2 MD1 MD0 01h 8Fh MWS 0 0 0 0 0 0 0 MXWS 00h 90h P1 P1.7 P1.6 INT4/MISO/SDA P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 T2 FFh INT5/SCK/SCL IE5 IE4 IE3 IE2 1 0 0 0 00h −−−−−−−−−−−−−−−Timer 1−−−−−−−−−−−−−−− GATE C/T M1 M0 −−−−−−−−−−−−−−−Timer 0−−−−−−−−−−−−−−− GATE C/T M1 00h M0 00h 91h EXIF 92h MPAGE 08h 08h 93hv CADDR 00h 94h CDATA 95h MCON 00h BPSEL 0 0 RAMMAP 96h 00h 00h 97h 98h SCON0 99h SBUF0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h 9Ah SPICON I2CCON(1) SCK2 START SCK1 STOP SCK0 ACK FIFO 0 ORDER FAST MSTR MSTR CPHA SCLA CPOL FILEN 00h 9Bh SPIDATA I2CDATA(1) 9Ch SPIRCON I2CGM(1) RXCNT7 RXFLUSH GCMEN RXCNT6 RXCNT5 RXCNT4 RXCNT3 RXCNT2 RXIRQ2 RXCNT1 RXIRQ1 RXCNT0 RXIRQ0 00h 9Dh SPITCON I2CSTAT(1) TXCNT7 TXFLUSH STAT7 TXCNT6 TXCNT5 CLK_EN STAT5 SCKD5/SA5 TXCNT4 DRV_DLY STAT4 SCKD4/SA4 TXCNT3 DRV_EN STAT3 SCKD3/SA3 TXCNT2 TXIRQ2 0 SCKD2/SA2 TXCNT1 TXIRQ1 0 SCKD1/SA1 TXCNT0 TXIRQ0 0 SCKD0/SA0 00h 00h 00h SCKD7/SAE STAT5 SCKD6/SA6 9Eh SPISTART I2CSTART(1) 1 80h 9Fh SPIEND 1 A0h P2 P2.7 P2.6 A1h PWMCON A2h PWMLOW TONELOW PWM7 TDIV7 PWM6 TDIV6 A3h PWMHI TONEHI PWM15 TDIV15 A4h AIPOL ESEC 80h P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FFh PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h PWM5 TDIV5 PWM4 TDIV4 PWM3 TDIV3 PWM2 TDIV2 PWM1 TDIV1 PWM0 TDIV0 00h PWM14 TDIV14 PWM13 TDIV13 PWM12 TDIV12 PWM11 TDIV11 PWM10 TDIV10 PWM9 TDIV9 PWM8 TDIV8 00h ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB RDSEL 00h (1) I2C is only available on the MSC1211 and MSC1213. (2) Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3) Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 43 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE A5h PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h A6h AIE ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h A7h AISTAT SEC SUM ADC MSEC SPIT SPIR/I2CSI ALVD DLVD 00h A8h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h A9h BPCON BP 0 0 0 0 0 PMSEL EBP 00h AAh BPL ABh BPH ACh P0DDRL P03H P03L P02H P02L P01H P01L P00H P00L 00h ADh P0DDRH P07H P07L P06H P06L P05H P05L P04H P04L 00h AEh P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00h AFh P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00h B0h P3 P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh B1h P2DDRL P23H P23L P22H P22L P21H P21L P20H P20L 00h B2h P2DDRH P27H P27L P26H P26L P25H P25L P24H P24L 00h B3h P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00h B4h P3DDRH P37H P33L P32H P32L P31H P31L P30H P30L 00h B5h DACL B6h DACH B7h DACSEL DSEL7 DSEL6 DSEL5 DSEL4 DSEL3 DSEL2 DSEL1 DSEL0 00h B8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h C0h SCON1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h C1h SBUF1 B9h BAh BBh BCh BDh BEh BFh 00h C2h C3h C4h C5h C6h EWU EWUWDT EWUEX1 EWUEX0 00h C7h SYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h C8h T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h C9h CAh RCAP2L 00h CBh RCAP2H 00h CCh TL2 00h CDh TH2 00h CEh CFh D0h PSW D1h OCL CY AC F0 RS1 RS0 (1) I2C is only available on the MSC1211 and MSC1213. (2) Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3) Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 44 OV F1 P 00h LSB 00h www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 9. Special Function Registers (continued) NOTE: (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14). ADDRESS REGISTER D2h OCM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUE D3h OCH D4h GCL D5h GCM D6h GCH MSB D7h ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 D8h EICON SMOD1 1 EAI AI WDTI 0 0 0 40h D9h ADRESL LSB 00h DAh ADRESM DBh ADRESH MSB DCh ADCON0 REFCLK BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h DDh ADCON1 OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000_0000b DEh ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh DFh ADCON3 0 0 0 0 0 DR10 DR9 DR8 06h E0h ACC E1h SSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h E2h SUMR0 00h E3h SUMR1 00h E4h SUMR2 00h E5h SUMR3 00h E6h ODAC E7h LVDCON ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 E8h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E9h HWPC0 0 0 0 0 0 1 EAh HWPC1 0 0 0 0 1 0 EBh HWVER ECh Reserved EDh Reserved EEh FMCON 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h EFh FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h F0h B B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h F1h PDCON 0 PDDAC PDI2C PDPWM PDADC PDWDT PDST PDSPI 7Fh F2h PASEL 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h F6h ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h F7h SRST 0 0 0 0 0 0 0 RSTREQ 00h F8h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h F9h SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh FAh MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh FBh USEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 FCh MSECL 9Fh FDh MSECH 0Fh FEh HMSEC FFh WDTCON 00h MSB 00h LSB 54h ECh 5Fh 01h 00h 00h 00h 00h MEMORY SIZE 0 0 00h E0h 0000_01xxb(2) 08h(3) 00h 00h F3h F4h F5h 03h 63h EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h (1) I2C is only available on the MSC1211 and MSC1213. (2) Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214. (3) Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214. 45 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM. POWER AND CLOCKS TIMER COUNTERS P0 80h Port 0 SP 81h Stack Pointer X DPL0 82h Data Pointer Low 0 X DPH0 83h Data Pointer High 0 X DPL1 84h Data Pointer Low 1 X DPH1 85h Data Pointer High 1 X DPS 86h Data Pointer Select X PCON 87h Power Control TCON 88h Timer/Counter Control X X TMOD 89h Timer Mode Control X X TL0 8Ah Timer0 LSB X TL1 8Bh Timer1 LSB X TH0 8Ch Timer0 MSB X TH1 8Dh Timer1 MSB CKCON 8Eh Clock Control MWS 8Fh Memory Write Select P1 90h Port 1 EXIF 91h External Interrupt Flag MPAGE 92h Memory Page CADDR 93h Configuration Address CDATA 94h Configuration Data MCON 95h Memory Control SCON0 98h Serial Port 0 Control X SBUF0 99h Serial Data Buffer 0 X SPI Control X I2C Control X SPI Data X I2C Data X SPI Receive Control X I2C Gen Call/Mult Master Enable X SPI Transmit Control X I2C Status X SPI Buffer Start Address X I2C Start X SPICON I2CCON 9Ah SPIDATA I2CDATA 9Bh SPIRCON I2CGM 9Ch SPITCON I2CSTAT 9Dh SPISTART I2CSTART 9Eh SPIEND 9Fh SPI Buffer End Address P2 A0h Port 2 PWMCON A1h PWM Control PWMLOW TONELOW A2h PWMHI TONEHI A3h PWM FLASH MEMORY ADC X X X X X X X X X X X X X X X X X X PWM Low Byte X Tone Low Byte X PWM HIgh Byte X Tone Low Byte X AIPOL A4h Auxiliary Interrupt Poll X X X X X X PAI A5h Pending Auxiliary Interrupt X X X X X X AIE A6h Auxiliary Interrupt Enable X X X X X X AISTAT A7h Auxiliary Interrupt Status X X X X X X IE A8h Interrupt Enable X 46 DAC www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) SFR ADDRESS FUNCTIONS CPU INTERRUPTS PORTS SERIAL COMM. POWER AND CLOCKS TIMER COUNTERS PWM FLASH MEMORY ADC DAC BPCON A9h Breakpoint Control X X BPL AAh Breakpoint Low Address X X BPH ABh Breakpoint High Address X P0DDRL ACh Port 0 Data Direction Low X P0DDRH ADh Port 0 Data Direction High X P1DDRL AEh Port 1 Data Direction Low X P1DDRH AFh Port 1 Data Direction High X P3 B0h Port 3 X P2DDRL B1h Port 2 Data Direction Low X P2DDRH B2h Port 2 Data Direction High X P3DDRL B3h Port 3 Data Direction Low X P3DDRH B4h Port 3 Data Direction High X DACL B5h DAC Low Byte X DACH B6h DAC High Byte X DACSEL B7h DAC Select X DACCON B7h DAC Control IP B8h Interrupt Priority SCON1 C0h Serial Port 1 Control X SBUF1 C1h Serial Data Buffer 1 X EWU C6h Enable Wake Up SYSCLK C7h System Clock Divider T2CON C8h Timer 2 Control X X RCAP2L CAh Timer 2 Capture LSB X X RCAP2H CBh Timer 2 Capture MSB X X TL2 CCh Timer 2 LSB X TH2 CDh Timer 2 MSB X PSW D0h Program Status Word OCL D1h ADC Offset Calibration Low Byte X OCM D2h ADC Offset Calibration Mid Byte X OCH D3h ADC Offset Calibration High Byte X GCL D4h ADC Gain Calibration Low Byte X GCM D5h ADC Gain Calibration Mid Byte X GCH D6h ADC Gain Calibration High Byte X ADMUX D7h ADC Input Multiplexer EICON D8h Enable Interrupt Control ADRESL D9h ADC Results Low Byte X ADRESM DAh ADC Results Middle Byte X ADRESH DBh ADC Results High Byte X ADCON0 DCh ADC Control 0 X ADCON1 DDh ADC Control 1 X ADCON2 DEh ADC Control 2 X ADCON3 DFh ADC Control 3 ACC E0h Accumulator X SSCON E1h Summation/Shifter Control X X SUMR0 E2h Summation 0 X X SUMR1 E3h Summation 1 X X SUMR2 E4h Summation 2 X X SUMR3 E5h Summation 3 X X X X X X X X X X X X X X X X X X X X X 47 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Table 10. Special Function Register Cross Reference (continued) SFR SERIAL COMM. POWER AND CLOCKS TIMER COUNTERS FLASH MEMORY ADDRESS FUNCTIONS ODAC E6h Offset DAC LVDCON E7h Low Voltage Detect Control EIE E8h Extended Interrupt Enable HWPC0 E9h Hardware Product Code 0 X HWPC1 EAh Hardware Product Code 1 X HWVER EBh Hardware Version X FMCON EEh Flash Memory Control FTCON EFh Flash Memory Timing Control B F0h Second Accumulator PDCON F1h Power Down Control PASEL F2h PSEN/ALE Select ACLK F6h Analog Clock SRST F7h System Reset EIP F8h Extended Interrupt Priority X SECINT F9h Seconds Timer Interrupt X X MSINT FAh Milliseconds Timer Interrupt X X USEC FBh One Microsecond TImer X MSECL FCh One Millisecond TImer Low Byte X X MSECH FDh One Millisecond Timer High Byte X X HMSEC FEh One Hundred Millisecond TImer WDTCON FFh Watchdog Timer HCR0 3Fh Hardware Configuration Reg. 0 HCR1 3Eh Hardware Configuration Reg. 1 48 CPU INTERRUPTS PORTS PWM ADC DAC X X X X X X X X X X X X X X X X X X X X X X X X www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 (P0) SFR 80h P0.7−0 bits 7−0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFh Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a generalpurpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is high, and Data when ALE is low. When used as a general-purpose I/O, this port drive is selected by P0DDRL and P0DDRH (ACh, ADh). Whether Port 0 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.1) (See SFR CADDR 93h). Stack Pointer (SP) SFR 81h SP.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07h Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h after reset. Data Pointer Low 0 (DPL0) SFR 82h DPL0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00h Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer High 0 (DPH0) SFR 83h DPH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00h Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h). Data Pointer Low 1 (DPL1) SFR 84h DPL1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00h Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) SFR 85h DPH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00h Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. 49 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Data Pointer Select (DPS) SFR 86h SEL bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 SEL 00h Data Pointer Select. This bit selects the active data pointer. 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. Power Control (PCON) SFR 87h 7 6 5 4 3 2 1 0 Reset Value SMOD 0 1 1 GF1 GF0 STOP IDLE 30h SMOD bit 7 Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 bit 3 General-Purpose User Flag 1. This is a general-purpose flag for software control. GF0 bit 2 General-Purpose User Flag 0. This is a general-purpose flag for software control. STOP bit 1 Stop Mode Select. Setting this bit halts the oscillator and blocks external clocks. This bit always reads as a 0. All digital pins and DACs keep their respective output values. Internal REF dies. Exit with RESET. IDLE bit 0 Idle Mode Select. Setting this bit freezes the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain active. This bit will always be read as a 0. All digital pins and DACs keep their respective output values. Internal REF remains unchanged. Exit with AI (A6h) and EWU (C6h) interrupts. 50 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer/Counter Control (TCON) SFR 88h 7 6 5 4 3 2 1 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 bit 6 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer preserves the current count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 bit 5 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 bit 4 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer preserves the current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 bit 3 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 bit 2 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. 0: INT1 is level-triggered. 1: INT1 is edge-triggered. IE0 bit 1 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 bit 0 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. 0: INT0 is level-triggered. 1: INT0 is edge-triggered. 51 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer Mode Control (TMOD) 7 6 GATE C/T 5 4 3 2 M1 M0 GATE C/T TIMER 1 SFR 89h 1 0 M1 M0 Reset Value TIMER 0 GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1. M1, M0 bits 5−4 Timer 1 Mode Select. These bits select the operating mode of Timer 1. M1 M0 0 0 Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Timer 1 is halted, but holds its count. 00h MODE GATE bit 3 Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T bit 2 Timer 0 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1. M1, M0 bits 1−0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. M1 M0 0 0 MODE Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) SFR 8Ah TL0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00h Timer 0 LSB. This register contains the least significant byte of Timer 0. Timer 1 LSB (TL1) SFR 8Bh TL1.7−0 bits 7−0 52 7 6 5 4 3 2 1 0 Reset Value TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00h Timer 1 LSB. This register contains the least significant byte of Timer 1. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 0 MSB (TH0) SFR 8Ch TH0.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h Timer 0 MSB. This register contains the most significant byte of Timer 0. Timer 1 MSB (TH1) SFR 8Dh TH1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h Timer 1 MSB. This register contains the most significant byte of Timer 1. Clock Control (CKCON) SFR 8Eh 7 6 5 4 3 2 1 0 Reset Value 0 0 T2M T1M T0M MD2 MD1 MD0 01h T2M bit 5 Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 2 uses a divide by 12 of the crystal frequency. 1: Timer 2 uses a divide by 4 of the crystal frequency. T1M bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. T0M bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. MD2, MD1, MD0 bits 2−0 Stretch MOVX Select 2−0. These bits select the time by which external MOVX cycles are to be stretched. This allows slower memory or peripherals to be accessed without using ports or manual software intervention. The width of the RD or WR strobe will be stretched by the specified interval, which will be transparent to the software except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate. MD2 MD1 MD0 STRETCH VALUE MOVX DURATION RD or WR STROBE WIDTH (SYS CLKs) RD or WR STROBE WIDTH (ms) at 12MHz 0 0 0 0 0 1 0 2 Instruction Cycles 2 0.167 1 3 Instruction Cycles (default) 4 0 1 0.333 0 2 4 Instruction Cycles 8 0 0.667 1 1 3 5 Instruction Cycles 12 1.000 1 0 0 4 6 Instruction Cycles 16 1.333 1 0 1 5 7 Instruction Cycles 20 1.667 1 1 0 6 8 Instruction Cycles 24 2.000 1 1 1 7 9 Instruction Cycles 28 2.333 53 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Memory Write Select (MWS) SFR 8Fh MXWS bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MXWS 00h MOVX Write Select. This allows writing to the internal Flash Program Memory. 0: MOVX operations will access Data Memory (default). 1: MOVX operations will access Program Memory. Write operations can be inhibited by the PML or RSL bits in HCR0. Port 1 (P1) SFR 90h P1.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value P1.7 INT5/SCK/SCL P1.6 INT4/MISO/SDA P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 T2 FFh General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh). INT5/SCK/SCL bit 7 External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled. SPI Clock. The master clock for SPI data transfers. Serial Clock. The serial clock for I2C data transfers (MSC1211 and MSC1213 only). INT4/MISO/SDA bit 6 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave. SDA. For I2C data transfers, this pin is the data line (MSC1211 and MSC1213 only). NT3/MOSI bit 5 External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data. INT2/SS bit 4 External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. Slave Select. During SPI operation, this pin provides the select signal for the slave device. TXD1 bit 3 Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. RXD1 bit 2 Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0. T2EX bit 1 Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be transferred into the capture registers if enabled by EXEN2 (T2CON.3, SFR C8h). When in auto-reload mode, a 1 to 0 transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2 (T2CON.3, SFR C8h). T2 bit 0 Timer 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment or decrement depending on the timer configuration. 54 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 External Interrupt Flag (EXIF) SFR 91h 7 6 5 4 3 2 1 0 Reset Value IE5 IE4 IE3 IE2 1 0 0 0 08h IE5 bit 7 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 bit 6 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 bit 5 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 bit 4 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. Memory Page (MPAGE) 7 6 5 4 3 2 1 0 SFR 92h MPAGE bits 7−0 Reset Value 00h The 8051 uses Port 2 for the upper 8 bits of the external Data Memory access by MOVX A@Ri and MOVX @Ri, A instructions. The MSC1211/12/13/14 uses register MPAGE instead of Port 2. To access external Data Memory using the MOVX A@Ri and MOVX @Ri, A instructions, the user should preload the upper byte of the address into MPAGE (versus preloading into P2 for the standard 8051). Configuration Address (CADDR) (write-only) 7 6 5 4 3 2 1 0 SFR 93h CADDR bits 7−0 Reset Value 00h Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration Memory. It is recommended that faddr_data_read be used when accessing Configuration Memory. CAUTION:If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data (CDATA) 7 6 5 4 3 2 1 0 SFR 94h CDATA bits 7−0 Reset Value 00h Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that is located at the last written address in the CADDR register. This is a read-only register. Memory Control (MCON) SFR 95h 7 6 5 4 3 2 1 0 Reset Value BPSEL 0 0 — — — — RAMMAP 00h BPSEL bit 7 Breakpoint Address Selection Write: Select one of two Breakpoint registers: 0 or 1. 0: Select breakpoint register 0. 1: Select breakpoint register 1. Read: Provides the Breakpoint register that created the last interrupt: 0 or 1. RAMMAP bit 0 Memory Map 1kB extended SRAM. 0: Address is: 0000h—03FFh (default) (Data Memory) 1: Address is 8400h—87FFh (Data and Program Memory) 55 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 0 Control (SCON0) SFR 98h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00h Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 0 0 0 0 FUNCTION Synchronous LENGTH 8 bits PERIOD 12 pCLK(1) 0 0 0 1 Synchronous 8 bits 4 pCLK(1) 1(2) 0 1 0 Asynchronous 10 bits Timer 1 or 2 Baud Rate Equation 1(2) 0 1 1 Valid Stop Required(3) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 2 1 0 1 Asynchronous with Multiprocessor Communication(4) 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 3(2) 1 1 0 Asynchronous 11 bits Timer 1 or 2 Baud Rate Equation 3(2) 1 1 1 Asynchronous with Multiprocessor Communication(4) 11 bits Timer 1 or 2 Baud Rate Equation (1) pCLK will be equal to tCLK, except that pCLK will stop for Idle mode. (2) For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the T2CON (C8h) register. (3) RI_0 will only be activated when a valid STOP is received. (4) RI_0 will not be activated if bit 9 = 0. REN_0 bit 4 Receive Enable. This bit enables/disables the serial Port 0 received shift register. 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 bit 3 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. RB8_0 bit 2 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 bit 1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 bit 0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software. Serial Data Buffer 0 (SBUF0) 7 SFR 99h SBUF0 bits 7−0 56 6 5 4 3 2 1 0 Reset Value 00h Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. SFR 9Ah SCK bits 7−5 7 6 5 4 3 2 1 0 Reset Value SCK2 SCK1 SCK0 FIFO ORDER MSTR CPHA CPOL 00h SCK Selection. Selection of tCLK divider for generation of SCK in Master mode. SCK2 SCK1 SCK0 SCK PERIOD 0 0 0 tCLK/2 0 0 1 tCLK/4 0 1 0 tCLK/8 0 1 1 tCLK/16 1 0 0 tCLK/32 1 0 1 tCLK/64 1 1 0 tCLK/128 1 1 1 tCLK/256 FIFO bit 4 Enable FIFO in On-Chip Indirect Memory. 0: Both transmit and receive are double buffers 1: Circular FIFO used for transmit and receive bytes ORDER bit 3 Set Bit Order for Transmit and Receive. 0: Most Significant Bits First 1: Least Significant Bits First MSTR bit 2 SPI Master Mode. 0: Slave Mode 1: Master Mode CPHA bit 1 Serial Clock Phase Control. 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK CPOL bit 0 Serial Clock Polarity. 0: SCK idle at logic low 1: SCK idle at logic high 57 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Control (I2CCON) (Available only on the MSC1211 and MSC1213) SFR 9Ah 7 6 5 4 3 2 1 0 Reset Value START STOP ACK 0 FAST MSTR SCLS FILEN 00h START bit 7 Start Condition (Master mode). Read: Current status of start condition or repeated start condition. Write: When operating as a master, a start condition is transmitted when the START bit is set to 1. During a data transfer, if the START bit is set, a repeated start is transmitted after the current data transfer is complete. If no transfer is in progress when the START and STOP bits are set simultaneously, a START will be followed by a STOP. STOP bit 6 Stop Condition (Master mode). Read: Current status of stop condition. Write: Setting STOP to logic 1 causes a stop condition to be transmitted. When a stop condition is received, hardware clears STOP to logic 0. If both START and STOP are set during a transfer, a stop condition is transmitted followed by a start condition. ACK bit 5 Acknowledge. Defines the ACK/NACK generation from the master/slave receiver during the acknowledge cycle. 0: A NACK (high level on SDA) is returned during the acknowledge cycle. 1: An ACK (low level on SDA) is returned during the acknowledge cycle. In slave transmit mode, 0 = Current byte is last byte, 1 = More to follow. 0 bit 4 Always set this value to zero. FAST bit 3 Fast Mode Enable. 0: Standard Mode (100kHz) 1: Fast Mode (400kHz) MSTR bit 2 SPI Master Mode. 0: Slave Mode 1: Master Mode SCLS bit 1 Clock Stretch. 0: No effect 1: Release the clock line. For the slave mode, the clock is stretched for each data transfer. This bit releases the clock. FILEN bit 0 Filter Enable. 50ns glitch filter. 0: Filter disabled 1: Filter enabled SPI Data (SPIDATA) / I2C Data (I2CDATA) 7 SFR 9Bh 6 5 4 3 2 1 0 Reset Value 00h SPIDATA bits 7−0 SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the transmit interrupt. I2CDATA I2C Data . (MSC1211 and MSC1213 only.) Data for I2C is read from or written to this location. The I2C transmit and receive buffers are separate registers, but both are addressed at this location. Writing to this register starts transmission. In Master mode, reading this register starts a Master read cycle. bits 7−0 58 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Receive Control (SPIRCON) SFR 9Ch 7 6 5 4 3 2 1 0 Reset Value RXCNT7 RXFLUSH RXCNT6 RXCNT5 RXCNT4 RXCNT3 RXCNT2 RXIRQ2 RXCNT1 RXIRQ1 RXCNT0 RXIRQ0 00h RXCNT bits 7−0 Receive Counter. Read-only bits which read the number of bytes in the receive buffer (0 to 128). RXFLUSH bit 7 Flush Receive FIFO. Write-only. 0: No Action 1: SPI Receive Buffer Set to Empty RXIRQ bits 2−0 Read IRQ Level. Write-only. 000 001 010 011 100 101 110 111 Generate IRQ when Receive Count = 1 or more. Generate IRQ when Receive Count = 2 or more. Generate IRQ when Receive Count = 4 or more. Generate IRQ when Receive Count = 8 or more. Generate IRQ when Receive Count = 16 or more. Generate IRQ when Receive Count = 32 or more. Generate IRQ when Receive Count = 64 or more. Generate IRQ when Receive Count = 128 or more. I2C GM (I2CGM) (Available only on the MSC1211 and MSC1213) 7 SFR 9Ch GCMEN bit 7 6 5 4 3 2 GCMEN 1 0 Reset Value 00h General Call/Multiple Master Enable. Write-only. Slave mode: 0 = General call ignored, 1 = General call will be detected Master mode: 0 = Single master, 1 = Multiple master mode 59 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 SPI Transmit Control (SPITCON) SFR 9Dh 7 6 5 4 3 2 1 0 Reset Value TXCNT7 TXFLUSH TXCNT6 TXCNT5 CLK_EN TXCNT4 DRV_DLY TXCNT3 DRV_EN TXCNT2 TXIRQ2 TXCNT1 TXIRQ1 TXCNT0 TXIRQ0 00h TXCNT bits 7−0 Transmit Counter. Read-only bits which read the number of bytes in the transmit buffer (0 to 128). TXFLUSH bit 7 Flush Transmit FIFO. This bit is write-only. When set, the SPI transmit pointer is set equal to the FIFO Output pointer. This bit is 0 for a read operation. CLK_EN bit 5 SCLK Driver Enable. 0: Disable SCLK Driver (Master Mode) 1: Enable SCLK Driver (Master Mode) DRV_DLY bit 4 Drive Delay (refer to DRV_EN bit). 0: Drive Output Immediately 1: Drive Output After Current Byte Transfer DRV_EN bit 3 Drive Enable. TXIRQ bits 2−0 DRV_DLY DRV_EN 0 0 Tristate immediately. 0 1 Drive immediately. 1 0 Tristate after the current byte transfer. 1 1 Drive after the current byte transfer. Transmit IRQ Level. Write-only bits. 000 001 010 011 100 101 110 111 60 MOSI or MISO OUTPUT CONTROL Generate IRQ when Transmit Count = 1 or less. Generate IRQ when Transmit Count = 2 or less. Generate IRQ when Transmit Count = 4 or less. Generate IRQ when Transmit Count = 8 or less. Generate IRQ when Transmit Count = 16 or less. Generate IRQ when Transmit Count = 32 or less. Generate IRQ when Transmit Count = 64 or less. Generate IRQ when Transmit Count = 128 or less. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Status (I2CSTAT) (Available only on the MSC1211 and MSC1213) SFR 9Dh STAT7−3 bit 7−3 7 6 5 4 3 2 1 0 Reset Value STAT7 SCKD7/SAE STAT6 SCKD6/SA6 STAT5 SCKD5/SA5 STAT4 SCKD4/SA4 STAT3 SCKD3/SA3 0 SCKD2/SA2 0 SCKD1/SA1 0 SCKD0/SA0 00h Status Code. Read-only. Reading this register clears the status interrupt. STATUS CODE STATUS OF THE HARDWARE MODE 0x08 START condition transmitted. Master 0x10 Repeated START condition transmitted. Master 0x18 Slave address + W transmitted and ACK received. Master 0x20 Slave address + W transmitted and NACK received. Master 0x28 Data byte transmitted and ACK received. Master 0x30 Data byte transmitted and NACK received. Master 0x38 Arbitration lost. Master 0x40 Slave address + R transmitted and ACK received. Master 0x48 Slave address + R transmitted and NACK received. Master 0x50 Data byte received and ACK transmitted. Master 0x58 Data byte received and NACK transmitted. Master 0x60 I2Cs slave address + W received and ACK transmitted. Slave 0x70 General call received and ACK transmitted. Slave 0x80 Previously addressed as slave, data byte received and ACK transmitted. Slave 0x88 Previously addressed as slave, data byte received and NACK transmitted. Slave 0x90 Previously addressed with GC, data byte received and ACK transmitted. Slave 0x98 Previously addressed with GC, data byte received and NACK transmitted. Slave 0xA0 A STOP or repeated START received when addressed as slave or GC. Slave 0xA8 I2Cs slave address + R received and ACK transmitted. Slave 0xB8 Previously addressed as slave, data byte transmitted and ACK received. Slave 0xC0 Previously addressed as slave, data byte transmitted and NACK received. Slave 0xC8 Previously addressed as slave, last data byte transmitted. Slave SCKD7−0 bit 7−0 Serial Clock Divisor. Write-only, master mode. The frequency of the SCL line is set equal to Sysclk/[2 • (SCKD + 1)]. The minimum value for SCKD is 3. SAE bit 7 Slave Address Enable. Write-only, slave mode. In slave mode, if this is set, address recognition is enabled. SA6−0 bit 6−0 Slave Address. Write-only, slave mode. The address of this device is used in slave mode for address recognition. 61 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 I2C Start (I2CSTART) (Available only on the MSC1211 and MSC1213) 7 6 5 4 3 2 1 0 SFR 9Eh I2CSTART bits 7−0 Reset Value 80h I2C Start. Write-only. When any value is written to this register, the I2C system is reset; that is, the counters and state machines will go back to the initial state. So, in multi-master mode when arbitration is lost, then the I2C should be reset so that the counters and finite state machines (FSMs) are brought back to the idle state. SPI Buffer Start Address (SPISTART) 7 SFR 9Eh 6 5 4 3 2 1 0 1 Reset Value 80h SPISTART bits 6−0 SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a circular FIFO that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters. SPITP bits 6−0 SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next byte will be written into the byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data register unless that would make it equal to the SPI Receive pointer. SPI Buffer End Address (SPIEND) 7 SFR 9Fh 6 5 4 3 2 1 0 1 Reset Value 80h SPIEND bits 6−0 SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer that is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address. SPIRP bits 6−0 SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the next byte to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero. Port 2 (P2) 7 SFR A0h P2 bits 7−0 62 6 5 4 3 2 1 0 Reset Value FFh Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port. During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0). www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 PWM Control (PWMCON) SFR A1h 7 6 5 4 3 2 1 0 Reset Value — — PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 00h PPOL bit 5 Period Polarity. Specifies the starting level of the PWM pulse. 0: ON Period. PWM Duty register programs the ON period. 1: OFF Period. PWM Duty register programs the OFF period. PWMSEL bit 4 PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHI. 0: Period (must be 0 for TONE mode) 1: Duty SPDSEL bit 3 Speed Select. 0: 1MHz (the USEC Clock) 1: SYSCLK TPCNTL bits 2−0 Tone Generator/Pulse Width Modulation Control. TPCNTL2 TPCNTL1 TPCNTL0 0 0 0 MODE Disable (default) 0 0 1 PWM 0 1 1 TONE—Square 1 1 1 TONE—Staircase Tone Low (TONELOW) /PWM Low (PWMLOW) SFR A2h 7 6 5 4 3 2 1 0 Reset Value PWM7 TDIV7 PWM6 TDIV6 PWM5 TDIV5 PWM4 TDIV4 PWM3 TDIV3 PWM2 TDIV2 PWM1 TDIV1 PWM0 TDIV0 00h PWMLOW bits 7−0 Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register. TDIV7−0 bits 7−0 Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance for the last 1/4 of this period. Tone High (TONEHI)/PWM High (PWMHI) SFR A3h 7 6 5 4 3 2 1 0 Reset Value PWM15 TDIV15 PWM14 TDIV14 PWM13 TDIV13 PWM12 TDIV12 PWM11 TDIV11 PWM10 TDIV10 PWM9 TDIV9 PWM8 TDIV8 00h PWMHI bits 7−0 Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register. TDIV15−8 bits 7−0 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance for the last 1/4 of this period. 63 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Poll (AIPOL) RD SFR A4h 7 6 5 4 3 2 1 ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV WR 0 Reset Value EDLVB 00h RDSEL 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC bit 7 Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Read-only. AIPOL.RDSEL = 1: Read: Current value of Seconds Timer Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESEC bit. ESUM bit 6 Enable Summation Interrupt. Read-only. AIPOL.RDSEL = 1: Read: Current value of Summation Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESUM bit. EADC bit 5 Enable ADC Interrupt. Read-only. AIPOL.RDSEL = 1: Read: Current value of ADC Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EADC bit. EMSEC bit 4 Enable Millisecond System Timer Interrupt. Read-only. AIPOL.RDSEL = 1: Read: Current value of Millisecond System Timer Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EMSEC bit. ESPIT bit 3 Enable SPI Transmit Interrupt. Read-only. AIPOL.RDSEL = 1: Read: Current value of Enable SPI Transmit Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESPIT bit. ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt (I2C available only on the MSC1213). Read-only. bit 2 AIPOL.RDSEL = 1: Read: Current value of Enable SPI Receive Interrupt or I2C Status Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of ESPIR/EI2C bit. EALV bit 1 Enable Analog Low Voltage Interrupt. Read-only. AIPOL.RDSEL = 1: Read: Current value of Enable Analog Low Voltage Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EALV bit. EDLVB bit 0 Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). Read-only. AIPOL.RDSEL = 1: Read: Current value of Enable Digital Low Voltage or Breakpoint Interrupt before masking. AIPOL.RDSEL = 0: Read: Value of EDLVB bit. RDSEL bit 0 Read Select. Write-only. AIPOL.RDSEL = 1: Read state for AIE and AIPOL registers. Reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of AIE register contents. AIPOL.RDSEL = 0: Read state for AIE and AIPOL registers. Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary interrupts before masking. 64 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Pending Auxiliary Interrupt (PAI) SFR A5h PAI3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00h Pending Auxiliary Interrupt. The results of this register can be used as an index to vector to the appropriate interrupt routine. All of these interrupts vector through address 0033h. PAI3 PAI2 PAI1 PAI0 0 0 0 0 AUXILIARY INTERRUPT STATUS No Pending Auxiliary IRQ 0 0 0 1 Digital Low Voltage IRQ Pending 0 0 1 0 0 0 1 1 Analog Low Voltage IRQ Pending SPI Receive IRQ Pending. I2C Status Pending. 0 1 0 0 SPI Transmit IRQ Pending. 0 1 0 1 One Millisecond System Timer IRQ Pending. 0 1 1 0 Analog-to-Digital Conversion IRQ Pending. 0 1 1 1 Accumulator IRQ Pending. 1 0 0 0 One Second System Timer IRQ Pending. 65 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Enable (AIE) SFR A6h 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC ESPIT ESPIR/EI2C EALV EDLVB 00h Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers. ESEC bit 7 Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Seconds Timer Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESEC bit. ESUM bit 6 Enable Summation Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Summation Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESUM bit. EADC bit 5 Enable ADC Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of ADC Interrupt before masking. When AIPOL.RDSEL = 1: Value of EADC bit. EMSEC bit 4 Enable Millisecond System Timer Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Millisecond System Timer Interrupt before masking. When AIPOL.RDSEL = 1: Value of EMSEC bit. ESPIT bit 3 Enable SPI Transmit Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of SPI Transmit Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESPIT bit. ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt. (I2C available only on the MSC1213.) bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of SPI Receive Interrupt or I2C Status Interrupt before masking. When AIPOL.RDSEL = 1: Value of ESPIR/EI2C bit. EALV bit 1 Enable Analog Low Voltage Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Analog Low Voltage Interrupt before masking. When AIPOL.RDSEL = 1: Value of EALV bit. EDLVB bit 0 Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: When AIPOL.RDSEL = 0: Current value of Digital Low Voltage or Breakpoint Interrupt before masking. When AIPOL.RDSEL = 1: Value of EDLVB bit. 66 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Auxiliary Interrupt Status (AISTAT) SFR A7h 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC SPIT SPIR/I2CSI ALVD DLVD 00h SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC interrupt inactive or masked. 1: SEC Interrupt active. SUM bit 6 Summation Register Interrupt Status Flag. 0: SUM interrupt inactive or masked (if active, it is set inactive by reading the lowest byte of the Summation register). 1: SUM interrupt active. ADC bit 5 ADC Interrupt Status Flag. 0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register). 1: ADC interrupt active (If active no new data will be written to the Data Output Register). MSEC bit 4 Millisecond System Timer Interrupt Status Flag. 0: MSEC interrupt inactive or masked. 1: MSEC interrupt active. SPIT bit 3 SPI Transmit Interrupt Status Flag. 0: SPI transmit interrupt inactive or masked. 1: SPI transmit interrupt active. SPIR/I2CSI SPI Receive Interrupt Status Flag. I2C Status Interrupt. (I2C available only on the MSC1213.) bit 2 0: SPI receive or I2CSI interrupt inactive or masked. 1: SPI receive or I2CSI interrupt active. ALVD bit 1 Analog Low Voltage Detect Interrupt Status Flag. 0: ALVD interrupt inactive or masked. 1: ALVD interrupt active. DLVD bit 0 Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI). 0: DLVD interrupt inactive or masked. 1: DLVD interrupt active. 67 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Interrupt Enable (IE) SFR A8h 7 6 5 4 3 2 1 0 Reset Value EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00h EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES1 bit 6 Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt. 0: Disable all serial Port 1 interrupts. 1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0h) or TI_1 (SCON1.1, SFR C0h) flags. ET2 bit 5 Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt. 0: Disable all Timer 2 interrupts. 1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8h). ES0 bit 4 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags. ET1 bit 3 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h). EX1 bit 2 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 bit 1 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h). EX0 bit 0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. 68 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Breakpoint Control (BPCON) SFR A9h 7 6 5 4 3 2 1 0 Reset Value BP 0 0 0 0 0 PMSEL EBP 00h Writing to this register sets the breakpoint condition specified by MCON, BPL, and BPH. BP bit 7 Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s). Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers. Write: 0: No effect. 1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95h). PMSEL bit 1 Program Memory Select. Write this bit to select memory for address breakpoints of register selected in MCON (SFR 95h). 0: Break on address in Data Memory. 1: Break on address in Program Memory. EBP bit 0 Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by MCON (SFR 95h). 0: Breakpoint disabled. 1: Breakpoint enabled. Breakpoint Low (BPL) Address for BP Register Selected in MCON (95h) SFR AAh BPL.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value BPL.7 BPL.6 BPL.5 BPL.4 BPL.3 BPL.2 BPL.1 BPL.0 00h Breakpoint Low Address. The low 8 bits of the 16-bit breakpoint address. Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95h) SFR ABh BPH.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value BPH.7 BPH.6 BPH.5 BPH.4 BPH.3 BPH.2 BPH.1 BPH.0 00h Breakpoint High Address. The high 8 bits of the 16-bit breakpoint address. 69 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction Low (P0DDRL) SFR ACh P0.3 bits 7−6 P0.2 bits 5−4 P0.1 bits 3−2 P0.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P03H P03L P02H P02L P01H P01L P00H P00L 00h Port 0 Bit 3 Control. P03H P03L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 2 Control. P02H P02L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 1 Control. P01H P01L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 0 Control. P00H P00L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0. 70 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 0 Data Direction High (P0DDRH) SFR ADh P0.7 bits 7−6 P0.6 bits 5−4 P0.5 bits 3−2 P0.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P07H P07L P06H P06L P05H P05L P04H P04L 00h Port 0 Bit 7 Control. P07H P07L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 6 Control. P06H P06L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 5 Control. P05H P05L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 0 Bit 4 Control. P04H P04L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0. 71 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction Low (P1DDRL) SFR AEh P1.3 bits 7−6 P1.2 bits 5−4 P1.1 bits 3−2 P1.0 bits 1−0 72 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00h Port 1 Bit 3 Control. P13H P13L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 2 Control. P12H P12L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 1 Control. P11H P11L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 0 Control. P10H P10L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 1 Data Direction High (P1DDRH) SFR AFh P1.7 bits 7−6 P1.6 bits 5−4 P1.5 bits 3−2 P1.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00h Port 1 Bit 7 Control. P17H P17L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 6 Control. P16H P16L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 5 Control. P15H P15L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 1 Bit 4 Control. P14H P14L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 73 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 (P3) SFR B0h 7 6 5 4 3 2 1 0 Reset Value P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFh P3.7−0 bits 7−0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. RD bit 7 External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device. If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. WR bit 6 External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory device. If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored. T1 bit 5 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. T0 bit 4 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. INT1 bit 3 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. INT0 bit 2 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. TXD0 bit 1 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. RXD0 bit 0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0. 74 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction Low (P2DDRL) SFR B1h P2.3 bits 7−6 P2.2 bits 5−4 P2.1 bits 3−2 P2.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P23H P23L P22H P22L P21H P21L P20H P20L 00h Port 2 Bit 3 Control. P23H P23L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 2 Control. P22H P22L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 1 Control. P21H P21L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 0 Control. P20H P20L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23. 75 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 2 Data Direction High (P2DDRH) SFR B2h P2.7 bits 7−6 P2.6 bits 5−4 P2.5 bits 3−2 P2.4 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P27H P27L P26H P26L P25H P25L P24H P24L 00h Port 2 Bit 7 Control. P27H P27L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 6 Control. P26H P26L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 5 Control. P25H P25L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 2 Bit 4 Control. P24H P24L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23. 76 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction Low (P3DDRL) SFR B3h P3.3 bits 7−6 P3.2 bits 5−4 P3.1 bits 3−2 P3.0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00h Port 3 Bit 3 Control. P33H P33L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 2 Control. P32H P32L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 1 Control. P31H P31L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 0 Control. P30H P30L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input 77 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Port 3 Data Direction High (P3DDRH) SFR B4h P3.7 bits 7−6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00h Port 3 Bit 7 Control. P37H P37L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5−4 Port 3 Bit 6 Control. P36H P36L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 bits 3−2 P3.4 bits 1−0 78 Port 3 Bit 5 Control. P35H P35L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input Port 3 Bit 4 Control. P34H P34L 0 0 Standard 8051 (Pull-Up) 0 1 CMOS Output 1 0 Open Drain Output 1 1 Input www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Low Byte (DACL) 7 6 5 4 3 2 1 0 SFR B5h DACL7−0 bits 7−0 Reset Value 00h Least Significant Byte Register for DAC0−3, DAC Control (0 and 2), and DAC Load Control . NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212. DAC High Byte (DACH) 7 6 5 4 3 2 1 0 SFR B6h DACH7−0 bits 7−0 Reset Value 00h Most Significant Byte Register for DAC0−3 and DAC Control (1 and 3). NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212. DAC Select (DACSEL) SFR B7h DSEL7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DSEL7 DSEL6 DSEL5 DSEL4 DSEL3 DSEL2 DSEL1 DSEL0 00h DAC Select and DAC Control Select. The DACSEL register selects which DAC output register or which DAC control register is accessed by the DACL and DACH registers. DACSEL (B7h) DACH (B6h) DACL (B5h) RESET VALUE 00h 01h 02h 03h 04h 05h 06h 07h DAC0 (high) DAC1 (high) DAC2(1) (high) DAC3(1) (high) DACCON1 DACCON3(1) — — DAC0 (low) DAC1 (low) DAC2(1) (low) DAC3(1) (low) DACCON0 DACCON2(1) LOADCON — 0000h 0000h 0000h 0000h 6363h 0303h −−00h — (1) DAC2 and DAC3 available only on the MSC1211 and MSC1212. 79 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC0 Control (DACCON0) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B5h COR0 EOD0 IDAC0DIS IDAC0SINK 0 SELREF0 DOM0_1 DOM0_0 63h COR0 bit 7 Current Over Range on DAC0 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = NOP Read: 0 = No current over range for DAC0. 0 = NOP 1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD0 = 1) or Current Over Range raw signal (EOD0 = 0). EOD0 bit 6 Enable Over-Current Detection 0 = Disable over-current detection. 1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is disabled; however, the register values are preserved. Writing to COR0 releases the high-impedance state. IDAC0DIS bit 5 IDAC0 Disable (for DOM0 = 00) 0 = IDAC on mode for DAC0. 1 = IDAC off mode for DAC0 (default). IDAC0SINK ENABLE CURRENT SINK bit 4 0 = DAC0 is sourcing current. 1 = DAC0 is sinking current using external device. Not Used bit 3 SELREF0 bit 2 Select the Reference Voltage for DAC0 Voltage Reference. 0 = DAC0 VREF = AVDD (default). 1 = DAC0 VREF = voltage on REF IN+/REFOUT pin. DOM0_1−0 DAC Output Mode DAC0. bits 1−0 DOM0 80 OUTPUT MODE for DAC0 00 Normal VDAC output; IDAC controlled by IDAC0DIS bit. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC1 Control (DACCON1) DACSEL = 04h 7 6 5 4 3 2 1 0 Reset Value SFR B6h COR1 EOD1 IDAC1DIS IDAC1SINK 0 SELREF1 DOM1_1 DOM1_0 63h COR1 bit 7 Current Over Range on DAC1 Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists. 1 = No effect. Read: 0 = No current over range for DAC1. 0 = No effect. 1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD1 = 1) or Current Over Range raw signal (EOD0 = 0). EOD1 bit 6 Enable Over-Current Detection 0 = Disable over-current detection. 1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is disabled; however, the register values are preserved. Writing to COR1 releases the high-impedance state. IDAC1DIS bit 5 IDAC1 Disable (for DOM1 = 00) 0 = IDAC on mode for DAC1. 1 = IDAC off mode for DAC1 (default). IDAC1SINK ENABLE CURRENT SINK bit 4 0 = DAC1 is sourcing current. 1 = DAC1 is sinking current using external device. Not Used bit 3 SELREF1 bit 2 Select the Reference Voltage for DAC1 Voltage Reference. 0 = DAC1 VREF = AVDD (default). 1 = DAC1 VREF = voltage on VREF IN pins. DOM1_1−0 DAC Output Mode DAC1. bits 1−0 DOM1 OUTPUT MODE for DAC1 00 Normal VDAC output; IDAC controlled by IDAC1DIS bit. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). 81 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC2 Control (DACCON2) (Available only on the MSC1211 and MSC1212) DACSEL = 05h 7 6 5 4 3 2 1 0 Reset Value SFR B5h 0 0 0 0 0 SELREF2 DOM2_1 DOM2_0 03h SELREF2 bit 2 Select the Reference Voltage for DAC2 Voltage Reference. 0 = DAC2 VREF = AVDD (default). 1 = DAC2 VREF = internal VREF. DOM2_1−0 DAC Output Mode DAC2. bits 1−0 DOM2 OUTPUT MODE for DAC2 00 Normal VDAC output. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). DAC3 Control (DACCON3) (Available only on the MSC1211 and MSC1212) DACSEL = 05h 7 6 5 4 3 2 1 0 Reset Value SFR B6h 0 0 0 0 0 SELREF3 DOM3_1 DOM3_0 03h SELREF3 bit 2 Select the Reference Voltage for DAC3 Voltage Reference. 0 = DAC3 VREF = AVDD (default). 1 = DAC3 VREF = internal VREF. DOM3_1−0 DAC Output Mode DAC3. bits 1−0 DOM2 82 OUTPUT MODE for DAC3 00 Normal VDAC output. 01 Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off. 10 Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off. 11 Power-Down mode—VDAC output off high impedance, IDAC off (default). www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 DAC Load Control (LOADCON) DACSEL = 06h 7 6 5 4 3 2 1 0 Reset Value SFR B5h D3LOAD1 D3LOAD0 D2LOAD1 D2LOAD0 D1LOAD1 D1LOAD0 D0LOAD1 D0LOAD0 00h D3LOAD1−0 (Available only on MSC1211 and MSC1212) bit 7−6 The DAC load options are listed below: DxLOAD OUTPUT MODE for 00 Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output). 01 Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next MSEC timer tick. 10 Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next HMSEC timer tick. 11 Sync load: the values contained in the DACxL/DACxH registers will be transferred to the DAC output immediately after 11b is written to this register. D2LOAD1−0 (Available only on MSC1211 and MSC1212) bit 5−4 D1LOAD1−0 bit 3−2 D0LOAD1−0 bit 1−0 Interrupt Priority (IP) SFR B8h 7 6 5 4 3 2 1 0 Reset Value 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80h PS1 bit 6 Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt. 0 = Serial Port 1 priority is determined by the natural priority order. 1 = Serial Port 1 is a high-priority interrupt. PT2 bit 5 Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt. 0 = Timer 2 priority is determined by the natural priority order. 1 = Timer 2 priority is a high-priority interrupt. PS0 bit 4 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high-priority interrupt. PT1 bit 3 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high-priority interrupt. PX1 bit 2 External Interrupt 1. This bit controls the priority of external interrupt 1. 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high-priority interrupt. PT0 bit 1 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high-priority interrupt. PX0 bit 0 External Interrupt 0. This bit controls the priority of external interrupt 0. 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high-priority interrupt. 83 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Serial Port 1 Control (SCON1) SFR C0h SM0−2 bits 7−5 7 6 5 4 3 2 1 0 Reset Value SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00h Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 Synchronous 8 bits 0 0 0 1 Synchronous 8 bits 12 pCLK(1) 4 pCLK(1) 1(2) 1(2) 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation 0 1 1 Valid Stop Required(3) 10 bits Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 2 1 0 1 Asynchronous with Multiprocessor Communication(4) 11 bits 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 64 pCLK(1) (SMOD = 0) 32 pCLK(1) (SMOD = 1) 3(2) 3(2) 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation 1 1 1 Asynchronous with Multiprocessor Communication(4) 11 bits Timer 1 Baud Rate Equation (1) pCLK will be equal to tCLK, except that pCLK will stop for Idle mode. (2) For modes 1 and 3, the selection of Timer 1 for baud rate is specified via the T2CON (C8h) register. (3) RI_0 will only be activated when a valid STOP is received. (4) RI_0 will not be activated if bit 9 = 0. REN_1 bit 4 Receive Enable. This bit enables/disables the serial Port 1 received shift register. 0 = Serial Port 1 reception disabled. 1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_1 bit 3 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3. RB8_1 bit 2 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0. TI_1 bit 1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be cleared by software to transmit the next byte. RI_1 bit 0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must be cleared by software to receive the next byte. Serial Data Buffer 1 (SBUF1) 7 SFR C1h 6 5 4 3 2 1 0 Reset Value 00h SBUF1.7−0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive bits 7−0 buffers are separate registers, but both are addressed at this location. 84 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Wake Up (EWU) Waking Up from Idle Mode SFR C6h 7 6 5 4 3 2 1 0 Reset Value — — — — — EWUWDT EWUEX1 EWUEX0 00h Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5). EWUWDT bit 2 Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt. 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 bit 1 Enable Wake Up External 1. Wake using external interrupt source 1. 0 = Don’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 bit 0 Enable Wake Up External 0. Wake using external interrupt source 0. 0 = Don’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. System Clock Divider (SYSCLK) SFR C7h 7 6 5 4 3 2 1 0 Reset Value 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00h NOTE: Changing SYSCLK registers affects all internal clocks, including the ADC clock. DIVMOD1−0 Clock Divide Mode bits 5−4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide). 01 Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition or by direct write to SFR. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit by directly writing to SFR. 11 Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR. Read: DIVMOD DIV2−0 DIVISION MODE STATUS 00 No divide 01 Divider is in Immediate mode 10 Divider is in Delay mode 11 Medium mode Divide Mode bit 2−0 DIV DIVISOR fCLK FREQUENCY 000 Divide by 2 (default) fCLK = fSYS/2 001 Divide by 4 fCLK = fSYS/4 010 Divide by 8 fCLK = fSYS/8 011 Divide by 16 fCLK = fSYS/16 100 Divide by 32 fCLK = fSYS/32 101 Divide by 1024 fCLK = fSYS/1024 110 Divide by 2048 fCLK = fSYS/2048 111 Divide by 4096 fCLK = fSYS/4096 85 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Control (T2CON) SFR C8h 7 6 5 4 3 2 1 0 Reset Value TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00h TF2 bit 7 Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software. TF2 will only be set if RCLK and TCLK are both cleared to ‘0’. Writing a ‘1’ to TF2 forces a Timer 2 interrupt if enabled. EXF2 bit 6 Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on the EXEN2 (T2CON.3) bit. If set by a negative transition, this flag must be cleared to ‘0’ by software. Setting this bit in software will force a timer interrupt if enabled. RCLK bit 5 Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3. 0 = Timer 1 overflow is used to determine receiver baud rate for USART0. 1 = Timer 2 overflow is used to determine receiver baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. TCLK bit 4 Transmit Clock Flag. This bit determines the serial Port 0 timebase when transmitting data in serial modes 1 or 3. 0 = Timer 1 overflow is used to determine transmitter baud rate for USART0. 1 = Timer 2 overflow is used to determine transmitter baud rate for USART0. Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the external clock. EXEN2 bit 3 Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating baud rates for the serial port. 0 = Timer 2 will ignore all external events at T2EX. 1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin. TR2 bit 2 Timer 2 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. C/T2 bit 1 Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode. 0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5). 1 = Timer 2 will count negative transitions on the T2 pin (P1.0). CP/RL2 bit 0 Capture/Reload Select. This bit determines whether the capture or reload function will be used for Timer 2. If either RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each overflow. 0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1. 1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1. Timer 2 Capture LSB (RCAP2L) 7 SFR CAh RCAP2L bits 7−0 86 6 5 4 3 2 1 0 Reset Value 00h Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Timer 2 Capture MSB (RCAP2H) 7 6 5 4 3 2 1 0 Reset Value SFR CBh RCAP2H bits 7−0 00h Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode. Timer 2 LSB (TL2) 7 6 5 4 3 2 1 0 Reset Value SFR CCh TL2 bits 7−0 00h Timer 2 LSB. This register contains the least significant byte of Timer 2. Timer 2 MSB (TH2) 7 6 5 4 3 2 1 0 Reset Value SFR CDh TH2 bits 7−0 00h Timer 2 MSB. This register contains the most significant byte of Timer 2. Program Status Word (PSW) SFR D0h 7 6 5 4 3 2 1 0 Reset Value CY AC F0 RS1 RS0 OV F1 P 00h CY bit 7 Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations. AC bit 6 Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations. F0 bit 5 User Flag 0. This is a bit-addressable, general-purpose flag for software control. RS1, RS0 bits 4−3 Register Bank Select 1−0. These bits select which register bank is addressed during register accesses. RS1 RS0 REGISTER BANK ADDRESS 0 0 0 00h − 07h 0 1 1 08h − 0Fh 1 0 2 10h − 17h 1 1 3 18h − 1Fh OV bit 2 Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations. F1 bit 1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. P bit 0 Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to ‘0’ on even parity. 87 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Offset Calibration Low Byte (OCL) 7 6 5 4 3 2 1 0 Reset Value SFR D1h OCL bits 7−0 00h ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration Middle Byte (OCM) 7 6 5 4 3 2 1 0 Reset Value SFR D2h OCM bits 7−0 00h ADC Offset Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Offset Calibration High Byte (OCH) 7 6 5 4 3 2 1 0 Reset Value SFR D3h OCH bits 7−0 00h ADC Offset Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC offset calibration. A value that is written to this location will set the ADC offset calibration value. ADC Gain Calibration Low Byte (GCL) 7 6 5 4 3 2 1 0 SFR D4h GCL bits 7−0 Reset Value 5Ah ADC Gain Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration Middle Byte (GCM) 7 6 5 4 3 2 1 0 SFR D5h GCM bits 7−0 Reset Value ECh ADC Gain Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. ADC Gain Calibration High Byte (GCH) 7 6 5 4 3 2 1 0 SFR D6h GCH bits 7−0 88 Reset Value 5Fh ADC Gain Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC gain calibration. A value that is written to this location will set the ADC gain calibration value. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Input Multiplexer (ADMUX) SFR D7h INP3−0 bits 7−4 INN3−0 bits 3−0 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01h Input Multiplexer Positive Input. This selects the positive signal input. INP3 INP2 INP1 INP0 0 0 0 0 POSITIVE INPUT AIN0 (default) 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) Input Multiplexer Negative Input. This selects the negative signal input. INN3 INN2 INN1 INN0 0 0 0 0 NEGATIVE INPUT AIN0 0 0 0 1 AIN1 (default) 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor (requires ADMUX = FFh) 89 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Enable Interrupt Control (EICON) SFR D8h 7 6 5 4 3 2 1 0 Reset Value SMOD1 1 EAI AI WDTI 0 0 0 40h SMOD1 bit 7 Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled. 0 = Standard baud rate for Port 1 (default). 1 = Double baud rate for Port 1. EAI bit 5 Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI bit 4 Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI bit 3 Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Low Byte (ADRESL) 7 6 5 4 3 2 1 0 SFR D9h ADRESL bits 7−0 Reset Value 00h The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 SFR DAh ADRESM bits 7−0 Reset Value 00h The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the A/D conversion results. ADC Results High Byte (ADRESH) 7 SFR DBh ADRESH bits 7−0 90 6 5 4 3 2 1 0 Reset Value 00h The ADC Results High Byte. This is the high byte of the 24-bit word that contains the A/D conversion results. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 0 (ADCON0) SFR DCh REFCLK bit 7 7 6 5 4 3 2 1 0 Reset Value REFCLK BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30h Reference Clock. The reference is specified with a 250kHz clock. The REFCLK should be selected by choosing the appropriate source so that it does not exceed 250kHz. t CLK (ACLK ) 1) * 4 1 + USEC 4 0+ BOD bit 6 Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. Used with Buffer ON. 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF bit 5 Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to save power and reduce noise. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). REF IN− should be connected to AGND in this mode. REF IN+ should have a 0.1µF capacitor. VREFH bit 4 Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. 0 = REFOUT/REF IN+ is 1.25V. 1 = REFOUT/REF IN+ is 2.5V (default). EBUF bit 3 Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. PGA2−0 bits 2−0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. PGA2 PGA1 PGA0 GAIN 0 0 0 1 (default) 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 91 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 ADC Control 1 (ADCON1) SFR DDh 7 6 5 4 3 2 1 0 Reset Value OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 0000 0000b OF_UF bit 7 Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow occurred. The bit is cleared by writing a ‘0’ to it. POL bit 6 Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution). POL ANALOG INPUT +FSR 7FFFFFh 0 ZERO 000000h 1 SM1−0 bits 5−4 CAL2−0 bits 2−0 DIGITAL OUTPUT −FSR 800000h +FSR FFFFFFh ZERO 000000h −FSR 000000h Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics. SM1 SM0 0 0 SETTLING MODE Auto 0 1 1 0 Fast Settling Filter Sinc2 Filter 1 1 Sinc3 Filter Calibration Mode Control Bits. Writing to these bits initiates the ADC calibration. CAL2 CAL1 CAL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CALIBRATION MODE No Calibration (default) Self-Calibration, Offset and Gain Self-Calibration, Offset only Self-Calibration, Gain only System Calibration, Offset only System Calibration, Gain only Reserved Reserved NOTE: Read Value—000b. ADC Control 2 (ADCON2) SFR DEh DR7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1Bh Decimation Ratio LSB. ADC Control 3 (ADCON3) SFR DFh DR10−8 bits 2−0 92 7 6 5 4 3 2 1 0 Reset Value — — — — — DR10 DR9 DR8 06h Decimation Ratio Most Significant 3 Bits. The ADC output data rate = (ACLK + 1)/64/Decimation Ratio. www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Accumulator (A or ACC) SFR E0h ACC.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h Accumulator. This register serves as the accumulator for arithmetic and logic operations. Summation/Shifter Control (SSCON) SFR E1h 7 6 5 4 3 2 1 0 Reset Value SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00h The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar mode is selected in ADCON1. SSCON1−0 Summation/Shift Count. bits 7−6 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION 0 0 0 0 0 0 0 0 Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 (sum count/shift ignored) 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 (sum count/shift ignored) 1 0 x x x Note (1) Note (1) Note (1) 0 1 Note (1) Note (1) Note (1) x x x 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) CPU Shift only ADC Summation only ADC Summation completes, then shift completes (1) Refer to register bit definition. SCNT2−0 bits 5−3 SHF2−0 bits 2−0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 0 0 0 SUMMATION COUNT 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 Shift Count. SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 1 2 0 0 1 2 4 0 1 0 3 8 0 1 1 4 16 1 0 0 5 32 1 0 1 6 64 1 1 0 7 128 1 1 1 8 256 93 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Summation 0 (SUMR0) 7 6 5 4 3 2 1 0 SFR E2h SUMR0 bits 7−0 Reset Value 00h Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7. Write: values in SUMR3−0 are added to the summation register. Read: clears the Summation Count Interrupt; however, AI in EICON (SFR D8) must also be cleared. Summation 1 (SUMR1) 7 6 5 4 3 2 1 0 SFR E3h SUMR1 bits 7−0 Reset Value 00h Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15. Summation 2 (SUMR2) 7 6 5 4 3 2 1 0 SFR E4h SUMR2 bits 7−0 Reset Value 00h Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23. Summation 3 (SUMR3) 7 6 5 4 3 2 1 0 SFR E5h SUMR3 bits 7−0 Reset Value 00h Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31. Offset DAC (ODAC) 7 6 5 4 SFR E6h 3 2 1 0 Reset Value 00h ODAC bits 7−0 Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC.. The offset DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input. bit 7 Offset DAC Sign bit. 0 = Positive 1 = Negative bit 6−0 Offset + ǒ Ǔ ODAC ƪ 6 : 0ƫ *V REF bit7 @ @ (* 1) 127 2 @ PGA NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND. 94 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Low Voltage Detect Control (LVDCON) SFR E7h 7 6 5 4 3 2 1 0 Reset Value ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 00h ALVDIS bit 7 Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage. 1 = Disable Detection of Low Analog Supply Voltage. ALVD2−0 bits 6−4 Analog Voltage Detection Level. ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL 0 0 0 0 0 1 AVDD 2.7V (default) AVDD 3.0V 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 AVDD 3.3V AVDD 4.0V AVDD 4.2V AVDD 4.5V AVDD 4.7V External Voltage AIN7 compared to 1.2V DLVDIS bit 3 Digital Low Voltage Detect Disable. 0 = Enable Detection of Low Digital Supply Voltage. 1 = Disable Detection of Low Digital Supply Voltage. DLVD2−0 bits 2−0 Digital Voltage Detection Level. DLVD2 DLVD1 DLVD0 VOLTAGE LEVEL 0 0 0 0 0 1 DVDD 2.7V (default) DVDD 3.0V 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 DVDD 3.3V DVDD 4.0V DVDD 4.2V DVDD 4.5V DVDD 4.7V External Voltage AIN6 compared to 1.2V 95 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Extended Interrupt Enable (EIE) SFR E8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 EWDI EX5 EX4 EX3 EX2 E0h EWDI bit 4 Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by (SFR FFh) and PDCON (SFR F1h) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 bit 3 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 bit 2 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 bit 1 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 bit 0 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 Hardware Product Code 0 (HWPC0) SFR E9h 7 6 5 4 3 2 1 0 0 0 0 0 1 MEMORY SIZE 0 Reset Value 0000_01xxb(1) (1) Applies to MSC1211 and MSC1213 only. Reset value for MSC1212 and MSC1214 is 0000_00xxb. HWPC0.7−0 Hardware Product Code LSB. Read-only. bits 7−0 MEMORY SIZE MODEL FLASH MEMORY 4kB 0 0 MSC121xY2 0 0 MSC121xY3 8kB 1 0 MSC121xY4 16kB 1 1 MSC121xY5 32kB Hardware Product Code 1 (HWPC1) SFR EAh 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 1 0 0 0 08h(1) (1) Applies to MSC1211 and MSC1212 only. Reset value for MSC1213 and MSC1214 is 18h. HWPC1.7−0 Hardware Product Code MSB. Read-only. bits 7−0 96 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Hardware Version (HDWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBh Flash Memory Control (FMCON) SFR EEh 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY SPM FPM 02h PGERA bit 6 Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine). FRCM bit 4 Frequency Control Mode. 0 = Bypass (default) 1 = Use Delay Line. Recommended for saving power. BUSY bit 2 Write/Erase BUSY Signal. 0 = Idle or Available 1 = Busy SPM bit 1 Serial/Parallel Programming Mode. Read-only. 0 = Indicates the device is in parallel programming mode. 1 = Indicates the device is in serial programming mode (if FPM also = 1). FPM bit 0 Flash Programming Mode. Read-only. 0 = Indicates the device is operating in UAM. 1 = Indicates the device is operating in programming mode. Flash Memory Timing Control (FTCON) SFR EFh 7 6 5 4 3 2 1 0 Reset Value FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5h Refer to Flash Memory Characteristics FER3−0 bits 7−4 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK. This can be broken into multiple shorter erase times. For more Information, see Application Report SBAA137, Incremental Flash Memory Page Erase, available for download from www.ti.com. Industrial temperature range: 10ms Commercial temperature range: 4ms FWR3−0 bits 3−0 Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK. Total writing time will be longer. For more Information, see Application Report SBAA087, In-Application Flash Programming, available for download from www.ti.com. Range: 30µs to 40µs. B Register (B) SFR F0h B.7−0 bits 7−0 7 6 5 4 3 2 1 0 Reset Value B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h B Register. This register serves as a second accumulator for certain arithmetic operations. 97 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Power-Down Control (PDCON) SFR F1h 7 6 5 4 3 2 1 0 Reset Value 0 PDDAC PDI2C PDPWM PDADC PDWDT PDST PDSPI 7Fh Turning peripheral modules off puts the MSC1211/12/13/14 in the lowest power mode. PDDAC bit 6 DAC Module Control. 0 = DACs On 1 = DACs Power Down PDI2C bit 5 I2C Control (MSC1211 and MSC1213 only). 0 = I2C On (the state is undefined if PDSPI is also = 0) 1 = I2C Power Down PDPWM bit 4 Pulse Width Module Control. 0 = PWM On 1 = PWM Power Down PDADC bit 3 ADC Control. 0 = ADC On 1 = ADC, VREF, and Summation registers are powered down. PDWDT bit 2 Watchdog Timer Control. 0 = Watchdog Timer On 1 = Watchdog Timer Power Down PDST bit 1 System Timer Control. 0 = System Timer On 1 = System Timer Power Down PDSPI bit 0 SPI System Control. 0 = SPI System On (the state is undefined if PDI2C is also = 0) 1 = SPI System Power Down PSEN/ALE Select (PASEL) SFR F2h PSEN2−0 bits 5−3 ALE1−0 bits 1−0 7 6 5 4 3 2 1 0 Reset Value 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 00h PSEN Mode Select. PSEN2 PSEN1 PSEN0 0 0 1 1 1 0 1 0 1 1 X X X 0 1 ALE Mode Select. ALE1 ALE0 0 1 1 X 0 1 ALE Low High NOTE: X = don’t care. 98 PSEN CLK ADC MODCLK Low High www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Analog Clock (ACLK) SFR F6h 7 6 5 4 3 2 1 0 Reset Value 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h FREQ6−0 Clock Frequency Selection. This value + 1 divides the system clock to create the ACLK frequency. bit 6−0 ACLK frequency + f MOD + f CLK FREQ ) 1 f CLK (ACLK ) 1) * 64 Data Rate + f MOD Decimation System Reset (SRST) SFR F7h RSTREQ bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 RSTREQ 00h Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset. Extended Interrupt Priority (EIP) SFR F8h 7 6 5 4 3 2 1 0 Reset Value 1 1 1 PWDI PX5 PX4 PX3 PX2 E0h PWDI bit 4 Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 bit 3 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 bit 2 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 bit 1 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 bit 0 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. 99 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Seconds Timer Interrupt (SECINT) SFR F9h 7 6 5 4 3 2 1 0 Reset Value WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7Fh This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt; however, AI in EICON (SFR D8h) must also be cleared. This Interrupt can be monitored in the AIE or AIPOL registers. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK. Milliseconds Timer Interrupt (MSINT) SFR FAh 7 6 5 4 3 2 1 0 Reset Value WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7Fh The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also be cleared. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6−0 bits 6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval. MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK One Microsecond Timer (USEC) SFR FBh FREQ5−0 bits 5−0 7 6 5 4 3 2 1 0 Reset Value 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03h Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock. USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh). One Millisecond Timer Low Byte (MSECL) SFR FCh 7 6 5 4 3 2 1 0 Reset Value MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9Fh MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh). 100 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 One Millisecond Timer High Byte (MSECH) SFR FDh 7 6 5 4 3 2 1 0 Reset Value MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0Fh MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock. bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. One Hundred Millisecond Timer (HMSEC) SFR FEh WRT bit 7 7 6 5 4 3 2 1 0 Reset Value WRT HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63h Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. HMSEC6−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 6−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK. Watchdog Timer (WDTCON) SFR FFh 7 6 5 4 3 2 1 0 Reset Value EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00h EWDT bit 7 Enable Watchdog (R/W). Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT bit 6 Disable Watchdog (R/W). Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT bit 5 Reset Watchdog (R/W). Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4−0 Watchdog Count (R/W). bits 4−0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. 101 www.ti.com SBAS323G − JUNE 2004 − REVISED OCTOBER 2007 Revision History DATE REV PAGE SECTION 10/07 G 29 Voltage Reference 7/06 F 32 Brownout Reset DESCRIPTION Added paragraph to end of section. Added paragraph on BOR voltage calibration. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 102 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSC1211Y2PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y2PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y3PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y4PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y5PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1211Y5PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1211Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1211Y5PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y2PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y2PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y3PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y4PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1212Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Aug-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSC1212Y5PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y2PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y2PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y2PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y2PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y3PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y3PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y3PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y4PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y4PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y4PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y5PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y5PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1213Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1213Y5PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y2PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Aug-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSC1214Y2PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y2PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y2PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y3PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y3PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y3PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y3PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y4PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y4PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y4PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y4PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y5PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y5PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Purchase Samples MSC1214Y5PAGT ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples MSC1214Y5PAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSC1211Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y3PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y4PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y5PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1211Y5PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y3PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y4PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1212Y5PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y2PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y3PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y3PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y4PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y4PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y5PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1213Y5PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y2PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2010 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSC1214Y2PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y3PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y3PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y4PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y4PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y5PAGR TQFP PAG 64 1500 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 MSC1214Y5PAGT TQFP PAG 64 250 330.0 24.8 13.0 13.0 1.5 16.0 24.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1211Y2PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1211Y3PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1211Y4PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1211Y5PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1211Y5PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1212Y2PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1212Y3PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1212Y4PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1212Y5PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1213Y2PAGR TQFP PAG 64 1500 346.0 346.0 41.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2010 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSC1213Y2PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1213Y3PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1213Y3PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1213Y4PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1213Y4PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1213Y5PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1213Y5PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1214Y2PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1214Y2PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1214Y3PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1214Y3PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1214Y4PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1214Y4PAGT TQFP PAG 64 250 346.0 346.0 41.0 MSC1214Y5PAGR TQFP PAG 64 1500 346.0 346.0 41.0 MSC1214Y5PAGT TQFP PAG 64 250 346.0 346.0 41.0 Pack Materials-Page 3 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. 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