STMicroelectronics M93C66-WMN3G 16kbit, 8kbit, 4kbit, 2kbit and 1kbit (8-bit or 16-bit wide) microwire serial access eeprom Datasheet

M93C86, M93C76, M93C66
M93C56, M93C46
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)
MICROWIRE® Serial Access EEPROM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
■
■
Industry Standard MICROWIRE Bus
Single Supply Voltage:
– 4.5 to 5.5V for M93Cx6
– 2.5 to 5.5V for M93Cx6-W
– 1.8 to 5.5V for M93Cx6-R
Dual Organization: by Word (x16) or Byte (x8)
Programming Instructions that work on: Byte,
Word or Entire Memory
Self-timed Programming Cycle with AutoErase: 5ms
Ready/Busy Signal During Programming
2MHz Clock Rate
Sequential Read Operation
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
Packages
– ECOPACK® (RoHS compliant)
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
Table 1. Product List
Reference
Part
Number
Reference
M93C86
M93C86
M93C76
M93C86-W
M93C56
M93C56
M93C56-W
M93C86-R
M93C56-R
M93C76
M93C46
M93C76-W
M93C76-R
M93C66
M93C66
Part
Number
M93C46
TSSOP8 (DW)
169 mil width
M93C46-W
M93C46-R
TSSOP8 (DS)
3x3mm² body size (MSOP)
M93C66-W
M93C66-R
UFDFPN8 (MB)
2x3mm² (MLP)
October 2005
1/31
M93C86, M93C76, M93C66, M93C56, M93C46
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1.
Figure 1.
Figure 2.
Table 2.
Table 3.
Table 4.
Figure 3.
Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INTERNAL DEVICE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ACTIVE POWER AND STANDBY POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Erase/Write Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. WRAL Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 12. AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15. DC Characteristics (M93Cx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 19. DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 23. AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 24
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 24
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 25
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Data . . . . . . 25
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 28
Table 28. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 28
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/31
M93C86, M93C76, M93C66, M93C56, M93C46
SUMMARY DESCRIPTION
These electrically erasable programmable memory (EEPROM) devices are accessed through a Serial Data Input (D) and Serial Data Output (Q)
using the MICROWIRE bus protocol.
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
lect (ORG). The bit, byte and word sizes of the
memories are as shown in Table 3.
Table 3. Memory Size versus Organization
Device
Number
of Bits
Number
of 8-bit
Bytes
Number
of 16-bit
Words
M93C86
16384
2048
1024
M93C76
8192
1024
512
M93C66
4096
512
256
M93C56
2048
256
128
M93C46
1024
128
64
Figure 2. Logic Diagram
The M93Cx6 is accessed by a set of instructions,
as summarized in Table 4., and in more detail in
Table 5. to Table 7.).
VCC
D
Table 4. Instruction Set for the M93Cx6
Q
Instruction
Description
Data
C
READ
Read Data from Memory
Byte or Word
S
WRITE
Write Data to Memory
Byte or Word
ORG
EWEN
Erase/Write Enable
EWDS
Erase/Write Disable
ERASE
Erase Byte or Word
ERAL
Erase All Memory
WRAL
Write All Memory
with same Data
M93Cx6
VSS
AI01928
Table 2. Signal Names
S
Chip Select Input
D
Serial Data Input
Q
Serial Data Output
C
Serial Clock
ORG
Organisation Select
VCC
Supply Voltage
VSS
Ground
The memory array organization may be divided
into either bytes (x8) or words (x16) which may be
selected by a signal applied on Organization Se-
4/31
Byte or Word
A Read Data from Memory (READ) instruction
loads the address of the first byte or word to be
read in an internal address register. The data at
this address is then clocked out serially. The address register is automatically incremented after
the data is output and, if Chip Select Input (S) is
held High, the M93Cx6 can output a sequential
stream of data bytes or words. In this way, the
memory can be read as a data stream from eight
to 16384 bits long (in the case of the M93C86), or
continuously (the address counter automatically
rolls over to 00h when the highest address is
reached).
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an Erase cycle prior to the Write
instruction. The Write instruction writes 8 or 16 bits
at a time into one of the byte or word locations of
the M93Cx6. After the start of the programming cycle, a Busy/Ready signal is available on Serial
M93C86, M93C76, M93C66, M93C56, M93C46
Data Output (Q) when Chip Select Input (S) is driven High.
An internal Power-on Data Protection mechanism
in the M93Cx6 inhibits the device when the supply
is too low.
Figure 3. DIP, SO, TSSOP and MLP
Connections (Top View)
The DU (Don’t Use) pin does not contribute to the
normal operation of the device. It is reserved for
use by STMicroelectronics during test sequences.
The pin may be left unconnected or may be connected to VCC or VSS. Direct connection of DU to
VSS is recommended for the lowest stand-by power consumption.
M93Cx6
S
C
D
Q
1
2
3
4
8
7
6
5
VCC
DU
ORG
VSS
AI01929B
Note: 1. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
2. DU = Don’t Use.
5/31
M93C86, M93C76, M93C66, M93C56, M93C46
MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to VCC)
the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to VSS or VCC for minimum
power consumption. Any voltage between VSS
and VCC applied to Organization Select (ORG)
may increase the stand-by current.
INTERNAL DEVICE RESET
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included.
At Power-up and Power-down, the device must
not be selected (that is, the Chip Select Input (S)
must be driven Low) until the supply voltage
reaches the operating voltage VCC (as defined in
Tables 9, 10 and 11).
During Power-up (phase during which VCC is lower than VCCmin but increases continuously), the
device will not respond to any instruction until VCC
has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC
operating voltage defined in DC AND AC PARAM-
ETERS). Once VCC has passed the POR threshold, the device is reset.
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (tW).
During Power-down (phase during which VCC decreases continuously), as soon as VCC drops from
the normal operating voltage below the Power On
Reset threshold voltage, the device stops responding to any instruction sent to it.
ACTIVE POWER AND STANDBY POWER MODES
When Chip Select (S) is High, the device is selected and in the Active Power mode. It consumes
ICC, as specified in Tables 15, 16, 17, 18 and 19.
When Chip Select (S) is Low, the device is deselected.
If no Erase/Write cycle is in progress when Chip
Select goes Low, the device enters the Standby
6/31
Power mode, and the power consumption drops to
ICC1.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
M93C86, M93C76, M93C66, M93C56, M93C46
INSTRUCTIONS
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table
5. to Table 7.. Each instruction consists of the following parts, as shown in Figure 4.:
■
Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
■
A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
■
Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
The address bits of the byte or word that is to
be accessed. For the M93C46, the address is
made up of 6 bits for the x16 organization or 7
bits for the x8 organization (see Table 5.). For
the M93C56 and M93C66, the address is
made up of 8 bits for the x16 organization or 9
bits for the x8 organization (see Table 6.). For
the M93C76 and M93C86, the address is
made up of 10 bits for the x16 organization or
11 bits for the x8 organization (see Table 7.).
The M93Cx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 20. to Table 23..
■
Table 5. Instruction Set for the M93C46
x8 Origination (ORG = 0)
Instruc
tion
Description
Start
bit
OpCode
Address(1)
Data
Required
Clock
Cycles
x16 Origination (ORG = 1)
Address(1)
Data
A5-A0
Q15-Q0
18
A5-A0
D15-D0
Required
Clock
Cycles
READ
Read Data from
Memory
1
10
A6-A0
Q7-Q0
WRITE
Write Data to
Memory
1
01
A6-A0
D7-D0
EWEN
Erase/Write Enable
1
00
11X XXXX
10
11 XXXX
9
EWDS
Erase/Write Disable
1
00
00X XXXX
10
00 XXXX
9
ERASE
Erase Byte or Word
1
11
A6-A0
10
A5-A0
9
ERAL
Erase All Memory
1
00
10X XXXX
10
10 XXXX
9
WRAL
Write All Memory
with same Data
1
00
01X XXXX
18
01 XXXX
D7-D0
D15-D0
25
25
Note: 1. X = Don't Care bit.
7/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 6. Instruction Set for the M93C56 and M93C66
x8 Origination (ORG = 0)
Instruction
Description
Start
bit
OpCode
Address(1,2)
Data
READ
Read Data from
Memory
1
10
A8-A0
Q7-Q0
WRITE
Write Data to
Memory
1
01
A8-A0
D7-D0
EWEN
Erase/Write Enable
1
00
EWDS
Erase/Write Disable
1
ERASE
Erase Byte or Word
ERAL
WRAL
x16 Origination (ORG = 1)
Required
Clock
Address(1,3)
Cycles
Data
Required
Clock
Cycles
A7-A0
Q15-Q0
20
A7-A0
D15-D0
1 1XXX
XXXX
12
11XX XXXX
11
00
0 0XXX
XXXX
12
00XX XXXX
11
1
11
A8-A0
12
A7-A0
11
Erase All Memory
1
00
1 0XXX
XXXX
12
10XX XXXX
11
Write All Memory
with same Data
1
00
0 1XXX
XXXX
20
01XX XXXX D15-D0
27
D7-D0
27
Note: 1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 7. Instruction Set for the M93C76 and M93C86
x8 Origination (ORG = 0)
Instruction
Description
Start
bit
OpCode
Address(1,2)
Data
READ
Read Data from
Memory
1
10
A10-A0
Q7-Q0
WRITE
Write Data to
Memory
1
01
A10-A0
D7-D0
EWEN
Erase/Write Enable
1
00
EWDS
Erase/Write Disable
1
ERASE
Erase Byte or Word
ERAL
WRAL
Required
Clock
Address(1,3)
Cycles
Data
Required
Clock
Cycles
A9-A0
Q15-Q0
22
A9-A0
D15-D0
11X XXXX
XXXX
14
11 XXXX
XXXX
13
00
00X XXXX
XXXX
14
00 XXXX
XXXX
13
1
11
A10-A0
14
A9-A0
13
Erase All Memory
1
00
10X XXXX
XXXX
14
10 XXXX
XXXX
13
Write All Memory
with same Data
1
00
01X XXXX
XXXX
22
01 XXXX
XXXX
Note: 1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
8/31
x16 Origination (ORG = 1)
D7-D0
D15-D0
29
29
M93C86, M93C76, M93C66, M93C56, M93C46
Read
Erase/Write Enable and Disable
The Read Data from Memory (READ) instruction
outputs data on Serial Data Output (Q). When the
instruction is received, the op-code and address
are decoded, and the data from the memory is
transferred to an output shift register. A dummy 0
bit is output first, followed by the 8-bit byte or 16bit word, with the most significant bit first. Output
data changes are triggered by the rising edge of
Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out
the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit
is not output between bytes (or words) and a continuous stream of data can be read.
The Erase/Write Enable (EWEN) instruction enables the future execution of erase or write instructions, and the Erase/Write Disable (EWDS)
instruction disables it. When power is first applied,
the M93Cx6 initializes itself so that erase and write
instructions are disabled. After an Erase/Write Enable (EWEN) instruction has been executed, erasing and writing remains enabled until an Erase/
Write Disable (EWDS) instruction is executed, or
until VCC falls below the power-on reset threshold
voltage. To protect the memory contents from accidental corruption, it is advisable to issue the
Erase/Write Disable (EWDS) instruction after every write cycle. The Read Data from Memory
(READ) instruction is not affected by the Erase/
Write Enable (EWEN) or Erase/Write Disable
(EWDS) instructions.
Figure 4. READ, WRITE, EWEN, EWDS Sequences
READ
S
D
1 1 0 An
A0
Q
Qn
ADDR
Q0
DATA OUT
OP
CODE
WRITE
S
CHECK
STATUS
D
1 0 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
ERASE
WRITE
ENABLE
S
D
ERASE
WRITE
DISABLE
1 0 0 1 1 Xn X0
OP
CODE
S
D
1 0 0 0 0 Xn X0
OP
CODE
AI00878C
Note: For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..
9/31
M93C86, M93C76, M93C66, M93C56, M93C46
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed. The completion of the cycle can be
detected by monitoring the Ready/Busy line, as
described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial
Clock (C) may be stopped or left running after the
start of a Write cycle). The cycle is automatically
preceded by an Erase cycle, so it is unnecessary
to execute an explicit erase instruction before a
Write Data to Memory (WRITE) instruction.
Erase
The Erase Byte or Word (ERASE) instruction sets
the bits of the addressed memory byte (or word) to
1. Once the address has been correctly decoded,
the falling edge of the Chip Select Input (S) starts
the self-timed Erase cycle. The completion of the
cycle can be detected by monitoring the Ready/
Busy line, as described in the READY/BUSY STATUS section.
Write
For the Write Data to Memory (WRITE) instruction,
8 or 16 data bits follow the op-code and address
bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is
sampled on the rising edge of Serial Clock (C).
Figure 5. ERASE, ERAL Sequences
ERASE
S
CHECK
STATUS
D
1 1 1 An
A0
Q
ADDR
BUSY
READY
OP
CODE
ERASE
ALL
S
CHECK
STATUS
D
1 0 0 1 0 Xn X0
Q
ADDR
BUSY
READY
OP
CODE
AI00879B
Note: For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..
10/31
M93C86, M93C76, M93C66, M93C56, M93C46
Erase All
Write All
The Erase All Memory (ERAL) instruction erases
the whole memory (all memory bits are set to 1).
The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction
(ERASE). The completion of the cycle can be detected by monitoring the Ready/Busy line, as described in the READY/BUSY STATUS section.
As with the Erase All Memory (ERAL) instruction,
the format of the Write All Memory with same Data
(WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All
Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word,
be provided. This value is written to all the addresses of the memory device. The completion of
the cycle can be detected by monitoring the
Ready/Busy line, as described next.
Figure 6. WRAL Sequence
WRITE
ALL
S
CHECK
STATUS
D
1 0 0 0 1 Xn X0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
AI00880C
Note: For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..
11/31
M93C86, M93C76, M93C66, M93C56, M93C46
READY/BUSY STATUS
When the Write cycle is completed, and Chip Select Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is
brought Low or until a new start bit is decoded.
While the Write or Erase cycle is underway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Select Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
INITIAL DELIVERY STATE
may lead to the writing of erroneous data at an erroneous address.
To combat this problem, the M93Cx6 has an onchip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the M93Cx6
family, are summarized in Table 5. to Table 7.. For
example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current limiting resistor, to form a common, single-wire data
bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a
short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application
note AN394 for details.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the
number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 7.) and
Figure 7. Write Sequence with One Clock Glitch
S
C
D
An
START
"0"
"1"
WRITE
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395
12/31
M93C86, M93C76, M93C66, M93C56, M93C46
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Ambient Operating Temperature
–40
130
°C
TSTG
Storage Temperature
–65
150
°C
TLEAD
PDIP-Specific Lead Temperature during Soldering
260(1)
°C
TA
Parameter
Output range (Q = VOH or Hi-Z)
–0.50
VCC+0.5
V
VIN
Input range
–0.50
VCC+1
V
VCC
Supply Voltage
–0.50
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model)(2)
–4000
4000
V
VOUT
Note: 1. TLEADmax must not be applied for more than 10s.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).
13/31
M93C86, M93C76, M93C66, M93C56, M93C46
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 9. Operating Conditions (M93Cx6)
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 7)
–40
105
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 7)
–40
105
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Table 10. Operating Conditions (M93Cx6-W)
Symbol
VCC
TA
Parameter
Table 11. Operating Conditions (M93Cx6-R)
Symbol
VCC
TA
14/31
Parameter
M93C86, M93C76, M93C66, M93C56, M93C46
Table 12. AC Measurement Conditions (M93Cx6)
Symbol
CL
Parameter
Min.
Max.
Load Capacitance
Unit
100
Input Rise and Fall Times
pF
50
Input Pulse Voltages
ns
0.4 V to 2.4 V
V
Input Timing Reference Voltages
1.0 V and 2.0 V
V
Output Timing Reference Voltages
0.8 V and 2.0 V
V
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)
Symbol
CL
Parameter
Min.
Max.
Load Capacitance
Unit
100
Input Rise and Fall Times
pF
50
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
Output Timing Reference Voltages
0.3VCC to 0.7VCC
V
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 8. AC Testing Input Output Waveforms
M93CXX
2.4V
2V
2.0V
1V
0.8V
0.4V
INPUT
OUTPUT
M93CXX-W & M93CXX-R
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02553
Table 14. Capacitance
Symbol
Parameter
Test Condition
COUT
Output
Capacitance
VOUT = 0V
CIN
Input
Capacitance
VIN = 0V
Min
Max
Unit
5
pF
5
pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1MHz.
15/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 15. DC Characteristics (M93Cx6, Device Grade 6)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
0V ≤VIN ≤VCC
±2.5
µA
0V ≤VOUT ≤VCC, Q in Hi-Z
±2.5
µA
VCC = 5V, S = VIH, f = 2 MHz, Q = open
2
mA
VCC = 5V, S = VSS, C = VSS,
ORG = VSS or VCC
15
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Stand-by)
VIL
Input Low Voltage
VCC = 5V ± 10%
–0.45
0.8
V
VIH
Input High Voltage
VCC = 5V ± 10%
2
VCC + 1
V
VOL
Output Low Voltage
VCC = 5V, IOL = 2.1mA
0.4
V
VOH
Output High Voltage
VCC = 5V, IOH = –400µA
2.4
V
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
0V ≤VIN ≤VCC
±2.5
µA
0V ≤VOUT ≤VCC, Q in Hi-Z
±2.5
µA
VCC = 5V, S = VIH, f = 2 MHz, , Q = open
2
mA
VCC = 5V, S = VSS, C = VSS,
ORG = VSS or VCC
15
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Stand-by)
VIL
Input Low Voltage
VCC = 5V ± 10%
–0.45
0.8
V
VIH
Input High Voltage
VCC = 5V ± 10%
2
VCC + 1
V
VOL
Output Low Voltage
VCC = 5V, IOL = 2.1mA
0.4
V
VOH
Output High Voltage
VCC = 5V, IOH = –400µA
16/31
2.4
V
M93C86, M93C76, M93C66, M93C56, M93C46
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current (CMOS
Inputs)
Test Condition
Min.
Max.
Unit
0V ≤VIN ≤VCC
±2.5
µA
0V ≤VOUT ≤VCC, Q in Hi-Z
±2.5
µA
VCC = 5V, S = VIH, f = 2 MHz, Q = open
2
mA
VCC = 2.5V, S = VIH, f = 2 MHz, Q = open
1
mA
5
µA
VCC = 2.5V, S = VSS, C = VSS,
ICC1
Supply Current (Stand-by)
VIL
Input Low Voltage (D, C, S)
–0.45
0.2 VCC
V
VIH
Input High Voltage (D, C, S)
0.7 VCC
VCC + 1
V
VCC = 5V, IOL = 2.1mA
0.4
V
VOL
Output Low Voltage (Q)
VCC = 2.5V, IOL = 100µA
0.2
V
VOH
ORG = VSS or VCC
VCC = 5V, IOH = –400µA
2.4
V
VCC = 2.5V, IOH = –100µA
VCC–0.2
V
Output High Voltage (Q)
17/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Symbol
Max. (1)
Unit
0V ≤VIN ≤VCC
±2.5
µA
0V ≤VOUT ≤VCC, Q in Hi-Z
±2.5
µA
VCC = 5V, S = VIH, f = 2 MHz, Q = open
2
mA
VCC = 2.5V, S = VIH, f = 2 MHz, Q = open
1
mA
VCC = 2.5V, S = VSS, C = VSS,
ORG = VSS or VCC
5
µA
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current (CMOS
Inputs)
Test Condition
Min. (1)
ICC1
Supply Current (Stand-by)
VIL
Input Low Voltage (D, C, S)
–0.45
0.2 VCC
V
VIH
Input High Voltage (D, C, S)
0.7 VCC
VCC + 1
V
VCC = 5V, IOL = 2.1mA
0.4
V
VOL
Output Low Voltage (Q)
VCC = 2.5V, IOL = 100µA
0.2
V
VOH
VCC = 5V, IOH = –400µA
2.4
V
VCC = 2.5V, IOH = –100µA
VCC–0.2
V
Output High Voltage (Q)
Note: 1. New product: identified by Process Identification letter W or G or S.
Table 19. DC Characteristics (M93Cx6-R)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current (CMOS
Inputs)
Max. (1)
Unit
0V ≤VIN ≤VCC
±2.5
µA
0V ≤VOUT ≤VCC, Q in Hi-Z
±2.5
µA
VCC = 5V, S = VIH, f = 2 MHz, Q = open
2
mA
VCC = 1.8V, S = VIH, f = 1 MHz, Q = open
1
mA
VCC = 1.8V, S = VSS, C = VSS,
ORG = VSS or VCC
2
µA
Test Condition
Min. (1)
ICC1
Supply Current (Stand-by)
VIL
Input Low Voltage (D, C, S)
–0.45
0.2 VCC
V
VIH
Input High Voltage (D, C, S)
0.8 VCC
VCC + 1
V
VOL
Output Low Voltage (Q)
VCC = 1.8V, IOL = 100µA
0.2
V
VOH
Output High Voltage (Q)
VCC = 1.8V, IOH = –100µA
VCC–0.2
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
18/31
V
M93C86, M93C76, M93C66, M93C56, M93C46
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3)
Test conditions specified in Table 12. and Table 9.
Symbol
Alt.
fC
fSK
tSLCH
tSHCH
tCSS
Parameter
Clock Frequency
Min.
Max.
Unit
D.C.
2
MHz
Chip Select Low to Clock High
50
ns
Chip Select Set-up Time
M93C46, M93C56, M93C66
50
ns
Chip Select Set-up time
M93C76, M93C86
50
ns
tSLSH(2)
tCS
Chip Select Low to Chip Select High
200
ns
tCHCL(1)
tSKH
Clock High Time
200
ns
tCLCH(1)
tSKL
Clock Low Time
200
ns
tDVCH
tDIS
Data In Set-up Time
50
ns
tCHDX
tDIH
Data In Hold Time
50
ns
tCLSH
tSKS
Clock Set-up Time (relative to S)
50
ns
tCLSL
tCSH
Chip Select Hold Time
0
ns
tSHQV
tSV
Chip Select to Ready/Busy Status
200
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
100
ns
tCHQL
tPD0
Delay to Output Low
200
ns
tCHQV
tPD1
Delay to Output Valid
200
ns
tW
tWP
Erase/Write Cycle time
5
ms
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
19/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6)
Test conditions specified in Table 13. and Table 10.
Symbol
Alt.
fC
fSK
tSLCH
Parameter
Clock Frequency
Min.
Max.
Unit
D.C.
2
MHz
Chip Select Low to Clock High
50
ns
tSHCH
tCSS
Chip Select Set-up Time
50
ns
tSLSH(2)
tCS
Chip Select Low to Chip Select High
200
ns
tCHCL(1)
tSKH
Clock High Time
200
ns
tCLCH(1)
tSKL
Clock Low Time
200
ns
tDVCH
tDIS
Data In Set-up Time
50
ns
tCHDX
tDIH
Data In Hold Time
50
ns
tCLSH
tSKS
Clock Set-up Time (relative to S)
50
ns
tCLSL
tCSH
Chip Select Hold Time
0
ns
tSHQV
tSV
Chip Select to Ready/Busy Status
200
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
100
ns
tCHQL
tPD0
Delay to Output Low
200
ns
tCHQV
tPD1
Delay to Output Valid
200
ns
tW
tWP
Erase/Write Cycle time
5
ms
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
20/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Test conditions specified in Table 13. and Table 10.
Symbol
Alt.
fC
fSK
tSLCH
Parameter
Clock Frequency
Min.
Max.
Unit
D.C.
2
MHz
Chip Select Low to Clock High
50
ns
tSHCH
tCSS
Chip Select Set-up Time
50
ns
tSLSH(2)
tCS
Chip Select Low to Chip Select High
200
ns
tCHCL(1)
tSKH
Clock High Time
200
ns
tCLCH(1)
tSKL
Clock Low Time
200
ns
tDVCH
tDIS
Data In Set-up Time
50
ns
tCHDX
tDIH
Data In Hold Time
50
ns
tCLSH
tSKS
Clock Set-up Time (relative to S)
50
ns
tCLSL
tCSH
Chip Select Hold Time
0
ns
tSHQV
tSV
Chip Select to Ready/Busy Status
200
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
100
ns
tCHQL
tPD0
Delay to Output Low
200
ns
tCHQV
tPD1
Delay to Output Valid
200
ns
tW
tWP
Erase/Write Cycle time
5
ms
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
21/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 23. AC Characteristics (M93Cx6-R)
Test conditions specified in Table 13. and Table 11.
Symbol
Alt.
fC
fSK
tSLCH
Min.(3)
Max.(3)
Unit
Clock Frequency
D.C.
1
MHz
Chip Select Low to Clock High
250
ns
Parameter
tSHCH
tCSS
Chip Select Set-up Time
50
ns
tSLSH(2)
tCS
Chip Select Low to Chip Select High
250
ns
tCHCL(1)
tSKH
Clock High Time
250
ns
tCLCH(1)
tSKL
Clock Low Time
250
ns
tDVCH
tDIS
Data In Set-up Time
100
ns
tCHDX
tDIH
Data In Hold Time
100
ns
tCLSH
tSKS
Clock Set-up Time (relative to S)
100
ns
tCLSL
tCSH
Chip Select Hold Time
0
ns
tSHQV
tSV
Chip Select to Ready/Busy Status
400
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
200
ns
tCHQL
tPD0
Delay to Output Low
400
ns
tCHQV
tPD1
Delay to Output Valid
400
ns
tW
tWP
Erase/Write Cycle time
10
ms
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. This product is under development. For more information, please contact your nearest ST sales office.
22/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 9. Synchronous Timing (Start and Op-Code Input)
tCLSH
tCHCL
C
tSHCH
tCLCH
S
tDVCH
D
tCHDX
OP CODE
START
START
OP CODE
OP CODE INPUT
AI01428
Figure 10. Synchronous Timing (Read or Write)
C
tCLSL
S
tDVCH
tCHDX
A0
An
D
tSLSH
tCHQV
tSLQZ
tCHQL
Hi-Z
Q15/Q7
Q
ADDRESS INPUT
Q0
DATA OUTPUT
AI00820C
Figure 11. Synchronous Timing (Read or Write)
tSLCH
C
tCLSL
S
tDVCH
An
D
tCHDX
tSLSH
A0/D0
tSHQV
tSLQZ
Hi-Z
Q
BUSY
READY
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI01429
23/31
M93C86, M93C76, M93C66, M93C56, M93C46
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
Note: Drawing is not to scale.
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
millimeters
inches
Symbol
Typ.
Min.
A
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
24/31
Max.
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Data
millimeters
inches
Symbol
Typ
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
ddd
Typ
0.10
E
3.80
4.00
–
–
H
5.80
h
0.004
0.150
0.157
–
–
6.20
0.228
0.244
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N (pin number)
8
e
1.27
0.050
8
25/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to
any other voltage or signal line on the PCB, for example during the soldering process.
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data
millimeters
inches
Symbol
A
Typ.
Min.
Max.
Typ.
Min.
Max.
0.55
0.50
0.60
0.022
0.020
0.024
0.00
0.05
0.000
0.002
0.20
0.30
0.008
0.012
0.061
0.065
A1
b
0.25
D
2.00
D2
0.079
1.55
ddd
E
0.010
1.65
0.05
3.00
E2
0.002
0.118
0.15
0.25
0.006
0.010
e
0.50
–
–
0.020
–
–
L
0.45
0.40
0.50
0.018
0.016
0.020
L1
0.15
0.006
L3
0.30
0.012
N (pin number)
8
8
26/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package
Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data
millimeters
inches
Symbol
Typ.
Min.
A
Max.
Min.
1.100
A1
0.050
0.150
0.750
0.950
b
0.250
c
A2
Typ.
0.850
Max.
0.0433
0.0020
0.0059
0.0295
0.0374
0.400
0.0098
0.0157
0.130
0.230
0.0051
0.0091
0.0335
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
E
4.900
4.650
5.150
0.1929
0.1831
0.2028
E1
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
CP
0.100
L
0.550
L1
0.950
0.400
0.700
0.0039
0.0217
0.0157
0.0276
0°
6°
0.0374
α
0°
N (pin number)
8
6°
8
27/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 28. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters
inches
Symbol
Typ.
Min.
A
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
Min.
1.200
A1
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394
α
0°
N (pin number)
8
28/31
Max.
8°
8
M93C86, M93C76, M93C66, M93C56, M93C46
PART NUMBERING
Table 29. Ordering Information Scheme
Example:
M93C86
–
W MN 6
T
P
/S
Device Type
M93 = MICROWIRE serial access EEPROM
Device Function
86 = 16 Kbit (2048 x 8)
76 = 8 Kbit (1024 x 8)
66 = 4 Kbit (512 x 8)
56 = 2 Kbit (256 x 8)
46 = 1 Kbit (128 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm body size)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
7 = Device tested with High Reliability Certified Flow(1).
Automotive temperature range (–40 to 105 °C)
3 = Device tested with High Reliability Certified Flow(1).
Automotive temperature range (–40 to 125 °C)
Packing
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPACK® (RoHS compliant)
Process(2)
/W or /S = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Used only for Device Grade 3.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
The category of second-Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
29/31
M93C86, M93C76, M93C66, M93C56, M93C46
REVISION HISTORY
Table 30. Document Revision History
Date
Rev.
Description of Revision
04-Feb-2003
2.0
Document reformatted, and reworded, using the new template. Temperature range 1 removed.
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and
corresponding parameters adjusted)
26-Mar-2003
2.1
Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
VOUT and VIN separated from VIO in the Absolute Maximum Ratings table
04-Apr-2003
2.2
Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices with
Process Identification Letter W
23-May-2003
2.3
Standby current corrected for -R range
27-May-2003
2.4
Turned-die option re-instated in Ordering Information Scheme
25-Nov-2003
3.0
Table of contents, and Pb-free options added. Temperature range 7 added. VIL(min) improved
to –0.45V.
30-Mar-2004
4.0
MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Soldering temperature information clarified for RoHS compliant devices. Device grade
information clarified. Process identification letter “G” information added
16-Aug-2004
5.0
M93C06 removed. Device grade information further clarified. Process identification letter “S”
information added. Turned-die package option removed. Product list summary added.
current product/new product distinction removed. ICC and ICC1 values for current product
removed from tables 15, 16 and 17 and AC characteristics for current product removed from
Tables 20 and 21. Clock rate added to FEATURES SUMMARY.
“Q = open” added to ICC Test conditions in DC Characteristics Tables 15, 16, 17, 18 and 19.
27-Oct-2005
30/31
6.0
Process(2) added to Table 29., Ordering Information Scheme. POWER ON DATA
PROTECTION section removed, replaced by INTERNAL DEVICE RESET and ACTIVE
POWER AND STANDBY POWER MODES. INITIAL DELIVERY STATE added.
SO8N and TSSOP8 packages updated. PDIP-specific TLEAD added to Table 8., Absolute
Maximum Ratings.
M93C86, M93C76, M93C66, M93C56, M93C46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
31/31