AD OP1177ARZ-REEL1 Precision low noise, low input bias current operational amplifier Datasheet

Precision Low Noise, Low Input
Bias Current Operational Amplifiers
OP1177/OP2177/OP4177
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
NC 1
OP1177
4
5
NC = NO CONNECT
+IN 3
7 V+
OP1177
6 OUT
5 NC
V– 4
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM Suffix)
Figure 2. 8-Lead SOIC_N (R Suffix)
OUT A 1
OUT A
–IN A
+IN A
V–
1
8
V+
OUT B
–IN B
+IN B
OP2177
4
5
–IN A 2
Figure 3. 8-Lead MSOP (RM Suffix)
OUT A 1
14 OUT D
–IN A 2
13 –IN D
+IN A 3
V+ 4
+IN B 5
OP4177
02627-002
NC
V+
OUT
NC
8 NC
+IN A 3
8 V+
OP2177
7 OUT B
6 –IN B
5 +IN B
V– 4
02627-004
8
02627-001
1
NC
–IN
+IN
V–
–IN 2
02627-003
APPLICATIONS
PIN CONFIGURATIONS
Figure 4. 8-Lead SOIC_N (R Suffix)
12 +IN D
11 V–
10 +IN C
–IN B 6
9
–IN C
OUT B 7
8
OUT C
02627-005
Low offset voltage: 60 μV maximum
Very low offset voltage drift: 0.7 μV/°C maximum
Low input bias current: 2 nA maximum
Low noise: 8 nV/√Hz typical
CMRR, PSRR, and AVO > 120 dB minimum
Low supply current: 400 μA per amplifier
Dual supply operation: ±2.5 V to ±15 V
Unity-gain stable
No phase reversal
Inputs internally protected beyond supply voltage
Figure 5. 14-Lead SOIC_N (R Suffix)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
1
14
OP4177
7
8
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
02627-006
FEATURES
Figure 6. 14-Lead TSSOP (RU Suffix)
GENERAL DESCRIPTION
The OPx177 family consists of very high precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power consumption. Outputs are stable with capacitive loads of over 1000 pF
with no external compensation. Supply current is less than 500 μA
per amplifier at 30 V. Internal 500 Ω series resistors protect the
inputs, allowing input signal levels several volts beyond either
supply without phase reversal.
Unlike previous high voltage amplifiers with very low offset
voltages, the OP1177 (single) and OP2177 (dual) amplifiers
are available in tiny 8-lead surface-mount MSOP and 8-lead
narrow SOIC packages. The OP4177 (quad) is available in
TSSOP and 14-lead narrow SOIC packages. Moreover, specified
performance in the MSOP and the TSSOP is identical to
performance in the SOIC package. MSOP and TSSOP are
available in tape and reel only.
The OPx177 family offers the widest specified temperature
range of any high precision amplifier in surface-mount packaging.
All versions are fully specified for operation from −40°C to
+125°C for the most demanding operating environments.
Applications for these amplifiers include precision diode
power measurement, voltage and current level setting, and
level detection in optical and wireless transmission systems.
Additional applications include line-powered and portable
instrumentation and controls—thermocouple, RTD, strainbridge, and other sensor signal conditioning—and precision filters.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
OP1177/OP2177/OP4177
TABLE OF CONTENTS
Features .............................................................................................. 1
Overload Recovery Time .......................................................... 15
Applications ....................................................................................... 1
THD + Noise ............................................................................... 16
Pin Configurations ........................................................................... 1
Capacitive Load Drive ............................................................... 16
General Description ......................................................................... 1
Stray Input Capacitance Compensation .................................. 17
Revision History ............................................................................... 2
Reducing Electromagnetic Interference .................................. 17
Specifications..................................................................................... 3
Proper Board Layout .................................................................. 18
Electrical Characteristics ............................................................. 4
Difference Amplifiers ................................................................ 18
Absolute Maximum Ratings............................................................ 5
A High Accuracy Thermocouple Amplifier ........................... 19
Thermal Resistance ...................................................................... 5
Low Power Linearized RTD ...................................................... 19
ESD Caution .................................................................................. 5
Single Operational Amplifier Bridge ....................................... 20
Typical Performance Characteristics ............................................. 6
Realization of Active Filters .......................................................... 21
Functional Description .................................................................. 14
Band-Pass KRC or Sallen-Key Filter........................................ 21
Total Noise-Including Source Resistors................................... 14
Channel Separation .................................................................... 21
Gain Linearity ............................................................................. 14
References on Noise Dynamics and Flicker Noise ............... 21
Input Overvoltage Protection ................................................... 15
Outline Dimensions ....................................................................... 22
Output Phase Reversal ............................................................... 15
Ordering Guide .......................................................................... 24
Settling Time ............................................................................... 15
REVISION HISTORY
11/09—Rev. F to Rev. G
Changes to Figure 64 ...................................................................... 19
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 22
Changes to Figure 67 and Figure 68............................................. 21
Removed SPICE Model Section ................................................... 21
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 24
5/09—Rev. E to Rev. F
Changes to Figure 64 ...................................................................... 19
Changes to Ordering Guide .......................................................... 24
4/04—Rev. B to Rev. C
Changes to Ordering Guide .............................................................4
Changes to TPC 6 ..............................................................................5
Changes to TPC 26 ............................................................................7
Updated Outline Dimensions ....................................................... 17
10/07—Rev. D to Rev. E
Changes to General Description .................................................... 1
Changes to Table 4 ............................................................................ 5
Updated Outline Dimensions ....................................................... 22
7/06—Rev. C to Rev. D
Changes to Table 4 ............................................................................ 5
Changes to Figure 51 ...................................................................... 14
Changes to Figure 52 ...................................................................... 15
Changes to Figure 54 ...................................................................... 16
Changes to Figure 58 to Figure 61 ................................................ 17
Changes to Figure 62 and Figure 63 ............................................. 18
Changes to Figure 64 ...................................................................... 19
Changes to Figure 65 and Figure 66 ............................................. 20
4/02—Rev. A to Rev. B
Added OP4177 ......................................................................... Global
Edits to Specifications .......................................................................2
Edits to Electrical Characteristics Headings ..................................4
Edits to Ordering Guide ...................................................................4
11/01—Rev. 0 to Rev. A
Edit to Features ..................................................................................1
Edits to TPC 6 ...................................................................................5
7/01—Revision 0: Initial Version
Rev. G | Page 2 of 24
OP1177/OP2177/OP4177
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
OP1177
OP2177/OP4177
OP1177/OP2177
OP4177
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Symbol
Large Signal Voltage Gain
Offset Voltage Drift
OP1177/OP2177
OP4177
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
OP1177
AVO
VCM = −3.5 V to +3.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VO = −3.5 V to +3.5 V
ΔVOS/ΔT
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
VOH
VOL
IOUT
IL = 1 mA, −40°C < TA < +125°C
IL = 1 mA, −40°C < TA < +125°C
VDROPOUT < 1.2 V
+4
PSRR
VS = ±2.5 V to ±15 V
−40°C < TA < +125°C
VS = ±2.5 V to ±15 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
120
115
118
114
OP2177/OP4177
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
1
VOS
VOS
VOS
VOS
IB
IOS
CMRR
PSRR
ISY
Conditions
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
Min
−2
−1
−3.5
120
118
1000
Typ 1
Max
Unit
15
15
25
25
+0.5
+0.2
60
75
100
120
+2
+1
+3.5
μV
μV
μV
μV
nA
nA
V
dB
dB
V/mV
0.2
0.3
0.7
0.9
μV/°C
μV/°C
+4.1
−4.1
±10
−4
V
V
mA
126
125
2000
130
125
121
120
400
500
SR
GBP
RL = 2 kΩ
0.7
1.3
en p-p
en
in
CS
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
DC
f = 100 kHz
0.4
7.9
0.2
0.01
−120
500
600
dB
dB
dB
dB
μA
μA
V/μs
MHz
8.5
μV p-p
nV/√Hz
pA/√Hz
μV/V
dB
Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically
low estimates for parameters that can have both positive and negative values.
Rev. G | Page 3 of 24
OP1177/OP2177/OP4177
ELECTRICAL CHARACTERISTICS
VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
OP1177
OP2177/OP4177
OP1177/OP2177
OP4177
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Symbol
Large Signal Voltage Gain
Offset Voltage Drift
OP1177/OP2177
OP4177
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
OP1177
AVO
VCM = −13.5 V to +13.5 V,
−40°C < TA < +125°C
RL = 2 kΩ, VO = –13.5 V to +13.5 V
ΔVOS/ΔT
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
VOH
VOL
IOUT
ISC
IL = 1 mA, −40°C < TA < +125°C
IL = 1 mA, −40°C < TA < +125°C
VDROPOUT < 1.2 V
+14
PSRR
VS = ±2.5 V to ±15 V
−40°C < TA < +125°C
VS = ±2.5 V to ±15 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
120
115
118
114
OP2177/OP4177
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
1
VOS
VOS
VOS
VOS
IB
IOS
CMRR
PSRR
ISY
Conditions
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
Min
−2
−1
−13.5
120
1000
Typ 1
Max
Unit
15
15
25
25
+0.5
+0.2
60
75
100
120
+2
+1
+13.5
μV
μV
μV
μV
nA
nA
V
125
3000
0.2
0.3
+14.1
−14.1
±10
±25
130
125
121
120
400
500
SR
GBP
RL = 2 kΩ
0.7
1.3
en p-p
en
in
CS
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
DC
f = 100 kHz
0.4
7.9
0.2
0.01
−120
dB
V/mV
0.7
0.9
−14
500
600
μV/°C
μV/°C
V
V
mA
mA
dB
dB
dB
dB
μA
μA
V/μs
MHz
8.5
μV p-p
nV/√Hz
pA/√Hz
μV/V
dB
Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically
low estimates for parameters that can have both positive and negative values.
Rev. G | Page 4 of 24
OP1177/OP2177/OP4177
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Storage Temperature Range
R, RM, and RU Packages
Operating Temperature Range
OP1177/OP2177/OP4177
Junction Temperature Range
R, RM, and RU Packages
Lead Temperature, Soldering (10 sec)
Rating
36 V
VS− to VS+
±Supply Voltage
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead MSOP (RM-8) 1
8-Lead SOIC_N (R-8)
14-Lead SOIC_N (R-14)
14-Lead TSSOP (RU-14)
1
θJA
190
158
120
240
MSOP is available in tape and reel only.
ESD CAUTION
Rev. G | Page 5 of 24
θJC
44
43
36
43
Unit
°C/W
°C/W
°C/W
°C/W
OP1177/OP2177/OP4177
TYPICAL PERFORMANCE CHARACTERISTICS
45
1.8
VSY = ±15V
1.6
ΔOUTPUT VOLTAGE (V)
1.4
35
30
25
20
15
1.2
1.0
0.8
0.4
5
0.2
0
–30
–40
–20
–10
0
10
20
INPUT OFFSET VOLTAGE (µV)
30
40
SOURCE
0.6
10
SINK
0
0.001
02627-007
NUMBER OF AMPLIFIERS
40
VSY = ±15V
TA = 25°C
Figure 7. Input Offset Voltage Distribution
0.01
0.1
LOAD CURRENT (mA)
1
10
02627-010
50
Figure 10. Output Voltage to Supply Rail vs. Load Current
3
90
VSY = ±15V
VSY = ±15V
80
INPUT BIAS CURRENT (nA)
NUMBER OF AMPLIFIERS
2
70
60
50
40
30
20
1
0
–1
–2
0.65
–3
–50
Figure 8. Input Offset Voltage Drift Distribution
100
50
120
80
60
40
VSY = ±15V
CL = 0
RL = ∞
225
180
40
OPEN-LOOP GAIN (dB)
100
135
30
GAIN
90
20
PHASE
10
20
–45
0.2
0.3
0.4
0.5
INPUT BIAS CURRENT (nA)
0.6
0.7
02627-009
–10
0.1
–20
100k
Figure 9. Input Bias Current Distribution
45
0
0
0
150
270
60
VSY = ±15V
NUMBER OF AMPLIFIERS
50
TEMPERATURE (°C)
Figure 11. Input Bias Current vs. Temperature
140
0
0
1M
FREQUENCY (Hz)
–90
10M
Figure 12. Open-Loop Gain and Phase Shift vs. Frequency
Rev. G | Page 6 of 24
PHASE SHIFT (Degrees)
0.15
0.25
0.35
0.45
0.55
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
02627-012
0.05
02627-008
0
02627-011
10
OP1177/OP2177/OP4177
120
VOLTAGE (100mV/DIV)
80
CLOSED-LOOP GAIN (dB)
VSY = ±15V
CL = 1,000pF
RL = 2kΩ
VIN = 100mV
AV = 1
VSY = ±15V
VIN = 4mV p-p
CL = 0
RL = ∞
100
60
AV = 100
40
AV = 10
20
0
AV = 1
–20
GND
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
TIME (100µs/DIV)
Figure 16. Small Signal Transient Response
Figure 13. Closed-Loop Gain vs. Frequency
50
500
VSY = ±15V
VIN = 50mV p-p
OUTPUT IMPEDANCE (Ω)
400
350
300
AV = 10
AV = 1
250
AV = 100
200
VSY = ±15V
RL = 2kΩ
VIN = 100mV p-p
45
SMALL SIGNAL OVERSHOOT (%)
450
02627-016
1k
150
100
40
35
30
25
+OS
20
15
10
–OS
5
50
1k
10k
100k
FREQUENCY (Hz)
1M
0
02627-014
0
100
1
10
100
CAPACITANCE (pF)
1k
10k
02627-017
–80
02627-013
–60
Figure 17. Small Signal Overshoot vs. Load Capacitance
Figure 14. Output Impedance vs. Frequency
VSY = ±15V
CL = 300pF
RL = 2kΩ
VIN = 4V
AV = 1
VOLTAGE (1V/DIV)
0V
VSY = ±15V
RL = 10kΩ
AV = –100
VIN = 200mV
OUTPUT
–15V
+200mV
GND
INPUT
TIME (10µs/DIV)
Figure 18. Positive Overvoltage Recovery
Figure 15. Large Signal Transient Response
Rev. G | Page 7 of 24
02627-018
TIME (100µs/DIV)
02627-015
0V
OP1177/OP2177/OP4177
15V
VSY = ±15V
OUTPUT
0V
VNOISE (0.2µV/DIV)
VSY = ±15V
RL = 10kΩ
AV = –100
VIN = 200mV
0V
TIME (4µs/DIV)
TIME (1s/DIV)
Figure 19. Negative Overvoltage Recovery
Figure 22. 0.1 Hz to 10 Hz Input Voltage Noise
18
140
VSY = ±15V
VSY = ±15V
VOLTAGE NOISE DENSITY (nV/√Hz)
120
80
60
40
20
16
14
12
10
8
6
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
2
02627-020
10
0
Figure 20. CMRR vs. Frequency
50
100
150
FREQUENCY (Hz)
200
Figure 23. Voltage Noise Density vs. Frequency
35
140
VSY = ±15V
VSY = ±15V
30
SHORT-CIRCUIT CURRENT (mA)
120
–PSRR
80
+PSRR
60
40
+ISC
25
–ISC
20
15
10
5
20
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
–50
02627-021
PSRR (dB)
100
0
250
02627-023
4
Figure 21. PSRR vs. Frequency
0
50
TEMPERATURE (°C)
100
Figure 24. Short-Circuit Current vs. Temperature
Rev. G | Page 8 of 24
150
02627-024
CMRR (dB)
100
0
02627-022
INPUT
02627-019
–200mV
OP1177/OP2177/OP4177
14.40
133
VSY = ±15V
131
14.30
130
+VOH
14.25
CMRR (dB)
–VOL
14.20
14.15
129
128
127
126
14.10
125
14.05
50
TEMPERATURE (°C)
100
150
123
–50
02627-025
0
0
Figure 25. Output Voltage Swing vs. Temperature
131
0.2
130
0.1
129
0
–0.1
128
127
–0.2
126
–0.3
125
–0.4
124
20
40
60
80
100
120
TIME FROM POWER SUPPLY TURN-ON (Sec)
140
123
–50
0
Figure 26. Warm-Up Drift
100
150
Figure 29. PSRR vs. Temperature
18
50
VSY = ±15V
45
16
VSY = ±5V
40
NUMBER OF AMPLIFIERS
14
12
10
8
6
4
35
30
25
20
15
10
2
5
0
50
100
TEMPERATURE (°C)
150
02627-027
0
–50
50
TEMPERATURE (°C)
02627-029
PSRR (dB)
0.3
0
VSY = ±15V
132
02627-026
ΔOFFSET VOLTAGE (µV)
150
133
VSY = ±15V
0.4
INPUT OFFSET VOLTAGE (µV)
100
Figure 28. CMRR vs. Temperature
0.5
–0.5
50
TEMPERATURE (°C)
02627-028
124
14.00
–50
Figure 27. Input Offset Voltage vs. Temperature
0
–40
–30
–20
–10
0
10
20
INPUT OFFSET VOLTAGE (µV)
30
Figure 30. Input Offset Voltage Distribution
Rev. G | Page 9 of 24
40
02627-030
OUTPUT VOLTAGE SWING (V)
VSY = ±15V
132
14.35
OP1177/OP2177/OP4177
500
1.4
1.2
VSY = ±5V
TA = 25°C
450
VSY = ±5V
VIN = 50mV p-p
OUTPUT IMPEDANCE (Ω)
0.8
SINK
0.6
SOURCE
0.4
350
300
250
200
150
AV = 10
100
0.2
0.1
1
LOAD CURRENT (mA)
10
0
100
02627-031
0.01
Figure 31. Output Voltage to Supply Rail vs. Load Current
270
VSY = ±5V
CL = 0
RL = ∞
225
40
180
30
135
GAIN
20
90
PHASE
10
VSY = ±5V
CL = 300pF
RL = 2kΩ
VIN = 1V
AV = 1
45
0
0
–10
VOLTAGE (1V/DIV)
50
GND
–90
10M
1M
FREQUENCY (Hz)
02627-032
–45
–20
100k
TIME (100µs/DIV)
Figure 32. Open-Loop Gain and Phase Shift vs. Frequency
Figure 35. Large Signal Transient Response
120
VSY = ±5V
CL = 1,000pF
RL = 2kΩ
VIN = 100mV
AV = 1
VSY = ±5V
VIN = 4mV p-p
CL = 0
RL = ∞
100
VOLTAGE (50mV/DIV)
80
60
AV = 100
40
AV = 10
20
0
AV = 1
–20
GND
–40
–80
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
TIME (10µs/DIV)
Figure 36. Small Signal Transient Response
Figure 33. Closed-Loop Gain vs. Frequency
Rev. G | Page 10 of 24
02627-036
–60
02627-033
CLOSED-LOOP GAIN (dB)
1M
10k
100k
FREQUENCY (Hz)
Figure 34. Output Impedance vs. Frequency
PHASE SHIFT (Degrees)
60
1k
02627-034
50
0
0.001
OPEN-LOOP GAIN (dB)
AV = 1
AV = 100
02627-035
ΔOUTPUT VOLTAGE (V)
400
1.0
OP1177/OP2177/OP4177
50
VSY = ±5V
RL = 2kΩ
VIN = 100mV
40
35
30
25
VS = ±5V
AV = 1
RL = 10kΩ
INPUT
VOLTAGE (2V/DIV)
SMALL SIGNAL OVERSHOOT (%)
45
+OS
20
GND
15
10
OUTPUT
–OS
1
10
100
CAPACITANCE (pF)
1k
10k
TIME (200µs/DIV)
Figure 40. No Phase Reversal
Figure 37. Small Signal Overshoot vs. Load Capacitance
0V
VSY = ±5V
RL = 10kΩ
AV = –100
VIN = 200mV
02627-040
0
02627-037
5
140
VSY = ±5V
120
OUTPUT
100
CMRR (dB)
–15V
+200mV
80
60
40
INPUT
0V
TIME (4µs/DIV)
0
10
100
200
VSY = ±5V
RL = 10kΩ
AV = –100
VIN = 200mV
OUTPUT
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 41. CMRR vs. Frequency
Figure 38. Positive Overvoltage Recovery
5V
1k
02627-041
02627-038
20
VSY = ±5V
180
160
140
PSRR (dB)
0V
INPUT
0V
120
100
–PSRR
80
60
+PSRR
40
–200mV
0
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 42. PSRR vs. Frequency
Figure 39. Negative Overvoltage Recovery
Rev. G | Page 11 of 24
1M
10M
02627-042
TIME (4µs/DIV)
02627-039
20
OP1177/OP2177/OP4177
4.40
VSY = ±5V
VSY = ±5V
VNOISE (0.2µV/DIV)
OUTPUT VOLTAGE SWING (V)
4.35
4.30
+VOH
4.25
–VOL
4.20
4.15
4.10
TIME (1s/DIV)
4.00
–50
0
50
TEMPERATURE (°C)
100
Figure 46. Output Voltage Swing vs. Temperature
Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise
25
18
VSY = ±5V
VSY = ±5V
INPUT OFFSET VOLTAGE (µV)
16
14
12
10
8
6
20
15
10
5
2
0
50
100
150
FREQUENCY (Hz)
200
250
0
–50
0
50
100
150
TEMPERATURE (°C)
Figure 44. Voltage Noise Density vs. Frequency
02627-047
4
02627-044
VOLTAGE NOISE DENSITY (nV/√Hz)
150
02627-046
02627-043
4.05
Figure 47. Input Offset Voltage vs. Temperature
35
600
VSY = ±5V
500
VSY = ±15V
25
SUPPLY CURRENT (µA)
+ISC
–ISC
20
15
10
VSY = ±5V
300
200
0
50
TEMPERATURE (°C)
100
150
0
–50
0
50
100
TEMPERATURE (°C)
Figure 45. Short-Circuit Current vs. Temperature
Figure 48. Supply Current vs. Temperature
Rev. G | Page 12 of 24
150
02627-048
0
–50
400
100
5
02627-045
SHORT-CIRCUIT CURRENT (mA)
30
OP1177/OP2177/OP4177
450
0
TA = 25°C
–20
CHANNEL SEPARATION (dB)
350
300
250
200
150
100
–40
–60
–80
–100
–120
0
0
5
10
15
20
25
30
SUPPLY VOLTAGE (V)
35
–160
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 50. Channel Separation vs. Frequency
Figure 49. Supply Current vs. Supply Voltage
Rev. G | Page 13 of 24
1M
02627-050
–140
50
02627-049
SUPPLY CURRENT (µA)
400
OP1177/OP2177/OP4177
FUNCTIONAL DESCRIPTION
The OPx177 series is the fourth generation of Analog Devices,
Inc., industry-standard OP07 amplifier family. OPx177 is a high
precision, low noise operational amplifier with a combination of
extremely low offset voltage and very low input bias currents.
Unlike JFET amplifiers, the low bias and offset currents are
relatively insensitive to ambient temperatures, even up to 125°C.
Analog Devices proprietary process technology and linear design
expertise has produced a high voltage amplifier with superior
performance to the OP07, OP77, and OP177 in a tiny MSOP
8­lead package. Despite its small size, the OPx177 offers numerous
improvements, including low wideband noise, very wide input
and output voltage range, lower input bias current, and complete
freedom from phase inversion.
OPx177 has a specified operating temperature range as wide as
any similar device in a plastic surface-mount package. This is
increasingly important as PCB and overall system sizes continue
to shrink, causing internal system temperatures to rise. Power
consumption is reduced by a factor of four from the OP177, and
bandwidth and slew rate increase by a factor of two. The low
power dissipation and very stable performance vs. temperature
also act to reduce warmup drift errors to insignificant levels.
For RS < 3.9 kΩ, en dominates and
en,TOTAL ≈ en
For 3.9 kΩ < RS < 412 kΩ, voltage noise of the amplifier, the
current noise of the amplifier translated through the source
resistor, and the thermal noise from the source resistor all
contribute to the total noise.
For RS > 412 kΩ, the current noise dominates and
en,TOTAL ≈ inRS
The total equivalent rms noise over a specific bandwidth is
expressed as
en =
(e
n , TOTAL
)
BW
where BW is the bandwidth in hertz.
The preceding analysis is valid for frequencies larger than 50 Hz.
When considering lower frequencies, flicker noise (also known
as 1/f noise) must be taken into account.
For a reference on noise calculations, refer to the Band-Pass
KRC or Sallen-Key Filter section.
Open-loop gain linearity under heavy loads is superior to competitive parts, such as the OPA277, improving dc accuracy and
reducing distortion in circuits with high closed-loop gains.
Inputs are internally protected from overvoltage conditions
referenced to either supply rail.
GAIN LINEARITY
Like any high performance amplifier, maximum performance is
achieved by following appropriate circuit and PCB guidelines.
The following sections provide practical advice on getting the
most out of the OPx177 under a variety of application conditions.
The OP1177 has excellent gain linearity even with heavy loads,
as shown in Figure 51. Compare its performance to the OPA277,
shown in Figure 52. Both devices are measured under identical
conditions, with RL = 2 kΩ. The OP2177 (dual) has virtually no
distortion at lower voltages. Compared to the OPA277 at several
supply voltages and various loads, OP1177 performance far
exceeds that of its counterpart.
TOTAL NOISE-INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the OPx177
make it useful for circuits with substantial input source resistance.
Input offset voltage increases by less than 1 μV maximum per
500 Ω of source resistance.
Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range. This is especially true for circuits with high
closed-loop gains.
VSY = ±15V
RL = 2kΩ
where:
en is the input voltage noise density.
in is the input current noise density.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (T = 273 + temperature
in degrees Celsius).
OP1177
(5V/DIV)
Figure 51. Gain Linearity
Rev. G | Page 14 of 24
02627-051
en, TOTAL = en2 + (in RS ) 2 + 4kTRS
(10µV/DIV)
The total noise density of the OPx177 is
OP1177/OP2177/OP4177
OPA277
(5V/DIV)
VIN
VOUT
TIME (400µs/DIV)
02627-053
VOLTAGE (5V/DIV)
VSY = 10V
AV = 1
02627-052
(10µV/DIV)
VSY = ±15V
RL = 2kΩ
Figure 53. No Phase Reversal
Figure 52. Gain Linearity
INPUT OVERVOLTAGE PROTECTION
SETTLING TIME
When input voltages exceed the positive or negative supply
voltage, most amplifiers require external resistors to protect
them from damage.
Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in measurement and control circuits in which amplifiers buffer ADC inputs
or DAC outputs.
The OPx177 has internal protective circuitry that allows voltages as
high as 2.5 V beyond the supplies to be applied at the input of
either terminal without any harmful effects.
Use an additional resistor in series with the inputs if the voltage
exceeds the supplies by more than 2.5 V. The value of the resistor
can be determined from the formula
(V IN − VS )
≤ 5 mA
R S + 500 Ω
With the OPx177 low input offset current of <1 nA maximum,
placing a 5 kΩ resistor in series with both inputs adds less than
5 μV to input offset voltage and has a negligible impact on the
overall noise performance of the circuit.
5 kΩ protects the inputs to more than 27 V beyond either supply.
Refer to the THD + Noise section for additional information on
noise vs. source resistance.
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this can
cause permanent damage to the amplifier. In feedback loops, it
can result in system lockups or equipment damage. The OPx177
is immune to phase reversal problems even at input voltages
beyond the supplies.
To minimize settling time in amplifier circuits, use proper
bypassing of power supplies and an appropriate choice of circuit
components. Resistors should be metal film types, because they
have less stray capacitance and inductance than their wire-wound
counterparts. Capacitors should be polystyrene or polycarbonate
types to minimize dielectric absorption.
The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OPx177
has a settling time of about 45 μs to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.
OVERLOAD RECOVERY TIME
Overload recovery is defined as the time it takes the output
voltage of an amplifier to recover from a saturated condition to
its linear response region. A common example is one in which
the output voltage demanded by the transfer function of the
circuit lies beyond the maximum output voltage capability of
the amplifier. A 10 V input applied to an amplifier in a closedloop gain of 2 demands an output voltage of 20 V. This is beyond
the output voltage range of the OPx177 when operating at ±15 V
supplies and forces the output into saturation.
Recovery time is important in many applications, particularly
where the operational amplifier must amplify small signals in
the presence of large transient voltages.
Rev. G | Page 15 of 24
OP1177/OP2177/OP4177
R2
100kΩ
V+
R1
1kΩ
200mV
Figure 56 is a scope shot of the output of the OPx177 in response
to a 400 mV pulse. The load capacitance is 2 nF. The circuit is
configured in positive unity gain, the worst-case condition for
stability.
7
2
+
–
OP1177
VOUT
6
3
As shown in Figure 58, placing an R-C network parallel to the
load capacitance (CL) allows the amplifier to drive higher values
of CL without causing oscillation or excessive overshoot.
10kΩ
02627-054
4
V–
Figure 54. Test Circuit for Overload Recovery Time
There is no ringing, and overshoot is reduced from 27% to 5%
using the snubber network.
Figure 18 shows the positive overload recovery time of the
OP1177. The output recovers in less than 4 μs after being
overdriven by more than 100%.
The negative overload recovery of the OP1177 is 1.4 μs, as seen
in Figure 19.
Optimum values for RS and CS are tabulated in Table 5 for several
capacitive loads, up to 200 nF. Values for other capacitive loads can
be determined experimentally.
Table 5. Optimum Values for Capacitive Loads
THD + NOISE
The OPx177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OPx177 a great choice for
high closed-loop gain precision circuits.
CL
10 nF
50 nF
200 nF
RS
20 Ω
30 Ω
200 Ω
CS
0.33 μF
6.8 nF
0.47 μF
Figure 55 shows that the OPx177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.
VSY = ±5V
RL = 10kΩ
CL = 2nF
0.1
VOLTAGE (200mV/DIV)
VSY = ±15V
RL = 10kΩ
BW = 22kHz
THD + N (%)
0.01
0
GND
100
1k
FREQUENCY (Hz)
6k
TIME (10µs/DIV)
02627-055
0.0001
20
02627-056
0.001
Figure 56. Capacitive Load Drive Without Snubber
Figure 55. THD + N vs. Frequency
In this case, a snubber network is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the Resistor RS is not inside the feedback loop.
VSY = ±5V
RL = 10kΩ
RS = 200Ω
CL = 2nF
CS = 0.47µF
GND
TIME (10µs/DIV)
Figure 57. Capacitive Load Drive with Snubber
Rev. G | Page 16 of 24
02627-057
OPx177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external
compensation, the OPx177 safely drives capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.
VOLTAGE (200mV/DIV)
CAPACITIVE LOAD DRIVE
OP1177/OP2177/OP4177
Cf
V+
7
OP1177
400mV
6
3
+
–
R1
VOUT
RS
4
CS
R2
V+
CL
+
02627-058
2
V–
7
2
V1
–
Ct
Figure 58. Snubber Network Configuration
OP1177
6
VOUT
3
02627-060
4
Caution: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
V–
Figure 60. Compensation Using Feedback Capacitor
STRAY INPUT CAPACITANCE COMPENSATION
REDUCING ELECTROMAGNETIC INTERFERENCE
The effective input capacitance in an operational amplifier
circuit (Ct) consists of three components. These are the internal
differential capacitance between the input terminals, the internal
common-mode capacitance of each input to ground, and the
external capacitance including parasitic capacitance. In the
circuit in Figure 59, the closed-loop gain increases as the signal
frequency increases.
A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.
The transfer function of the circuit is
R2
(1 + sC t R1)
R1
This is usually achieved by inserting a capacitor between the inputs
of the amplifier, as shown in Figure 61. However, this method can
also cause instability, depending on the value of capacitance.
R1
V+
indicating a zero at
+
R2 + R1
1
=
R2R1C t
2π (R1/ R2 ) C t
The resulting pole can be positioned to adjust the phase margin.
Setting Cf = (R1/R2) Ct achieves a phase margin of 90°.
R2
2
Ct
V–
Placing a resistor in series with the capacitor (see Figure 62)
increases the dc loop gain and reduces the output error. Positioning
the breakpoint (introduced by R-C) below the secondary pole of
the operational amplifier improves the phase margin and,
therefore, stability.
R can be chosen independently of C for a specific phase margin
according to the formula
7
OP1177
VOUT
Figure 61. EMI Reduction
R =
6
VOUT
3
4
V–
02627-059
–
6
4
V+
V1
OP1177
C
3
A simple way to overcome this problem is to insert a capacitor
in the feedback path, as shown in Figure 60.
+
2
V1
–
Depending on the value of R1 and R2, the cutoff frequency of
the closed-loop gain can be well below the crossover frequency.
In this case, the phase margin (ΦM) can be severely degraded,
resulting in excessive ringing or even oscillation.
R1
7
02627-061
s =
R2
R2
R2 ⎞
− ⎛⎜ 1 +
⎟
a ( jf 2 ) ⎝
R1 ⎠
where:
a is the open-loop gain of the amplifier.
f2 is the frequency at which the phase of a = ΦM − 180°.
R2
Figure 59. Stray Input Capacitance
V+
R1
2
+
R
V1
–
C
7
OP1177
6
VOUT
3
4
V–
Figure 62. Compensation Using Input R-C Network
Rev. G | Page 17 of 24
02627-062
1+
In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the CMRR of the amplifier.
OP1177/OP2177/OP4177
In the single instrumentation amplifier (see Figure 63), where
PROPER BOARD LAYOUT
R4
R2
=
R3
R1
The OPx177 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout.
To avoid leakage currents, the surface of the board should be
kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic
resistance on the board.
Keeping supply traces short and properly bypassing the power
supplies minimizes power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. It is recommended that
signal traces be kept at least 5 mm from supply lines to
minimize coupling.
A variation in temperature across the PCB can cause a mismatch in
the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To
minimize these thermocouple effects, orient resistors so heat
sources warm both ends equally. Input signal paths should contain
matching numbers and types of components, where possible to
match the number and type of thermocouple junctions. For
example, dummy components such as zero value resistors can
be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and
should be oriented in the same manner. Ensure leads are of equal
length so that thermal conduction is in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as
is practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.
VO =
R2
(V 2 − V1 )
R1
a mismatch between the ratio R2/R1 and R4/R3 causes the
common-mode rejection ratio to be reduced.
To better understand this effect, consider that, by definition,
CMRR =
A DM
ACM
where ADM is the differential gain and ACM is the commonmode gain.
A DM =
VO
V
and ACM = O
VCM
V DIFF
V DIFF = V1 − V 2 and VCM =
1
(V1 + V 2 )
2
For this circuit to act as a difference amplifier, its output must
be proportional to the differential input signal.
From Figure 63,
⎡ ⎛ R2 ⎞ ⎤
⎢ ⎜⎝1 + R1 ⎟⎠ ⎥
R2 ⎞
⎛
⎥ V2
+
VO = − ⎜
V
⎟ 1 ⎢
⎝ R1 ⎠
⎢ ⎛1 + R3 ⎞ ⎥
⎢⎣ ⎜⎝ R4 ⎟⎠ ⎥⎦
Arranging terms and combining the previous equations yields
CMRR =
R4R1 + R3R2 + 2 R4R2
2 R4R1 − 2 R2R3
The sensitivity of CMRR with respect to the R1 is obtained by
taking the derivative of CMRR, in Equation 1, with respect to R1.
δCMRR
δ ⎛
R1R4
2R2R4 + R2R3 ⎞
=
+
⎜
⎟
δR1
δR1 ⎝ 2R1R4 − 2R2R3 2R1R4 − 2R2R3 ⎠
DIFFERENCE AMPLIFIERS
Difference amplifiers are used in high accuracy circuits to improve
the common-mode rejection ratio (CMRR).
δCMRR
1
=
(2R2R3 )
δR1
2−
R1R4
R2
100kΩ
V+
V1
R1
2
Assuming that
7
OP1177
6
R1 ≈ R2 ≈ R3 ≈ R4 ≈ R
VOUT
3
and
4
V–
R3 = R1
R(1 − δ) < R1, R2, R3, R4 < R(1 + δ)
R4 = R1
R4 R2
=
R3 R1
02627-063
V2
(1)
the worst-case CMRR error arises when
R1 = R4 = R(1 + δ) and R2 = R3 = R(1 − δ)
Figure 63. Difference Amplifier
Rev. G | Page 18 of 24
OP1177/OP2177/OP4177
VCC
CMRR MIN ≅
1
2δ
C1
2.2µF
R9
200kΩ
ADR293
R3
47kΩ
where δ is the tolerance of the resistors.
D1
TR
(–)
Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. Alternatively, using 0.1% tolerance resistors
results in a common-mode rejection ratio of at least 54 dB
(assuming that the operational amplifier CMRR × 54 dB).
With the CMRR of OPx177 at 120 dB minimum, the resistor
match is the limiting factor in most circuits. A trimming resistor
can be used to further improve resistor matching and CMRR of
the difference amplifier circuit.
A HIGH ACCURACY THERMOCOUPLE AMPLIFIER
A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage
VTC = α(TJ − TR)
where:
TJ is the temperature at the measurement of the hot junction.
TR is the temperature at the cold junction.
α is the Seebeck coefficient specific to the dissimilar metals used
in the thermocouple.
VTC is the thermocouple voltage and becomes larger with
increasing temperature.
Maximum measurement accuracy requires cold junction compensation of the thermocouple. To perform the cold junction compensation, apply a copper wire short across the terminating junctions
(inside the isothermal block) simulating a 0°C point. Adjust the
output voltage to zero using the R5 trimming resistor, and remove
the copper wire.
The OPx177 is an ideal amplifier for thermocouple circuits
because it has a very low offset voltage, excellent PSRR and
CMRR, and low noise at low frequencies.
TJ
(+)
0.1µF
10µF
D1
Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the operational amplifier).
V+
R7
80.6kΩ
R2
4.02kΩ
Cu
R8
1kΩ
VTC
TR
R6
50Ω
2
3
R5
100Ω
Cu
R1
50Ω
10µF
10µF
R4
50Ω
ISOTHERMAL
BLOCK
7
OP1177
4
6
VOUT
10µF
0.1µF
V–
02627-064
Plugging these values into Equation 1 yields
Figure 64. Type K Thermocouple Amplifier Circuit
LOW POWER LINEARIZED RTD
A common application for a single element varying bridge is an
RTD thermometer amplifier, as shown in Figure 65. The excitation is delivered to the bridge by a 2.5 V reference applied at the
top of the bridge.
RTDs may have thermal resistance as high as 0.5°C to 0.8°C
per mW. To minimize errors due to resistor drift, the current
through each leg of the bridge must be kept low. In this circuit,
the amplifier supply current flows through the bridge. However,
at the OPx177 maximum supply current of 600 μA, the RTD
dissipates less than 0.1 mW of power, even at the highest resistance. Errors due to power dissipation in the bridge are kept
under 0.1°C.
Calibration of the bridge is made at the minimum value of
temperature to be measured by adjusting RP until the output is zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint and apply a 500°C temperature to
the sensor or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
better than ±0.5°C accuracy after adjustment.
It can be used to create a thermocouple circuit with great
linearity. Resistor R1, Resistor R2, and Diode D1, shown in
Figure 64, are mounted in an isothermal block.
Rev. G | Page 19 of 24
OP1177/OP2177/OP4177
+15V
0.1µF
ADR421
4.12kΩ
4.37kΩ
500Ω
where δ = ΔR/R is the fractional deviation of the RTD resistance
with respect to the bridge resistance due to the change in temperature at the RTD.
200Ω
For δ << 1, the preceding expression becomes
⎛
⎞
⎜
⎟
R2 ⎞
δ
⎛
⎟ =
VO ≅ ⎜ ⎟ VREF ⎜
⎜ 1 + R1 + R1 ⎟
⎝ R ⎠
⎜
⎟
R R2 ⎠
⎝
⎡⎛ R2 ⎞ ⎛ R1 ⎞ ⎛ R1 ⎞⎤
⎢⎜ R ⎟ ⎜1 + R2 ⎟ + ⎜ R2 ⎟⎥ VREF δ
⎠ ⎝ ⎠⎦
⎣⎝ ⎠ ⎝
6
4.12kΩ
100Ω
5
100Ω
1/2
OP2177
7
VOUT
20Ω
5kΩ
49.9kΩ
V+
3
8
1/2
OP2177
1
R2 ⎞ ⎡⎛
R1 ⎞ ⎛ R1 ⎞ ⎤
V REF ⎛⎜
⎟
⎟ ⎜1 +
⎟+⎜
⎝ R ⎠ ⎢⎣⎝ R2 ⎠ ⎝ R2 ⎠ ⎥⎦
VOUT
4
V–
02627-065
2
With VREF constant, the output voltage is linearly proportional
to δ with a gain factor of
Figure 65. Low Power Linearized RTD Circuit
15V
RF
0.1µF
SINGLE OPERATIONAL AMPLIFIER BRIDGE
R
V+
R
7
2
The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal conditioning. It is often more economical to use a single bridge
operational amplifier as opposed to an instrumentation amplifier.
R(1+δ)
OP1177
R
Rev. G | Page 20 of 24
VOUT
4
V–
Figure 66. Single Bridge Amplifier
⎛
⎞⎤
⎜
⎟⎥
δ
⎜
⎟⎥
⎜ R1 ⎛ R1 ⎞
⎟⎥
+ ⎜1 +
⎟ (1 + δ ) ⎟⎥
⎜
R
R2
⎝
⎠
⎝
⎠⎦
6
3
RF
In the circuit shown in Figure 66, the output voltage at the
operational amplifier is
⎡
R2 ⎢⎢
VO =
VREF
R ⎢
⎢
⎣
ADR421
02627-066
100Ω
RTD
OP1177/OP2177/OP4177
REALIZATION OF ACTIVE FILTERS
BAND-PASS KRC OR SALLEN-KEY FILTER
CHANNEL SEPARATION
Because the common-mode voltage into the amplifier varies with
the input signal in the KRC filter circuit, a high CMRR is required
to minimize distortion. Also, the low offset voltage of the OPx177
allows a wider dynamic range when the circuit gain is chosen to
be high.
Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to prevent
feedthrough of signals from one amplifier channel to the other.
As a result, the OP2177 has an impressive channel separation of
greater than −120 dB for frequencies up to 100 kHz and greater
than −115 dB for signals up to 1 MHz.
C3
680pF
R2
10kΩ
The circuit of Figure 67 consists of two stages. The first stage is
a simple high-pass filter where the corner frequency (fC) is
1
2π C1C2R1R2
V+
(2)
6
C2
10nF
and
C1
10nF
V1
R1
R2
(3)
1/2
OP2177
7
R3
33kΩ
–
R1
20kΩ
R4
33kΩ
3
1/2
OP2177
1
VOUT
C4
330pF
4
+
Q=K
5
2
8
V–
02627-067
The low offset voltage and the high CMRR of the OPx177 make
it an excellent choice for precision filters, such as the band-pass
KRC filter shown in Figure 67. This filter type offers the capability
to tune the gain and the cutoff frequency independently.
Figure 67. Two-Stage, Band-Pass KRC Filter
where K is the dc gain.
Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to
10kΩ
V+
6
2πC R1R2
5
The value of Q determines the peaking of the gain vs. frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.
V1
50mV
8
2
1/2
OP2177
+
4
–
V–
7
1
1/2
OP2177
100Ω
3
02627-068
1
Figure 68. Channel Separation Test Circuit
Setting Q =
1
yields minimum gain peaking and minimum
2
ringing. Determine values for R1 and R2 by using Equation 3.
1
For Q =
, R1/R2 = 2 in the circuit example. Select R1 = 5 kΩ
2
and R2 = 10 kΩ for simplicity.
The second stage is a low-pass filter where the corner frequency
can be determined in a similar fashion. For R3 = R4 = R
1
fC =
2πR
C3
C4
and Q =
REFERENCES ON NOISE DYNAMICS
AND FLICKER NOISE
S. Franco, Design with Operational Amplifiers and Analog
Integrated Circuits. McGraw-Hill, 1998.
Analog Devices, Inc., The Best of Analog Dialogue, 1967 to
1991. Analog Devices, Inc., 1991.
1 C3
2 C4
Rev. G | Page 21 of 24
OP1177/OP2177/OP4177
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 70. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. G | Page 22 of 24
060606-A
4.00 (0.1575)
3.80 (0.1496)
OP1177/OP2177/OP4177
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
6°
0°
0.40
0.25
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
0.15
0.05
COPLANARITY
0.10
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. G | Page 23 of 24
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
OP1177/OP2177/OP4177
ORDERING GUIDE
Model
OP1177AR
OP1177ARZ 1
OP1177ARZ-REEL1
OP1177ARZ-REEL71
OP1177ARM-REEL
OP1177ARMZ1
OP1177ARMZ-REEL1
OP1177ARMZ-R71
OP2177AR
OP2177AR-REEL
OP2177AR-REEL7
OP2177ARZ1
OP2177ARZ-REEL1
OP2177ARZ-REEL71
OP2177ARM-REEL
OP2177ARMZ1
OP2177ARMZ-REEL1
OP2177ARMZ-R71
OP4177AR
OP4177AR-REEL
OP4177AR-REEL7
OP4177ARZ1
OP4177ARZ-REEL1
OP4177ARZ-REEL71
OP4177ARU
OP4177ARU-REEL
OP4177ARUZ1
OP4177ARUZ-REEL1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Z = RoHS Compliant Part; # denotes Pb-free product may be top or bottom marked.
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02627-0-11/09(G)
Rev. G | Page 24 of 24
Package Option
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
Branding
AZA
AZA#
AZA#
AZA#
B2A
B2A#
B2A#
B2A#