ISSI IS24C52-2ZI 2k-bit 2-wire serial cmos eeprom with permanent write-protection Datasheet

ISSI
IS24C52
2k-bit 2-WIRE SERIAL CMOS EEPROM
with Permanent Write-Protection
®
ADVANCED INFORMATION
JANUARY 2004
FEATURES
DESCRIPTION
• Two-Wire Serial Interface
The IS24C52 is an electrically erasable PROM device
that uses the standard 2-wire interface for
communications. The IS24C52 contains a memory array
of 2,048-bits (256K x 8), and is further subdivided into 16
pages of 16 bytes each for page-write mode. The
software write-protection feature is initiated with a unique
irreversible instruction. After this command is
transmitted, the first 128 bytes of the array become
permanently read-only. This feature is popular in
applications like DRAM DIMMs to retain DRAM related
data. This EEPROM is offered in wide operating voltages
of 1.8V to 5.5V (IS24C52-2) and 2.5V to 5.5V (IS24C523) to be compatible with most application voltages. ISSI
designed the IS24C52 as a low-cost and low-power 2wire EEPROM solution. The devices are packaged in 8pin SOIC, and 8-pin TSSOP, and 8-pin MSOP.
– Bidirectional data transfer protocol
– 400 kHz (I2C TM Protocol) Compatibility
• Organization:
– 256-bit x 8-bit
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
• 16-Byte Page Write Buffer
– Partial Page-writes permitted
• Low Power CMOS Technology
– Active Current less than 2 mA (5V)
– Standby Current less than 6 µA (5V)
– Standby Current less than 2 µA (2.5V)
• Low Voltage Operation
– IS24C52-2: Vcc = 1.8V to 5.5V
– IS24C52-3: Vcc = 2.5V to 5.5V
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle with auto clear
The IS24C52 maintains compatibility with the popular 2wire bus protocol, so it is easy to use in applications
implementing this bus type. The simple bus consists of
the Serial Clock wire (SCL) and the Serial Data wire
(SDA). Using the bus, a Master device such as a
microcontroller is usually connected to one or more
Slave devices such as the IS24C52. The bit stream over
the SDA line includes a series of bytes, which identifies
a particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C52 has a Write Protect pin (WP)
to allow blocking of any write instruction transmitted over
the bus.
– 5 ms @ 2.5V
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 40 Years
• Commercial and Industrial temperature ranges
•
8-pin SOIC, 8-pin TSSOP, and 8-pin MSOP
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published
information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
01/26/04
1
ISSI
IS24C52
®
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
Vcc
SDA
CONTROL
LOGIC
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
00H-7FH
X
DECODER
SCL
ARRAY
80H-FFH
WORD ADDRESS
COUNTER
A1
Y
DECODER
A2
ACK
GND
nMOS
2
Clock
DI/O
>
DATA
REGISTER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
01/26/04
ISSI
IS24C52
®
PIN CONFIGURATION
8-Pin SOIC, TSSOP, MSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
GND
Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software writeprotection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read -only
regardless of the setting of the WP pin.
DEVICE OPERATION
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
The IS24C52 features a serial communication and supports
a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C52 is the Slave device on the bus.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left unconnected for hardware flexibility. When
pins are hardwired, as many as eight devices may be
addressed on a single bus system. When the pins are not
hardwired, the default A0, A1, and A2 are zero.
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PRELIMINARY INFORMATION Rev. 00B
01/26/04
3
ISSI
IS24C52
®
DEVICE ADDRESSING
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the
data line while the clock line is high will be interpreted
as a Start or Stop condition.
The state of the data line represents valid data after a Start
condition. The data line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C52 monitors the SDA and SCL lines
and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
(Fig. 5) address is 8 bits.
The four most significant bits of the device address are fixed
as 1010 for normal read/write operations, and 0110 for
permanent write-protection operations.
This device has three address bits (A1, A2, and A0) that
allow up to eight IS24C52 devices to share the 2-wire
bus. Upon receiving the Slave address, the device
compares the three address bits with the hardwired A2,
A1, and A0 input pins to determine if it is the appropriate
Slave. If any of the A2 - A0 pins is neither biased to High
nor Low, then internal circuitry defaults the value to Low.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and
Slave address byte (Fig. 5), the appropriate 2-wire
Slave (eg. IS24C52) will respond with ACK on the SDA
line. The Slave will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data. The
selected IS24C52 then prepares for a Read or Write
operation by monitoring the bus.
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C52 contains a reset function in case the 2-wire
bus transmission is accidentally interrupted (eg. a power
loss), or needs to be terminated mid-stream. The reset
is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption in reduced in standby mode. The
IS24C52 will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if no write operation is initiated; or c) Following any
internal write operation
4
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PRELIMINARY INFORMATION Rev. 00B
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ISSI
IS24C52
®
WRITE OPERATION
Permanent Write Protection
Byte Write
The IS24C52 contains a permanent write protection feature
that is initiated by means of a software command. After the
command is transmitted, the protected area becomes
irreversibly read-only despite power removal and reapplication on the device. The address range of the 128
bytes of the array that is affected by this feature is 00h-7Fh.
Once enabled, the permanent protection is independent of
the status of the WP pin. (If WP is raised to High, the entire
array is read-only. If WP is low, the region 00h-7Fh can still
be read-only.)
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends a byte address that is written into
the address pointer of the IS24C52. After receiving another
ACK from the Slave, the Master device transmits the data
byte to be written into the address memory location. The
IS24C52 acknowledges once more and the Master generates
the Stop condition, at which time the device begins its
internal programming cycle. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
Page Write
The IS24C52 is capable of 16-byte Page-Write operation. A
Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
first data byte is transferred, the Master device can transmit
up to 15 more bytes. After the receipt of each data byte, the
IS24C52 responds immediately with an ACK on SDA line,
and the four lower order data byte address bits are internally
incremented by one, while the higher order bits of the data
byte address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the first
byte of that page. If the Master device should transmit more
than 16 bytes prior to issuing the Stop condition, the address
counter will “roll over,” and the previously written data will be
overwritten. Once all 16 bytes are received and the Stop
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS24C52 in a single Write cycle. All inputs are
disabled until completion of the internal Write cycle.
The software command is initiated similarly to a normal
byte write operation; however, the slave address begins
with the bits 0110 (see Figure 5). The following three bits are
A2 - A0. The last bit of the slave address (R/W) is 0. If the
IS24C52 responds with ACK, then the device has not yet
had its write-protection permanently enabled. To complete
the command, the Master must transmit a dummy address
byte, dummy data byte, and a Stop signal
(see Figure 11). The WP pin must be Low during this
command. Before resuming any other command, the
internal write cycle should be observed.
The status of the permanent write protection can be safely
determined without any changes by transmitting the same
Slave address as above, but with the last bit (R/W) set to
1(see Figure 12). If the permanent write protection has been
enabled, then the IS24C52 will not acknowledge any slave
address starting with bits 0110 (see Figure 5).
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C52 initiates the internal Write cycle. ACK polling can be
initiated immediately. This involves issuing the Start condition
followed by the Slave address for a Write operation. If the
IS24C52 is still busy with the Write operation, no ACK will be
returned. If the IS24C52 has completed the Write operation,
an ACK will be returned and the host can then proceed with
the next Read or Write operation.
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PRELIMINARY INFORMATION Rev. 00B
01/26/04
5
ISSI
IS24C52
®
READ OPERATION
Sequential Read
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address is
set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the IS24C52
sends the initial byte sequence, the Master device responds
with an ACK indicating it requires additional data from the
IS24C52. The IS24C52 continues to output data for each
ACK received. The Master device terminates the sequential
Read operation by pulling SDA High (no ACK) indicating the
last data byte to be read, followed by a Stop condition.
Current Address Read
The IS24C52 contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous
operation is either a Read or Write operation addressed
to the address location n, the internal address counter
would increment to address location n+1. When the
IS24C52 receives the Device Addressing Byte with a
Read operation (R/W bit set to “1”), it will respond an ACK
and transmit the 8-bit data byte stored at address
location n+1. The Master should not acknowledge the
transfer but should generate a Stop condition so the
IS24C52 discontinues transmission. If 'n' is the last byte
of the memory, then the data from location '0' will be
transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
The data output is sequential, with the data from address n
followed by the data from address n+1, ... etc. The address
counter increments by one automatically, allowing the
entire memory contents to be serially read during sequential
Read operations. When the memory address boundary 255
is reached, the address counter “rolls over” to address 0, and
the IS24C52 continues to output data for each ACK received.
(Refer to Figure 10. Sequential Read Operation Starting with
a Random Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and word address
of the location it wishes to read. After the IS24C52
acknowledges the word address, the Master device resends
the Start condition and the Slave address, this time with the
R/W bit set to one. The IS24C52 then responds with its ACK
and sends the data requested. The Master device does not
send an ACK but will generate a Stop condition. (Refer to
Figure 9. Random Address Read Diagram.)
6
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PRELIMINARY INFORMATION Rev. 00B
01/26/04
ISSI
IS24C52
®
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24C52
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. Start and Stop Conditions
SDA
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7
ISSI
IS24C52
®
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Slave Address
BIT
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
7
6
5
4
3
2
1
0
0
1
1
0
A2
A1
A0
R/W
Normal
Instruction
Permanent Write Protect
Instruction
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E *
A
C
K
L
S
B
R/W
*
Word Address
Data
A
C
K
S
T
O
* P
A
C
K
M
S
B
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E * Word Address (n) *
A
A
C
C
K
K
Data (n)
*
A
C
K
Data (n+1)
*
A
C
K
Data (n+15)
S
T
O
* P
A
C
K
L
S
B
R/W
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
8
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PRELIMINARY INFORMATION Rev. 00B
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ISSI
IS24C52
®
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
SDA
Bus
Activity
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
W
R
I
T
E
Device
Address
SDA
Bus
Activity
Word
Address (n)
A
C
K
M
S
B
S
T
A
R
T
Device
Address
A
C
K
R
E
A
D
S
T
O
P
Data n
A
C
K
L
S
B
R/W
N
O
A
C
K
DUMMY WRITE
Figure 10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+2
A
C
K
S
T
O
P
Data Byte n+X
A
C
K
N
O
R/W
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A
C
K
9
ISSI
IS24C52
®
FIGURE 11. PERMANENT WRITE PROTECTION INITIATION
SDA
Bus
Activity
S
T
A
R
T
W
R
I
Device
T
Data
Address
E * Word Address
A
A
A
C # # ## # # # #C # # # ## # # # C
K
K
K
M
L
M
S
S
S
B
B
B
R/W
S
T
O
P
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
# Don't care bits are required.
FIGURE 12. PERMANENT WRITE PROTECTION VERIFICATION
S
T
A
R
T
R S
E T
A O
D * P
A
C
K
Device
Address
SDA
Bus
Activity
M
S
B
L
S
B
R/W
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
10
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PRELIMINARY INFORMATION Rev. 00B
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ISSI
IS24C52
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
0.5 to +6.25
–0.5 to Vcc + 0.5
–40 to +85
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
(IS24C52-2)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
1.8V to 5.5V
1.8V to 5.5V
OPERATING RANGE
(IS24C52-3)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.5V to 5.5V
2.5V to 5.5V
Automotive
–40°C to +125°C
2.5V to 5.5V
Note: Automotive data is preliminary.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
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11
ISSI
IS24C52
®
DC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOL1
Output Low Voltage
VOL2
Output Low Voltage
VCC = 1.8V, IOL = 0.15 mA
—
0.2
V
VCC = 2.5V, IOL = 3 mA
—
0.4
V
V IH
Input High Voltage
V IL
Input Low Voltage
ILI
Input Leakage Current
ILO
Output Leakage Current
VCC
X
0.7 VCC + 0.5
–1.0
VIN = VCC max.
VCC
0.3
X
V
V
—
3
µA
—
3
µA
Min.
Max.
Unit
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
Symbol Parameter
Test Conditions
ICC1
Vcc Operating Current
Read at 400 KHz (Vcc = 5V)
—
2.0
mA
ICC2
Vcc Operating Current
Write at 400 KHz (Vcc = 5V)
—
3.0
mA
ISB1
Standby Current
Vcc = 1.8V
—
1
µA
ISB2
Standby Current
Vcc = 2.5V
—
2
µA
ISB3
Standby Current
Vcc = 5.0 V
—
6
µA
AC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0oC to +70oC) Industrial (TA = -40oC to +85oC)
Symbol Parameter
fSCL
SCL Clock Frequency
Time(1)
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Min. Max.
Min. Max.
Min. Max.
Unit
0
100
0
400
0
1000
KHz
—
100
—
50
—
50
ns
T
Noise Suppression
tLow
Clock Low Period
4.7
—
1.2
—
0.6
—
µs
tHigh
Clock High Period
4
—
0.6
—
0.4
—
µs
t BUF
Bus Free Time Before New Transmission(1)
4.7
—
1.2
—
0.5
—
µs
tSU:STA
Start Condition Setup Time
4
—
0.6
—
0.25
—
µs
tSU:STO
Stop Condition Setup Time
4
—
0.6
—
0.25
—
µs
tHD:STA
Start Condition Hold Time
4
—
0.6
—
0.25
—
µs
tHD:STO
Stop Condition Hold Time
4
—
0.6
—
0.25
—
µs
tSU:DAT
Data In Setup Time
100
—
100
—
100
—
ns
t HD:DAT
Data In Hold Time
0
—
0
—
0
—
ns
tSU : WP
WP pin Setup Time
4
—
0.6
—
0.6
—
µs
t HD : WP
WP pin Hold Time
4.7
—
1.2
—
1.2
—
µs
t DH
Data Out Hold Time (SCL Low to SDA Data Out Change) 100
—
50
—
50
—
ns
tAA
Clock to Output (SCL Low to SDA Data Out Valid)
100
3500
50
900
50
400
ns
tR
SCL and SDA Rise Time(1)
—
1000
—
300
—
300
ns
—
300
—
300
—
100
ns
—
10
—
10
—
5
ms
tF
SCL and SDA Fall
t WR
Write Cycle Time
12
Time(1)
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ISSI
IS24C52
®
FIGURE 13. AC WAVEFORMS
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
FIGURE 14. WRITE CYCLE TIMING
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
01/26/04
START
Condition
13
ISSI
IS24C52
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
Voltage
Range
Part Number
Package
100 KHz
1.8V
to 5.5V
IS24C52-2G
IS24C52-2S
IS24C52-2Z
Small Outline (JEDEC STD) (8-pin)
MSOP
TSSOP
400 KHz
2.5V
to 5.5V
IS24C52-3G
IS24C52-3S
IS24C52-3Z
Small Outline (JEDEC STD) (8-pin)
MSOP
TSSOP
Part Number
Package
Industrial Range: –40°C to +85°C
Frequency
Voltage
Range
100 KHz
1.8V
to 5.5V
IS24C52-2GI
IS24C52-2SI
IS24C52-2ZI
Small Outline (JEDEC STD) (8-pin)
MSOP
TSSOP
400 KHz
2.5V
to 5.5V
IS24C52-3GI
IS24C52-3SI
IS24C52-3ZI
Small Outline (JEDEC STD) (8-pin)
MSOP
TSSOP
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
14
®
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
01/26/04
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