TI LMZ10501SH Lmz10501 1a simple switcher nano module with 5.5v maximum input voltage Datasheet

LMZ10501
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SNVS677D – MAY 2011 – REVISED MARCH 2013
LMZ10501 1A SIMPLE SWITCHER® Nano Module with 5.5V Maximum Input Voltage
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FEATURES
DESCRIPTION
•
•
The LMZ10501 SIMPLE SWITCHER® nano module
is an easy-to-use step-down DC-DC solution capable
of driving up to 1A load in space-constrained
applications. Only an input capacitor, an output
capacitor, a small VCON filter capacitor, and two
resistors are required for basic operation. The nano
module comes in 8-pin POS footprint package with
an integrated inductor. Internal current limit based
softstart function, current overload protection, and
thermal shutdown are also provided.
1
2
•
•
•
•
•
•
•
•
•
•
Integrated Inductor
Miniature Form Factor (3.0 mm x 2.5 mm x
1.425 mm)
8-pin LLP Footprint
-40°C to 125°C Junction Temperature Range
Adjustable Output Voltage
2.0MHz Fixed PWM Switching Frequency
Integrated Compensation
Soft Start Function
Current Limit Protection
Thermal Shutdown Protection
Input Voltage UVLO for Power-up, Powerdown, and Brown-out Conditions
Only 5 External Components — Resistor
Divider and 3 Ceramic Capacitors
System Performance
(Quick Overview Links: VOUT = 1.2V, 1.8V, 2.5V,
3.3V)
Typical Efficiency at VIN = 3.6V
100
90
•
•
•
Point of Load Conversions From 3.3V and 5V
Rails
Space Constrained Applications
Low Output Noise Applications
EFFICIENCY (%)
APPLICATIONS
80
70
60
50
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
40
ELECTRICAL SPECIFICATIONS
•
•
•
•
Up to 1A Output Current
Input Voltage Range 2.7V to 5.5V
Output Voltage Range 0.6V to 3.6V
Efficiency up to 95%
PERFORMANCE BENEFITS
•
•
•
•
Small Solution Size
Low Output Voltage Ripple
Easy Component Selection and Simple PCB
Layout
High Efficiency Reduces System Heat
Generation
30
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Output Voltage Ripple
VIN = 5.0V, VOUT = 1.8V, IOUT = 1A
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
10 mV/Div
500 MHz BW
1 µs/Div
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMZ10501
SNVS677D – MAY 2011 – REVISED MARCH 2013
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Radiated EMI (CISPR22)
VIN = 5.0V, VOUT = 1.8V, IOUT = 1A
RADIATED EMISSIONS (dB V/m)
80
Emissions (Evaluation Board)
EN 55022 Class B Limit
EN 55022 Class A Limit
70
60
50
40
30
20
10
0
0
200
400
600
800
FREQUENCY (MHz)
1000
Connection Diagram
PAD
PAD
PAD
Figure 1. Package Number NQB0008A
PIN DESCRIPTIONS
Pin #
Name
1
EN
2
VCON
3
FB
4
SGND
Ground for analog and control circuitry. Connect to PGND at a single point.
5
VOUT
Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter capacitor between
VOUT and PGND.
6
PGND
Power ground for the power MOSFETs and gate-drive circuitry.
7
VIN
8
VREF
PAD
Description
Enable Input. Set this digital input higher than 1.2V for normal operation. For shutdown, set low. Pin is
internally pulled up to VIN and can be left floating for always-on operation.
Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to set the VOUT
voltage. VOUT = 2.5 x VCON. Connect a small (470pF) capacitor from this pin to SGND to provide noise
filtering.
Feedback of the error amplifier. Connect directly to output capacitor to sense VOUT.
Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to these two
pins. Typical capacitor values are between 4.7µF and 22µF.
2.35V voltage reference output. Typically connected to VCON pin through a resistive divider to set the output
voltage.
The 3 pads underneath the module are not internally connected to any node. These pads should be
connected to the ground plane for improved thermal performance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2)
VIN, VREF to SGND
−0.2V to +6.0V
PGND to SGND
−0.2V to +0.2V
EN, FB, VCON
(SGND −0.2V)
to (VIN +0.2V)
w/6.0V max
VOUT
(PGND −0.2V)
to (VIN +0.2V)
w/6.0V max
Junction Temperature (TJ-MAX)
+150°C
Storage Temperature Range
−65°C to +150°C
Maximum Lead Temperature
+260°C
ESD Susceptibility
(1)
(2)
(3)
(3)
±2kV
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
Operating Ratings
(1)
Input Voltage Range
2.7V to 5.5V
Recommended Load Current
0 mA to 1000 mA
Junction Temperature (TJ) Range
−40°C to +125°C
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Thermal Properties
Junction-to-Ambient Thermal
120°C/W
Resistance (θJA), NQB0008A Package
(1)
(1)
Junction-to-ambient thermal resistance (θJA) is based on 4 layer board thermal measurements, performed under the conditions and
guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. θJA varies with PCB copper area, power dissipation, and airflow.
Electrical Characteristics
(1)
Specifications with standard typeface are for TJ = 25°C only; Limits in bold face type apply over the operating junction
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. Unless otherwise stated the following conditions apply: VIN = 3.6V, VEN = 1.2V.
Symbol
Parameter
Conditions
Min
Typ
Max
(1)
Units
(1)
(2)
SYSTEM PARAMETERS
VREF x GAIN
Reference voltage x VCON to
FB Gain
VIN = VEN = 5.5V, VCON = 1.44V
5.7575
5.875
5.9925
V
GAIN
VCON to FB Gain
VIN = 5.5V, VCON = 1.44V
2.4375
2.5
2.5750
V/V
VINUVLO
VIN rising threshold
2.4
V
VINUVLO
VIN falling theshold
2.25
V
ISHDN
Shutdown supply current
VIN = 3.6V, VEN = 0.5V
(3)
11
18
µA
Iq
DC bias current into VIN
VIN = 5.5V, VCON = 1.6V, IOUT =
0A
6.5
8.5
mA
RDROPOUT
VIN to VOUTresistance
IOUT = 200 mA
285
425
mΩ
(1)
(2)
(3)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate the Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Shutdown current includes leakage current of the high side PFET.
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Electrical Characteristics (1) (continued)
Specifications with standard typeface are for TJ = 25°C only; Limits in bold face type apply over the operating junction
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. Unless otherwise stated the following conditions apply: VIN = 3.6V, VEN = 1.2V.
Symbol
Parameter
Conditions
Min
Typ
1125
1350
2.0
(1)
(2)
Max
(1)
Units
SYSTEM PARAMETERS
DC Output Current Limit
FOSC
Internal oscillator frequency
1.75
VIH,ENABLE
Enable logic HIGH voltage
1.2
VIL,ENABLE
Enable logic LOW voltage
TSD
Thermal shutdown
150
°C
TSD-HYST
Thermal shutdown hysteresis
20
°C
DMAX
Maximum duty cycle
100
%
TON-MIN
Minimum on-time
50
ns
θJA
Package Thermal Resistance
(4)
VCON = 0.24V
(4)
I LIM
mA
2.25
V
0.5
Rising Threshold
MHz
20mm x 20mm board
2 layers, 2 oz copper, 0.5W, no
airlow
118
15mm x 15mm board
2 layers, 2 oz copper, 0.5W, no
airlow
132
10mm x 10mm board
2 layers, 2 oz copper, 0.5W, no
airlow
157
V
°C/W
Current limit is built-in, fixed, and not adjustable.
System Characteristics
The following specifications are guaranteed by design providing the component values in the Typical Application Circuit are
used (CIN = COUT = 10 µF, 6.3V, 0603, TDK C1608X5R0J106K). These parameters are not guaranteed by production
testing. Unless otherwise stated the following conditions apply: TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ΔVOUT/VOUT Output Voltage Regulation Over
Line Voltage and Load Current
VOUT = 0.6V
ΔVIN =2.7V to 4.2V
ΔIOUT = 0A to 1A
±1.75
%
ΔVOUT/VOUT Output Voltage Regulation Over
Line Voltage and Load Current
VOUT = 1.5V
ΔVIN = 2.7V to 5.5V
ΔIOUT = 0A to 1A
±0.92
%
ΔVOUT/VOUT Output Voltage Regulation Over
Line Voltage and Load Current
VOUT = 3.6V
ΔVIN = 4.0V to 5.5V
ΔIOUT = 0A to 1A
±0.38
%
VREF TRISE Rise time of reference voltage
EN = Low to High, VIN = 4.2V
VOUT = 2.7V, IOUT = 1A
10
µs
VIN = 5.0V, VOUT = 3.3V
IOUT = 200 mA
95
VIN = 5.0V, VOUT = 3.6V
IOUT = 1000 mA
91
VIN = 5.0V, VOUT = 1.8V
IOUT = 1000 mA (1)
10
mV pk-pk
Peak Efficiency
η
Full Load Efficiency
VOUT Ripple Output voltage ripple
%
Line
Transient
Line transient response
VIN = 2.7V to 5.5V,
TR = TF= 10 µs,
VOUT = 1.8V, IOUT = 1000mA
30
mV pk-pk
Load
Transient
Load transient response
VIN = 5.0V
TR = TF = 40 µs,
VOUT = 1.8V
IOUT = 100mA to 1000 mA
30
mV pk-pk
(1)
4
Ripple voltage should be measured across COUT on a well-designed PC board using the suggested capacitors.
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Typical Performance Characteristics
Unless otherwise specified the following conditions apply: VIN = 3.6V, TA = 25°C
Dropout Voltage
vs
Load Current and Input Voltage
Thermal Derating VOUT = 1.2V, θJA = 120°C/W
0.30
0.25
1.2
VIN = 2.7V
VIN = 3.3V
VIN = 3.6V
VIN = 4.0V
OUTPUT CURRENT (A)
DROPOUT VOLTAGE (V)
0.35
0.20
0.15
0.10
0.8
0.6
0.4
0.2
0.05
0.00
0.0
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
1.0
0.0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
1.0
60
70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
Figure 2.
Figure 3.
Thermal Derating VOUT = 1.8V, θJA = 120°C/W
Thermal Derating VOUT = 2.5V, θJA = 120°C/W
1.2
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
1.2
0.8
0.6
0.4
0.2
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
1.0
0.8
0.6
0.4
0.2
0.0
0.0
60
70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
60
70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
Figure 4.
Figure 5.
Thermal Derating VOUT = 3.3V, θJA = 120°C/W
Radiated EMI (CISPR22)
VIN = 5.0V, VOUT = 1.8V, IOUT = 1A
Default evaluation board BOM
80
VIN = 4.0V
VIN = 4.5V
VIN = 5.0V
VIN = 5.5V
1.0
RADIATED EMISSIONS (dB V/m)
OUTPUT CURRENT (A)
1.2
0.8
0.6
0.4
0.2
0.0
Emissions (Evaluation Board)
EN 55022 Class B Limit
EN 55022 Class A Limit
70
60
50
40
30
20
10
0
60
70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
Figure 6.
0
200
400
600
800
FREQUENCY (MHz)
1000
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 3.6V, TA = 25°C
Conducted EMI
VIN = 5.0V, VOUT = 1.8V, IOUT = 1A
Default evaluation board BOM with additional 1µH 1µF LC
input filter
CONDUCTED EMISSIONS (dB V)
80
70
Startup
VCON
Conducted Emissions
CISPR 22 Quasi Peak
CISPR 22 Average
500 mV/Div
60
50
40
300 mA/Div
IL
30
300 mA/Div
20
10
IOUT
500 mV/Div
VOUT
10 µs/Div
0
100m
1
10
FREQUENCY (MHz)
100
Figure 8.
6
Figure 9.
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1.2V
Schematic VOUT = 1.2V
VIN
CIN
VIN
EN
Efficiency VOUT = 1.2V
100
1.2V
VOUT
90
VOUT
EFFICIENCY (%)
VREF
FB
RT
VCON
PGND
RB
COUT
SGND
CVC
80
70
60
50
VIN = 2.7V
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
243 k: 1%
63.4 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 10.
Figure 11.
Output Ripple VOUT = 1.2V
Load Transient VOUT = 1.2V
COUT = 10 F 10V 0805 X5R
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
30 mV/Div
OUTPUT VOLTAGE
10 mV/Div
500 mA/Div
500 MHz BW
1 µs/Div
LOAD CURRENT
250 MHz BW
Figure 12.
Figure 13.
Line and Load Regulation VOUT = 1.2V
DC Current Limit VOUT = 1.2V
1.5
DC CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
1.24
1.23
1.22
1.21
500 µs/Div
VIN = 2.7V
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
1.20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 14.
TA= 85°C
1.4
1.3
1.2
1.1
1.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
Figure 15.
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1.8V
Schematic VOUT = 1.8V
VIN
CIN
VIN
EN
Efficiency VOUT = 1.8V
100
1.8V
VOUT
90
VOUT
EFFICIENCY (%)
VREF
FB
RT
VCON
PGND
RB
COUT
SGND
CVC
80
70
60
50
VIN = 2.7V
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
187 k: 1%
82.5 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 16.
Figure 17.
Output Ripple VOUT = 1.8V
Load Transient VOUT = 1.8V
COUT = 10 F 10V 0805 X5R
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
30 mV/Div
OUTPUT VOLTAGE
500 mA/Div
LOAD CURRENT
10 mV/Div
1 µs/Div
500 MHz BW
250 MHz BW
Figure 18.
Figure 19.
Line and Load Regulation VOUT = 1.8V
DC Current Limit VOUT = 1.8V
1.5
DC CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
1.81
1.80
1.79
1.78
VIN = 2.7V
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
1.77
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 20.
8
500 µs/Div
TA= 85°C
1.4
1.3
1.2
1.1
1.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
Figure 21.
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2.5V
Schematic VOUT = 2.5V
VIN
CIN
VIN
EN
Efficiency VOUT = 2.5V
100
2.5V
VOUT
90
VOUT
EFFICIENCY (%)
VREF
FB
RT
VCON
PGND
RB
COUT
SGND
CVC
80
70
60
50
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
150 k: 1%
118 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 22.
Figure 23.
Output Ripple VOUT = 2.5V
Load Transient VOUT = 2.5V
COUT = 10 F 10V 0805 X5R
VOUT RIPPLE
COUT = 10 PF 10V 0805 X5R
30 mV/Div
OUTPUT VOLTAGE
10 mV/Div
500 mA/Div
500 MHz BW
LOAD CURRENT
1 Ps/Div
250 MHz BW
Figure 24.
Figure 25.
Line and Load Regulation VOUT = 2.5V
DC Current Limit VOUT = 2.5V
1.5
DC CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
2.53
2.52
2.51
2.50
2.50
500 µs/Div
VIN = 3.3V
VIN = 3.6V
VIN = 5.0V
VIN = 5.5V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 26.
TA= 85°C
1.4
1.3
1.2
1.1
1.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
Figure 27.
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3.3V
Schematic VOUT = 3.3V
VIN
CIN
VIN
EN
Efficiency VOUT = 3.3V
100
3.3V
VOUT
90
VOUT
FB
VCON
RB
PGND
80
EFFICIENCY (%)
VREF
RT
COUT
SGND
CVC
70
60
50
VIN = 3.6V
VIN = 4.0V
VIN = 4.5V
VIN = 5.0V
VIN = 5.5V
40
CIN
COUT
CVC
RT
RB
10 P) 8 6.3V
10 PF 8 6.3V
470 pF 8 6.3V
118 k: 1%
150 k: 1%
0805 X7R or X5R
0805 X7R or X5R
0603 X7R or X5R
0603
0603
30
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
Figure 28.
Figure 29.
Output Ripple VOUT = 3.3V
Load Transient VOUT = 3.3V
COUT = 10 F 10V 0805 X5R
VOUT RIPPLE
COUT = 10 F 10V 0805 X5R
30 mV/Div
OUTPUT VOLTAGE
10 mV/Div
500 mA/Div
500 MHz BW
1 µs/Div
Figure 30.
Line and Load Regulation VOUT = 3.3V
DC Current Limit VOUT = 3.3V
DC CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
1.5
3.28
3.26
VIN = 3.6V
VIN = 4.0V
VIN = 4.5V
VIN = 5.0V
VIN = 5.5V
3.22
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
TA= 85°C
1.4
1.3
1.2
1.1
1.0
2.5
Figure 32.
10
500 µs/Div
Figure 31.
3.30
3.24
LOAD CURRENT
250 MHz BW
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
Figure 33.
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BLOCK DIAGRAM
VREF
VIN
UVLO
REFERENCE
VOLTAGE
VCON
ERROR
AMPLIFIER
FB
COMP
CURRENT
COMP
CURRENT SENSE
L
VOUT
MOSFET
CONTROL
LOGIC
Integrated
Inductor
VIN
UVLO
MAIN CONTROL
EN
TSD
OSCILLATOR
SGND
PGND
Figure 34. Functional Block Diagram
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OVERVIEW
The LMZ10501 SIMPLE SWITCHER® nano module is an easy-to-use step-down DC-DC solution capable of
driving up to 1A load in space-constrained applications. Only an input capacitor, an output capacitor, a small
VCON filter capacitor, and two resistors are required for basic operation. The nano module comes in 8-pin POS
footprint package with an integrated inductor. The LMZ10501 operates in fixed 2.0MHz PWM (Pulse Width
Modulation) mode, and is designed to deliver power at maximum efficiency. The output voltage is typically set by
using a resistive divider between the built-in reference voltage VREF and the control pin VCON. The VCON pin is the
positive input to the error amplifier. The output voltage of the LMZ10501 can also be dynamically adjusted
between 0.6V and 3.6V by driving the VCON pin externally. Internal current limit based softstart function, current
overload protection, and thermal shutdown are also provided.
CIRCUIT OPERATION
The LMZ10501 is a synchronous Buck power module using a PFET for the high side switch and an NFET for the
synchronous rectifier switch. The output voltage is regulated by modulating the PFET switch on-time. The circuit
generates a duty-cycle modulated rectangular signal. The rectangular signal is averaged using a low pass filter
formed by the integrated inductor and an output capacitor. The output voltage is equal to the average of the dutycycle modulated rectangular signal. In PWM mode, the switching frequency is constant. The energy per cycle to
the load is controlled by modulating the PFET on-time, which controls the peak inductor current. In current mode
control architecture, the inductor current is compared with the slope compensated output of the error amplifier. At
the rising edge of the clock, the PFET is turned ON, ramping up the inductor current with a slope of (VIN VOUT)/L. The PFET is ON until the current signal equals the error signal. Then the PFET is turned OFF and
NFET is turned ON, ramping down the inductor current with a slope of VOUT /L. At the next rising edge of the
clock, the cycle repeats. An increase of load pulls the output voltage down, resulting in an increase of the error
signal. As the error signal goes up, the peak inductor current is increased, elevating the average inductor current
and responding to the heavier load. To ensure stability, a slope compensation ramp is subtracted from the error
signal and internal loop compensation is provided.
INPUT UNDER VOLTAGE DETECTION
The LMZ10501 implements an under voltage lock out (UVLO) circuit to ensure proper operation during startup,
shutdown and input supply brownout conditions. The circuit monitors the voltage at the VIN pin to ensure that
sufficient voltage is present to bias the regulator. If the under voltage threshold is not met, all functions of the
controller are disabled and the controller remains in a low power standby state.
SHUTDOWN MODE
To shutdown the LMZ10501, pull the EN pin low (<0.5V). In the shutdown mode all internal circuits are turned
OFF.
EN PIN OPERATION
The EN pin is internally pulled up to VIN through a 790kΩ (typ.) resistor. This allows the nano module to be
enabled by default when the EN pin is left floating. In such cases VIN will set EN high when VIN reaches 1.2V. As
the input voltage continues to rise, operation will start once VIN exceeds the under-voltage lockout (UVLO)
threshold. To set EN high externally, pull it up to 1.2V or higher. Note that the voltage on EN must remain at less
than VIN+ 0.2V due to absolute maximum ratings of the device.
INTERNAL SYNCHRONOUS RECTIFICATION
The LMZ10501 uses an internal NFET as a synchronous rectifier to minimize the switch voltage drop and
increase efficiency. The NFET is designed to conduct through its intrinsic body diode during the built-in dead time
between the PFET on-time and the NFET on-time. This eliminates the need for an external diode. The dead time
between the PFET and NFET connection prevents shoot through current from VIN to PGND during the switching
transitions.
12
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CURRENT LIMIT
The LMZ10501 current limit feature protects the module during an overload condition. The circuit employs
positive peak current limit in the PFET and negative peak current limit in the NFET switch. The positive peak
current through the PFET is limited to 1.7A (typ.). When the current reaches this limit threshold the PFET switch
is immediately turned off until the next switching cycle. This behavior continues on a cycle-by-cycle basis until the
overload condition is removed from the output. The typical negative peak current limit through the NFET switch is
-0.6A (typ.).
The ripple of the inductor current depends on the input and output voltages. This means that the DC level of the
output current when the peak current limiting occurs will also vary over the line voltage and the output voltage
level. Refer to the DC Output Current Limit plots in the Typical Performance Characteristics section for more
information.
STARTUP BEHAVIOR AND SOFTSTART
The LMZ10501 features a current limit based soft start circuit in order to prevent large in-rush current and output
overshoot as VOUT is ramping up. This is achieved by gradually increasing the PFET current limit threshold to the
final operating value as the output voltage ramps during startup. The maximum allowed current in the inductor is
stepped up in a staircase profile for a fixed number of switching periods in each step. Additionally, the switching
frequency in the first step is set at 450kHz and is then increased for each of the following steps until it reaches
2MHz at the final step of current limiting. This current limiting behavior is illustrated in Figure 35 and allows for a
smooth VOUT ramp up.
VCON
500 mV/Div
300 mA/Div
IL
300 mA/Div
IOUT
500 mV/Div
VOUT
10 µs/Div
Figure 35. Startup behavior of current limit based softstart.
The soft start rate is also limited by the VCON ramp up rate. The VCON pin is discharged internally through a pull
down device before startup occurs. This is done to deplete any residual charge on the VCON filter capacitor and
allow the VCON voltage to ramp up from 0V when the part is started. The events that cause VCON discharge are
thermal shutdown, UVLO, EN low, or output short circuit detection. The minimum recommended capacitance on
VCON is 220pF and the maximum is 1nF. The duration of startup current limiting sequence takes approximately
75µs. After the sequence is completed, the feedback voltage is monitored for output short circuit events.
OUTPUT SHORT CIRCUIT PROTECTION
In addition to cycle by cycle current limit, the LMZ10501 features a second level of short circuit protection. If the
load pulls the output voltage down and the feedback voltage falls to 0.375V, the output short circuit protection will
engage. In this mode the internal PFET switch is turned OFF after the current limit comparator trips and the
beginning of the next cycle is inhibited for approximately 230µs. This forces the inductor current to ramp down
and limits excessive current draw from the input supply when the output of the regulator is shorted. The
synchronous rectifier is always OFF in this mode. After 230µs of non-switching a new startup sequence is
initiated. During this new startup sequence the current limit is gradually stepped up to the nominal value as
illustrated in the STARTUP BEHAVIOR AND SOFTSTART section. After the startup sequence is completed
again, the feedback voltage is monitored for output short circuit. If the short circuit is still persistent after the new
startup sequence, switching will be stopped again and there will be another 230µs off period. A persistent output
short condition results in a hiccup behavior where the LMZ10501 goes through the normal startup sequence,
then detects the output short at the end of startup, terminates switching for 230µs, and repeats this cycle until the
output short is released. This behavior is illustrated in Figure 36.
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VOUT
1V/Div
IIN
100 mA/Div
IL
0.5A/Div
VCON
100 µs/Div
1V/Div
Figure 36. Hiccup behavior with persistent output short circuit.
Since the output current is limited during normal startup by the softstart function, the current charging the output
capacitor is also limited. This results in a smooth VOUT ramp up to nominal voltage. However, using excessively
large output capacitance or VCON capacitance under normal conditions can prevent the output voltage from
reaching 0.375V at the end of the startup sequence. In such cases the module will maintain the described above
hiccup mode and the output voltage will not ramp up to final value. To cause this condition, one would have to
use unnecessarily large output capacitance for 1A load applications. See the INPUT AND OUTPUT CAPACITOR
SELECTION section for guidance on maximum capacitances for different output voltage settings.
HIGH DUTY CYCLE OPERATION
The LMZ10501 features a transition mode designed to extend the output regulation range to the minimum
possible input voltage. As the input voltage decreases closer and closer to VOUT, the off-time of the PFET gets
smaller and smaller and the duty cycle eventually needs to reach 100% to support the output voltage. The input
voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10501 input voltage is
lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10501 doubles the switching
period to extend the off-time for that VIN and maintain regulation. If VIN is lowered even more, the off-time of the
PFET will reach the 35ns mark again. The LMZ10501 will then reduce the frequency again, achieving less than
100% duty cycle operation and maintaining regulation. As VIN is lowered even more, the LMZ10501 will continue
to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases
further, 100% duty cycle is reached. This behavior of extending the VIN regulation range is illustrated in the
following plot.
1V/Div
INPUT VOLTAGE
1V/Div
SWITCH NODE
20 MHz BW
5 µs/Div
Figure 37. High duty cycle operation and switching frequency reduction.
14
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THERMAL OVERLOAD PROTECTION
The junction temperature of the LMZ10501 should not be allowed to exceed its maximum operating rating of
125°C. Thermal protection is implemented by an internal thermal shutdown circuit which activates at 150°C (typ).
When this temperature is reached, the device enters a low power standby state. In this state switching remains
off causing the output voltage to fall. Also, the VCON capacitor is discharged to SGND. When the junction
temperature falls back below 130 °C (typ) normal startup occurs and VOUT rises smoothly from 0V. Applications
requiring maximum output current may require derating at elevated ambient temperature. See the Typical
Performance Characteristics section for thermal derating plots for various output voltages.
Application Information
VREF
EN
RT
VCON
VIN
CIN
10 PF
CVC
RB
FB
PGND
SGND
FB
VOUT
COUT
10 PF
Figure 38. Typical Application Circuit
SETTING THE OUTPUT VOLTAGE
The LMZ10501 provides a fixed 2.35V VREF voltage output. As shown in Figure 38 above, a resistive divider
formed by RT and RB sets the VCON pin voltage level. The VOUT voltage tracks VCON and is governed by the
following relationship:
VOUT = GAIN x VCON
where
•
GAIN is 2.5V/V from VCON to VFB.
(1)
This equation is valid for output voltages between 0.6V and 3.6V and corresponds to VCON voltage between
0.24V and 1.44V, respectively.
RT and RB Selection for Fixed VOUT
The parameters affecting the output voltage setting are the RT, RB, and the product of the VREF voltage x GAIN.
The VREF voltage is typically 2.35V. Since VCON is derived from VREF via RT and RB,
VCON = VREF x RB/ (RB + RT)
(2)
After substitution,
VOUT = VREF x GAIN x RB/ (RB + RT)
RT = ( GAIN x VREF / VOUT – 1 ) x RB
(3)
(4)
The ideal product of GAIN x VREF = 5.875V.
Choose RT to be between 80kΩ and 300kΩ. Then, RB can be calculated using Equation 5 below.
RB = ( VOUT / (5.875V – VOUT) ) x RT
(5)
Note that the resistance of RT should be ≥ 80kΩ. This ensures that the VREF output current loading is not
exceeded and the reference voltage is maintained. The current loading on VREF should not be greater than 30
µA.
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OUTPUT VOLTAGE ACCURACY OPTIMIZATION
Each nano module is optimized to achieve high VOUT accuracy. Equation 1 shows that, by design, the output
voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from
VREF. Therefore, as shown in Equation 3, the accuracy of the output voltage is a function of the VREF x GAIN
product as well as the tolerance of the RT and RB resistors. The typical VREF x GAIN product by design is 5.875V.
Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875V value as
possible, achieving high VOUT accuracy. See the Electrical Specifications section for the VREF x GAIN product
tolerance limits.
DYNAMIC OUTPUT VOLTAGE SCALING
The VCON pin on the LMZ10501 can be driven externally by a DAC to scale the output voltage dynamically. The
output voltage VOUT = 2.5V/V x VCON. When driving VCON with a source different than VREF place a 1.5kΩ resistor
in series with the VCON pin. Current limiting the external VCON helps to protect this pin and allows the VCON
capacitor to be fully discharged to 0V after fault conditions.
INTEGRATED INDUCTOR
The LMZ10501 uses a Low Temperature Co-fired Ceramic (LTCC) type 2.6 µH inductor with over 1.2A DC
current rating and soft saturation profile for up to 2A. This inductor allows for the 1.425mm maximum package
height providing an easy to use, compact solution with reduced EMI.
INPUT AND OUTPUT CAPACITOR SELECTION
The LMZ10501 is designed for use with low ESR multi-layer ceramic capacitors (MLCC) for its input and output
filters. Using a 10 µF 0603 or 0805 with 6.3V or 10V rating ceramic input capacitor typically provides sufficient
VIN bypass. Use of multiple 4.7 µF or 2.2µF capacitors can also be considered. Ceramic capacitors with X5R and
X7R temperature characteristics are recommended for both input and output filters. These provide an optimal
balance between small size, cost, reliability, and performance for space sensitive applications.
The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating
and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC
voltage bias applied across its terminals. For example, a typical 0805 case size X5R 6.3V 10 µF ceramic
capacitor may only have 4.8 µF left in it when a 5.0V DC bias is applied. Similarly, a typical 0603 case size X5R
6.3V 10 µF ceramic capacitor may only have 2.4 µF at the same 5.0V DC. Smaller case size capacitors may
have even larger percentage drop in value with DC bias.
The optimum output capacitance value is application dependent. Too small output capacitance can lead to
instability due to lower loop phase margin. On the other hand, if the output capacitor is too large, it may prevent
the output voltage from reaching the 0.375V required voltage level at the end of the startup sequence. In such
cases, the output short circuit protection can be engaged and the nano module will enter a hiccup mode as
described in the OUTPUT SHORT CIRCUIT PROTECTION section. Table 1 sets the minimum output
capacitance for stability and maximum output capacitance for proper startup for various output voltage settings.
Note that the maximum COUT value in Table 1 assumes that the filter capacitance on VCON is the maximum
recommended value of 1nF and the RT resistor value is less than 300kΩ. Lower VCON capacitance can extend
the maximum COUT range. There is no great performance benefit in using excessive COUT values.
Table 1. Output Capacitance Range
16
Output Voltage
Minimum
COUT
Suggested
COUT
Maximum
COUT
0.6V
4.7µF
10µF
47µF
1.0V
3.3µF
10µF
47µF
1.2V
3.3µF
10µF
47µF
1.8V
3.3µF
10µF
68µF
2.5V
3.3µF
10µF
100µF
3.3V
3.3µF
10µF
100µF
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Use of multiple 4.7 µF or 2.2µF output capacitors can be considered for reduced effective ESR and smaller
output voltage ripple. In addition to the main output capacitor, small 0.1µF – 0.01µF parallel capacitors can be
used to reduce high frequency noise.
PACKAGE CONSIDERATIONS
The nano module package includes an LTCC inductor on the bottom and a micro SMD die mounted on top. The
die has exposed edges and can be sensitive to ambient light. For applications with direct high intensity ambient
red, infrared, LED, or natural light it is recommended to have the device shielded from the light source to avoid
abnormal behavior.
Since the die is exposed on top of the package, care should be taken when picking and placing the module on
the board.
Use the following recommendations when utilizing machine placement:
• Use 1.06mm (42mil) or smaller nozzle size so that the nozzle head does not touch the outer area of the
exposed die.
• Use a soft tip pick and place head.
• Add 0.05mm to the component thickness so that the device will be released 0.05mm (2mil) into the solder
paste without putting pressure or splashing the solder paste.
• Slow the pick arm when picking the part from the tape and reel carrier and when depositing the IC on the
board.
• If the machine releases the component by force, use minimum force or no more than 3 Newtons.
• For PCBs with surface mount components on both sides, it is suggested to put the LMZ10501 on the top
side. In case the application requires bottom side placement, a reflow fixture may be required to protect the
module during the second reflow.
For manual placement:
• Use a vacuum pick up hand tool with soft tip head.
• If vacuum pick up tool is not available, use non-metal tweezers and hold the part by the inductor body side
terminals rather than the micro SMD die on top.
• Use minimal force when picking and placing the module on the board.
• In case a heat gun is required for rework, make sure that the heat source is pointing at the interface between
the inductor and the PCB. Do not apply heat gun directly on top of the component since it may affect the
solder joint between the micro SMD and the inductor. Using hot air station provides better temperature control
and better controlled air flow than a heat gun.
• Go to the video section at www.ti.com/product/lmz10501 for a quick video on how to solder rework the
LMZ10501.
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Board Layout Considerations
RB
RESISTOR
RT
RESISTOR
HIGH di/dt LOOP
KEEP IT SMALL
EN
VREF
VCON
VIN
FB
PGND
SGND
VOUT
VIN
PGND
INPUT
CAPACITOR
VOUT
FEEDBACK
TRACE
SGND CONNECTION TO
QUIET PGND PLANE
OUTPUT
CAPACITOR
VCON
CAPACITOR
Figure 39. Example Top Layer Board Layout
The board layout of any DC-DC switching converter is critical for the optimal performance of the design. Bad
PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still
converts the voltage properly, the board layout can mean the difference between passing or failing EMI
regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground
terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a
path for the high di/dt switching current during each switching period. This loop should always be kept as short
as possible when laying out a board for any Buck converter.
The LMZ10501 integrates the inductor and simplifies the DC-DC converter board layout. Refer to the example
layout in Figure 39. There are a few basic requirements to achieve a good LMZ10501 layout.
1. Place the input capacitor CIN as close as possible to the VIN and PGND terminals. VIN (pin 7) and PGND
(pin 6) on the LMZ10501 are next to each other which makes the input capacitor placement simple.
2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and
SGND terminals.The CVC capacitor (not RB) should be the component closer to the VCON pin, as shown in
Figure 39. This allows for better bypass of the control voltage set at VCON.
3. Run the feedback trace (from VOUT to FB) away from noise sources.
4. Connect SGND to a quiet GND plane.
5. Provide enough PCB area for proper heatsinking. Refer to the Electrical Characteristics table for example
θJA values for different board areas. Also, refer to AN-2020 for additional thermal design hints.
Refer to the evaluation board application note AN-2166 for a complete board layout example.
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
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PACKAGE OPTION ADDENDUM
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24-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMZ10501SH/NOPB
LIFEBUY
POS
NQB
8
1000
TBD
Call TI
Call TI
-40 to 85
SP
LMZ10501SHE/NOPB
LIFEBUY
POS
NQB
8
250
TBD
Call TI
Call TI
-40 to 85
SP
LMZ10501SHX/NOPB
LIFEBUY
POS
NQB
8
3000
TBD
Call TI
Call TI
-40 to 85
SP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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