Intersil ISL78420 100v, 2a peak, half-bridge driver with tri-level pwm input and adjustable dead-time Datasheet

100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM
Input and Adjustable Dead-Time
ISL78420
Features
The ISL78420 is a 100V, high frequency, half-bridge MOSFET
driver with a tri-level PWM input. This part is a derivative of the
HIP2121 half-bridge driver. The non-automotive version of the
ISL78420 is the HIP2124.
• Programmable break-before-make dead-time prevents
shoot-through and is adjustable up to 220ns
This driver is designed to work in conjunction with the ISL78220,
“6-Phase Interleaved Boost PWM Controller with Light Load
Efficiency Enhancement”. Equally, it can be used in most
applications where a half-bridge driver is used.
• Supply undervoltage protection
This driver has a programmable dead-time to ensure
break-before-make operation between the high-side and low-side
drivers. A resistor is used to adjust the dead-time up to 220ns.
The tri-level input allows the PWM input to also function as a
disable input. When the PWM input is a logic high, the high-side
bridge FET is turned on and the low-side FET is off. When the
input is a logic low, the low-side bridge FET is turned on and the
high-side FET is turned off. When the input voltage is midrange,
both the high and low-side bridge FETs are turned off.
The enable pin (EN), when low, drives both outputs to a low state.
This input is used when the controller does not utilize a tri-state
output. All logic inputs are VDD tolerant.
Two package options are provided. The 10 Ld 4x4 DFN package
has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
• Bootstrap supply maximum voltage to 114VDC
• Wide supply voltage range (8V to 14V)
• On-chip 1Ω bootstrap diode
• Unique tri-level PWM input logic enables phase shedding when
using multi-phase PWM controllers (e.g. ISL78220/225)
• 9 Ld TDFN “B” package compliant with 100V conductor
spacing guidelines per IPC-2221
• AEC-Q100 Qualified
Applications
• Automotive applications
• Multi-phase boost (ISL78220/225)
• Half-bridge DC/DC converter
• Class-D amplifiers
• Forward converter with active clamp
Related Literature
• FN7668 HIP2120, HIP2121 “100V, 2A Peak, High Frequency
Half-Bridge Drivers with Adjustable Dead Time Control and
PWM Input”
• FN8363 HIP2124, “100V, 2A Peak, Half Bridge Driver with
Tri-level Input and Adjustable Dead Time” (non-automotive)
• FN7688 ISL78220, “6-Phase Interleaved Boost PWM
Controller with Light Load Efficiency Enhancement”
• FN7909 ISL78225, “4-Phase Interleaved Boost PWM
Controller with Light Load Efficiency Enhancement”
100V MAX
ISL78420
VDD
HB
PWM
HO
EN
PWM
CONTROLLER
SECONDARY
CIRCUITS
HS
RDT
VSS
LO
EPAD
FEEDBACK
WITH
ISOLATION
DEAD-TIME (ns)
HALF BRIDGE
200
160
140
120
100
80
60
40
20
8
16
24
32
40
48 56 64
80
RDT (kΩ)
FIGURE 1. TYPICAL APPLICATION
September 24, 2012
FN8296.1
1
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78420
Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL
SHIFT
HS
100K
5V
DELAY
-
PWM
100K
+
UNDER
VOLTAGE
+
LO
DELAY
5V
210k
VSS
EN
ISL78420
RDT
EPAD
Pin Configurations
Pin Descriptions
ISL78420ARTAZ
(10 LD 4X4 TDFN)
TOP VIEW
10 9
LD LD SYMBOL
VDD
1
10
LO
HB
2
9
VSS
HO
3
8
PWM
HS
4
7
EN
NC
5
6
RDT
EPAD
ISL78420ARTBZ
(9 LD 4X4 TDFN)
TOP VIEW
VDD
1
EPAD
10
LO
9
VSS
8
PWM
HB
3
HO
4
7
EN
HS
5
6
RDT
2
DESCRIPTION
1
1
VDD
Positive supply voltage for lower gate driver.
Decouple this pin to ground with a 4.7µF or larger
ceramic capacitor to VSS
2
3
HB
High-side bootstrap supply voltage referenced to
HS. Connect bootstrap capacitor to this pin and HS.
3
4
HO
High-side output connected to gate of high-side FET.
4
5
HS
High-side source connect to source of high-side FET.
Connect bootstrap capacitor to this pin and HB.
8
8
PWM
7
7
EN
Output enable, when low, HO = LO = 0
9
PWM input. For PWM = 5V, HO = 1, LO = 0. For
PWM = 0V, HO = 0, LO = 1. For PWM = 2.5V,
HO = LO = 0.
9
VSS
Negative voltage supply, Connected to ground.
10 10
LO
Low-side output. Connect to gate of low-side FET.
5
-
NC
No Connect. This pin is isolated from all other pins.
May optionally be connected to VSS. Note that on
the 9 Ld package, there is no pin present at the
location normally occupied by pin 2.
6
6
RDT
A resistor connected between this pin and VSS adds
dead time by adding delay time to the falling and
rising edges of the PWM input.
-
-
EPAD
The epad is electrically isolated. It is recommended
that the epad be connected to the VSS plane for
heat removal.
FN8296.1
September 24, 2012
ISL78420
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
INPUT
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL78420ARTAZ
78420 AZ
5V Tri-level
-40 +125
10 Ld 4x4 TDFN
L10.4x4
ISL78420ARTBZ (Note 4)
78420 BZ
5V Tri-level
-40 +125
9 Ld 4x4 TDFN
L9.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78420. For more information on MSL please see tech brief TB363.
and TB477.
4. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing between pins 1 and 3.
3
FN8296.1
September 24, 2012
ISL78420
Absolute Maximum Ratings (Note 6)
Thermal Information
Supply Voltage, VDD, VHB - VHS (Notes 5) . . . . . . . . . . . . . . . . . -0.3V to 18V
PWM and EN Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on HO . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .
42
4
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .
42
4
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile (*) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB487
*Peak temperature during solder reflow . . . . . . . . . . . . . . +235°C max
Maximum Recommended Operating
Conditions (Note 6)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The ISL78420 is capable of derated operation at supply voltages exceeding 14V. Figure 17 shows the high-side voltage derating curve for this mode
of operation.
6. All voltages referenced to VSS unless otherwise specified.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
TA = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 9)
MAX
(Note 9)
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
VDD Operating Current
IDD8k
RDT = 8k
-
650
950
-
1000
µA
IDD80k
RDT = 80k
-
1.0
2.1
-
2.2
mA
IDDO8k
f = 500kHz, RDT = 8k
-
2.5
3
-
3
mA
IDDO80k
f = 500kHz, RDT = 80k
-
3.4
4
-
4
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
65
115
-
150
µA
Total HB Operating Current
IHBO
f = 500kHz
-
2.0
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
LI = HI = 0V; VHB = VHS = 114V
-
0.05
1.5
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz; VHB = VHS = 114V
-
1.2
1.5
-
1.6
mA
Tri-Level PWM Input
High Level Threshold
VPWMH
-
3.6
4.0
-
4.3
V
High Middle Level Threshold
VMIDH
3.0
3.4
-
2.9
-
V
Low Middle Level Threshold
VMIDL
-
1.6
2.1
-
2.2
V
Low Level Threshold
VPWML
0.8
1.1
-
0.7
-
V
Rmid
-
160
-
-
-
kΩ
PWM Mid level Pull-up Resistors
4
FN8296.1
September 24, 2012
ISL78420
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
TA = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 9)
MAX
(Note 9)
UNITS
EN Input
Low Level Input Threshold
VENL
1.4
1.8
-
1.2
-
V
High Level Input Threshold
VENH
-
1.8
2.2
-
2.4
V
EN Pull-up Resistance
Rpu
-
210
-
100
320
kΩ
VDD Rising Threshold
VDDR
6.8
7.3
7.8
6.5
8.1
V
VDD Threshold Hysteresis
VDDH
-
0.6
-
-
-
V
HB Rising Threshold
VHBR
6.2
6.9
7.5
5.9
7.8
V
HB Threshold Hysteresis
VHBH
-
0.6
-
-
-
V
UNDERVOLTAGE PROTECTION
BOOTSTRAP DIODE
Low Current Forward Voltage
VDL
IVDD-HB = 100mA
-
0.6
0.7
-
0.8
V
High Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.9
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5
Ω
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.4
-
0.5
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD - VLO
-
0.25
0.4
-
0.5
V
Peak Pull-Up Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.4
-
0.5
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB - VHO
-
0.25
0.4
-
0.5
V
Peak Pull-Up Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pull-Down Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C.
TJ = +25°C
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C to +125°C
MIN
TYPE
MAX
MIN
(Note 9)
MAX
(Note 9)
UNITS
HO Turn-Off Propagation Delay
PWM Falling to HO Falling
tPLHO
-
32
50
-
60
ns
LO Turn-Off Propagation Delay
PWM Rising to LO Falling
tPLLO
-
32
50
-
60
ns
Minimum Dead-Time Delay (Note 10)
HO Falling to LO Rising
tDTHLmin
RDT = 80k,
PWM 1 to 0
15
35
50
10
60
ns
Minimum Dead-Time Delay (Note 10)
LO Falling to HO Rising
tDTLHmin
RDT = 80k
PWM 0 to 1
15
25
50
10
60
ns
Maximum Dead-Time Delay (Note 10)
HO Falling to LO Rising
tDTHLmax
RDT = 8k,
PWM 1 to 0
150
220
300
-
-
ns
5
FN8296.1
September 24, 2012
ISL78420
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
PARAMETERS
Maximum Dead-Time Delay (Note 10)
LO Falling to HO Rising
SYMBOL
tDTLHmax
tRC,tFC
Either Output Rise/Fall Time
(10% to 90%/90% to 10%)
Bootstrap Diode Turn-On or Turn-Off Time
TEST
CONDITIONS
RDT = 8k,
PWM 0 to 1
CL = 1nF
tBS
TJ = -40°C to +125°C
MIN
TYPE
MAX
MIN
(Note 9)
MAX
(Note 9)
UNITS
150
220
300
-
-
ns
-
10
-
-
-
ns
-
10
-
-
-
ns
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising.
Timing Diagram
t PLLO
V PW M H
V M IDL
t PHHO
V M IDH
V PW M L
PWM
R ise and fall transitions of the P W M inputs are
exaggerated to clearly illustrate the low, m id, and high
threshold levels.
PWM
HO
HO
LO
LO
t DTLH
t DTHL
EN
EN
6
FN8296.1
September 24, 2012
ISL78420
Typical Performance Curves
10.0
10.0
T = -40°C
IDDO (mA)
IDDO (mA)
T = -40°C
T = +25°C
1.0
T = +25°C
1.0
T = +125°C
T = +150°C
T = +125°C
T = +150°C
0.1
10k
0.1
100k
1M
10k
100k
FIGURE 3. IDD OPERATING CURRENT vs FREQUENCY, RDT = 8K
FIGURE 4. IDD OPERATING CURRENT vs FREQUENCY, RDT = 80k
10.0
10.0
T = +150°C
1.0
IHBSO (mA)
IHBO (mA)
T = -40°C
T = +25°C
T = +150°C
0.1
T = +125°C
0.01
10k
100k
1.0
T = -40°C
T = +25°C
0.1
0.01
10k
1M
T = +125°C
100k
FREQUENCY (Hz)
1M
FREQUENCY (Hz)
FIGURE 5. IHB OPERATING CURRENT vs FREQUENCY, RDT = 8k
FIGURE 6. IHBS OPERATING CURRENT vs FREQUENCY RDT = 80k
300
200
VOLL, VOLH (mV)
VDD = VHB = 14V
250
VOHL, VOHH (mV)
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
200
150
VDD = VHB = 8V
100
VDD = VHB = 14V
150
100
VDD = VHB = 8V
VDD = VHB = 12V
VDD = VHB = 12V
50
50
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
7
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FN8296.1
September 24, 2012
ISL78420
Typical Performance Curves
(Continued)
6.7
0.70
6.5
0.65
VDDR
VDDH, VHBH (V)
VDDR, VHBR (V)
6.3
6.1
VHBR
5.9
5.7
VHBH
0.60
0.55
0.50
0.45
5.5
VDDH
0.40
5.3
-50
0
50
100
-50
150
0
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
150
55
tLPLH, tLPHL, tHPLH, tHPHL (ns)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
100
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
55
50
tLPLH
45
40
tHPLH
35
tLPHL
30
tHPHL
25
-50
0
50
100
50
tLPLH
45
40
tHPLH
tLPHL
35
30
tHPHL
25
-50
150
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. DELAY MATCHING vs TEMPERATURE
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
3.5
4.5
3.0
4.0
3.5
IOHL, IOHH (A)
2.5
IOHL, IOHH (A)
50
TEMPERATURE (°C)
TEMPERATURE (°C)
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0
0
2
4
6
8
VLO, VHO (V)
10
12
FIGURE 13. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
8
0
0
2
4
6
VLO, VHO (V)
8
10
12
FIGURE 14. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
FN8296.1
September 24, 2012
ISL78420
120
110
100
90
80
70
60
50
40
30
20
10
0
(Continued)
1.00
IDD
FORWARD CURRENT (A)
IDD, IHB (µA)
Typical Performance Curves
IHB
0.10
0.01
1.10-3
1.10-4
1.10-5
1.10-6
0
5
10
VDD, VHB (V)
15
20
0.3
0.4
0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
FIGURE 16. BOOTSTRAP DIODE I-V CHARACTERISTICS
VDD TO VSS VOLTAGE (V)
120
100
80
60
40
20
0
12
13
14
15
16
VHS TO VSS VOLTAGE (V)
FIGURE 17. VHS VOLTAGE vs VDD VOLTAGE
Functional Description
Functional Overview
When connected to a half bridge, the output of the bridge on the
HS node follows the PWM input. In other words, when the PWM
input is high, the high-side bridge FET is turned on and the
low-side FET is off. When the PWM input is low, the low-side
bridge FET is turned on and the high-side is turned off. The
enable pin (EN), when low, drives both outputs to a low state.
A unique feature of the ISL78420 is the tri-level logic of the PWM
input. The logic thresholds of the PWM input is divided into 3
levels. A logic low ensures that the output of the low-side bridge
FET is on and the high-side FET is off. A logic high ensures that
the high-side bridge FET is on and the low-side FET is off. When
the logic input is midrange (2.5V), both the high and low side
FETs are off. This driver is designed to work in conjunction with
the ISL78220, “6-Phase Interleaved Boost PWM Controller with
Light Load Efficiency Enhancement”.
When the PWM input transitions high or low, it is necessary to
ensure that both bridge FETS are not on at the same time to
prevent shoot-through currents (break before make). The internal
programmable timers delay the rising edge of either output
resulting with both outputs being off before either of the bridge
FETs are driven on. An 8kΩ resistor connected between RDT and
9
VSS results in a nominal dead time of 220ns. An 80kΩ results
with a minimum nominal dead time of 25ns. Resistors values
less than 8k and greater than 80k are not recommended.
While the voltage of the input signal to the PWM is within the
boundaries of the mid-level logic, the outputs are in a dead time
state because both outputs are off. The actual delay time, as
programed by the RDT value, begins when the high or low logic
levels are transitioned. The period while the input logic in the
mid-level range, is consequently added to the programmed dead
time period. This may be a consideration when selecting the RDT
value.
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to VDD.
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
boot capacitor, the boot voltage will charge very close to VDD
(less the boot diode drop and the on-voltage of the low-side
bridge FET).
When the PWM input transitions high, the high-side bridge FET is
driven on after the dead time. Because the HS node is connected
FN8296.1
September 24, 2012
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is VDD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is approximately 20x
the gate charge of the driven power FET for a 5% drop in voltage
after the charge has been transferred from the boot capacitor to
the gate capacitance.
VGS, GATE-TO-SOURCE VOLTAGE (V)
ISL78420
12
ID = 33A
VDS = 80V
10
VDS = 50V
8
VDS = 20V
6
4
2
0
0
10
20
30
40
50
60
70
80
QG TOTAL GATE CHARGE (nC)
FIGURE 18. TYPICAL GATE CHARGE OF A POWER FET
The following equations calculate the total charge required for
the Period. These equations assume that all of the parameters
are constant during the period duration. The error is insignificant
if the ripple is small.
Q C = Q gate80V + Period × I HB + V HO ⁄ ( R GS + I gate_leak )
(EQ. 1)
C boot = Q C ⁄ ( Ripple∗ VDD )
(EQ. 2)
C boot = 0.52μF
If the gate to source resistor is removed (RGS is usually not
needed or recommended), then:
Cboot = 0.33µF
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
VDD = 10V
VDD can be any value between 7 and 14VDC
VHB = VDD - 0.6V = VHO High side driver bias voltage (VDD - boot diode
voltage) referenced to VHS
Period = 1ms
This is the longest expected switching period
IHB = 100µA
Worst case high side driver current when
xHO = high (this value is specified for VDD =
12V but the error is not significant)
RGS = 100kΩ
Gate-source resistor (usually not needed)
Ripple= 5%
Desired ripple voltage on the boot cap (larger
ripple is not recommended)
Igate_leak = 100nA
From the FET vendor’s datasheet
Qgate80V = 64nC
From Figure 18
10
FN8296.1
September 24, 2012
ISL78420
8V TO 15V
VDD
HI
DRIVER
PWM
PWM
CONTROLLER
EN
LOGIC
PWM*
HB
100V MAX
HO
HS
LO
DRIVER
RDT
LO
VSS
ISL78420
FIGURE 19. TYPICAL ACTIVE CLAMP FORWARD APPLICATION
Typical Application Circuit
Figure 19 is an example of how the ISL78420 can be configured
for an active clamp forward power supply application. Note that
the PWM signal from the controller must be inverted for this
active clamp forward topology.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high-side FETs
are not usually required if low-side gate-source resistors are
used. If relatively low value gate-source resistors are used on the
high-side FETs, be aware that a larger value for the boot capacitor
may be required.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high-side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
When the high-side bridge FET turns off (see Figure 20), because
of the inductive characteristics the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low-side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
L is the total parasitic inductance of the low-side FET
drain-source path and di/dt is the rate at which the high-side FET
is turned off. With the increasing power levels of power supplies
and motors, clamping this transient become more and more
significant for the proper operation of the ISL78420.
11
HB
HO
HS
IN D U C T IV E
LO AD
+
LO
VSS
+
FIGURE 20. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 20
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low-side FET, a
small value resistor is necessary to limit current when the body
diode of the low-side bridge FET is conducting during the dead
time. The resistor in series with HS, can be used instead of the
gate resistor of the high-side FET.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
FN8296.1
September 24, 2012
ISL78420
Power Dissipation
PC Board Layout
The dissipation of the ISL78420 is dominated by the gate charge
required by the driven bridge FETs and the switching frequency.
The internal bias and boot diode also contribute to the total
dissipation but these losses are usually insignificant compared to
the gate charge losses.
The AC performance of the ISL78420 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the ISL78420:
The calculation of the power dissipation of the ISL78420 is very
simple.
GATE POWER (FOR THE HO AND LO OUTPUTS)
P gate = 4 × Q gate × Freq × VDD
• Keep power loops as short as possible by paralleling the
source and return traces.
(EQ. 3)
where
• Use planes where practical; they’re usually more effective than
parallel traces.
• Planes can also be non-grounded nodes.
Qgate is the charge of the driven bridge FET at VDD, and
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
Freq is the switching frequency.
BOOT DIODE DISSIPATION
I diode_avg = Q gate × Freq
(EQ. 4)
P diode = I diode_avg × 0.6V
(EQ. 5)
where 0.6V is the diode conduction voltage
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
BIAS CURRENT
P bias = I bias × VDD
• Understand well how power currents flow. The high amplitude
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
(EQ. 6)
where Ibias is the internal bias current of the ISL78420 at the
switching frequency
TOTAL POWER DISSIPATION
Ptotal = Pgate + Pdiode + Pbias
OPERATING TEMPERATURES
Tj = Ptotal x θJA + Tamb
where Tj is the junction temperature at the operating air
temperature, Tamb, in the vicinity of the part.
Tj = Ptotal x θJC + TPCB
where Tj is the junction temperature with the operating
temperature of the PCB, TPCB, as measured where the EPAD is
soldered.
• The use of low inductance components such as chip resistors
and chip capacitors is recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. In PCB designs with long leads on the LO and
HO outputs, it may be necessary to add series gate resistors on
the bridge FETs to dampen the oscillations.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components.
12
FN8296.1
September 24, 2012
ISL78420
EPAD Design Considerations
The thermal pad of the ISL78420 is electrically isolated. It’s
primary function is to provide heat sinking for the IC. It is
recommended to tie the EPAD to VSS (GND).
Figure 21 is an example of how to use vias to remove heat from
the IC substrate. Depending on the amount of power dissipated by
the ISL78420, it may be necessary, to connect the EPAD to one or
more ground plane layers. A via array, within the area of the EPAD,
will conduct heat from the EPAD to the ground plane on the bottom
layer. If inner PCB layers are available, it is also be desirable to
connect these additional layers with the plated-through vias.
The number of vias and the size of the GND planes required for
adequate heatsinking is determined by the power dissipated by
the ISL78420, the air flow, and the maximum temperature of the
air around the IC.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias.
VDD
EPAD GND
PLANE
LO
HB
VSS
HO
PWM
HS
NC
EN
COMPONENT
LAYER
VDD
This plane is
connected to
HS and is under
all high side
driver circuits
RDT
EPAD GND
PLANE
HB
HB
HO
HO
HS
HS
NC
LS
BOTTOM
LAYER
FIGURE 21. RECOMENDED PCB HEATSINK
13
FN8296.1
September 24, 2012
ISL78420
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
September 24, 2012
FN8296.1
CHANGE
Initial Release
Products
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14
FN8296.1
September 24, 2012
ISL78420
Package Outline Drawing
L9.4x4
9 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/10
3.2 REF
4.00
A
PIN #1 INDEX AREA
6X 0.80 BSC
6
B
4
1
9X 0 . 40 ± 0.100
6
PIN 1
INDEX AREA
4.00
2.20
1.2 REF
0.15
(4X)
9
5
0.10 M C A B
0.05 M C
4 9 X 0.30
TOP VIEW
3.00
BOTTOM VIEW
(3.00)
SEE DETAIL "X"
0 .75
(9 X 0.60)
0.10 C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(3.80)
C
(2.20)
(1.2)
4
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
(9X 0.30)
(6X 0.8)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. E-Pad is offset from center.
5. Tiebar (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
15
FN8296.1
September 24, 2012
ISL78420
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08
3.2 REF
4.00
A
PIN #1 INDEX AREA
8X 0.80 BSC
6
B
5
1
10X 0 . 40
6
PIN 1
INDEX AREA
4.00
2.60
0.15
(4X)
10
6
0.10 M C A B
0.05 M C
4 10 X 0.30
TOP VIEW
3.00
BOTTOM VIEW
( 3.00 )
SEE DETAIL "X"
0 .75
( 10 X 0.60 )
0.10 C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 3.80)
C
( 2.60)
0 . 2 REF
C
( 8X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
( 10X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN8296.1
September 24, 2012