Infineon HYS64T128020HU 240-pin unbuffered ddr2 sdram module Datasheet

D a t a S h e e t , Rev. 0.87, J u n e 2 0 0 4
HYS64T32000[G/H]U–[3.7/5]–A
HYS[64/72]T64000[G/H]U–[3.7/5]–A
HYS[64/72]T128020[G/H]U–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
The information in this document is subject to change without notice.
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , Rev. 0.87, J u n e 2 0 0 4
HYS64T32000[G/H]U–[3.7/5]–A
HYS[64/72]T64000[G/H]U–[3.7/5]–A
HYS[64/72]T128020[G/H]U–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
Revision History:
Rev. 0.87
2004-06
Previous Revision:
Rev. 0.84
2003-09
Page
Subjects (major changes since last revision)
all
New template
chapter 5
add currents
all
updated timings
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Template: mp_a4_v2.3_2004-01-14.fm
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Table of Contents
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
9
2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
3.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
4.1
4.2
IDD Specifications and Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
27
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
5.1
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Timing Parameter by Speed Grade (Component level data, for reference only) . . . . . . . . . . . . . 28
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
7.1
7.2
7.3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
62
62
63
64
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
1
Overview
This chapter gives an overview of the 1.8 V 240-pin Unbuffered DDR2 SDRAM Modules, 256 MByte, 512 MByte
& 1 GByte ECC and non-ECC Modules and describes its main characteristics.
1.1
•
•
•
•
Features
•
240-pin ECC and Non-ECC Unbuffered 8-Byte
Dual-In-Line DDR2 SDRAM Module for PC,
Workstation and Server main memory applications
One rank 32M x 64, 64M x 64, 64M x 72 and two
ranks 128M × 64 and 128M x 72 organization
JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
256 ,512 MByte and 1GByte modules built with
512Mb DDR2 SDRAMs in 60-ball (P–TFBGA–60)
and 84-ball FBGA (P–TFBGA–84) chipsize
packages
Table 1
•
•
•
•
•
•
Programmable CAS Latencies (3, 4 & 5), Burst
Length (8 & 4) and Burst Type
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_1.8 compatible
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
Based on JEDEC standard reference card layouts
Raw Card “A”, “B” & “C”
Performance
Speed Grade Indicator
–5
–-3.7
Unit
Component Speed Grade
DDR2–400
DDR2–533
—
Module Speed Grade
PC2–3200
PC2–4200
—
Max. Clock Frequency @ CL = 3
200
200
MHz
Max. Clock Frequency @ CL = 4 & 5
200
266
MHz
1.2
Description
The memory array is designed with 512Mb Double
Data Rate (DDR2) Synchronous DRAMs for ECC and
Non-ECC applications. Decoupling capacitors are
mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E2PROM device
using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
The INFINEON HYS[64/72]Txxxx0[G/H]U module
family are low profile Unbuffered DIMM modules with
30,0 mm height based on DDR2 technology. DIMMs
are available as non-ECC modules in 32M x 64
(256MB), 64M x 64 (512MB) and 128M x 64 (1024MB)
and as ECC-modules in 64M x 72 (512MB) and 128M
x 72 (1024MB) organisation and density, intended for
mounting into 240 pin connector sockets.
Data Sheet
6
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
HYS64T32000GU–5–A
256MB 1R×16 PC2–3200U–333–11–C0
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000GU–5–A
512MB 1R×8 PC2–3200U–333–11–A0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000GU–5–A
512MB 1R×8 PC2–3200E–333–11–A0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020GU–5–A
1GB 2R×8 PC2–3200U–333–11–B0
2 Ranks, Non-ECC
512 Mbit (×8
HYS72T128020GU–5–A
1GB 2R×8 PC2–3200E–333–11–B0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–5–A
256MB 1R×16 PC2–3200U–333–11–C0
1 rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–5–A
512MB 1R×8 PC2–3200U–333–11–A0
1 rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–5–A
512MB 1R×8 PC2–3200E–333–11–A0
1 rank, ECC
512 Mbit (×8)
HYS64T128020HU–5–A
1GB 2R×8 PC2–3200U–333–11–B0
2 ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–5–A
1GB 2R×8 PC2–3200E–333–11–B0
2 ranks, ECC
512 Mbit (×8)
HYS64T32000GU–3.7–A
256MB 1R×16 PC2–4200U–444–11–C0
1 rank, Non-ECC
512 Mbit (×16)
HYS64T64000GU–3.7–A
512MB 1R×8 PC2–4200U–444–11–A0
1 rank, Non-ECC
512 Mbit (×8)
HYS72T64000GU–3.7–A
512MB 1R×8 PC2–4200E–444–11–A0
1 rank, ECC
512 Mbit (×8)
HYS64T128020GU–3.7–A
1GB 2R×8 PC2–4200U–444–11–B0
2 ranks, Non-ECC
512 Mbit (×8
HYS72T128020GU–3.7–A
1GB 2R×8 PC2–4200E–444–11–B0
2 ranks, ECC
512 Mbit (×8)
HYS64T32000HU–3.7–A
256MB 1R×16 PC2–4200U–444–11–C0
1 rank, Non-ECC
512 Mbit (×16)
HYS72T64000HU–3.7–A
512MB 1R×8 PC2–4200E–444–11–A0
1 rank, ECC
512 Mbit (×8)
HYS64T64000HU–3.7–A
512MB 1R×8 PC2–4200U–444–11–A0
1 rank, Non-ECC
512 Mbit (×8)
HYS64T128020HU–3.7–A
1GB 2R×8 PC2–4200U–444–11–B0
2 ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3.7–A
1GB 2R×8 PC2–4200E–444–11–B0
2 ranks, ECC
512 Mbit (×8)
PC2-3200
PC2–4200
Note:
4200U-44410-C”, where 4200U means Unbuffered
DIMM modules with 4.26 GB/sec Module
Bandwidth and “44410” means CAS latency = 4,
trcd latency = 4 and trp latency = 4 using the latest
JEDEC SPD Revision 1.1 and produced on the
Raw Card “C”.
1. All part numbers end with a place code, designating
the
silicon
die
revision.
Example:
HYS72T64000GU–5-A, indicating Rev. A dice are
used for DDR2 SDRAM components. For all
INFINEON DDR2 module and component
nomenclature see section 8 of this datasheet.
2. The Compliance Code is printed on the module
label and describes the speed grade, f.e. “PC2-
Data Sheet
7
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 3
DIMM
Density
Address Format
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw
Card
256 MB
32M ×64
1
Non-ECC
4
13/2/10
C
512 MB
64M ×64
1
Non-ECC
8
14/2/10
A
512 MB
64M ×72
1
ECC
9
14/2/10
A
1 GB
2 × 64M ×72
2
Non-ECC
16
14/2/10
B
1 GB
2 × 64M ×72
2
ECC
18
14/2/10
B
Table 4
Components on Modules1)
Part Number
DIMM
Density
HYS64T32000GU
HYS64T32000HU
256 MB
2)
HYS64T64000GU
HYS64T64000HU
2)
DRAM components
reference datasheet
DRAM Density
DRAM Organisation
HYB18T512160AC
512 Mbit
32M ×16
512 Mbit
32M ×16
512 Mbit
64Mb ×8
512 Mbit
64Mb ×8
2)
256 MB
HYB18T512160AF
512 MB
HYB18T512800AC
2)
512 MB
HYB18T512800AF
HYS72T64000GU
512 MB
HYB18T512800AC
512 Mbit
64Mb ×8
HYS72T64000HU2)
512 MB
HYB18T512800AF2)
512 Mbit
64Mb ×8
HYS64T128020GU
1 GB
HYB18T1G800AC
512 Mbit
64Mb ×8
HYS64T128020HU
2)
HYS72T128020GU
HYS72T128020HU
2)
1 GB
HYB18T1G800AF
512 Mbit
64Mb ×8
1 GB
HYB18T1G800AC
512 Mbit
64Mb ×8
512 Mbit
64Mb ×8
1 GB
2)
2)
HYB18T1G800AF
1) For a detailed description of all functionalities of the DRAM components on these modules see the referenced component
datasheet.
2) Green Product
Data Sheet
8
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
1.3
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1 for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
Table 5
Pin Configuration of UDIMM
Pin#
Name
Pin Buffer Function
Type Type
185
CK0
I
SSTL
137
CK1
I
SSTL
220
CK2
I
SSTL
186
CK0
I
SSTL
138
CK1
I
SSTL
221
CK2
I
SSTL
52
CKE0
I
SSTL
Clock Enable Rank 0
171
CKE1
I
SSTL
Clock Enable Rank 1
NC
NC
—
Note: 1 Rank module
193
S0
I
SSTL
Chip Select Rank 0
76
S1
I
SSTL
Chip Select Rank 1
Clock Signals
Clock Signals 2:0
Complement Clock Signals 2:0
Note: 2 Ranks module
Control Signals
Note: 2 Ranks module
NC
NC
—
Note: 1 Rank module
192
RAS
I
SSTL
Row Address Strobe
74
CAS
I
SSTL
Column Address Strobe
73
WE
I
SSTL
Write Enable
71
BA0
I
SSTL
Bank Address Bus 1:0
190
BA1
I
SSTL
54
BA2
I
SSTL
NC
NC
—
Note: less than 1Gb DDR2 SDRAMS
188
A0
I
SSTL
Address Bus 12:0
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
Address Signals
Bank Address Bus 2
Note: greater than 512Mb DDR2 SDRAMS
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
Data Sheet
9
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of UDIMM (cont’d)
Pin#
Name
Pin Buffer Function
Type Type
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Bus 12:0
Address Signal 13
Note: 1 Gbit based module and 512M ×4/×8
NC
NC
—
Note:
1. Module based on 1 Gbit ×16
2. Module based on 512 Mbit ×16 or smaller
174
A14
I
SSTL
Address Signal 14
Note: Modules based on 2 Gbit
NC
NC
—
Note: Modules based on 1 Gbit or smaller
3
DQ0
I/O
SSTL
Data Bus 63:0
4
DQ1
I/O
SSTL
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
21
DQ10
I/O
SSTL
Data Signals
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
Data Sheet
10
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of UDIMM (cont’d)
Pin#
Name
Pin Buffer Function
Type Type
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
206
DQ39
I/O
SSTL
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
Data Sheet
11
Data Bus 63:0
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of UDIMM (cont’d)
Pin#
Name
Pin Buffer Function
Type Type
CB0
I/O
Check Bit Signal
42
SSTL
Check Bit 0
Note: ECC type module only
43
NC
NC
—
Note: Non-ECC module
CB1
I/O
SSTL
Check Bit 1
Note: ECC type module only
48
NC
NC
—
Note: Non-ECC module
CB2
I/O
SSTL
Check Bit 2
Note: ECC type module only
49
NC
NC
—
Note: Non-ECC module
CB3
I/O
SSTL
Check Bit 3
Note: ECC type module only
161
NC
NC
—
Note: Non-ECC module
CB4
I/O
SSTL
Check Bit 4
Note: ECC type module only
162
NC
NC
—
Note: Non-ECC module
CB5
I/O
SSTL
Check Bit 5
Note: ECC type module only
167
NC
NC
—
Note: Non-ECC module
CB6
I/O
SSTL
Check Bit 6
Note: ECC type module only
168
NC
NC
—
Note: Non-ECC module
CB7
I/O
SSTL
Check Bit 7
Note: ECC type module only
NC
NC
—
Note: Non-ECC module
7
DQS0
I/O
SSTL
Data Strobe Bus 8:0
16
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
Note: See block diagram for corresponding DQ
signals
37
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
45
DQS8
I/O
SSTL
6
DQS0
I/O
SSTL
Complement Data Strobe Bus 8:0
15
DQS1
I/O
SSTL
27
DQS2
I/O
SSTL
Note: See block diagram for corresponding DQ
signals
36
DQS3
I/O
SSTL
83
DQS4
I/O
SSTL
Data Strobe Bus
Data Sheet
12
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of UDIMM (cont’d)
Pin#
Name
Pin Buffer Function
Type Type
92
DQS5
I/O
SSTL
104
DQS6
I/O
SSTL
113
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
125
DM0
I
SSTL
134
DM1
I
SSTL
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
120
SCL
I
CMOS Serial Bus Clock
119
SDA
I/O
OD
239
SA0
I
CMOS Slave Address Select Bus 2:0
240
SA1
I
CMOS
101
SA2
I
CMOS
Complement Data Strobe Bus 8:0
Data Mask Signals
Data Mask Bus 8:0
EEPROM
Serial Bus Data
Power Supplies
VREF
AI
—
238
VDDSPD PWR —
51,56,62,72,75,78,170,175,181, VDDQ
PWR —
1
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
191,194
53,59,64,67,69,172,178,184,187 VDD
189,197
PWR —
Power Supply
VSS
GND —
Ground Plane
2,5,8,11,14,17,20,23,26,29,32,
35,38,41,44,47,50,65,66,79,82,
85,88,91,94,97,100,103,106,
109,112,115,118,121,124,127,
130,133,136,139,142,145,148,
151,154,157,160,163,166,169,
198,201,204,207,210,213,216,
219,222,225,228,231,234,237
Other Pins
195
ODT0
77
ODT1
18,19,55,68,102,126,135,147,
156,165,173,203,212, 224,233
Data Sheet
On-Die Termination Control 0
On-Die Termination Control 1
NC
NC
—
Note: 1 Rank modules
NC
NC
—
Not connected
Note: Pins not connected on Infineon UDIMMs
13
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 6
Abbreviations for Buffer Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
OD
Data Sheet
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and
tristate, and allows multiple devices to share as a wire-OR.
14
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
- Pin 003
V SS
- Pin 005
DQS0 - Pin 007
DQ2
- Pin 009
V SS
- Pin 011
DQ9
- Pin 013
DQS1 - Pin 015
V SS - Pin 017
NC
- Pin 019
DQ10 - Pin 021
- Pin 023
V
SS
DQ17 - Pin 025
DQS2 - Pin 027
V SS
- Pin 029
DQ19 - Pin 031
DQ24 - Pin 033
V SS
- Pin 035
DQS0
- Pin 006
Pin 126 - NC
V SS
- Pin 008
Pin 128 - DQ6
Pin 127 - V SS
DQ3
- Pin 010
Pin 130 - V SS
DQ8
- Pin 012
Pin 132 - DQ13
Pin 131 - DQ12
V SS
- Pin 014
Pin 134 - DM1
DQS1
- Pin 016
Pin 136 - V SS
NC
- Pin 018
Pin 138 - CK1
V SS
- Pin 020
- Pin 022
- Pin 024
Pin 140 - DQ14
Pin 142 - V SS
Pin 144 - DQ21
- Pin 026
- Pin 028
Pin 146 - DM2
Pin 148 - V SS
Pin 150 - DQ23
DQ11
DQ16
V SS
DQS2
DQ18
V SS
DQ25
- Pin 030
- Pin 032
- Pin 034
Pin 152 - DQ28
Pin 154 - V SS
Pin 156 - NC
DQ26 - Pin 039
V SS
- Pin 038
Pin 158 - DQ30
V SS
- Pin 041
DQ27
- Pin 040
NC
- Pin 043
NC
NC
V SS
- Pin 045
- Pin 047
- Pin 042
- Pin 044
- Pin 046
Pin 160 - V SS
Pin 162 - NC
Pin 164 - NC
NC
- Pin 049
V DD
- Pin 053
NC
- Pin 055
A11
- Pin 057
V DD
- Pin 059
A4
A2
- Pin 061
- Pin 063
V SS
- Pin 065
V DD
- Pin 067
V DD
BA0
WE
- Pin 069
- Pin 071
- Pin 073
V SS
NC
NC
V SS
Pin 166 - V SS
Pin 168 - NC
Pin 170 - V DDQ
- Pin 048
- Pin 050
CKE0 - Pin 052
NC/BA2 - Pin 054
- Pin 056
V DDQ
A7
A5
V DDQ
V DD
V SS
Pin 172 - V DD
Pin 174 - A14
Pin 176 - A12
Pin 178 - V DD
- Pin 058
- Pin 060
- Pin 062
Pin 180 - A6
Pin 182 - A3
Pin 184 - V DD
- Pin 064
Pin 186 - CK0
Pin 188 - A0
Pin 190 - BA1
Pin 192 - RAS
- Pin 066
NC
- Pin 068
A10/AP - Pin 070
- Pin 072
V
DDQ
- Pin 074
- Pin 076
Pin 194 - V DDQ
Pin 196 - NC/A13
- Pin 078
- Pin 080
Pin 198 - V SS
Pin 200 - DQ37
DQS4
- Pin 082
- Pin 084
Pin 202 - DM4
Pin 204 - V SS
DQ40 - Pin 089
DQ34
V SS
- Pin 086
- Pin 088
Pin 206 - DQ39
Pin 208 - DQ44
V SS
DQ41
- Pin 090
Pin 210 - V SS
DQS5
- Pin 092
Pin 212 - NC
DQ42 - Pin 095
V SS
- Pin 094
V SS
DQ43
- Pin 096
DQ48
- Pin 098
- Pin 100
- Pin 102
Pin 214 - DQ46
Pin 216 - V SS
Pin 218 - DQ53
V DDQ - Pin 075
ODT1 - Pin 077
V SS
- Pin 079
DQ33 - Pin 081
DQS4 - Pin 083
V SS
- Pin 085
DQ35 - Pin 087
- Pin 091
DQS5 - Pin 093
- Pin 097
DQ49 - Pin 099
SA2 - Pin 101
V SS
- Pin 103
DQS6 - Pin 105
CAS
NC/S1
V DDQ
DQ32
V SS
V SS
NC
DQS6
DQ50 - Pin 107
V SS
V SS
DQ56
- Pin 109
DQ57 - Pin 111
DQS7 - Pin 113
V SS
- Pin 115
DQ59 - Pin 117
SDA
Data Sheet
Pin 122 - DQ4
Pin 124 - V SS
- Pin 036
V DDQ - Pin 051
Figure 1
- Pin 002
- Pin 004
DQS3
DQS3 - Pin 037
- Pin 119
Pin 121 - V SS
V SS
DQ1
BACKSIDE
DQ0
FRONTSIDE
VREF - Pin 001
DQ51
- Pin 104
- Pin 106
Pin 226 - DQ54
Pin 228 - V SS
Pin 230 - DQ61
- Pin 108
- Pin 110
DQS7
- Pin 112
- Pin 114
DQ58
V SS
- Pin 116
- Pin 118
SCL
- Pin 120
V SS
Pin 220 - CK2
Pin 222 - V SS
Pin 224 - NC
Pin 232 - DM7
Pin 234 - V SS
Pin 236 - DQ63
Pin 238
V DDSPD
Pin 240
SA1
Pin 123 - DQ5
Pin 125 - DM0
Pin 129 - DQ7
Pin 133 - V SS
Pin 135 - NC
Pin 137 - CK1
Pin 139 - V SS
Pin 141 - DQ15
Pin 143 - DQ20
Pin 145 - V SS
Pin 147 - NC
Pin 149 - DQ22
Pin 151 - V SS
Pin 153 - DQ29
Pin 155 - DM3
Pin 157 - V SS
Pin 159 - DQ31
Pin 161 - NC
Pin 163 - V SS
Pin 165 - NC
Pin 167 - NC
Pin 169 - V SS
Pin 171 - CKE1
Pin 173 - NC
Pin 175 - V DDQ
Pin 177 - A9
Pin 179 - A8
Pin 181 - V DDQ
Pin 183 - A1
Pin 185 - CK0
Pin 187 - V DD
Pin 189 - V DD
Pin 191 - V DDQ
Pin 193 - S0
Pin 195 - ODT0
Pin 197 - V DD
Pin 199 - DQ36
Pin 201 - V SS
Pin 203 - NC
Pin 205 - DQ38
Pin 207 - V SS
Pin 209 - DQ45
Pin 211 - DM5
Pin 213 - V SS
Pin 215 - DQ47
Pin 217 - DQ52
Pin 219 - V SS
Pin 221 - CK2
Pin 223 - DM6
Pin 225 - V SS
Pin 227 - DQ55
Pin 229 - DQ60
Pin 231 - V SS
Pin 233 - NC
Pin 235 - DQ62
Pin 237
V SS
Pin 239
SA0
MPPT0150
Pin Configuration UDIMM ×64 (240 Pin)
15
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
- Pin 003
V SS
- Pin 005
DQS0 - Pin 007
DQ2
- Pin 009
V SS
- Pin 011
DQ9
- Pin 013
DQS1 - Pin 015
V SS - Pin 017
NC
- Pin 019
DQ10 - Pin 021
- Pin 023
V SS
DQ17 - Pin 025
DQS2 - Pin 027
V SS
- Pin 029
DQ19 - Pin 031
DQ24 - Pin 033
V SS
- Pin 035
DQS0
- Pin 006
Pin 126 - NC
V SS
- Pin 008
Pin 128 - DQ6
Pin 127 - V SS
DQ3
- Pin 010
Pin 130 - V SS
DQ8
- Pin 012
Pin 132 - DQ13
Pin 131 - DQ12
V SS
- Pin 014
Pin 134 - DM1
DQS1
- Pin 016
Pin 136 - NC
NC
- Pin 018
Pin 138 - CK1
V SS
- Pin 020
- Pin 022
- Pin 024
Pin 140 - DQ14
Pin 142 - V SS
Pin 144 - DQ21
Pin 146 - DM2
DQ11
DQ16
V SS
DQS2
V SS
V SS
DQ25
- Pin 026
- Pin 028
- Pin 030
- Pin 032
- Pin 034
Pin 148 - V SS
Pin 150 - DQ23
Pin 152 - DQ28
Pin 154 - V SS
Pin 156 - NC
- Pin 036
DQ26 - Pin 039
- Pin 038
Pin 158 - DQ30
V SS
- Pin 041
DQ27
- Pin 040
CB1
- Pin 043
CB0
- Pin 042
- Pin 044
- Pin 046
Pin 160 - V SS
Pin 162 - CB5
Pin 164 - DM8
CB3
- Pin 049
V DDQ - Pin 051
V DD
- Pin 053
NC
- Pin 055
A11
- Pin 057
V DD
- Pin 059
A4
A2
- Pin 061
- Pin 063
V SS
- Pin 065
V DD
- Pin 067
V DD
BA0
WE
- Pin 069
- Pin 071
- Pin 073
V DDQ - Pin 075
ODT1 - Pin 077
V SS
- Pin 079
V SS
DQS8
CB2
V SS
Pin 166 - V SS
Pin 168 - CB7
Pin 170 - V DDQ
- Pin 048
- Pin 050
- Pin 052
NC/BA2 - Pin 054
- Pin 056
V DDQ
Pin 172 - V DD
Pin 174 - A14
Pin 176 - A12
- Pin 058
- Pin 060
- Pin 062
Pin 178 - V DD
Pin 180 - A6
Pin 182 - A3
Pin 184 - V DD
CKE0
A7
A5
V DDQ
V DD
V SS
- Pin 064
Pin 186 - CK0
Pin 188 - A0
Pin 190 - BA1
Pin 192 - RAS
- Pin 066
NC
- Pin 068
A10/AP - Pin 070
- Pin 072
V
DDQ
CAS
NC/S1
V DDQ
- Pin 074
- Pin 076
Pin 194 - V DDQ
Pin 196 - NC/A13
Pin 198 - V SS
- Pin 078
- Pin 080
DQS4
- Pin 082
- Pin 084
Pin 200 - DQ37
Pin 202 - DM4
Pin 204 - V SS
DQ40 - Pin 089
DQ34
V SS
- Pin 086
- Pin 088
Pin 206 - DQ39
Pin 208 - DQ44
V SS
DQ41
- Pin 090
Pin 210 - V SS
DQS5
- Pin 092
Pin 212 - NC
V SS
- Pin 094
DQ43
- Pin 096
DQ48
- Pin 098
- Pin 100
- Pin 102
Pin 214 - DQ46
Pin 216 - V SS
Pin 218 - DQ53
DQ33 - Pin 081
DQS4 - Pin 083
V SS
- Pin 085
DQ35 - Pin 087
- Pin 091
DQS5 - Pin 093
V SS
- Pin 095
V SS
- Pin 097
DQ49 - Pin 099
SA2 - Pin 101
V SS
- Pin 103
DQS6 - Pin 105
DQ50 - Pin 107
V SS
- Pin 109
DQ57 - Pin 111
DQS7 - Pin 113
V SS
- Pin 115
DQ59 - Pin 117
SDA
Data Sheet
Pin 122 - DQ4
Pin 124 - V SS
V SS
DQS8 - Pin 045
V SS
- Pin 047
Figure 2
- Pin 002
- Pin 004
DQS3
DQS3 - Pin 037
- Pin 119
Pin 121 - V SS
V SS
DQ1
BACKSIDE
DQ0
FRONTSIDE
VREF - Pin 001
DQ32
V SS
V SS
NC
DQS6
V SS
DQ51
DQ56
- Pin 104
- Pin 106
Pin 226 - DQ54
Pin 228 - V SS
- Pin 108
- Pin 110
DQS7
- Pin 112
- Pin 114
DQ58
V SS
- Pin 116
- Pin 118
SCL
- Pin 120
V SS
Pin 220 - CK2
Pin 222 - V SS
Pin 224 - NC
Pin 230 - DQ61
Pin 232 - DM7
Pin 234 - V SS
Pin 236 - DQ63
Pin 238
V DDSPD
Pin 240
SA1
Pin 123 - DQ5
Pin 125 - DM0
Pin 129 - DQ7
Pin 133 - V SS
Pin 135 - NC
Pin 137 - CK1
Pin 139 - V SS
Pin 141 - DQ15
Pin 143 - DQ20
Pin 145 - V SS
Pin 147 - NC
Pin 149 - DQ22
Pin 151 - V SS
Pin 153 - DQ29
Pin 155 - DM3
Pin 157 - V SS
Pin 159 - DQ31
Pin 161 - CB4
Pin 163 - V SS
Pin 165 - NC
Pin 167 - CB6
Pin 169 - V SS
Pin 171 - CKE1
Pin 173 - NC
Pin 175 - V DDQ
Pin 177 - A9
Pin 179 - A8
Pin 181 - V DDQ
Pin 183 - A1
Pin 185 - CK0
Pin 187 - V DD
Pin 189 - V DD
Pin 191 - V DDQ
Pin 193 - S0
Pin 195 - ODT0
Pin 197 - V DD
Pin 199 - DQ36
Pin 201 - V SS
Pin 203 - NC
Pin 205 - DQ38
Pin 207 - V SS
Pin 209 - DQ45
Pin 211 - DM5
Pin 213 - V SS
Pin 215 - DQ47
Pin 217 - DQ52
Pin 219 - V SS
Pin 221 - CK2
Pin 223 - DM6
Pin 225 - V SS
Pin 227 - DQ55
Pin 229 - DQ60
Pin 231 - V SS
Pin 233 - NC
Pin 235 - DQ62
Pin 237
V SS
Pin 239
SA0
MPPT0160
Pin Configuration UDIMM ×72 (240 Pin)
16
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 8
Input/Output Functional Description
Symbol
Type
Polarity Function
CK0-CKn,
CK0-CKn
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE0CKEn
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
S0-Sn
I
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA0-BAn
I
—
Selects internal SDRAM memory bank
ODT0ODTn
I
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[12:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge.
DQ[63:0]
I/O
—
Data Input/Output pins
DM[8:0]
I
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[8:0],
DQS[8:0]
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm
resistor and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply —
VDDSPD, VSS
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
SDA
I/O
—
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to to VDDSPD on the motherboard to act
as a pull-up.
SCL
I
—
This signal is used to clock data into and out of the SPD EEPROM.
SA0-SAn
I
—
Address pins used to select the Serial Presence Detect base address.
Data Sheet
17
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
2
Block Diagrams
!
!
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#
#
"
Figure 3
Block Diagram Raw Card A UDIMM (×64, 1 Rank, ×8)
Note
1.
2.
3.
4.
DQ,DQS,DQS,DM resistors are 22 Ω ± 5 %
BAn, An, RAS, CAS, WE resistors are 5.1 Ω ± 5 %
ODT,CKE,S capacitors are 24 pF
All CK lines have resistor termination between CK
an CK.
Data Sheet
Table 9
18
Clock Signal Loads
Clock Input
SDRAMs
CK0,CKO
2
CK1,CK1
3
CK2,CK3
3
Note
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
#
!
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!
!
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!
Figure 4
Block Diagram Raw Card A UDIMM (×72, 1 Rank, ×8)
Note
1.
2.
3.
4.
DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
BAn, An, RAS, CAS, WE resistors are 5.1 Ω ± 5 %
ODT,CKE,S capacitors are 24 pF
All CK lines have resistor termination between CK
an CK.
Table 10
Clock Input
SDRAMs
Note
CK0,CK0
3
1)
CK1,CK1
3
CK2,CK3
3
1)
Data Sheet
19
Clock Signal Loads
2 SDRAMS for CK0 in case of non-ECC
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
)
BA0 - BA2
A0 - An
RAS
CAS
WE
CKE 0
CKE 1
ODT 0
ODT 1
BA0 - BA2: SDRAMs D0 - D15
A0 - An: SDRAMs D0 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
CKE 0: SDRAMs D0 - D7
CKE 1: SDRAMs D8 - D15
ODT 0: SDRAMs D0 - D7
ODT 0: SDRAMs D8 - D15
VDD,SPD
VDD/VDDQ
VREF
VSS
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D15
VREF: SDRAMs D0 - D15
VSS: SDRAMs D0 - D15
VSS
SCL
SDA
SA0
SA1
VSS
E0
SCL
SDA
A0
A1
A2
WP
S0
S1
DM0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM1
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM2
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM3
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
Figure 5
D0
D1
D2
D3
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
D9
D10
D11
DM4
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM7
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
D5
D6
D7
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D12
D13
D14
D15
MPBT0130
Block Diagram Raw Card B UDIMM (×64, 1 Rank, ×8)
Note
1.
2.
3.
4.
DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %
ODT,CKE,S capacitors are 24 pF
All CK lines have resistor termination between CK
an CK.
Data Sheet
Table 11
20
Clock Signal Loads
Clock Input
SDRAMs
CK0,CK0
4
CK1,CK1
6
CK2,CK3
6
Note
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
!
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Figure 6
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#
#
"
Block Diagram Raw Card B UDIMM (×72, 1 Rank, ×8)
Note:
1.
2.
3.
4.
DQ,DQS,DQS,DM,CB resistors are 22 Ω ± 5 %
BAn, An, RAS, CAS, WE resistors are 7.5 Ω ± 5 %
ODT,CKE,S capacitors are 24 pF
All CK lines have resistor termination between CK
an CK.
Data Sheet
Table 12
21
Clock Signal Loads
Clock Input
SDRAMs
CK0,CK0
6
CK1,CK1
6
CK2,CK3
6
Note
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
#
#
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#
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%
%
%
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Figure 7
Block Diagram Raw Card C UDIMM (×64, 1Rank, ×16)
Note
1. DQ, DQS, DM resistors are 22 Ω ± 5 %
2. BAn, An, RAS, CAS, WE resistors are 10 Ω ± 5 %
Data Sheet
22
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 13
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pins relative to VSS
VIN, VOUT
VDD
VDDQ
THSTG
HSTG
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage temperature range
Storage Humidity (without condensation)
Limit Values
Unit
min.
max.
– 0.5
2.3
V
– 1.0
2.3
V
– 0.5
2.3
-55
+100
°C
5
95
%
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Table 14
Operating Conditions
Parameter
Symbol
Limit Values
min.
max.
Unit
TOPR
TCASE
0
+55
°C
DRAM Component Case Temperature Range
0
+95
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
DIMM Module Operating Temperature Range (ambient)
Notes
1)2)3)4)
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the
DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2.
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the
DRAM is below 85°C case temperature before initiating self-refresh operation.
Table 15
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
DC Input Logic Low
In / Output Leakage Current
1) Under all conditions,
VDD
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
Limit Values
Unit
Notes
1.9
V
-
1.8
1.9
V
1)
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2)
1.7
–
3.6
V
VREF + 0.125
–
V
– 0.30
–
VDDQ + 0.3
VREF – 0.125
V
5
µA
min.
nom.
max.
1.7
1.8
1.7
–5
3)
VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations
in VDDQ.
3) Voltage for pin connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all othe pins at 0 V. Current is per pin
Data Sheet
23
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
IDD Specifications and Conditions
Table 16
IDD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,
tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
IDD2N
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
IDD3P(1)
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD4R
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Distributed Refresh Current
IDD5D
tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
24
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 16
IDD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
IDD6
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
HYS64T64000GU-3.7-A
HYS64T64000HU-3.7-A
HYS72T64000GU-3.7-A
HYS72T64000HU-3.7-A
HYS64T128020GU-3.7-A
HYS64T128020HU-3.7-A
HYS72T128020GU-3.7-A
HYS72T128020HU-3.7-A
IDD Specification
HYS64T32000GU-3.7-A
HYS64T32000HU-3.7-A
Table 17
256MB
512MB
512MB
1GB
1GB
×64
×64
×72
×64
×72
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
–3.7
–3.7
–3.7
–3.7
–3.7
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
320
520
585
552
621
mA
1)
360
600
675
632
711
mA
1)
16
32
36
64
72
mA
1)
160
320
360
640
720
mA
1)
120
240
270
480
540
mA
1)
64
128
144
256
288
mA
1)
20
40
45
80
90
mA
1)
160
320
360
640
720
mA
1)
400
720
810
752
846
mA
1)
440
760
855
792
891
mA
1)
520
1040
1170
1072
1206
mA
1)
24
48
54
96
108
mA
1)
16
32
36
64
72
mA
1)
880
1120
1260
1152
1296
mA
1)
Product Type
Organization
Unit
Notes
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
25
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
HYS64T128020GU-5-A
HYS64T128020HU-5-A
HYS72T128020GU-5-A
HYS72T128020HU-5-A
Organization
HYS72T64000GU-5-A
HYS72T64000HU-5-A
Product Type
HYS64T64000GU-5-A
HYS64T64000HU-5-A
IDD Specification
HYS64T32000GU-5-A
HYS64T32000HU-5-A
Table 18
256MB
512MB
512MB
1GB
1GB
×64
×64
×72
×64
×72
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
Unit
Notes
–5
–5
–5
–5
–5
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
280
440
495
472
531
mA
1)
300
480
540
512
576
mA
1)
16
32
36
64
72
mA
1)
128
256
288
512
576
mA
1)
100
200
225
400
450
mA
1)
52
104
117
208
234
mA
1)
20
40
45
80
90
mA
1)
140
280
315
560
630
mA
1)
340
560
630
592
666
mA
1)
360
600
675
632
711
mA
1)
480
960
1080
992
1116
mA
1)
24
48
54
96
108
mA
1)
16
32
36
64
72
mA
1)
840
1040
1170
1072
1206
mA
1)
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
Data Sheet
26
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
Table 19
IDD Measurement Test Conditions
Parameter
Symbol
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
1)
Active bank A to Active bank B x8
command delay
x16 2)
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command
period
Average periodic Refresh interval
-5
-3.7
Unit
PC2-3200
PC2-4200
3-3-3
4-4-4
CLmin
tCKmin
tRCDmin
tRCmin
tRRDmin
tRRDmin
tRASmin
tRPmin
tRFCmin
3
4
tCK
5
3.75
ns
15
15
ns
55
60
ns
7.5
7.5
ns
10
10
ns
40
45
ns
15
15
ns
105
105
ns
tREFI
7.8
7.8
µs
1) For modules based on x8 components
2) For modules based on x16 components
4.2
ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current
consumption for any terminated input pin, depends on the input pin is in tristate or driving 0 or 1, as long a ODT
is enabled during a given period of time.
Table 20
ODT current per terminated pin:
EMRS(1)
State
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are
FLOATING
IODTO
IODTT
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
min.
typ.
max.
Unit
A6 = 0, A2 = 1 5
6
7.5
mA/DQ
A6 = 1, A2 = 0 2.5
3
3.75
mA/DQ
A6 = 0, A2 = 1 10
12
15
mA/DQ
A6 = 1, A2 = 0 5
6
7.5
mA/DQ
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
27
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
5.1
AC Timing Parameter by Speed Grade (Component level data, for reference only)
Table 21
AC Timing - Absolute Specifications –5 / –3.7
Symbol Parameter
tAC
tCCD
tCH
tCK
DQ output access time from CK/CK
–5
–3.7
Unit Notes
DDR2–400
DDR2–533
min.
max.
min.
max.
− 600
+ 600
-500
+500
ps
1)
CAS A to CAS B Command Period
2
-
2
-
tCK
1)
CK, CK high-level width
0.45
0.55
0.45
0.55
tCK
1)
Clock cycle time
5000
8000
5000
8000
ps
1)2)
5000
8000
3750
8000
ps
1)3)
tCKE
tCL
tDAL
tDELAY
CKE minimum high and low pulse width
3
-
3
-
tCK
1)
CK, CK low-level width
0.45
0.55
0.45
0.55
tCK
1)
-
WR+tRP -
tCK
1)
Minimum time clocks remain ON after CKE
asynchronously drops low
-
ns
1)
H
tIS+tCK
+tIH
tDH
tDIPW
tDQSCK
tDQSL,H
tDQSS
DQ and DM input hold time
400
-
350
-
ps
1)4)
DQ and DM input pulse width (each input)
0.35
-
0.35
-
tCK
1)
DQS output access time from CK/CK
− 500
+ 500
−450
+450
ps
1)
DQS input low (high) pulse width (write cycle)
0.35
-
0.35
-
1)
Write command to 1st DQS latching transition
WL 0.25
WL
+0.25
WL
-0.25
WL
+0.25
tCK
tCK
tDQSQ
DQS-DQ skew
(for DQS & associated DQ signals)
-
350
-
300
ps
1)
tDS
tDSH
DQ and DM input setup time
400
-
350
-
ps
1)4)
DQS falling edge hold time from CLK
(write cycle)
0.2
-
0.2
-
tCK
1)
tDSS
DQS falling edge to CLK setup time
(write cycle)
0.2
-
0.2
-
tCK
1)
tHP
tHZ
tIH
tIPW
tIS
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tRAS
tRC
tRCD
Clock Half Period
min. (tCL, tCH)
Data-out high-impedance time from CK/CK
-
tACmax
-
tACmax
ps
1)
Address and control input hold time
600
-
600
-
ps
1)4)
Control and Addr. input pulse width (each input) 0.6
-
0.6
-
tCK
1)
Address and control input setup time
600
-
600
-
ps
1)4)
DQ low-impedance from CK / CK
2*tACmin
2*tACmin tACmax
ps
1)
DQS low-impedance from CK / CK
tACmin
tACmax
tACmax
tACmin
ps
1)
Auto precharge write recovery + precharge time WR+tRP
tIS+tCK+tI -
1)
min. (tCL, tCH)
tACmax
1)
Mode register set command cycle time
2
-
2
-
tCK
1)
OCD drive mode output delay
0
12
0
12
ns
1)
Active to Precharge command
40
70000
45
70000
ns
1)
Active to Active/Auto-refresh command period
55
-
60
-
ns
1)
Active to Read or Write delay (with and without
Auto-Precharge) delay
15
-
15
-
ns
1)
Data Sheet
28
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 21
AC Timing - Absolute Specifications –5 / –3.7
Symbol Parameter
tREFI
Average Periodic Refresh
Interval
–5
–3.7
DDR2–400
DDR2–533
min.
max.
min.
max.
0 C - 85 C
-
7.8
-
7.8
85οC - 95οC
-
3.9
-
3.9
ο
ο
Unit Notes
µs
1)
1)
tRFC
Auto-refresh to Active/Auto-refresh command
period
105
-
105
-
ns
1)
tRP
tRPRE
tRPST
tRRD
Precharge command period
15
-
15
-
ns
1)
Read preamble
0.9
1.1
0.9
1.1
1)
Read postamble
0.40
0.60
0.40
0.60
tCK
tCK
x8
7.5
(1k page size)
-
7.5
-
ns
1)
x16
10
(2k page size)
-
10
-
ns
1)
-
7.5
-
ns
1)
tRTP
Active bank A to Active bank B
command
Internal read to precharge command delay
7.5
1)
1)
1)
tQH
tQHS
tWPRE
tWPST
tWR
tWTR
tXARD
Data Output hold time from DQS
tHP - tQHS -
tHP-tQHS -
Data hold skew factor
-
450
-
400
ps
1)
Write preamble
0.25
-
0.25
-
1)
Write postamble
0.40
0.60
0.40
0.60
tCK
tCK
Write recovery time
15
-
15
-
ns
1)
Internal write to read command delay
10
-
7.5
-
ns
1)
Exit power down to any valid command
(other than NOP or Deselect)
2
-
2
-
tCK
1)
tXARDS
Exit active power-down mode to read command 6 - AL
(slew exit, lower power)
-
6 - AL
-
tCK
1)
tXP
Exit precharge power-down to any valid
command (other than NOP or Deselect)
2
-
2
-
tCK
1)
tXSNR
Exit Self-Refresh to non-read command
tRFC + 10 -
tRFC +
-
ns
1)5)
-
tCK
1)6)
1)
10
tXSRD
Exit Self-Refresh to read command
200
-
200
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) Timing definition and values for tIS, tIH, tDS and tDH may change due to actual JEDEC work. This may also effect the SPD
code for these parameters
5) 0 °C ≤
TCASE ≤ 85 °C
6) 85 °C < TCASE ≤ 95 °C
Data Sheet
29
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 22
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
min.
max.
Unit
tANPD
tAOF
tAOFD
tAOFPD
tAON
ODT to Power Down Mode Entry Latency
3
-
tCK
ODT turn-off
tAC(min)
tAC(max) + 0.6 ns
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off delay (Power-Down Modes)
tAC(min) + 2 ns
tAC(min)
2.5 tCK + tAC(max) + 1 ns ns
tAC(max) + 1 ns
ns
tAOND
tAONPD
tAXPD
ODT turn-on delay
2
2
tCK
ODT turn-on
DDR2400/533
ODT turn-on (Power-Down Modes)
tAC(min) + 2 ns
2 tCK + tAC(max) + 1 ns
ns
ODT Power Down Exit Latency
8
-
tCK
Data Sheet
30
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A
Product Type
HYS72T64000GU–3.7–A
Table 23
HYS64T64000GU–3.7–A
SPD Codes
HYS64T32000GU–3.7–A
6
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
3D
3D
3D
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
08
08
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
Not used
00
00
00
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
01
01
01
23
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
3D
3D
3D
50
50
50
50
50
50
60
60
60
24
25
26
Data Sheet
31
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–3.7–A
HYS72T64000GU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
HYS64T32000GU–3.7–A
Table 23
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
27
3C
3C
3C
28
1E
1E
3C
3C
3C
30
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
25
25
25
37
37
37
10
10
10
22
22
22
3C
3C
3C
1E
1E
1E
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
46
47
28
29
33
34
35
36
37
00
00
00
3C
3C
3C
69
69
69
80
80
80
1E
1E
1E
28
28
28
PLL Relock Time
00
00
00
TCASE.max Delta / ∆ T4R4W Delta
53
51
51
48
Psi(T-A) DRAM
72
78
78
49
∆ T0 (DT0)
52
3E
3E
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM) 2B
2E
2E
51
∆ T2P (DT2P)
1D
1E
1E
52
∆ T3N (DT3N)
1D
1E
1E
53
∆ T3P.fast (DT3P fast)
23
24
24
54
∆ T3P.slow (DT3P slow)
16
17
17
41
42
43
44
Data Sheet
32
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–3.7–A
HYS72T64000GU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
HYS64T32000GU–3.7–A
Table 23
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
36
34
34
56
∆ T5B (DT5B)
1C
1E
1E
57
∆ T7 (DT7)
30
20
20
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆ TPLL (DTPLL)
00
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
11
11
11
63
Checksum of Bytes 0-62
B9
CF
E1
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65 - 71 JEDEC ID Code of Infineon (2 - 8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
36
77
Product Type, Char 5
32
34
34
78
Product Type, Char 6
30
30
30
79
Product Type, Char 7
30
30
30
80
Product Type, Char 8
30
30
30
81
Product Type, Char 9
47
47
47
82
Product Type, Char 10
55
55
55
83
Product Type, Char 11
33
33
33
84
Product Type, Char 12
2E
2E
2E
85
Product Type, Char 13
37
37
37
86
Product Type, Char 14
41
41
41
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
Data Sheet
33
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–3.7–A
HYS72T64000GU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d)
HYS64T32000GU–3.7–A
Table 23
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
99 -127 Not Used
00
00
00
128255
FF
FF
FF
BLANK
Data Sheet
34
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–3.7–A
SPD Codes HYS[64/72]T128020GU–3.7–A
HYS64T128020GU–3.7–A
Table 24
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
1
Total number of Bytes in EEPROM
08
08
2
Memory Type (DDR2)
08
08
3
Number of Row Addresses
0E
0E
4
Number of Column Addresses
0A
0A
5
DIMM Rank and Stacking Information
61
61
6
Data Width
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
3D
3D
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
11
Error Correction Support (non-ECC, ECC)
00
02
12
Refresh Rate and Type
82
82
13
Primary SDRAM Width
08
08
14
Error Checking SDRAM Width
00
08
15
Not used
00
00
16
Burst Length Supported
0C
0C
17
Number of Banks on SDRAM Device
04
04
18
Supported CAS Latencies
38
38
19
Not used
00
00
20
DIMM Type Information
02
02
21
DIMM Attributes
00
00
22
Component Attributes
01
01
23
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
3D
3D
50
50
50
50
60
60
24
25
26
Data Sheet
35
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–3.7–A
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
HYS64T128020GU–3.7–A
Table 24
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
27
3C
3C
1E
1E
3C
3C
30
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
31
Module Density per Rank
80
80
32
25
25
37
37
10
10
22
22
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
39
40
28
29
33
34
35
36
3C
3C
1E
1E
1E
1E
Analysis Characteristics
00
00
00
00
3C
3C
69
69
80
80
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
46
37
41
42
43
44
1E
1E
28
28
PLL Relock Time
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
48
Psi(T-A) DRAM
78
78
49
∆ T0 (DT0)
3E
3E
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
2E
2E
51
∆ T2P (DT2P)
1E
1E
52
∆ T3N (DT3N)
1E
1E
53
∆ T3P.fast (DT3P fast)
24
24
54
∆ T3P.slow (DT3P slow)
17
17
Data Sheet
36
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–3.7–A
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
HYS64T128020GU–3.7–A
Table 24
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
34
34
56
∆ T5B (DT5B)
1E
1E
57
∆ T7 (DT7)
20
20
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
60
∆ TPLL (DTPLL)
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
62
SPD Revision
11
11
63
Checksum of Bytes 0-62
D0
E2
64
JEDEC ID Code of Infineon (1)
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
73
Product Type, Char 1
36
37
74
Product Type, Char 2
34
32
75
Product Type, Char 3
54
54
76
Product Type, Char 4
31
31
77
Product Type, Char 5
32
32
78
Product Type, Char 6
38
38
79
Product Type, Char 7
30
30
80
Product Type, Char 8
32
32
81
Product Type, Char 9
30
30
82
Product Type, Char 10
47
47
83
Product Type, Char 11
55
55
84
Product Type, Char 12
33
33
85
Product Type, Char 13
2E
2E
86
Product Type, Char 14
37
37
87
Product Type, Char 15
41
41
88
Product Type, Char 16
20
20
Data Sheet
37
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–3.7–A
SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d)
HYS64T128020GU–3.7–A
Table 24
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
89
Product Type, Char 17
20
20
90
Product Type, Char 18
20
20
91
Module Revision Code
2x
2x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95
Module Serial Number (1)
xx
xx
96
Module Serial Number (2)
xx
xx
97
Module Serial Number (3)
xx
xx
98
Module Serial Number (4)
xx
xx
99 -127
Not Used
00
00
128-255
BLANK
FF
FF
Data Sheet
38
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–3.7–A
HYS72T64000HU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A
HYS64T32000HU–3.7–A
Table 25
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
3D
3D
3D
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
08
08
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
Not used
00
00
00
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
01
01
01
23
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
3D
3D
3D
50
50
50
50
50
50
60
60
60
3C
3C
3C
24
25
26
27
Data Sheet
39
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–3.7–A
HYS72T64000HU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
HYS64T32000HU–3.7–A
Table 25
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
28
28
1E
1E
3C
3C
3C
30
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
25
25
25
37
37
37
10
10
10
22
22
22
3C
3C
3C
1E
1E
1E
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
46
29
33
34
35
36
37
41
3C
3C
3C
69
69
69
80
80
80
1E
1E
1E
28
28
28
PLL Relock Time
00
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
53
51
51
48
Psi(T-A) DRAM
72
78
78
42
43
44
49
∆ T0 (DT0)
52
3E
3E
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
2B
2E
2E
51
∆ T2P (DT2P)
1D
1E
1E
52
∆ T3N (DT3N)
1D
1E
1E
53
∆ T3P.fast (DT3P fast)
23
24
24
54
∆ T3P.slow (DT3P slow)
16
17
17
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
36
34
34
Data Sheet
40
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–3.7–A
HYS72T64000HU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
HYS64T32000HU–3.7–A
Table 25
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
56
∆ T5B (DT5B)
1C
1E
1E
57
∆ T7 (DT7)
30
20
20
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆ TPLL (DTPLL)
00
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
11
11
11
63
Checksum of Bytes 0-62
B9
CF
E1
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
36
77
Product Type, Char 5
32
34
34
78
Product Type, Char 6
30
30
30
79
Product Type, Char 7
30
30
30
80
Product Type, Char 8
30
30
30
81
Product Type, Char 9
48
48
48
82
Product Type, Char 10
55
55
55
83
Product Type, Char 11
33
33
33
84
Product Type, Char 12
2E
2E
2E
85
Product Type, Char 13
37
37
37
86
Product Type, Char 14
41
41
41
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
Data Sheet
41
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–3.7–A
HYS72T64000HU–3.7–A
SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d)
HYS64T32000HU–3.7–A
Table 25
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
99 -127
Not Used
00
00
00
FF
FF
FF
128-255 BLANK
Data Sheet
42
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–3.7–A
SPD Codes for HYS[64/72]T128020HU–3.7–A
HYS64T128020HU–3.7–A
Table 26
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
1
Total number of Bytes in EEPROM
08
08
2
Memory Type (DDR2)
08
08
3
Number of Row Addresses
0E
0E
4
Number of Column Addresses
0A
0A
5
DIMM Rank and Stacking Information
61
61
6
Data Width
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
3D
3D
10
50
50
11
Error Correction Support (non-ECC, ECC)
00
02
12
Refresh Rate and Type
82
82
13
Primary SDRAM Width
08
08
14
Error Checking SDRAM Width
00
08
15
Not used
00
00
16
Burst Length Supported
0C
0C
17
Number of Banks on SDRAM Device
04
04
18
Supported CAS Latencies
38
38
19
Not used
00
00
20
DIMM Type Information
02
02
21
DIMM Attributes
00
00
22
Component Attributes
01
01
23
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
3D
3D
50
50
50
50
60
60
24
25
26
Data Sheet
43
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–3.7–A
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
HYS64T128020HU–3.7–A
Table 26
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
27
3C
3C
1E
1E
3C
3C
30
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
31
Module Density per Rank
80
80
32
25
25
37
37
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
39
40
28
29
33
34
10
10
22
22
3C
3C
1E
1E
1E
1E
Analysis Characteristics
00
00
00
00
3C
3C
69
69
80
80
1E
1E
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
28
28
46
PLL Relock Time
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
48
Psi(T-A) DRAM
78
78
49
∆ T0 (DT0)
3E
3E
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
2E
2E
51
∆ T2P (DT2P)
1E
1E
52
∆ T3N (DT3N)
1E
1E
53
∆ T3P.fast (DT3P fast)
24
24
54
∆ T3P.slow (DT3P slow)
17
17
35
36
37
41
42
43
44
Data Sheet
44
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–3.7–A
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
HYS64T128020HU–3.7–A
Table 26
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
34
34
56
∆ T5B (DT5B)
1E
1E
57
∆ T7 (DT7)
20
20
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
60
∆ TPLL (DTPLL)
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
62
SPD Revision
11
11
63
Checksum of Bytes 0-62
D0
E2
64
JEDEC ID Code of Infineon (1)
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
73
Product Type, Char 1
36
37
74
Product Type, Char 2
34
32
75
Product Type, Char 3
54
54
76
Product Type, Char 4
31
31
77
Product Type, Char 5
32
32
78
Product Type, Char 6
38
38
79
Product Type, Char 7
30
30
80
Product Type, Char 8
32
32
81
Product Type, Char 9
30
30
82
Product Type, Char 10
48
48
83
Product Type, Char 11
55
55
84
Product Type, Char 12
33
33
85
Product Type, Char 13
2E
2E
86
Product Type, Char 14
37
37
87
Product Type, Char 15
41
41
88
Product Type, Char 16
20
20
Data Sheet
45
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–3.7–A
SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d)
HYS64T128020HU–3.7–A
Table 26
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
89
Product Type, Char 17
20
20
90
Product Type, Char 18
20
20
91
Module Revision Code
2x
2x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95
Module Serial Number (1)
xx
xx
96
Module Serial Number (2)
xx
xx
97
Module Serial Number (3)
xx
xx
98
Module Serial Number (4)
xx
xx
99 -127
Not Used
00
00
128-255
BLANK
FF
FF
Data Sheet
46
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–5–A
HYS72T64000GU–5–A
SPD Codes for HYS[64/72]T32000GU–5–A
HYS64T32000GU–5–A
Table 27
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
50
50
50
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
60
60
60
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
08
08
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
Not used
00
00
00
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
01
01
01
23
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
50
50
50
60
60
60
50
50
50
60
60
60
3C
3C
3C
24
25
26
27
Data Sheet
47
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–5–A
HYS72T64000GU–5–A
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
HYS64T32000GU–5–A
Table 27
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
28
28
1E
1E
3C
3C
3C
30
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
35
35
35
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
39
40
29
33
47
47
47
15
15
15
27
27
27
3C
3C
3C
28
28
28
1E
1E
1E
Analysis Characteristics
00
00
00
00
00
00
3C
3C
3C
69
69
69
80
80
80
23
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
2D
2D
2D
46
PLL Relock Time
00
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
51
48
Psi(T-A) DRAM
72
78
78
49
∆ T0 (DT0)
42
32
32
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
23
24
24
51
∆ T2P (DT2P)
1D
1E
1E
52
∆ T3N (DT3N)
19
1B
1B
53
∆ T3P.fast (DT3P fast)
1C
1E
1E
54
∆ T3P.slow (DT3P slow)
16
17
17
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
2E
28
28
56
∆ T5B (DT5B)
1A
1B
1B
34
35
36
37
41
42
43
44
Data Sheet
48
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–5–A
HYS72T64000GU–5–A
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
HYS64T32000GU–5–A
Table 27
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
57
∆ T7 (DT7)
2D
1E
1E
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆ TPLL (DTPLL)
00
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
11
11
11
63
Checksum of Bytes 0-62
0B
23
35
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2- 8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
36
77
Product Type, Char 5
32
34
34
78
Product Type, Char 6
30
30
30
79
Product Type, Char 7
30
30
30
80
Product Type, Char 8
30
30
30
81
Product Type, Char 9
47
47
47
82
Product Type, Char 10
55
55
55
83
Product Type, Char 11
35
35
35
84
Product Type, Char 12
41
41
41
85
Product Type, Char 13
20
20
20
86
Product Type, Char 14
20
20
20
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
Data Sheet
49
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000GU–5–A
HYS72T64000GU–5–A
SPD Codes for HYS[64/72]T32000GU–5–A (cont’d)
HYS64T32000GU–5–A
Table 27
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
99 -127
Not Used
00
00
00
128-255
BLANK
FF
FF
FF
Product Type
HYS72T128020GU–5–A
SPD Codes for HYS[64/72]T128020GU–5–A
HYS64T128020GU–5–A
Table 28
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
1
Total number of Bytes in EEPROM
08
08
2
Memory Type (DDR2)
08
08
3
Number of Row Addresses
0E
0E
Data Sheet
50
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–5–A
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
HYS64T128020GU–5–A
Table 28
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
4
Number of Column Addresses
0A
0A
5
DIMM Rank and Stacking Information
61
61
6
Data Width
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
60
60
10
11
Error Correction Support (non-ECC, ECC)
00
02
12
Refresh Rate and Type
82
82
13
Primary SDRAM Width
08
08
14
Error Checking SDRAM Width
00
08
15
Not used
00
00
16
Burst Length Supported
0C
0C
17
Number of Banks on SDRAM Device
04
04
18
Supported CAS Latencies
38
38
19
Not used
00
00
20
DIMM Type Information
02
02
21
DIMM Attributes
00
00
22
Component Attributes
01
01
23
50
50
60
60
50
50
60
60
3C
3C
1E
1E
3C
3C
30
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
31
Module Density per Rank
80
80
24
25
26
27
28
29
Data Sheet
51
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–5–A
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
HYS64T128020GU–5–A
Table 28
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
HEX
32
35
35
47
47
15
15
27
27
3C
3C
28
28
38
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
1E
1E
39
Analysis Characteristics
00
00
40
00
00
3C
3C
69
69
80
80
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
2D
2D
46
PLL Relock Time
00
00
33
34
35
36
37
41
42
43
44
Rev. 1.1
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
48
Psi(T-A) DRAM
78
78
49
∆ T0 (DT0)
32
32
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
24
24
51
∆ T2P (DT2P)
1E
1E
52
∆ T3N (DT3N)
1B
1B
53
∆ T3P.fast (DT3P fast)
1E
1E
54
∆ T3P.slow (DT3P slow)
17
17
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
28
28
56
∆ T5B (DT5B)
1B
1B
57
∆ T7 (DT7)
1E
1E
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
Data Sheet
52
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–5–A
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
HYS64T128020GU–5–A
Table 28
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
60
∆ TPLL (DTPLL)
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
62
SPD Revision
11
11
63
Checksum of Bytes 0-62
24
36
64
JEDEC ID Code of Infineon (1)
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
73
Product Type, Char 1
36
37
74
Product Type, Char 2
34
32
75
Product Type, Char 3
54
54
76
Product Type, Char 4
31
31
77
Product Type, Char 5
32
32
78
Product Type, Char 6
38
38
79
Product Type, Char 7
30
30
80
Product Type, Char 8
32
32
81
Product Type, Char 9
30
30
82
Product Type, Char 10
47
47
83
Product Type, Char 11
55
55
84
Product Type, Char 12
35
35
85
Product Type, Char 13
41
41
86
Product Type, Char 14
20
20
87
Product Type, Char 15
20
20
88
Product Type, Char 16
20
20
89
Product Type, Char 17
20
20
90
Product Type, Char 18
20
20
91
Module Revision Code
2x
2x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
Data Sheet
53
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020GU–5–A
SPD Codes for HYS[64/72]T128020GU–5–A (cont’d)
HYS64T128020GU–5–A
Table 28
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
95
Module Serial Number (1)
xx
xx
96
Module Serial Number (2)
xx
xx
97
Module Serial Number (3)
xx
xx
98
Module Serial Number (4)
xx
xx
99 -127 Not Used
00
00
128-255 BLANK
FF
FF
Product Type
HYS64T64000HU–5–A
HYS72T64000HU–5–A
SPD Codes for HYS[64/72]T[32/64]000HU–5–A
HYS64T32000HU–5–A
Table 29
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
Data Sheet
54
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–5–A
HYS72T64000HU–5–A
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
HYS64T32000HU–5–A
Table 29
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
10
60
60
60
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
08
08
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
Not used
00
00
00
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
01
01
01
23
50
50
50
60
60
60
50
50
50
60
60
60
3C
3C
3C
28
1E
1E
3C
3C
3C
30
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
35
35
35
47
47
47
15
15
15
24
25
26
27
28
29
33
34
Data Sheet
55
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–5–A
HYS72T64000HU–5–A
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
HYS64T32000HU–5–A
Table 29
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
35
27
27
27
3C
3C
3C
28
28
28
38
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
3C
3C
3C
69
69
69
80
80
80
23
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
2D
2D
2D
46
PLL Relock Time
00
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
51
48
Psi(T-A) DRAM
72
78
78
49
∆ T0 (DT0)
42
32
32
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
23
24
24
51
∆ T2P (DT2P)
1D
1E
1E
52
∆ T3N (DT3N)
19
1B
1B
53
∆ T3P.fast (DT3P fast)
1C
1E
1E
36
37
41
42
43
44
54
∆ T3P.slow (DT3P slow)
16
17
17
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
2E
28
28
56
∆ T5B (DT5B)
1A
1B
1B
57
∆ T7 (DT7)
2D
1E
1E
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆ TPLL (DTPLL)
00
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
11
11
11
63
Checksum of Bytes 0-62
0B
23
35
Data Sheet
56
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–5–A
HYS72T64000HU–5–A
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
HYS64T32000HU–5–A
Table 29
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
36
77
Product Type, Char 5
32
34
34
78
Product Type, Char 6
30
30
30
79
Product Type, Char 7
30
30
30
80
Product Type, Char 8
30
30
30
81
Product Type, Char 9
48
48
48
82
Product Type, Char 10
55
55
55
83
Product Type, Char 11
35
35
35
84
Product Type, Char 12
41
41
41
85
Product Type, Char 13
20
20
20
86
Product Type, Char 14
20
20
20
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
Data Sheet
57
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64000HU–5–A
HYS72T64000HU–5–A
SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d)
HYS64T32000HU–5–A
Table 29
Organization
256 MB
512 MB
512 MB
×64
×64
×72
1 Rank (×16)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
99 -127
Not Used
00
00
00
128-255
BLANK
FF
FF
FF
Product Type
HYS72T128020HU–5–A
SPD Codes for HYS[64/72]T128020HU–5–A
HYS64T128020HU–5–A
Table 30
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
1
Total number of Bytes in EEPROM
08
08
2
Memory Type (DDR2)
08
08
3
Number of Row Addresses
0E
0E
4
Number of Column Addresses
0A
0A
5
DIMM Rank and Stacking Information
61
61
6
Data Width
40
48
7
Not used
00
00
8
Interface Voltage Level
05
05
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
60
60
10
Data Sheet
58
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–5–A
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
HYS64T128020HU–5–A
Table 30
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
11
Error Correction Support (non-ECC, ECC)
00
02
12
Refresh Rate and Type
82
82
13
Primary SDRAM Width
08
08
14
Error Checking SDRAM Width
00
08
15
Not used
00
00
16
Burst Length Supported
0C
0C
17
Number of Banks on SDRAM Device
04
04
18
Supported CAS Latencies
38
38
19
Not used
00
00
20
DIMM Type Information
02
02
21
DIMM Attributes
00
00
22
Component Attributes
01
01
23
50
50
60
60
50
50
30
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tCK @ CLmax -2 (Byte 18) [ns]
tAC SDRAM @ CLmax -2 [ns]
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
31
32
24
25
26
27
28
29
33
34
35
36
37
38
Data Sheet
60
60
3C
3C
1E
1E
3C
3C
2D
2D
Module Density per Rank
80
80
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
35
35
47
47
59
15
15
27
27
3C
3C
28
28
1E
1E
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–5–A
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
HYS64T128020HU–5–A
Table 30
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
39
Analysis Characteristics
00
00
40
00
00
3C
3C
69
69
80
80
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
2D
2D
46
PLL Relock Time
00
00
47
TCASE.max Delta / ∆ T4R4W Delta
51
51
48
Psi(T-A) DRAM
78
78
49
∆ T0 (DT0)
32
32
50
∆ T2N (DT2N, UDIMM) or ∆ T2Q ( (DT2Q, RDIMM)
24
24
51
∆ T2P (DT2P)
1E
1E
52
∆ T3N (DT3N)
1B
1B
53
∆ T3P.fast (DT3P fast)
1E
1E
41
42
43
44
54
∆ T3P.slow (DT3P slow)
17
17
55
∆ T4R (DT4R) / ∆ T4R4W S Sign (DT4R4W)
28
28
56
∆ T5B (DT5B)
1B
1B
57
∆ T7 (DT7)
1E
1E
58
Psi(ca) PLL
00
00
59
Psi(ca) REG
00
00
60
∆ TPLL (DTPLL)
00
00
61
∆ TREG (DTREG) / Toggle Rate
00
00
62
SPD Revision
11
11
63
Checksum of Bytes 0-62
24
36
64
JEDEC ID Code of Infineon (1)
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
Data Sheet
60
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS72T128020HU–5–A
SPD Codes for HYS[64/72]T128020HU–5–A (cont’d)
HYS64T128020HU–5–A
Table 30
Organization
1 GByte
1 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–3200U–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
73
Product Type, Char 1
36
37
74
Product Type, Char 2
34
32
75
Product Type, Char 3
54
54
76
Product Type, Char 4
31
31
77
Product Type, Char 5
32
32
78
Product Type, Char 6
38
38
79
Product Type, Char 7
30
30
80
Product Type, Char 8
32
32
81
Product Type, Char 9
30
30
82
Product Type, Char 10
48
48
83
Product Type, Char 11
55
55
84
Product Type, Char 12
35
35
85
Product Type, Char 13
41
41
86
Product Type, Char 14
20
20
87
Product Type, Char 15
20
20
88
Product Type, Char 16
20
20
89
Product Type, Char 17
20
20
90
Product Type, Char 18
20
20
91
Module Revision Code
2x
2x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95
Module Serial Number (1)
xx
xx
96
Module Serial Number (2)
xx
xx
97
Module Serial Number (3)
xx
xx
98
Module Serial Number (4)
xx
xx
99 -127
Not Used
00
00
128-255
BLANK
FF
FF
Data Sheet
61
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
Package Outlines
7.1
Raw Card A
0.1 A B C
7
133.35
0.3
128.95 ±0.1
1.27 ±0.1
30
4
C
1
120
4 ±0.1
2.5 ±0.1
2.7 MAX.
5 ±0.1
63 ±0.1
55 ±0.1
17.8 ±0.1
240
10 ±0.1
3.8
121
2.3 ±0.1
A
1.5 ±0.1
B
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1
0.8 ±0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 8
Data Sheet
GLD09652
Package Outline L-DIM-240-1
62
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
Raw Card B
0.1 A B C
7.2
133.35
0.4
128.95 ±0.1
1.27 ±0.1
30
4
C
1
120
4 ±0.1
2.5 ±0.1
4 MAX.
5 ±0.1
63 ±0.1
55 ±0.1
17.8 ±0.1
240
10 ±0.1
3.8
121
2.3 ±0.1
A
1.5 ±0.1
B
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1
0.8 ±0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 9
Data Sheet
GLD09653
Package Outline L-DIM-240-2
63
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7.3
Raw Card C
0.1 A B C
133.35
2.7 MAX.
30
4
4x
128.95
1
120
4
C
2.5
0.4
5
63
1.27 ±0.1
55
17.8
240
10
3.8
121
2.3 ±0.1
A
1.5 ±0.1
B
(3)
0.2
2.5 ±0.2
Detail of contacts
1
0.8 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Figure 10
Data Sheet
GLD09654
Package Outline L-DIM-240-3
64
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 31 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 32 and for components in Table 33.
Table 31
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512
16
0
A
C
–5
Table 32
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
INFINEON Modul Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
5
Raw Card Generation
0 .. 9
look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
look up table
8
Package, Lead-Free Status
A .. Z
look up table
9
Module Type
S
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
10
11
Speed Grade
Die Revision
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules
gives the overall module memory density in MBytes as listed in column “Coding”.
Data Sheet
65
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Table 33
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
INFINEON
Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL1.8
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
5+6
Number of I/Os
2G
2 Gbit
40
×4
80
×8
16
×16
7
Product Variations
0 .. 9
look up table
8
Die Revision
A
First
B
Second
C
FBGA,
lead-containing
F
FBGA, lead-free
–3.7
DDR2-533
–5
DDR2-400
9
Package,
Lead-Free Status
10
Speed Grade
11
Data Sheet
N/A for Components
66
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
www.infineon.com
Published by Infineon Technologies AG