Intersil ICL3232CBNZ One microamp supply-current, 3v to 5.5v, 250kbps, rs-232 transmitters/receiver Datasheet

ICL3221, ICL3222, ICL3223,
ICL3232, ICL3241, ICL3243
®
Data Sheet
March 1, 2006
One Microamp Supply-Current, +3V to +5.5V,
250kbps, RS-232 Transmitters/Receivers
The Intersil ICL32XX devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Targeted
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower
standby, power consumption is critical. Efficient on-chip
charge pumps, coupled with manual and automatic
powerdown functions (except for the ICL3232), reduce the
standby supply current to a 1µA trickle. Small footprint
packaging, and the use of small, low value capacitors ensure
board space savings as well. Data rates greater than
250kbps are guaranteed at worst case load conditions. This
family is fully compatible with 3.3V only systems, mixed 3.3V
and 5.0V systems, and 5.0V only systems.
The ICL324X are 3-driver, 5-receiver devices that provide a
complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting alwaysactive receivers for “wake-up” capability.
The ICL3221, ICL3223 and ICL3243, feature an
automatic powerdown function which powers down the
on-chip power-supply and driver circuits. This occurs when
an attached peripheral device is shut off or the RS-232
cable is removed, conserving system power automatically
without changes to the hardware or operating system.
These devices power up again when a valid RS-232
voltage is applied to any receiver input.
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XX 3V family.
FN4805.21
Features
• Pb-Free Plus Anneal Available as an Option
(RoHS Compliant) (See Ordering Info)
• 15kV ESD Protected (Human Body Model)
• Drop in Replacements for MAX3221, MAX3222,
MAX3223, MAX3232, MAX3241, MAX3243, SP3243
• ICL3221 is Low Power, Pin Compatible Upgrade for 5V
MAX221
• ICL3222 is Low Power, Pin Compatible Upgrade for 5V
MAX242, and SP312A
• ICL3232 is Low Power Upgrade for HIN232/ICL232 and
Pin Compatible Competitor Devices
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Powerdown Features (Except
ICL3232)
• Guaranteed Mouse Driveability (ICL324X Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
TABLE 1. SUMMARY OF FEATURES
NO. OF NO. OF
PART NUMBER
Tx.
Rx.
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWERDOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3221
1
1
0
250
Yes
No
Yes
Yes
ICL3222
2
2
0
250
Yes
No
Yes
No
ICL3223
2
2
0
250
Yes
No
Yes
Yes
ICL3232
2
2
0
250
No
No
No
No
ICL3241
3
5
2
250
Yes
No
Yes
No
ICL3243
3
5
1
250
No
No
Yes
Yes
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Ordering Information
PART NUMBER (NOTE 1)
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ICL3221CA
ICL3221CA
0 to 70
16 Ld SSOP
M16.209
ICL3221CAZ (Note 2)
ICL3221CAZ
0 to 70
16 Ld SSOP (Pb-free)
M16.209
ICL3221CV
ICL3221CV
0 to 70
16 Ld TSSOP
M16.173
ICL3221CVZ (Note 2)
3221CVZ
0 to 70
16 Ld TSSOP (Pb-free)
M16.173
ICL3221IA
ICL3221IA
-40 to 85
16 Ld SSOP
M16.209
ICL3221IAZ (Note 2)
ICL3221IAZ
-40 to 85
16 Ld SSOP (Pb-free)
M16.209
ICL3222CA
ICL3222CA
0 to 70
20 Ld SSOP
M20.209
ICL3222CAZ (Note 2)
ICL3222CAZ
0 to 70
20 Ld SSOP (Pb-free)
M20.209
ICL3222CB
ICL3222CB
0 to 70
18 Ld SOIC
M18.3
ICL3222CBZ (Note 2)
3222CBZ
0 to 70
18 Ld SOIC (Pb-free)
M18.3
ICL3222CP
ICL3222CP
0 to 70
18 Ld PDIP
E18.3
ICL3222CPZ (Note 2)
ICL3222CPZ
0 to 70
18 Ld PDIP* (Pb-free)
E18.3
ICL3222CV
ICL3222CV
0 to 70
20 Ld TSSOP
M20.173
ICL3222CVZ (Note 2)
ICL3222CVZ
0 to 70
20 Ld TSSOP (Pb-free)
M20.173
ICL3222IA
ICL3222IA
-40 to 85
20 Ld SSOP
M20.209
ICL3222IAZ (Note 2)
ICL3222IAZ
-40 to 85
20 Ld SSOP (Pb-free)
M20.209
ICL3222IB
ICL3222IB
-40 to 85
18 Ld SOIC
M18.3
ICL3222IV
ICL3222IV
-40 to 85
20 Ld TSSOP
M20.173
ICL3222IVZ (Note 2)
ICL3222IVZ
-40 to 85
20 Ld TSSOP (Pb-free)
M20.173
ICL3223CA
ICL3223CA
0 to 70
20 Ld SSOP
M20.209
ICL3223CAZ (Note 2)
ICL3223CAZ
0 to 70
20 Ld SSOP (Pb-free)
M20.209
ICL3223CP
ICL3223CP
0 to 70
20 Ld PDIP
E20.3
ICL3223CPZ (Note 2)
ICL3223CPZ
0 to 70
20 Ld PDIP* (Pb-free)
E20.3
ICL3223CV
ICL3223CV
0 to 70
20 Ld TSSOP
M20.173
ICL3223IA
ICL3223IA
-40 to 85
20 Ld SSOP
M20.209
ICL3223IAZ (Note 2)
ICL3223IAZ
-40 to 85
20 Ld SSOP (Pb-free)
M20.209
ICL3223IV
ICL3223IV
-40 to 85
20 Ld TSSOP
M20.173
ICL3223IVZ (Note 2)
ICL3223IVZ
-40 to 85
20 Ld TSSOP (Pb-free)
M20.173
ICL3232CA
ICL3232CA
0 to 70
16 Ld SSOP
M16.209
ICL3232CAZ (Note 2)
3232CAZ
0 to 70
16 Ld SSOP (Pb-free)
M16.209
ICL3232CB
ICL3232CB
0 to 70
16 Ld SOIC
M16.3
ICL3232CBZ (Note 2)
3232CBZ
0 to 70
16 Ld SOIC (Pb-free)
M16.3
ICL3232CBN
3232CBN
0 to 70
16 Ld SOIC (N)
M16.15
ICL3232CBNZ (Note 2)
3232CBNZ
0 to 70
16 Ld SOIC (N) (Pb-free)
M16.15
ICL3232CP
ICL3232CP
0 to 70
16 Ld PDIP
E16.3
ICL3232CPZ (Note 2)
ICL3232CPZ
0 to 70
16 Ld PDIP* (Pb-free)
E16.3
ICL3232CV
ICL3232CV
0 to 70
16 Ld TSSOP
M16.173
2
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Ordering Information
PART NUMBER (NOTE 1)
(Continued)
PART MARKING
TEMP. RANGE (°C)
ICL3232CVZ (Note 2)
3232CVZ
0 to 70
ICL3232IA
ICL3232IA
ICL3232IAZ (Note 2)
PACKAGE
PKG. DWG. #
16 Ld TSSOP (Pb-free)
M16.173
-40 to 85
16 Ld SSOP
M16.209
3232IAZ
-40 to 85
16 Ld SSOP (Pb-free)
M16.209
ICL3232IB
ICL3232IB
-40 to 85
16 Ld SOIC
M16.3
ICL3232IBZ (Note 2)
3232IBZ
-40 to 85
16 Ld SOIC (Pb-free)
M16.3
ICL3232IBN
3232IBN
-40 to 85
16 Ld SOIC (N)
M16.15
ICL3232IBNZ (Note 2)
3232IBNZ
-40 to 85
16 Ld SOIC (N) (Pb-free)
M16.15
ICL3232IV
ICL3232IV
-40 to 85
16 Ld TSSOP
M16.173
ICL3232IVZ (Note 2)
3232IVZ
-40 to 85
16 Ld TSSOP (Pb-free)
M16.173
ICL3241CA
ICL3241CA
0 to 70
28 Ld SSOP
M28.209
ICL3241CAZ (Note 2)
ICL3241CAZ
0 to 70
28 Ld SSOP (Pb-free)
M28.209
ICL3241CB
ICL3241CB
0 to 70
28 Ld SOIC
M28.3
ICL3241CBZ (Note 2)
ICL3241CBZ
0 to 70
28 Ld SOIC (Pb-free)
M28.3
ICL3241CV
ICL3241CV
0 to 70
28 Ld TSSOP
M28.173
ICL3241CVZ (Note 2)
ICL3241CVZ
0 to 70
28 Ld TSSOP (Pb-free)
M28.173
ICL3241IA
ICL3241IA
-40 to 85
28 Ld SSOP
M28.209
ICL3241IAZ (Note 2)
ICL3241IAZ
-40 to 85
28 Ld SSOP (Pb-free)
M28.209
ICL3241IB
ICL3241IB
-40 to 85
28 Ld SOIC
M28.3
ICL3241IBZ (Note 2)
ICL3241IBZ
-40 to 85
28 Ld SOIC (Pb-free)
M28.3
ICL3241IV
ICL3241IV
-40 to 85
28 Ld TSSOP
M28.173
ICL3241IVZ (Note 2)
ICL3241IVZ
-40 to 85
28 Ld TSSOP (Pb-free)
M28.173
ICL3243CA
ICL3243CA
0 to 70
28 Ld SSOP
M28.209
ICL3243CAZ (Note 2)
ICL3243CAZ
0 to 70
28 Ld SSOP (Pb-free)
M28.209
ICL3243CB
ICL3243CB
0 to 70
28 Ld SOIC
M28.3
ICL3243CBZ (Note 2)
ICL3243CBZ
0 to 70
28 Ld SOIC (Pb-free)
M28.3
ICL3243CV
ICL3243CV
0 to 70
28 Ld TSSOP
M28.173
ICL3243CVZ (Note 2)
ICL3243CVZ
0 to 70
28 Ld TSSOP (Pb-free)
M28.173
ICL3243IA
ICL3243IA
-40 to 85
28 Ld SSOP
M28.209
ICL3243IAZ (Note 2)
ICL3243IAZ
-40 to 85
28 Ld SSOP (Pb-free)
M28.209
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTES:
1. Most surface mount devices are available on tape and reel; add “-T” to suffix.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Pinouts
ICL3221 (SSOP, TSSOP)
TOP VIEW
16 FORCEOFF
EN 1
C1+ 2
15 VCC
3
14 GND
V+
C1- 4
13 T1OUT
C2+ 5
12 FORCEON
C2- 6
11 T1IN
10 INVALID
V- 7
9 R1OUT
R1IN 8
ICL3222 (PDIP, SOIC)
TOP VIEW
EN 1
17 VCC
3
16 GND
V+
C1- 4
15 T1OUT
C2+ 5
14 R1IN
C2- 6
13 R1OUT
V- 7
12 T1IN
T2OUT 8
11 T2IN
R2IN 9
ICL3222 (SSOP, TSSOP)
TOP VIEW
20 SHDN
EN 1
18 SHDN
C1+ 2
10 R2OUT
ICL3223 (PDIP, SSOP, TSSOP)
TOP VIEW
20 FORCEOFF
EN 1
C1+ 2
19 VCC
3
18 GND
V+
C1- 4
17 T1OUT
C1- 4
17 T1OUT
C2+ 5
16 R1IN
C2+ 5
16 R1IN
C2- 6
15 R1OUT
C2- 6
15 R1OUT
V+
V-
14 NC
7
C1+ 2
19 VCC
3
18 GND
V-
14 FORCEON
7
T2OUT 8
13 T1IN
T2OUT 8
13 T1IN
R2IN 9
12 T2IN
R2IN 9
12 T2IN
11 NC
R2OUT 10
ICL3232 (PDIP, SOIC, SSOP, TSSOP)
TOP VIEW
C1+ 1
V+ 2
C1-
3
11 INVALID
R2OUT 10
ICL3241 (SOIC, SSOP, TSSOP)
TOP VIEW
16 VCC
C2+ 1
28 C1+
15 GND
C2- 2
27 V+
14 T1OUT
V-
3
26 VCC
C2+ 4
13 R1IN
R1IN 4
25 GND
C2- 5
12 R1OUT
R2IN 5
24 C1-
11 T1IN
R3IN 6
23 EN
10 T2IN
R4IN 7
22 SHDN
V-
6
T2OUT 7
9 R2OUT
R2IN 8
4
R5IN 8
21 R1OUTB
T1OUT 9
20 R2OUTB
T2OUT 10
19 R1OUT
T3OUT 11
18 R2OUT
T3IN 12
17 R3OUT
T2IN 13
16 R4OUT
T1IN 14
15 R5OUT
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Pinouts
(Continued)
ICL3243 (SOIC, SSOP, TSSOP)
TOP VIEW
C2+ 1
28 C1+
C2- 2
27 V+
3
26 VCC
R1IN 4
25 GND
R2IN 5
24 C1-
R3IN 6
23 FORCEON
R4IN 7
22 FORCEOFF
R5IN 8
21 INVALID
T1OUT 9
20 R2OUTB
V-
T2OUT 10
19 R1OUT
T3OUT 11
18 R2OUT
T3IN 12
17 R3OUT
T2IN 13
16 R4OUT
T1IN 14
15 R5OUT
Pin Descriptions
PIN
VCC
FUNCTION
System power supply input (3.0V to 5.5V).
V+
Internally generated positive transmitter supply (+5.5V).
V-
Internally generated negative transmitter supply (-5.5V).
GND
Ground connection.
C1+
External capacitor (voltage doubler) is connected to this lead.
C1-
External capacitor (voltage doubler) is connected to this lead.
C2+
External capacitor (voltage inverter) is connected to this lead.
C2-
External capacitor (voltage inverter) is connected to this lead.
TIN
TTL/CMOS compatible transmitter Inputs.
TOUT
RS-232 level (nominally ±5.5V) transmitter outputs.
RIN
RS-232 compatible receiver inputs.
ROUT
TTL/CMOS level receiver outputs.
ROUTB
INVALID
EN
SHDN
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low receiver enable control; doesn’t disable ROUTB outputs.
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table 2).
FORCEON
Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
5
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Typical Operating Circuits
ICL3221
ICL3222
C3 (OPTIONAL CONNECTION, NOTE)
C3 (OPTIONAL CONNECTION, NOTE)
VCC
V+
V- 7
T1
11
T1IN
13
9
R1OUT
3
8
+ C3
0.1µF
C4
+ 0.1µF
T1OUT
R1IN
5kΩ
R1
1 EN
FORCEOFF
12
INVALID
FORCEON
GND
16
10
VCC
C1
0.1µF
+
C2
0.1µF
+
4
5
6
+
17
C1+
3
V+
+
T1
15
T2
8
14
13
R1OUT
5kΩ
R1
C4
0.1µF
T1OUT
T2OUT
R1IN
9
10
R2OUT
+ C3
0.1µF
7
V-
C2-
11
T2IN
VCC
C1C2+
12
T1IN
TO POWER
CONTROL
LOGIC
2
RS-232
LEVELS
C1+
C15
+ C2+
6
C2-
C2
0.1µF
+
0.1µF
15
TTL/CMOS
LOGIC LEVELS
2
+
4
C1
0.1µF
TTL/CMOS
LOGIC LEVELS
+3.3V
0.1µF
RS-232
LEVELS
+
+
+3.3V
1 EN
R2IN
5kΩ
R2
14
GND
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
SHDN
18
VCC
16
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
ICL3223
R1OUT
C1C2+
V- 7
C2T1
13
17
T2
12
8
15
16
5kΩ
R1
R2OUT
V+
10
1
9
EN
5kΩ
R2
FORCEOFF
14
3
INVALID
FORCEON
GND
20
11
+ C3
0.1µF
C4
0.1µF
+
+
+
C2
0.1µF
+
T1IN
T2OUT
R1IN
R2IN
T2IN
R1OUT
VCC
3
4
5
11
10
C1+
16
VCC
V+
C1C2+
V-
C2T1
2
+ C3
0.1µF
6
C4
0.1µF
+
14
T2
7
13
12
R1
R2OUT
TO POWER
CONTROL LOGIC
1
C1
0.1µF
T1OUT
0.1µF
T1OUT
T2OUT
R1IN
RS-232
LEVELS
5
+
6
VCC
+3.3V
+
C2
0.1µF
C1+
19
TTL/CMOS
LOGIC LEVELS
2
+
4
T2IN
C3 (OPTIONAL CONNECTION, NOTE)
0.1µF
C1
0.1µF
T1IN
TTL/CMOS
LOGIC LEVELS
+
RS-232
LEVELS
+3.3V
ICL3232
5kΩ
9
8
R2
R2IN
5kΩ
GND
15
18
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
6
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
(Continued)
ICL3241
V+
V-
14
T1
13
T2
12
T3
27
3
9
10
TTL/CMOS
LOGIC LEVELS
R2OUTB
R1OUT
+
T1IN
T1OUT
T2OUT
T2IN
24
1
2
27
V+
C1C2+
V-
C2-
14
T1
13
T2
12
T3
3
9
10
+
C3
0.1µF
C4
0.1µF
+
T1OUT
T2OUT
11
T3OUT
20
19
4
19
R1IN
5kΩ
18
5
R2IN
4
R1OUT
R1IN
R1
R2OUT
17
5
R2
R3IN
5kΩ
16
R4OUT
6
R3OUT
R3IN
R3
R4OUT
7
7
8
R5OUT
EN
SHDN
5kΩ
R5
GND
25
7
R4
5kΩ
15
R5IN
5kΩ
16
R4IN
R4
R5OUT
22
21
R4IN
5kΩ
15
23
VCC
R2IN
5kΩ
17
6
R3
5kΩ
18
5kΩ
R3OUT
22
VCC
R2OUTB
20
23
26
C1+
T3IN
21
R2
VCC
C2
0.1µF
T3OUT
R1
R2OUT
C4
0.1µF
+
28
+
11
T3IN
R1OUTB
+ C3
0.1µF
0.1µF
RS-232
LEVELS
T2IN
VCC
+
C1
0.1µF
TO POWER
CONTROL LOGIC
T1IN
28
C1+
+
24
C11
C2+
+
2
C2-
26
TTL/CMOS
LOGIC LEVELS
C2
0.1µF
0.1µF
RS-232
LEVELS
C1
0.1µF
+3.3V
+
RS-232
LEVELS
+3.3V
ICL3243
RS-232
LEVELS
Typical Operating Circuits
8
5kΩ
R5
R5IN
FORCEON
FORCEOFF
INVALID
GND
25
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
90
18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
80
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
77
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . .
100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . .
115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .
100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
ICL32XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All RIN Open, FORCEON = GND, FORCEOFF = VCC
(ICL3221, ICL3223, ICL3243 Only)
25
-
1.0
10
µA
Supply Current, Powerdown
FORCEOFF = SHDN = GND (Except ICL3232)
25
-
1.0
10
µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded,
FORCEON = FORCEOFF =
SHDN = VCC
VCC = 3.15V,
ICL3221-32
25
-
0.3
1.0
mA
VCC = 3.0V, ICL3241-43
25
-
0.3
1.0
mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
TIN, FORCEON, FORCEOFF, EN, SHDN
Full
-
-
0.8
V
Input Logic Threshold High
TIN, FORCEON, FORCEOFF, EN, VCC = 3.3V
SHDN
VCC = 5.0V
Full
2.0
-
-
V
Full
2.4
-
-
V
Input Leakage Current
TIN, FORCEON, FORCEOFF, EN, SHDN
Full
-
±0.01
±1.0
µA
Output Leakage Current
(Except ICL3232)
FORCEOFF = GND or EN = VCC
Full
-
±0.05
±10
µA
Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
Output Voltage High
IOUT = -1.0mA
Full
-
V
VCC -0.6 VCC -0.1
AUTOMATIC POWERDOWN (ICL3221, ICL3223, ICL3243 Only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters
ICL32XX Powers Up (See Figure 6)
Full
-2.7
-
2.7
V
Receiver Input Thresholds to
Disable Transmitters
ICL32XX Powers Down (See Figure 6)
Full
-0.3
-
0.3
V
INVALID Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
INVALID Output Voltage High
IOUT = -1.0mA
Full
VCC-0.6
-
-
V
8
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
Electrical Specifications
TEMP
(°C)
MIN
TYP
MAX
UNITS
Receiver Threshold to
Transmitters Enabled Delay (tWU)
25
-
100
-
µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25
-
1
-
µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25
-
30
-
µs
PARAMETER
TEST CONDITIONS
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
Input Threshold High
Full
-25
-
25
V
VCC = 3.3V
25
0.6
1.2
-
V
VCC = 5.0V
25
0.8
1.5
-
V
VCC = 3.3V
25
-
1.5
2.4
V
VCC = 5.0V
25
-
1.8
2.4
V
Input Hysteresis
25
-
0.3
-
V
Input Resistance
25
3
5
7
kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
All Transmitter Outputs Loaded with 3kΩ to Ground
Full
±5.0
±5.4
-
V
Output Resistance
VCC = V+ = V- = 0V, Transmitter Output = ±2V
Full
300
10M
-
Ω
Full
-
±35
±60
mA
Full
-
-
±25
µA
T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ to
GND, T1OUT and T2OUT Loaded with 2.5mA Each
Full
±5
-
-
V
Maximum Data Rate
RL = 3kΩ, CL = 1000pF, One Transmitter Switching
Full
250
500
-
kbps
Receiver Propagation Delay
Receiver Input to Receiver
Output, CL = 150pF
tPHL
25
-
0.3
-
µs
tPLH
25
-
0.3
-
µs
Output Short-Circuit Current
VOUT = ±12V, VCC = 0V or 3V to 5.5V
Automatic Powerdown or FORCEOFF = SHDN = GND
Output Leakage Current
MOUSE DRIVEABILITY (ICL324X Only)
Transmitter Output Voltage
(See Figure 9)
TIMING CHARACTERISTICS
Receiver Output Enable Time
Normal Operation (Except ICL3232)
25
-
200
-
ns
Receiver Output Disable Time
Normal Operation (Except ICL3232)
25
-
200
-
ns
Transmitter Skew
tPHL - tPLH
Full
-
200
1000
ns
Receiver Skew
tPHL - tPLH
Full
-
100
500
ns
Transition Region Slew Rate
VCC = 3.3V,
RL = 3kΩ to 7kΩ,
Measured From 3V to -3V or -3V
to 3V
CL = 200pF to 2500pF
25
4
8.0
30
V/µs
CL = 200pF to 1000pF
25
6
-
30
V/µs
Human Body Model
ICL3221 - ICL3243
25
-
±15
-
kV
IEC61000-4-2 Contact Discharge ICL3221 - ICL3243
25
-
±8
-
kV
IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232
25
-
±8
-
kV
ICL3241 - ICL3243
25
-
±6
-
kV
ICL3221 - ICL3243
25
-
±2
-
kV
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
All Other Pins
Human Body Model
9
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Detailed Description
ICL32XX interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
Charge-Pump
Intersil’s new ICL32XX family utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions at VCC = 3.3V. See
the Capacitor Selection section, and Table 3 for capacitor
recommendations for other operating conditions. The charge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal
values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Except for the ICL3232, all transmitter outputs disable and
assume a high impedance state when the device enters the
powerdown mode (See Table 2). These outputs may be
driven to ±12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32XX devices contain standard inverting receivers
that three-state (except for the ICL3232) via the EN or
FORCEOFF control lines. Additionally, the two ICL324X
products include noninverting (monitor) receivers (denoted
by the ROUTB label) that are always active, regardless of the
state of any control lines. All the receivers convert RS-232
signals to CMOS output levels and accept inputs up to ±25V
while presenting the required 3kΩ to 7kΩ input impedance
(See Figure 1) even if the power is off (VCC = 0V). The
receivers’ Schmitt trigger input stage uses hysteresis to
increase noise immunity and decrease errors due to slow
input signal transitions.
10
The ICL3221/22/23/41 inverting receivers disable only when
EN is driven high. ICL3243 receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(See Table 2).
ICL324X monitor receivers remain active even during
manual powerdown and forced receiver disable, making
them extremely useful for Ring Indicator monitoring.
Standard receivers driving powered down peripherals must
be disabled to prevent current flow through the peripheral’s
protection diodes (See Figures 2 and 3). This renders them
useless for wake up functions, but the corresponding
monitor receiver can be dedicated to this task as shown in
Figure 3.
VCC
RXIN
-25V ≤ VRIN ≤ +25V
RXOUT
5kΩ
GND ≤ VROUT ≤ VCC
GND
FIGURE 1. INVERTING RECEIVER CONNECTIONS
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at VCC = 5.5V, during normal operation (not in
powerdown mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching
to this new family.
Pin Compatible Replacements For 5V Devices
The ICL3221/22/32 are pin compatible with existing 5V
RS-232 transceivers - see the Features section on the front
page for details.
This pin compatibility coupled with the low Icc and wide
operating supply range, make the ICL32XX potential lower
power, higher performance drop-in replacements for existing
5V applications. As long as the ±5V RS-232 output swings
are acceptable, and transmitter input pull-up resistors aren’t
required, the ICL32XX should work in most 5V applications.
When replacing a device in an existing 5V application, it is
acceptable to terminate C3 to VCC as shown on the Typical
Operating Circuit. Nevertheless, terminate C3 to GND if
possible, as slightly better performance results from this
configuration.
Powerdown Functionality (Except ICL3232)
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1µA, because the on-chip charge
pump turns off (V+ collapses to VCC, V- collapses to GND),
and the transmitter outputs three-state. Inverting receiver
outputs may or may not disable in powerdown; refer to
Table 2 for details. This micro-power mode makes these
devices ideal for battery powered and portable applications.
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Software Controlled (Manual) Powerdown
The ICL3221, ICL3223, and ICL3243 utilize a two pin
approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and powerdown modes, under logic
or software control, only the FORCEOFF input need be
driven. The FORCEON state isn’t critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown
circuitry. ICL3243 inverting (standard) receiver outputs also
disable when the device is in manual powerdown, thereby
eliminating the possible current path through a shutdown
peripheral’s input protection diode (See Figures 2 and 3).
Most devices in the ICL32XX family provide pins that allow
the user to force the IC into the low power, standby state.
On the ICL3222 and ICL3241, the powerdown control is via
a simple shutdown (SHDN) pin. Driving this pin high enables
normal operation, while driving it low forces the IC into its
powerdown state. Connect SHDN to VCC if the powerdown
function isn’t needed. Note that all the receiver outputs
remain enabled during shutdown (See Table 2). For the
lowest power consumption during powerdown, the receivers
should also be disabled by driving the EN input high (See
next section, and Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
FORCEOFF
(NOTE 4)
ROUTB
OR SHDN FORCEON
EN
TRANSMITTER RECEIVER
INVALID
INPUT
INPUT
INPUT
OUTPUTS
OUTPUTS OUTPUTS OUTPUT
MODE OF OPERATION
ICL3222, ICL3241
N.A.
L
N.A.
L
High-Z
Active
Active
N.A.
Manual Powerdown
N.A.
L
N.A.
H
High-Z
High-Z
Active
N.A.
Manual Powerdown w/Rcvr. Disabled
N.A.
H
N.A.
L
Active
Active
Active
N.A.
Normal Operation
N.A.
H
N.A.
H
Active
High-Z
Active
N.A.
Normal Operation w/Rcvr. Disabled
No
H
H
L
Active
Active
N.A.
L
No
H
H
H
Active
High-Z
N.A.
L
Yes
H
L
L
Active
Active
N.A.
H
Yes
H
L
H
Active
High-Z
N.A.
H
No
H
L
L
High-Z
Active
N.A.
L
No
H
L
H
High-Z
High-Z
N.A.
L
Yes
L
X
L
High-Z
Active
N.A.
H
Manual Powerdown
Yes
L
X
H
High-Z
High-Z
N.A.
H
Manual Powerdown w/Rcvr. Disabled
No
L
X
L
High-Z
Active
N.A.
L
Manual Powerdown
No
L
X
H
High-Z
High-Z
N.A.
L
Manual Powerdown w/Rcvr. Disabled
No
H
H
N.A.
Active
Active
Active
L
Normal Operation
(Auto Powerdown Disabled)
Yes
H
L
N.A.
Active
Active
Active
H
Normal Operation
(Auto Powerdown Enabled)
No
H
L
N.A.
High-Z
Active
Active
L
Powerdown Due to Auto Powerdown
Logic
Yes
L
X
N.A.
High-Z
High-Z
Active
H
Manual Powerdown
No
L
X
N.A.
High-Z
High-Z
Active
L
Manual Powerdown
ICL3221, ICL3223
Normal Operation
(Auto Powerdown Disabled)
Normal Operation
(Auto Powerdown Enabled)
Powerdown Due to Auto Powerdown
Logic
ICL3243
NOTE:
4. Applies only to the ICL3241 and ICL3243.
11
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
The INVALID output always indicates whether or not a valid
RS-232 signal is present at any of the receiver inputs (See
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
automatic powerdown feature, enabling them to function as
a manual SHUTDOWN input (See Figure 4).
VCC
FORCEON
INVALID
ICL3221/23/43
I/O
UART
CPU
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic powerdown is being utilized, the
RS-232 device will reenter powerdown if valid receiver levels
aren’t reestablished within 30µs of the ICL32XX powering
up. Figure 5 illustrates a circuit that keeps the ICL32XX from
initiating automatic powerdown for 100ms after powering up.
This gives the slow-to-wake peripheral circuit time to
reestablish valid RS-232 output levels.
VCC
CURRENT
FLOW
VCC
FORCEOFF
PWR
MGT
LOGIC
VOUT = VCC
Rx
POWERED
DOWN
UART
Tx
SHDN = GND
GND
OLD
RS-232 CHIP
POWER
MANAGEMENT
UNIT
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
MASTER POWERDOWN LINE
0.1µF
FORCEOFF
1MΩ
FORCEON
ICL3221/23/43
VCC
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
ICL324X
Automatic Powerdown (ICL3221/23/43 Only)
VCC
R2OUTB
RX
POWERED
DOWN
UART
VOUT = HI-Z
R2OUT
TX
R2IN
T1IN
T1OUT
FORCEOFF = GND
OR SHDN = GND, EN = VCC
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
12
Even greater power savings is available by using the
devices which feature an automatic powerdown function.
When no valid RS-232 voltages (See Figure 6) are sensed
on any receiver input for 30µs, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. The ICL32XX
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
2.7V
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
0.3V
INVALID LEVEL - POWERDOWN OCCURS AFTER 30ms
Capacitor Selection
-0.3V
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
-2.7V
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
Automatic powerdown operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input.
Table 2 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (See Figure 7). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry. When automatic
powerdown is utilized, INVALID = 0 indicates that the
ICL32XX is in powerdown mode.
RECEIVER
INPUTS
INVALID
} REGION
VCC
0
tINVH
tINVL
PWR UP
AUTOPWDN
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
VCC
(V)
C1
(µF)
C2, C3, C4
(µF)
3.0 to 3.6
0.1
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.1
0.47
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
when driving the input of a powered down (VCC = GND)
peripheral (See Figure 2). The enable input has no effect on
transmitter nor monitor (ROUTB) outputs.
V+
Operation Down to 2.7V
ICL32XX transmitter outputs meet RS-562 levels (±3.7V), at
full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
VCC
0
V-
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
The time to recover from automatic powerdown mode is
typically 100µs.
Receiver ENABLE Control (ICL3221/22/23/41 Only)
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
13
Transmitter Outputs when Exiting
Powerdown
Figure 8 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
5V/DIV
for a single transmitter driving 1000pF and an RS-232 load
at 250kbps. The static transmitters were also loaded with an
RS-232 receiver.
FORCEOFF
T1
VCC
+
0.1µF
2V/DIV
+
C1
C1+
VCC
V+
+
C3
C1T2
+
C2
VCC = +3.3V
C1 - C4 = 0.1µF
V-
C4
+
C2TIN
TIME (20µs/DIV)
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
Mouse Driveability
The ICL324X have been specifically designed to power a
serial mouse while operating from low voltage supplies.
Figure 9 shows the transmitter output voltages under
increasing load current. The on-chip switching regulator
ensures the transmitters will supply at least ±5V during worst
case conditions (15mA for paralleled V+ transmitters, 7.3mA
for single V- transmitter). The Automatic Powerdown feature
does not work with a mouse, so FORCEOFF and
FORCEON should be connected to VCC.
VCC
TOUT
ROUT
RIN
EN
5K
1000pF
SHDN OR
FORCEOFF
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV
T1IN
T1OUT
6
TRANSMITTER OUTPUT VOLTAGE (V)
ICL32XX
C2+
5
VOUT+
4
3
VCC = 3.0V
2
1
R1OUT
T1
0
VCC = +3.3V
C1 - C4 = 0.1µF
VOUT+
-1
5µs/DIV
T2
-2
ICL3241/43
-3
-4
VCC
T3
1
2
FIGURE 11. LOOPBACK TEST AT 120kbps
VOUT -
VOUT -
-5
-6
0
3
4
5
6
7
8
9
10
LOAD CURRENT PER TRANSMITTER (mA)
5V/DIV.
T1IN
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
T1OUT
High Data Rates
The ICL32XX maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 10 details a
transmitter loopback test circuit, and Figure 11 illustrates the
loopback test result at 120kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
1000pF, at 120kbps. Figure 12 shows the loopback results
14
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 12. LOOPBACK TEST AT 250kbps
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ICL32XX inputs, but ICL32XX outputs do not reach the
minimum VIH for these logic families. See Table 4 for more
information.
Typical Performance Curves
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
VCC
SYSTEM
POWER-SUPPLY SUPPLY
VOLTAGE
VOLTAGE
(V)
(V)
3.3
5
5
5
3.3
Compatible with all TTL and
CMOS logic families.
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
25
VOUT+
4
SLEW RATE (V/µs)
20
2
1 TRANSMITTER AT 250kbps
1 OR 2 TRANSMITTERS AT 30kbps
0
-2
15
-SLEW
+SLEW
10
VOUT -
-4
-6
0
1000
2000
3000
4000
5
5000
0
1000
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
3000
4000
5000
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
45
45
ICL3221
ICL3222 - ICL3232
40
35
SUPPLY CURRENT (mA)
40
250kbps
30
25
20
120kbps
15
10
20kbps
5
0
2000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
Compatible with all CMOS
families.
VCC = 3.3V, TA = 25°C
6
TRANSMITTER OUTPUT VOLTAGE (V)
3.3
COMPATIBILITY
250kbps
35
30
25
120kbps
20
15
20kbps
10
5
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
15
0
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Typical Performance Curves
3.5
ICL324X
40
250kbps
35
30
120kbps
25
20
20kbps
15
10
ICL3221 - ICL3232
2.5
2.0
1.5
1.0
ICL324X
0.5
ICL324X
5
0
NO LOAD
ALL OUTPUTS STATIC
3.0
SUPPLY CURRENT (mA)
45
SUPPLY CURRENT (mA)
VCC = 3.3V, TA = 25°C (Continued)
0
2000
1000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221: 286
ICL3222: 338
ICL3223: 357
ICL3232: 296
ICL324X: 464
PROCESS:
Si Gate CMOS
16
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.355
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
N
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.204
18.66
16
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
16
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
17
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Dual-In-Line Plastic Packages (PDIP)
N
E18.3 (JEDEC MS-001-BC ISSUE D)
E1
INDEX
AREA
1 2 3
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AD
-C-
SEATING
PLANE
A2
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
C
L
B
0.014
0.022
0.356
0.558
-
eA
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.845
0.880
21.47
D1
0.005
-
0.13
-
5
A
L
MAX
A1
E
BASE
PLANE
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
22.35
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
18
18
9
Rev. 2 11/03
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
18
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
19
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
e
A2
B S
0.002
0.246
L
0.020
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
0.026 BSC
E
N
NOTES:
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
6.50
0.70
16
8o
0o
6
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
20
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
INDEX
AREA
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
A
D
-C-
α
e
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.233
0.255
5.90
6.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
A1
B
0.25(0.010) M
L
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.026 BSC
H
0.292
L
0.022
N
α
NOTES:
MILLIMETERS
0.65 BSC
0.322
7.40
0.037
0.55
16
0°
-
8.20
-
0.95
6
16
8°
0°
7
8°
Rev. 3
6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
21
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
INDEX
AREA
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
22
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
M18.3 (JEDEC MS-013-AB ISSUE C)
N
INDEX
AREA
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4469
0.4625
11.35
11.75
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
18
0°
18
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
23
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
SYMBOL
3
L
0.05(0.002)
-A-
MAX
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
A
D
-C-
α
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MIN
c
0.10(0.004)
C A M
B S
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
0.65 BSC
α
20
0o
20
7
8o
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
24
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Shrink Small Outline Plastic Packages (SSOP)
M20.209 (JEDEC MO-150-AE ISSUE B)
N
INDEX
AREA
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
E
2
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
B M
A
D
-C-
α
e
A1
B
0.25(0.010) M
L
MIN
MAX
A2
C
B S
MAX
NOTES
A
0.068
0.078
1.73
1.99
0.002
0.008’
0.05
0.21
A2
0.066
0.070’
1.68
1.78
B
0.010’
0.015
0.25
0.38
C
0.004
0.008
0.09
0.20’
D
0.278
0.289
7.07
7.33
3
E
0.205
0.212
5.20’
5.38
4
0.026 BSC
0.301
0.311
7.65
7.90’
L
0.025
0.037
0.63
0.95
8 deg.
0 deg.
N
20
0 deg.
9
0.65 BSC
H
α
NOTES:
MILLIMETERS
MIN
A1
e
0.10(0.004)
C A M
SYMBOL
6
20
7
8 deg.
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
25
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
A2
c
0.10(0.004)
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
28
0o
28
7
8o
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
26
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
INDEX
AREA
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
A
D
-C-
α
e
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.390
0.413
9.90
10.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
A1
B
0.25(0.010) M
L
B S
NOTES:
0.026 BSC
H
0.292
L
0.022
N
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MILLIMETERS
0.65 BSC
0.322
7.40
0.037
0.55
28
0°
-
0.95
6
28
8°
0°
-
8.20
7
8°
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
27
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
10.00
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
28
0o
10.65
-
0.394
N
0.419
1.27 BSC
H
α
NOTES:
MAX
A1
e
α
MIN
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
28
FN4805.21
March 1, 2006