Qimonda HYE18M1G160BF-7.5 1-gbit x16 ddr mobile-ram Datasheet

March 2007
HYB18M1G16[0/1]BF–6
HYE18M1G16[0/1]BF–6
HYB18M1G16[0/1]BF–7.5
HYE18M1G16[0/1]BF–7.5
DRAMs for Mobile Applications
1-Gbit x16 DDR Mobile-RAM
RoHS compliant
Data S heet
Rev.1.0
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
HYB18M1G16[0/1]BF–6, HYE18M1G16[0/1]BF–6, HYB18M1G16[0/1]BF–7.5
Revision History: 2007-03, Rev.1.0
Page
Subjects (major changes since last revision)
52, 54
Tables updated
Previous Revision: Rev. 0.61, 2007-02
53
Table 21 updated
Previous Revision: Rev. 0.60, 2006-11
All
New Qimonda Template
Updates see Change List
Rev.1.0, 2007-03
10242006-Y557-TZXW
2
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low power DDR 1Gbit x16 dual die implementation
Each die organized as 4 banks x 8 MBit x 16
2 KByte page size
Two Chip Selects (2 CS) for reducing power consumption
Options for one CKE and two CKEs are available. Option with second CKE provides futher power saving
Double-data-rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver
DQS is edge-aligned with data for READs and center-aligned with data for WRITEs
Differential clock input (CK / CK)
Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS
Four internal banks for concurrent operation
Programmable CAS latency: 2 and 3
Programmable burst length: 2, 4, 8 and 16
Programmable drive strength (full, half, quarter)
Auto refresh and self refresh modes
8192 refresh cycles / 64ms
Auto precharge
Commercial (-0°C to +70°C) and Extended (-25°C to +85°C) operating temperature ranges
60-ball PG-VFBGA-60-6 package (11 × 10.5 × 1.0 mm)
RoHS Compliant Product1)
Power Saving Features
•
•
•
•
•
•
Low supply voltages: VDD = 1.70 V − 1.90 V, VDDQ = 1.70 V − 1.90 V
Optimized operating (IDD0, IDD4), self refresh (IDD6) and standby currents (IDD2, IDD3)
DDR I/O scheme with no DLL
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Clock Stop, Power-Down and Deep Power-Down modes
TABLE 1
Performance
Part Number Speed Code
Clock Frequency (fCKmax)
-6
- 7.5
Unit
CL = 3
166
133
MHz
CL = 2
83
66
MHz
5.5
6.5
ns
Access Time (tACmax)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.1.0, 2007-03
10242006-Y557-TZXW
3
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 2
Memory Addressing Scheme
Item
Addresses
Banks
BA0, BA1
Rows
A0 - A12
Columns
A0 - A9
TABLE 3
Ordering Information
Type1)
Description
Commercial Temperature Range
HYB18M1G160BF-6
HYB18M1G161BF-6
HYB18M1G160BF-7.5
HYB18M1G161BF-7.5
166 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, one CKE (CKE)
166 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, two CKE (CKE0 and CKE1)
133 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, one CKE (CKE)
133 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, two CKE (CKE0 and CKE1)
Extended Temperature Range
HYE18M1G160BF-6
HYE18M1G161BF-6
HYE18M1G160BF-7.5
HYE18M1G161BF-7.5
166 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, one CKE (CKE)
166 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, two CKE (CKE0 and CKE1)
133 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, one CKE (CKE)
133 MHz 4 Banks × 8 Mbit × 16 Low Power DDR Mobile-RAM, two CKE (CKE0 and CKE1)
1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range)
18M: 1.8V DDR Mobile-RAM
1G: 1Gbit density
160: 16 bit interface width; DDR-Mobile-RAM - One CKE (CKE)
161: 16 bit interface width; DDR-Mobile-RAM - Two CKE (CKE0 and CKE1)
B: die revision
F: green product
- 6/-7.5: speed grades (min. clock cycle time)
Rev.1.0, 2007-03
10242006-Y557-TZXW
4
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
1.2
Ball Configuration
FIGURE 1
Standard ballout 1-Gbit DDR Mobile-RAM with 1CKE (CKE)
966
'4
9664
$
9''4
'4
9''
9''4
'4
'4
%
'4
'4
9664
9664
'4
'4
&
'4
'4
9''4
9''4
'4
'4
'
'4
'4
9664
9664
8'46
'4
(
'4
/'46
9''4
966
8'0
1&
)
&6
/'0
9''
&.(
&.
&.
*
:(
&$6
5$6
$
$
$
+
&6
%$
%$
$
$
$
-
$$3
$
$
$
9''
966
$
$
.
$
FIGURE 2
Standard ballout 1-Gbit DDR Mobile-RAM with two CKE (CKE0 and CKE1)
Rev.1.0, 2007-03
10242006-Y557-TZXW
966
'4
9664
$
9''4
'4
9''
9''4
'4
'4
%
'4
'4
9664
9664
'4
'4
&
'4
'4
9''4
9''4
'4
'4
'
'4
'4
9664
9664
8'46
'4
(
'4
/'46
9''4
966
8'0
&.(
)
&6
/'0
9''
&.(
&.
&.
*
:(
&$6
5$6
$
$
$
+
&6
%$
%$
$
$
$
-
$$3
$
$
966
$
$
.
$
$
9''
5
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
1.3
Description
The HY[B/E]18M1G16[0/1]BF is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is
internally configured as a quad-bank DRAM.
The HY[B/E]18M1G16[0/1]BF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate
architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at
the I/O balls. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O balls.
The HY[B/E]18M1G16[0/1]BF is especially designed for mobile applications. It operates from a 1.8V power supply. Power
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced
by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD)
mode. For further power-savings the clock may be stopped during idle periods.
The HY[B/E]18M1G16[0/1]BF is housed in a 60-ball PG-VFBGA-60-6 package. It is available in Commercial (-0°C to +70°C)
and Extended (-25°C to +85°C) temperature range.
This product provides two options in Clock Enable (CKE) configurations – 1 CKE and 2 CKE, in addition to the 2 Chip Select
scheme. The options provide independent control of CS and CKE of each DRAM dies as required to achieve low power
consumption.
For example, a possible combination is that while one DRAM die is in active mode, the other could be in standby via
independent CS control, or in Deep Power Down mode via independent CS and CKE control. As shown in Table 26 SDRAM
Maximum Operating Currents, number of figures for various scenarios are demonstrated, where one die is in active mode
controlled by CS0; the other is in standby mode controlled by CS1 (for 1 CKE option), or in Power-Down mode controlled by
CKE1 (for 2 CKE option).
The HY[B/E]18M1G16[0/1]BF package contains two dies, each die assigned a separate chip select, which is functionally
equivalent to having two seperate BGA components, with each component containing one die. The same functional limitations
apply and care must be taken to avoid possible bus contention, since both dies share the same data bus. Any back-to-back
read or write from a different die can only start when the existing burst operation is completed. For example, restricted
operations involving two dies may include:
• Consecutive READ/WRITE bursts,
• Random READ/WRITE accesses,
• READ or WRITE truncations, and
• Simultaneous READ or WRITE on both dies
In case of an ongoing read burst, the Burst Terminate (BST) command can be used before any access from the different die
occurs.
The dual-die device must follow the predefined command sequences for power-up and initialization. The operation can be
performed for the two dies together or separately.
Note: All the timing diagrams of operations shown int the following sections assume that operations occur within the same die.
Rev.1.0, 2007-03
10242006-Y557-TZXW
6
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 3
Functional Block Diagram
&.(RU
&.(&.(
%DQN
0HPRU\$UUD\
&.&.
[[
'DWD
%DQN&ROXPQ/RJLF
&ROXPQ$GGUHVV
&RXQWHU/DWFK
,2*DWLQJ
'400DVN/RJLF
:ULWH
),)2
0DVN
FON 'DWD
LQ
'ULYHUV
'4
'4
/'0
8'0
'46
*HQHUDWRU
,QSXW5HJ
FON
RXW
&ROXPQ
'HFRGHU
'ULYHUV
6HQVH$PSOLILHU
&.&.
5HFHLYHUV
%DQN
08;
%DQN
5HIUHVK&RXQWHU
$$
%$%$
$GGUHVV5HJLVWHU
%DQN
5RZ$GGUHVV/DWFK
'HFRGHU
0RGH
5HJLVWHUV
5RZ$GGUHVV0X[
%DQN
5HDG/DWFK
&RPPDQG
'HFRGH
&6&6
5$6
&$6
:(
&RQWURO/RJLF
&.
&.
&RO
&RO
1RWH7KH)XQFWLRQDO%ORFN'LDJUDPLVLQWHQGHGWRIDFLOLWDWHXVHUXQGHUVWDQGLQJRIWKHRSHUDWLRQRIWKHGHYLFHLWGRHVQRWUHSUHVHQWWKHDFWXDO
FLUFXLWLPSOHPHQWDWLRQ
1RWH8'0/'0DUHXQLGLUHFWLRQDOVLJQDOV LQSXWRQO\ EXWLQWHUQDOO\ORDGHGWRPDWFKWKHORDGRIWKHELGLUHFWLRQDO'4DQG8'46/'46
Rev.1.0, 2007-03
10242006-Y557-TZXW
7
8'46
/'46
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
1.4
Ball Definition and Description
TABLE 4
Ball Description
Ball
Type
Detailed Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on
crossing of the positive edge of CK and negative edge of CK.
CKE or CKE0,
CKE1
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides precharge power-down and self
refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be
maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE
are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh.
CS0
CS1
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DQ0 - DQ15
I/O
Data Inputs/Output: Bi-directional data bus (16 bit)
LDQS, UDQS
I/O
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data.
LDQS corresponds to the data on DQ0 - DQ7, UDQS to the data on DQ8 - DQ15
LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM balls are input only, the DM loading matches the DQ and DQS
loading. DM may be driven HIGH, LOW, or floating during READs. LDM corresponds to the data
on DQ0 - DQ7, UDM to the data on DQ8 - DQ15
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be
loaded during a MODE REGISTER SET command (MRS or EMRS).
A0 - A12
Input
Address Inputs: Provide the row address for ACTIVE commands and the column address and
Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array
in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether
the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is
to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the opcode during a MODE REGISTER SET command.
VDDQ
Supply
I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70
V − 1.90 V
VSSQ
VDD
VSS
Supply
I/O Ground
Supply
Power Supply: Power for the core logic and input buffers, VDD = 1.70 V − 1.90 V
Supply
Ground
N.C.
–
No Connect
Rev.1.0, 2007-03
10242006-Y557-TZXW
8
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2
Functional Description
The 1-Gbit x16 DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It
is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command,
followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select
the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The DDR Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 4). Operational procedures
other than those specified may result in undefined operation.
FIGURE 4
Power-Up Sequence and Mode Register Sets
6$$
6$$1
—S
T#+
T20
T2&#
T2&#
T-2$
T-2$
#+
#+
#+%
#OMMAND
./0
02%
!2&
!DDRESS
!LL
"ANKS
!
!2&
-23
-23
!#4
#ODE
#ODE
2!
#ODE
#ODE
2!
"!,
"!,
"!,
"!(
"!
"! "!
$$1 $13
(IGH :
Rev.1.0, 2007-03
10242006-Y557-TZXW
9
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ
are driven from a single power converter output.
Assert and hold CKE to a HIGH level.
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each
followed by NOP or DESELECT commands for at least tMRD period; the order in which both registers are programmed is
not important.
Following these steps, the DDR Mobile-RAM is ready for normal operation.
Rev.1.0, 2007-03
10242006-Y557-TZXW
10
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2
Register Definition
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the
selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed
via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Mode Register Definition (BA[1:0] = 00B)
%$
%$
$
$
$
$
$
$
$
$
&/
$
$
%7
$
$
$
%/
03%/
Field
Bits
Type
Description
CL
[6:4]
w
CAS Latency
010B CL 2
011B CL 3
Note: All other bit combinations are RESERVED.
BT
3
w
Burst Type
BT Sequential
0B
1B
BT Interleaved
BL
[2:0]
w
Burst Length
001B BL 2
010B BL 4
011B BL 8
100B BL 16
Note: All other bit combinations are RESERVED.
2.2.1.1
Burst Length
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, 8 or 16 locations are available.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1 - A9 when the burst length is set to two, by A2 - A9 when the burst length is set to four, by A3 - A9
when the burst length is set to eight and by A4 - A9 when the burst length is set to sixteen. The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ
and WRITE bursts.
Rev.1.0, 2007-03
10242006-Y557-TZXW
11
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 5.
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 * tCK + tAC). If a READ
command is registered and the latency is 2 clocks, the first data element will be valid after (tCK + tAC). For details please refer
to the READ command description.
Rev.1.0, 2007-03
10242006-Y557-TZXW
12
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 5
Burst Definition
Burst
Length
Starting Column
Address
A3
A2
A1
2
4
8
16
Order of Accesses Within a Burst (Hexadecimal Notation)
A0
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
0
0
0
0
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0
0
0
1
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
0
0
1
0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
0
0
1
1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
0
1
0
0
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
0
1
0
1
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
0
1
1
0
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
0
1
1
1
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
1
0
0
0
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1
0
0
1
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
1
0
1
0
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
1
0
1
1
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
1
1
0
0
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
1
1
0
1
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
1
1
1
0
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
1
1
1
1
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
Notes
1.
2.
3.
4.
5.
For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
For a burst length of 16, A4-Ai select the sixteen-data-element block; A0-A3 select the first access within the block.
Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block.
Rev.1.0, 2007-03
10242006-Y557-TZXW
13
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended
Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - A12 shall be written to
zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Extended Mode Register Definition (BA[1:0] = 10B)
%$
%$
$
$
$
$
$
$
$
$
'6
$
$
7&65
$
$
$
3$65
03%/
Field
Bits
Type
Description
DS
[6:5]
w
Selectable Drive Strength
00B DS Full Drive Strength
01B DS Half Drive Strength
10B DS Quarter Drive Strength
Note: All other bit combinations are RESERVED.
TCSR
[4:3]
w
Temperature Compensated Self Refresh
XXB TCSR Superseded by on-chip temperature sensor (see text)
PASR [2:0]
w
Partial Array Self Refresh
000B PASR all banks
001B PASR half array (BA1 = 0)
010B PASR quarter array (BA1 = BA0 = 0)
101B PASR 1/8 array (BA1 = BA0 = RA12 = 0)
110B PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
2.2.2.1
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may be restricted
to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank,
and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by tREF (cf.
Table 14).
Rev.1.0, 2007-03
10242006-Y557-TZXW
14
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2.2.2
Temperature Compensated Self Refresh (TCSR) with OnChip Temperature Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored
information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh
periods, and low temperatures correspond to long refresh periods.
The DDR Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature
and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the
Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because
• it is fully compatible to all processors that do not support the Extended Mode Register
• it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an
external temperature sensor
• it does not require any processor interaction for regular TCSR updates
2.2.2.3
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6. The “full drive strength” (default) is suitable for
heavier loaded systems. The “half drive strength” is intended for lightly loaded systems or systems with reduced performance
requirements. For systems with point-to-point connection, a “quarter drive strength” is available. I-V curves for full and half drive
strengths are included in this document.
Rev.1.0, 2007-03
10242006-Y557-TZXW
15
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.3
State Diagram
FIGURE 5
State Diagram
Power
applied
Power
On
Deep
Power
Down
DPDSX
Precharge
All Banks
Self
Refresh
DPDS
REFSX
REFS
Idle
MRS
MRS
EMRS
Auto
Refresh
REFA
All banks
precharged
CKEL
CKEH
Active
Power
Down
Precharge
Power
Down
ACT
CKEH
CKEL
Row
Active
Burst
Stop
WRITE
READ
BST
WRITE
WRITEA
WRITE
READ
WRITEA
READA
WRITE A
PRE
PRE
READ
READA
PRE
PRE
READ
READA
READ A
Precharge
PREALL
Automatic Sequence
Command Sequence
ACT = Active
BST = Burst Terminate
CKEL = Enter Power-Down
CKEH = Exit Power-Down
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power-Down
EMRS = Ext. Mode Reg. Set
MRS = Mode Register Set
PRE = Precharge
PREALL = Precharge All Banks
REFA = Auto Refresh
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
READ = Read w/o Auto Precharge
READA = Read with Auto Precharge
WRITE = Write w/o Auto Precharge
WRITEA = Write with Auto Precharge
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and commands
to control them, not all details. In particular situations involving more than one bank are not captured in full detail.
Rev.1.0, 2007-03
10242006-Y557-TZXW
16
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4
Commands
TABLE 6
Command Overview
Command
CS
RAS
CAS
WE
Address
Note
DESELECT
H
X
X
X
X
1)2)
NO OPERATION
L
H
H
H
X
1)2)
ACT
ACTIVE (Select bank and row)
L
L
H
H
Bank / Row
1)3)
RD
READ (Select bank and column and start read burst)
L
H
L
H
Bank / Col
1)4)
WR
WRITE (Select bank and column and start write burst)
L
H
L
L
Bank / Col
1)4)
BST
BURST TERMINATE or DEEP POWER-DOWN
L
H
H
L
X
1)5)
PRE
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
Code
1)6)
ARF
AUTO REFRESH or SELF REFRESH entry
L
L
L
H
X
1)7)8)
MRS
MODE REGISTER SET
L
L
L
L
Op-Code
1)9)
NOP
1)
2)
3)
4)
5)
6)
7)
8)
9)
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN.
DESELECT and NOP are functionally interchangeable.
BA0, BA1 provide the bank address, and A0 - A12 provide the row address.
BA0, BA1 provide the bank address, A0 - A9 provide the column address; A10 HIGH enables the Auto Precharge feature (non persistent),
A10 LOW disables the Auto Precharge feature.
This command is BURST TERMINATE if CKE is HIGH, DEEP POWER-DOWN if CKE is LOW. The BURST TERMINATE command is
defined for READ bursts with Auto Precharge disabled only; it is undefined (and should not be used) for read bursts with Auto Precharge
enabled, and for write bursts.
A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of
BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
TABLE 7
DM Operation
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data provided coincident with the corresponding data
Address (BA0, BA1, A0 - A12) and command inputs (CKE, CS, RAS, CAS, WE) are all registered on the crossing of the positive
edge of CK and the negative edge of CK. Figure 6 shows the basic timing parameters, which apply to all commands and
operations.
Rev.1.0, 2007-03
10242006-Y557-TZXW
17
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 6
Address / Command Inputs Timing Parameters
tCK
tCH
tCL
CK
CK
Input
tIS tIH
Valid
Valid
Valid
= Don't Care
TABLE 8
Inputs Timing Parameters
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
Note
max.
Clock high-level width
tCH
0.45
0.55
0.45
0.55
tCK
1)
Clock low-level width
tCL
0.45
0.55
0.45
0.55
tCK
1)
tCK
6
–
7.5
–
ns
1)2)
12
–
15
–
1.1
–
1.3
–
ns
1)3)4)5)
1.3
–
1.5
–
1.1
–
1.3
–
1.3
–
1.5
–
2.7
–
3.0
–
Clock cycle time
CL = 3
CL = 2
Address and control input setup time
fast slew rate
tIS
slow slew rate
Address and control input hold time
fast slew rate
tIH
slow slew rate
Address and control input pulse width
1)
2)
3)
4)
5)
6)
7)
tIPW
All AC timing characteristics assume an input slew rate of 1.0 V/ns.
The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
The transition time for address and command inputs is measured between VIH and VIL.
For command / address input slew rate ≥ 1V/ns.
A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
For command / address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
Rev.1.0, 2007-03
10242006-Y557-TZXW
18
1)3)6)
ns
1)3)4)
1)3)6)
ns
1)7)
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.1
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to a DDR Mobile-RAM which is selected (CS = LOW).
This prevents unwanted commands from being registered
during idle states. Operations already in progress are not
affected.
FIGURE 7
No Operation Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the DDR Mobile-RAM. The DDR
Mobile-RAM is effectively deselected. Operations already in progress are not affected.
Rev.1.0, 2007-03
10242006-Y557-TZXW
19
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.3
MODE REGISTER SET
The Mode Register and Extended Mode Register are loaded
via inputs A0 - A12 (see mode register descriptions in
Chapter 2.2). The MODE REGISTER SET command can
only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be
issued until tMRD is met.
FIGURE 8
Mode Register Set Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A12
Code
BA0,BA1
Code
= Don't Care
FIGURE 9
Mode Register Definition
CK
CK
Command
MRS
NOP
Valid
tMRD
Address
Code
Valid
= Don't Care
Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - A12)
TABLE 9
Timing Parameters for Mode Register Set Command
Parameter
Symbol
-6
min.
MODE REGISTER SET command period
Rev.1.0, 2007-03
10242006-Y557-TZXW
tMRD
20
2
- 7.5
max.
–
min.
2
Unit
Note
tCK
–
max.
–
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.4
ACTIVE
Before any READ or WRITE commands can be issued to a
bank within the DDR Mobile-RAM, a row in that bank must be
“opened” (activated). This is accomplished via the ACTIVE
command and addresses BA0, BA1, A0 - A12 (see
Figure 10), which decode and select both the bank and the
row to be activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be issued to
that row, subject to the tRCD specification. A subsequent
ACTIVE command to a different row in the same bank can
only be issued after the previous active row has been “closed”
(precharged).
The minimum time interval between successive ACTIVE
commands to the same bank is defined by tRC. A subsequent
ACTIVE command to another bank can be issued while the
first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval
between successive ACTIVE commands to different banks is
defined by tRRD.
FIGURE 10
ACTIVE Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A12
RA
BA0,BA1
BA
= Don't Care
BA = Bank Address
RA = Row Address
FIGURE 11
Bank Activate Timings
CK
CK
Command
ACT
NOP
ACT
NOP
A0-A12
Row
Row
Col
BA0, BA1
BA x
BA y
BA y
tRRD
Rev.1.0, 2007-03
10242006-Y557-TZXW
NOP
tRCD
21
RD/WR
NOP
= Don't Care
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 10
Timing Parameters for ACTIVE Command
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
Note
1)
max.
ACTIVE to ACTIVE command period
tRC
60
–
65
–
ns
ACTIVE to READ or WRITE delay
tRCD
18
–
22.5
–
ns
ACTIVE bank A to ACTIVE bank B delay
tRRD
12
–
15
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
2.4.5
READ
READ bursts are initiated with a READ command, as shown
in Figure 12.
Basic timings for the DQs are shown in Figure 13; they apply
to all read operations.
The starting column and bank addresses are provided with
the READ command and Auto Precharge is either enabled or
disabled for that burst access. If Auto Precharge is enabled,
the row that is accessed will start precharge at the completion
of the burst, provided tRAS has been satisfied. For the generic
READ commands used in the following illustrations, Auto
Precharge is disabled.
FIGURE 12
READ Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A9
CA
Enable AP
A10
AP
Disable AP
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Rev.1.0, 2007-03
10242006-Y557-TZXW
22
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 13
Basic READ Timing Parameters for DQs
tCK
CK
tCK
tCH
tCL
CK
tDQSCK
tACmax
tDQSCK
tRPST
tRPRE
DQS
tDQSQmax
tAC
DQ
tHZ
DO n
tLZ
DO n+1 DO n+2 DO n+3
tQH
tQH
tDQSCK
tACmin
tDQSCK
tRPRE
DQS
tDQSQmax
tAC
DQ
tRPST
DO n
tLZ
tHZ
DO n+1 DO n+2 DO n+3
tQH
tQH
DO n = Data Out from column n
= Don't Care
Burst Length = 4 in the case shown
CAS Latency = 3 in the case shown
All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC
TABLE 11
Timing Parameters for READ Command
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
Note
max.
DQ output access time from CK/CK
tAC
2.0
5.5
2.0
6.5
ns
1)2)
DQS output access time from CK/CK
tDQSCK
2.0
5.5
2.0
6.5
ns
1)2)
DQ & DQS low-impedance time from CK/CK
tLZ
1.0
–
1.0
–
ns
3)
DQ & DQS high-impedance time from CK/CK
tHZ
–
5.5
–
6.5
ns
3)
DQS - DQ skew
tDQSQ
–
0.5
–
0.6
ns
4)
DQ / DQS output hold time from DQS
tQH
tHP-tQHS
–
tHP-tQHS
–
ns
5)
Data hold skew factor
tQHS
–
0.65
–
0.75
ns
5)
tCK
–
Read preamble
CL = 3
tRPRE
CL = 2
0.9
1.1
0.9
1.1
0.7
1.1
0.7
1.1
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
–
ACTIVE to PRECHARGE command period
tRAS
42
70,000
45
70,000
ns
6)
ACTIVE to ACTIVE command period
tRC
60
–
65
–
ns
6)
Rev.1.0, 2007-03
10242006-Y557-TZXW
23
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
Note
max.
ACTIVE to READ or WRITE delay
tRCD
18
–
22.5
–
ns
6)
PRECHARGE command period
tRP
18
–
22.5
–
ns
6)
1) The output timing reference level is VDDQ/2.
2) Parameters tAC and tQH are specified for full drive strength and a reference load of 20pF. This reference load is not intended to be either a
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters tAC and tQH are expected to be in the same range. However, these parameters are not
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
4)tDQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
5) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).tQHS accounts
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency
after the READ command.
The diagrams in Figure 14 show general timing for each supported CAS latency setting. DQS is driven by the DDR MobileRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last
data-out element is known as the read postamble.
Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
FIGURE 14
READ Burst
CK
CK
Command
Address
READ
NOP
NOP
NOP
NOP
NOP
BA,Col n
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
DO n
= Don't Care
DO n = Data Out from column n
BA, Col n = Bank A, Column n
Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n
Rev.1.0, 2007-03
10242006-Y557-TZXW
24
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either
case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of
a completed burst or the last desired data element of a longer burst which is being truncated.
The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data
element pairs (pairs are required by the 2n pre fetch architecture). This is shown in Figure 15.
FIGURE 15
Consecutive READ Bursts
CK
CK
Command
Address
READ
NOP
BA,Col n
READ
NOP
NOP
NOP
BA,Col b
CL=2
DQS
DQ
DO n
DO b
CL=3
DQS
DQ
DO n
DO b
= Don't Care
DO n (or b) = Data Out from column n (or column b)
Burst Length = 4, 8 or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7 or 15) subsequent elements of Data Out appear in the programmed order following DO b
Read commands shown must be to the same device
Rev.1.0, 2007-03
10242006-Y557-TZXW
25
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive READ data is
illustrated in Figure 16.
FIGURE 16
Nonconsecutive READ Bursts
CK
CK
Command
Address
READ
NOP
NOP
READ
BA,Col n
NOP
NOP
BA,Col b
CL=2
DQS
DQ
DO n
DO b
CL=3
DQS
DQ
DO n
= Don't Care
DO n (or b) = Data Out from column n (or column b)
BA A Col n (b) = Bank A, Column n (b)
Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (b)
Rev.1.0, 2007-03
10242006-Y557-TZXW
26
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Full-speed random READ accesses (Burst Length = 2, 4, 8 or 16) within a page (or pages) can be performed as shown in
Figure 17.
FIGURE 17
Random READ Accesses
CK
CK
Command
Address
READ
READ
READ
READ
NOP
BA,Col n
BA,Col x
BA,Col b
BA,Col g
NOP
CL=2
DQS
DQ
DO n
DO n'
DO x
DO x'
DO b
DO b'
DO g
DO g'
DO n
DO n'
DO x
DO x'
DO b
DO b'
CL=3
DQS
DQ
DO n, etc. = Data Out from column n, etc.
n', x', etc. = Data Out elements, according to the programmed burst order
BA, Col n = Bank A, Column n
Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8 or 16, the burst is interrupted)
Reads are to active rows in any banks
= Don't Care
Note: This timing diagram is only applicable for the consecutive READ from the same die.
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Figure 21), provided that Auto
Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE
command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs.
This is shown in Figure 18.
Rev.1.0, 2007-03
10242006-Y557-TZXW
27
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 18
Terminating a READ Burst
CK
CK
Command
Address
READ
NOP
BST
NOP
NOP
NOP
BA,Col n
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
DO n
DO n = Data Out from column n
BA, Col n = Bank A, Column n
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of Data Out appear in the programmed order following DO n
Rev.1.0, 2007-03
10242006-Y557-TZXW
28
= Don't Care
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.5.2
READ to WRITE
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation
is necessary, the BURST TERMINATE command must be used, as shown in Figure 19.
FIGURE 19
READ to WRITE
CK
CK
Command
Address
READ
BST
NOP
BA,Col n
WRITE
NOP
NOP
BA,Col b
CL=2
tDQSS
DQS
DQ
DO n
Di b
DM
Command
Address
READ
BST
NOP
NOP
BA,Col n
WRITE
NOP
BA,Col b
CL=3
DQS
DQ
DO n
Di b
DM
DO n = Data Out from column n; DI b = Data In to column b
1 subsequent element of Data Out appear in the programmed order following DO n.
Data In elements are applied following DI b in the programmed order
2.4.5.3
= Don't Care
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank (provided that Auto
Precharge was not activated).
The PRECHARGE command should be issued x clock cycles after the READ command, where x equals the number of desired
data element pairs. This is shown in Figure 20. Following the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met. Please note that part of the row precharge time is hidden during the access of the last
data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as described
above) provides the same operation that would result from the same READ burst with Auto Precharge enabled. The
disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the
appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
Rev.1.0, 2007-03
10242006-Y557-TZXW
29
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 20
READ to PRECHARGE
CK
CK
Command
Address
READ
NOP
PRE
NOP
NOP
Bank
(a or all)
BA,Col n
ACT
BA, Row
tRP
CL=2
DQS
DQ
DO n
CL=3
DQS
DQ
DO n
= Don't Care
DO n = Data Out from column n
Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 or 16
3 subsequent elements of Data Out appear in the programmed order following DO n
Precharge may be applied at (BL / 2) tCK after the READ command.
Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.
The ACTIVE command may be applied if tRC has been met.
2.4.6
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with Auto Precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated, as shown in
Figure 18.
FIGURE 21
BURST TERMINATE Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
Rev.1.0, 2007-03
10242006-Y557-TZXW
30
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.7
WRITE
WRITE bursts are initiated with a WRITE command, as
shown in Figure 22. Basic timings for the DQs are shown in
Figure 23; they apply to all write operations.The starting
column and bank addresses are provided with the WRITE
command, and Auto Precharge is either enabled or disabled
for that access. If Auto Precharge is enabled, the row being
accessed is precharged at the completion of the write burst.
For the generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
FIGURE 22
WRITE Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A9
CA
Enable AP
A10
AP
Disable AP
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Rev.1.0, 2007-03
10242006-Y557-TZXW
31
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 23
Basic WRITE Timing Parameters for DQs
tCK
CK
tCH
tCL
CK
Case 1:
tDQSS = min
tDQSS
tDSH
tDQSH
tDSH
tWPST
DQS
tWPRES
tDQSL
tWPRE
tDH
tDS
DQ, DM
DI n
Case 2:
tDQSS = max
tDQSS
tDSS
tDQSH
tDSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
tDH
tDS
DQ, DM
DI n
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order following DI n.
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS
must fall within the ± 25% window of the corresponding positive clock edge.
= Don't Care
TABLE 12
Timing Parameters for WRITE Command
Parameter
Symbol
-6
min.
DQ and DM input setup time
fast slew rate
fast slew rate
Note
ns
1)2)3)
max.
–
0.75
–
TBD
–
0.85
–
0.6
–
0.75
–
TBD
–
0.85
–
tDIPW
2.1
–
1.7
–
ns
5)
tDH
slow slew rate
DQ and DM input pulse width
min.
Unit
0.6
tDS
slow slew rate
DQ and DM input hold time
max.
- 7.5
1)2)4)
ns
1)2)3)
1)2)4)
Write command to 1st DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
–
DQS input high-level width
tDQSH
0.4
0.6
0.4
0.6
tCK
–
DQS input low-level width
tDQSL
0.4
0.6
0.4
0.6
tCK
–
DQS falling edge to CK setup time
tDSS
0.2
–
0.2
–
tCK
–
DQS falling edge hold time from CK
tDSH
0.2
–
0.2
–
tCK
–
Write preamble setup time
tWPRES
0
–
0
–
ns
6)
Rev.1.0, 2007-03
10242006-Y557-TZXW
32
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
-6
min.
Write postamble
max.
- 7.5
min.
Unit
Note
tCK
7)
max.
tWPST
0.4
0.6
0.4
0.6
Write preamble
tWPRE
0.25
–
0.25
–
tCK
–
ACTIVE to PRECHARGE command period
tRAS
42
70,000
45
70,000
ns
8)
ACTIVE to ACTIVE command period
tRC
60
–
65
–
ns
8)
ACTIVE to READ or WRITE delay
tRCD
18
–
22.5
–
ns
8)
WRITE recovery time
tWR
15
–
15
–
ns
8)
Internal write to Read command delay
tWTR
1
–
1
–
tCK
–
ns
8)
18
–
22.5 –
1) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
PRECHARGE command period
tRP
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
3) Input slew rate ≥ 1.0 V/ns.
4) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
8) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command,
and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is
known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS)
is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in Figure 24 show the two extremes
of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain
High-Z and any additional input data is ignored.
Rev.1.0, 2007-03
10242006-Y557-TZXW
33
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 24
WRITE Burst (min. and max. tDQSS)
CK
CK
Command
Address
WRITE
NOP
NOP
NOP
NOP
NOP
BA,Col b
tDQSSmin
DQS
DQ
Di b
DM
tDQSSmax
DQS
DQ
Di b
DM
DI b = Data In to column b.
3 subsequent elements of Data In are applied in the programmed order following DI b.
A non-interrupted burst of 4 is shown.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
= Don't Care
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a
continuous flow of input data can be maintained. The new WRITE command can be issued on any clock cycle following the
previous WRITE command. The first data element from the new burst is applied after either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued
x clock cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by
the 2n pre fetch architecture).
Figure 25 shows concatenated WRITE bursts of 4.
Rev.1.0, 2007-03
10242006-Y557-TZXW
34
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 25
WRITE to WRITE (min. and max. tDQSS)
CK
CK
Command
Address
WRITE
NOP
WRITE
BA,Col b
NOP
NOP
NOP
BA,Col n
tDQSSmin
DQS
DQ
Di b
Di n
DM
tDQSSmax
DQS
DQ
Di b
Di n
DM
DI b (n) = Data In to column b (column n)
3 subsequent elements of Data In are applied in the programmed order following DI b.
3 subsequent elements of Data In are applied in the programmed order following DI n.
Non-interrupted bursts of 4 are shown.
Each WRITE command may be to any active bank
An example of non-consecutive WRITEs is shown in Figure 26.
Rev.1.0, 2007-03
10242006-Y557-TZXW
35
= Don't Care
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 26
Non-Consecutive WRITE to WRITE (max. tDQSS)
CK
CK
Command
Address
WRITE
NOP
NOP
WRITE
BA,Col b
NOP
NOP
BA,Col n
tDQSSmax
DQS
DQ
Di b
Di n
DM
DI b (n) = Data In to column b (or column n).
3 subsequent elements of Data In are applied in the programmed order following DI b.
3 subsequent elements of Data In are applied in the programmed order following DI n.
Non-interrupted bursts of 4 are shown.
Each WRITE command may be to any active bank and may be to the same or different devices.
= Don't Care
Full-speed random WRITE accesses within a page or pages can be performed as shown in Figure 27.
FIGURE 27
Random WRITE Cycles (max. tDQSS)
CK
CK
Command
Address
WRITE
WRITE
WRITE
WRITE
WRITE
BA,Col b
BA,Col x
BA,Col n
BA,Col a
BA,Col g
NOP
tDQSSmax
DQS
DQ
Di b
Di b'
Di x
Di x'
Di n
Di n'
Di a
Di a'
DM
DI b etc. = Data In to column b, etc. .
= Don't Care
b', etc. = the next Data In following DI b, etc. according to the programmed burst order
Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4, 8 or 16, burst would be truncated.
Each WRITE command may be to any active bank and may be to the same or different devices.
Rev.1.0, 2007-03
10242006-Y557-TZXW
36
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.7.1
WRITE to READ
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE
burst, tWTR (WRITE to READ) should be met as shown in Figure 28.
FIGURE 28
Non-Interrupting WRITE to READ (max. tDQSS)
CK
CK
Command
WRITE
Address
BA,Col b
NOP
NOP
NOP
READ
NOP
NOP
BA,Col n
tDQSSmax
tWTR
CL=3
DQS
DQ
Di b
DM
DI b = Data In to column b .
3 subsequent elements of Data In are applied in the programmed order following DI b.
A non-interrupted burst of 4 is shown.
tWTR is referenced from the positive clock edge after the last Data In pair.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
The READ and WRITE commands are to the same device but not necessarily to the same bank.
= Don't Care
Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 29. Note that only the datain pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked
with DM, as shown in Figure 29.
Rev.1.0, 2007-03
10242006-Y557-TZXW
37
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 29
Interrupting WRITE to READ (max. tDQSS)
CK
CK
Command
WRITE
Address
BA,Col b
NOP
NOP
READ
NOP
NOP
NOP
BA,Col n
tDQSSmax
tWTR
CL=3
DQS
DQ
Di b
DO n
DM
DI b = Data In to column b. DO n = Data Out from column n.
An interrupted burst of 4 is shown, 2 data elements are written.
3 subsequent elements of Data In are applied in the programmed order following DI b.
tWTR is referenced from the positive clock edge after the last Data In pair.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
The READ and WRITE commands are to the same device but not necessarily to the same bank.
Rev.1.0, 2007-03
10242006-Y557-TZXW
38
= Don't Care
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.7.2
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating
the WRITE burst, tWR should be met as shown in Figure 30.
FIGURE 30
Non-Interrupting WRITE to PRECHARGE (max. tDQSS)
CK
CK
Command
Address
WRITE
NOP
NOP
NOP
NOP
PRE
BA a
(or all)
BA,Col b
tDQSSmax
tWR
DQS
DQ
Di b
DM
DI b = Data In to column b .
3 subsequent elements of Data In are applied in the programmed order following DI b.
A non-interrupted burst of 4 is shown.
tWR is referenced from the positive clock edge after the last Data In pair.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
= Don't Care
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 31. Note that only
the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should
be masked with DM. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until
tRP is met.
In the case of a WRITE burst being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage
of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time
to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
Rev.1.0, 2007-03
10242006-Y557-TZXW
39
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 31
Interrupting WRITE to PRECHARGE (max. tDQSS)
CK
CK
Command
Address
WRITE
NOP
NOP
NOP
PRE
BA a
(or all)
BA,Col b
tDQSSmax
tWR
*2
DQS
DQ
Di b
DM
*1
DI b = Data In to column b .
An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written.
tWR is referenced from the positive clock edge after the last desired Data In pair.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
*1 = can be Don't Care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes Don't Care at this point
Rev.1.0, 2007-03
10242006-Y557-TZXW
NOP
40
*1
*1
*1
= Don't Care
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.8
PRECHARGE
The PRECHARGE command is used to deactivate (close) the
open row in a particular bank or the open rows in all banks.
The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are to
be precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will be
treated as a NOP if there is no open row in that bank, or if the
previously open row is already in the process of precharging.
FIGURE 32
PRECHARGE Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A9
A11,A12
All Banks
A10
One Bank
BA0,BA1
BA
= Don't Care
BA = Bank Address
(if A10 = L, otherwise Don't Care)
TABLE 13
Timing Parameters for PRECHARGE Command
Parameter
Symbol
-6
min.
max.
- 7.5
min.
Unit
Note
max.
ACTIVE to PRECHARGE command period
tRAS
42
70,000
45
70,000
ns
1)
PRECHARGE command period
tRP
18
–
22.5
–
ns
1)
WRITE recovery time
tWR
15
–
15
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
Rev.1.0, 2007-03
10242006-Y557-TZXW
41
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without
requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst. Auto Precharge is non persistent in that it is either enabled or
disabled for each individual READ or WRITE command.
Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described for each burst type.
2.4.9
AUTO REFRESH and SELF REFRESH
The DDR Mobile-RAM requires a refresh of all rows in an rolling 64ms interval. Each refresh is generated in one of two ways:
by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. Dividing the number of
rows into the rolling 64ms interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed
refresh timing.
2.4.9.1
AUTO REFRESH
Auto Refresh is used during normal operation of the DDR
Mobile-RAM. The command is non persistent, so it must be
issued each time a refresh is required. A minimum time tRFC
is required between two AUTO REFRESH commands. The
same rule applies to any access command after the Auto
Refresh operation. All banks must be precharged prior to the
AUTO REFRESH command.The refresh addressing is
generated by the internal refresh controller. This makes the
address bits “Don’t Care” during an AUTO REFRESH
command. The DDR Mobile-RAM requires Auto Refresh
cycles at an average periodic interval of tREFI (max.).Partial
array mode has no influence on Auto Refresh mode.
To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of eight AUTO REFRESH
commands can be posted to the DDR Mobile-RAM, and the
maximum absolute interval between any AUTO REFRESH
command and the next AUTO REFRESH command is 8 *
tREFI.
Rev.1.0, 2007-03
10242006-Y557-TZXW
FIGURE 33
AUTO REFRESH Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
42
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 34
Auto Refresh
CK
CK
Command
tRP
PRE
NOP
tRFC
ARF
NOP
NOP
NOP
NOP
ACT
Row n
Pre All
High-Z
DQ
= Don't Care
Ba A, Row n = Bank A, Row n
2.4.9.2
ARF
Ba A,
Row n
Address
A10 (AP)
tRFC
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR Mobile-RAM, even if the rest of the system is powered
down. When in the Self Refresh mode, the DDR Mobile-RAM retains data without external clocking. The DDR Mobile-RAM
device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. The user may halt
the external clock one clock after Self Refresh entry is registered.
Once the command is registered, CKE must be held low to
keep the device in Self Refresh mode. The device executes a
minimum of one AUTO REFRESH command internally once
it enters Self Refresh mode. The clock is internally disabled
during Self Refresh operation to save power. The minimum
time that the device must remain in Self Refresh mode is tRFC.
The procedure for exiting Self Refresh requires a sequence of
commands. First, the clock must be stable prior to CKE going
back HIGH. Once Self Refresh Exit is registered, a delay of at
least tXSR must be satisfied before a valid command can be
issued to the device to allow for completion of any internal
refresh in progress.The use of Self Refresh mode introduces
the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh an extra AUTO REFRESH
command is recommended.
FIGURE 35
SELF REFRESH Entry Command
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
Rev.1.0, 2007-03
10242006-Y557-TZXW
43
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 36
Self Refresh Entry and Exit
CK
CK
tRP
> tRFC
tXSR
tRFC
CKE
Command
PRE
NOP
ARF
NOP
NOP
NOP
ARF
NOP
ACT
Ba A,
Row n
Address
A10 (AP)
DQ
Row n
Pre All
High-Z
Enter
Self Refresh
Mode
Any Command
(Auto Refresh
Recommended)
Exit from
Self Refresh
Mode
= Don't Care
TABLE 14
Timing Parameters for AUTO REFRESH and SELF REFRESH Commands
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
Note
max.
AUTO REFRESH to ACTIVE/AUTO REFRESH command period
tRFC
72
–
75
–
ns
1)
PRECHARGE command period
tRP
18
–
22.5
–
ns
1)
Self refresh exit to next valid command delay
tXSR
120
–
120
–
ns
1)
Refresh period
tREF
–
64
–
64
ms
–
Average periodic refresh interval (8192 rows)
tREFI
–
7.8
–
7.8
µs
2)
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
2) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8 * tREFI.
Rev.1.0, 2007-03
10242006-Y557-TZXW
44
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.4.10
POWER-DOWN
Power-down is entered when CKE is registered LOW (no
accesses can be in progress). If power-down occurs when all
banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers,
excluding CK, CK and CKE. In power-down mode, CKE LOW
must be maintained, and all other input signals are “Don’t
Care”. The minimum power-down duration is specified by
tCKE. However, power-down duration is limited by the refresh
requirements of the device.
The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT
command). A valid command may be applied tXP after exit
from power-down.
FIGURE 37
Power-Down Entry Command
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
FIGURE 38
Power-Down Entry and Exit
#+
#+
T20
T#+%
T80
#+%
#OMMAND
02%
./0
./0
./0
!DDRESS
! !0
$1
6ALID
6ALID
0RE !LL
(IGH :
0OWER $OWN
%NTRY
%XIT FROM
0OWER $OWN
0RECHARGE 0OWER $OWN MODE SHOWN ALL BANKS ARE IDLE AND T20 MET
WHEN 0OWER $OWN %NTRY #OMMAND IS ISSUED
Rev.1.0, 2007-03
10242006-Y557-TZXW
6ALID
45
!NY
#OMMAND
$ONgT #ARE
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 15
Timing Parameters for POWER-DOWN
Parameter
Symbol
-6
min.
- 7.5
max.
min.
Unit
max.
Exit power down delay
tXP
tCK + tIS
–
tCK + tIS
–
ns
CKE minimum low time
tCKE
2
–
2
–
tCK
2.4.10.1
Note
–
DEEP POWER-DOWN
Deep Power-Down mode is a unique feature of DDR Mobile-RAMs for extremely low power consumption. Deep Power-Down
mode is entered using the BURST TERMINATE command (cf Table 6) except that CKE is LOW. All internal voltage generators
are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged.
The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence
as for power-up initialization, including the 200µs initial pause, has to be applied before any other command may be issued (cf.
Figure 5).
2.4.11
CLOCK STOP
Stopping the clock during idle periods is a very effective method to reduce power consumption. The DDR Mobile-RAM supports
clock stop in case:
• the last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access command
depends on the device’s AC timing parameters and the clock frequency (see Table 16);
• the related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;
• CKE is held HIGH.
When all conditions have been met, the device is either in “idle” or “row active” state (cf. Figure 5), and clock stop mode may
be entered with CK held LOW and CK held HIGH.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access
command may be applied. Additional clock pulses might be required depending on the system characteristics.
Figure 39 illustrates the clock stop mode:
• initially the device is in clock stop mode;
• the clock is restarted with the rising edge of T0 and a NOP on the command inputs;
• with T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as
soon as this access command has completed;
• Tn is the last clock pulse required by the access command latched with T1
• the timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required
by this command and the clock is then stopped.
Rev.1.0, 2007-03
10242006-Y557-TZXW
46
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 39
Clock Stop
T0
CK
T1
T2
Tn
CK
CKE
Timing Condition
Command
Clock
Stopped
NOP
CMD
Exit
Clock
Stop
Valid
Command
NOP
NOP
NOP
= Don't Care
Enter
Clock
Stop
TABLE 16
Minimum Number of Required Clock Pulses per Access Command
Command
Timing Condition
-6
- 7.5
Unit
Note
ACTIVE
tRCD
3
3
tCK
1)
READ (Auto-Precharge Disabled)
(BL / 2) + CL
5
5
tCK
1)2)
READ (Auto-Precharge Enabled)
[(BL / 2) + tRP]; [(BL / 2) + CL]
5
5
tCK
1)2)3)
WRITE (Auto-Precharge Disabled)
1 + (BL / 2) + tWR
6
5
tCK
1)2)
WRITE (Auto-Precharge Enabled)
1 + (BL / 2) + tDAL
9
8
tCK
1)2)
PRECHARGE
tRP
3
3
tCK
1)
AUTO REFRESH
tRFC
12
10
tCK
1)
MODE REGISTER SET
tMRD
2
2
tCK
1) These parameters depend on the operating frequency; the number of clock cycles shown are calculated for a clock frequency of 133 MHz
for -7.5.
2) The values apply for a burst length of 4 and a CAS latency of 3.
3) Both timing conditions need to be satisfied; if not equal, the larger value applies
2.4.12
Clock Frequency Change
Depending on system considerations, it might be desired to change the DDR Mobile-RAM’s clock frequency while the device
is powered up. The DDR Mobile-RAM supports a clock frequency change when the device is in:
• self refresh mode (see Figure 36);
• power-down mode (see Figure 38);
• clock stop mode (see Figure 39).
Once the clock runs stable at the new clock frequency, the timing conditions for exiting these states have to be met before
applying the next access command. It should be pointed out that a continuous frequency drift is not considered a stable clock
and therefore is not supported.
Rev.1.0, 2007-03
10242006-Y557-TZXW
47
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.5
Function Truth Tables
TABLE 17
Truth Table - CKE
CKEn-1
L
Current State
L
L
H
H
L
H
1)
2)
3)
4)
5)
6)
CKEn
H
Command
Action
Note
Power-Down
X
Maintain Power-Down
1)2)3)4)
Self Refresh
X
Maintain Self Refresh
1)2)3)4)
Deep Power-Down
X
Maintain Deep Power-Down
1)2)3)4)
Power-Down
DESELECT or NOP
Exit Power-Down
1)2)3)4)5)
Self Refresh
DESELECT or NOP
Exit Self Refresh
1)2)3)4)
Deep Power-Down
X
Exit Deep Power-Down
1)2)3)4)6)
All Banks Idle
DESELECT or NOP
Enter Precharge Power-Down
1)2)3)4)
Bank(s) Active
DESELECT or NOP
Enter Active Power-Down
1)2)3)4)
All Banks Idle
AUTO REFRESH
Enter Self Refresh
1)2)3)4)
All Banks Idle
BURST TERMINATE
Enter Deep Power-Down
1)2)3)4)
1)2)3)4)
see Table 18 and Table 19
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
DESELECT or NOP commands should be issued on any clock edges occurring during tXP or tXSR period.
Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
TABLE 18
Current State Bank n - Command to Bank n
Current State
Any
Idle
Row Active
Read (AutoPrecharge
Disabled)
CS
RAS
CAS
H
X
X
L
H
L
Command / Action
Note
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
H
H
NO OPERATION (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
L
L
L
H
AUTO REFRESH
1)2)3)4)5)6)7)
L
L
L
L
MODE REGISTER SET
1)2)3)4)5)6)7)
L
H
L
H
READ (select column and start Read burst)
1)2)3)4)5)6)8)
L
H
L
L
WRITE (select column and start Write burst)
1)2)3)4)5)6)8)
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
1)2)3)4)5)6)9)
L
H
L
H
READ (truncate Read and start new Read burst)
1)2)3)4)5)6)8)
L
H
L
L
WRITE (truncate Read and start new Write burst)
1)2)3)4)5)6)8)10)
L
L
H
L
PRECHARGE (truncate Read and start Precharge)
1)2)3)4)5)6)9)
BURST TERMINATE
1)2)3)4)5)6)11)
L
Rev.1.0, 2007-03
10242006-Y557-TZXW
H
H
WE
L
48
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Current State
Write (AutoPrecharge
Disabled)
CS
RAS
CAS
WE
Command / Action
Note
L
H
L
H
READ (truncate Write and start Read burst)
1)2)3)4)5)6)8)12)
L
H
L
L
WRITE (truncate Write and start Write burst)
1)2)3)4)5)6)8)
1)2)3)4)5)6)9)12)
PRECHARGE (truncate Write burst, start Precharge)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the previous state was
L
L
H
L
power-down or self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to
be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable
commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank
are determined by its current state and according to Table 19.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the “idle” state.
Row Activating:
Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state.
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is
in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each
positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR Mobile-RAM is in the “all
banks idle” state.
Accessing Mode
Register:
Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR Mobile-RAM
is in the “all banks idle” state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle and no bursts are in progress.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to
end the Read burst prior to issuing a WRITE command.
11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
12) Requires appropriate DM masking.
Rev.1.0, 2007-03
10242006-Y557-TZXW
49
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 19
Current State Bank n - Command to Bank m (different bank)
Current State
RAS
CAS
Command / Action
Note
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
1)2)3)4)5)6)
Idle
X
X
X
X
Any command otherwise allowed to bank m
1)2)3)4)5)6)
Row Activating,
Active, or
Precharging
L
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
L
H
L
H
READ (select column and start Read burst)
1)2)3)4)5)6)7)
L
H
L
L
WRITE (select column and start Write burst)
1)2)3)4)5)6)7)
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
1)2)3)4)5)6)
L
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
L
H
L
H
READ (truncate Read and start new Read burst)
1)2)3)4)5)6)7)
L
H
L
L
WRITE (truncate Read and start Write burst)
1)2)3)4)5)6)7)8)
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
1)2)3)4)5)6)
L
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
L
H
L
H
READ (truncate Write and start Read burst)
1)2)3)4)5)6)7)9)
L
H
L
L
WRITE (truncate Write and start new Write burst)
1)2)3)4)5)6)7)
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
1)2)3)4)5)6)
Read (with Auto- L
Precharge)
L
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
H
L
H
READ (truncate Read and start new Read burst)
1)2)3)4)5)6)7)
L
H
L
L
WRITE (truncate Read and start Write burst)
1)2)3)4)5)6)7)8)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1)2)3)4)5)6)
Write (with Auto- L
Precharge)
L
L
H
H
ACTIVE (select and activate row)
1)2)3)4)5)6)
H
L
H
READ (truncate Write and start Read burst)
1)2)3)4)5)6)7)
L
H
L
L
WRITE (truncate Write and start new Write burst)
1)2)3)4)5)6)7)
Any
Read (AutoPrecharge
Disabled)
Write (AutoPrecharge
Disabled)
CS
WE
1)2)3)4)5)6)
PRECHARGE (Deactivate row in bank or banks)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the previous state was
L
L
H
L
power-down or self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
Rev.1.0, 2007-03
10242006-Y557-TZXW
50
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register
accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Read with AP Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is
met, the bank is in the idle state.
Write with AP Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is
met, the bank is in the idle state.
4)
5)
6)
7)
AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
All states and sequences not shown are illegal or reserved.
Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to
end the Read burst prior to issuing a WRITE command.
9) Requires appropriate DM masking.
Rev.1.0, 2007-03
10242006-Y557-TZXW
51
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
3
Electrical Characteristics
3.1
Operating Conditions
TABLE 20
Absolute Maximum Ratings
Parameter
Symbol
VDD
VDDQ
VIN
VOUT
TC
TC
TSTG
PD
IOUT
Power Supply Voltage
Power Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Operating Case Temperature
Commercial
Extended1)
Storage Temperature
Power Dissipation
Short Circuit Output Current
Values
min.
max.
-0.3
2.7
Unit
V
-0.3
2.7
V
-0.3
V
-0.3
VDDQ + 0.3
VDDQ + 0.3
0
+70
°C
-25
+85
°C
-55
+150
°C
–
0.7
W
–
50
mA
V
1) Clock Frequency (fCKmax) 166 MHz (CL = 3) not guaranteed for VDDmin = VDDQmin = 1.70V at Tcmin of extended temperature range
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage
to the integrated circuit.
Rev.1.0, 2007-03
10242006-Y557-TZXW
52
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 21
Pin Capacitances
Parameter
Symbol
Values
min.
Input capacitance: CK, CK
Input capacitance: all other input-only balls
Input/output capacitance: DQ, DQS, DM
CI1
CI2
CIO
Unit
Note
1)2)3)
max.
4.0
6.5
pF
2.0
6.5
pF
7.0
10
pF
1) These values are not subject to production test but verified by device characterization.
2) Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ
are applied and all other balls (except the ball under test) are floating. DQ’s should be in high impedance state. This may be achieved by
pulling CKE to low level.
3) Although DM is an input-only ball, it’s input capacitance models the input capacitance of the DQ and DQS balls.
Rev.1.0, 2007-03
10242006-Y557-TZXW
53
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 22
Electrical Characteristics
Parameter
Symbol
Values
min.
Power Supply Voltage
Power Supply Voltage for DQ Output Buffer
Input leakage current
Output leakage current
VDD
VDDQ
IIL
IOL
Unit
Note
max.
1.70
1.90
V
1)2)
1.70
1.90
V
1)2)
-1.0
1.0
µΑ
2)
-1.5
1.5
µA
2)
V
2)
V
2)
Address and Command Inputs (BA, BA1, CKE, CS, RAS, CAS, WE)
Input high voltage
Input low voltage
VIH
VIL
0.8 × VDDQ
-0.3
VDDQ + 0.3
0.2 × VDDQ
VIN
VID(DC)
VID(AC)
VIX
-0.3
VDDQ + 0.3
V
2)
0.4 × VDDQ
V
2)3)
V
2)3)
0.4 × VDDQ
VDDQ + 0.6
VDDQ + 0.6
0.6 × VDDQ
V
2)4)
VIHD(DC)
VILD(DC)
VIHD(AC)
VILD(AC)
0.7 × VDDQ
VDDQ + 0.3
V
2)
-0.3
0.3 x VDDQ
V
2)
0.8 × VDDQ
V
2)
-0.3
VDDQ + 0.3
0.2 × VDDQ
V
2)
VOH
VOL
0.9 × VDDQ
–
V
2)
–
0.1 × VDDQ
V
2)
Clock Inputs (CK, CK)
DC input voltage
DC input differential voltage
AC input differential voltage
AC differential cross point voltage
0.6 × VDDQ
Data Inputs (DQ, DM, DQS)
DC input high voltage
DC input low voltage
AC input high voltage
AC input low voltage
Data Outputs (DQ, DQS)
Output high voltage (IOH = -0.1 mA)
Output low voltage (IOL = 0.1 mA)
1)
2)
3)
4)
Clock Frequency (fCKmax) 166 MHz (CL = 3) not guaranteed for VDDmin = VDDQmin = 1.70V at Tcmin of extended temperature range
See Table 25 and Figure 41 for overshoot and undershoot definition.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to be equal to 0.5 x VDDQ and must track variations in the DC level.
Rev.1.0, 2007-03
10242006-Y557-TZXW
54
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
3.2
AC Characteristics
TABLE 23
AC Characteristics
Parameter
Symbol
-6
min.
DQ output access time from CK/CK
DQS output access time from CK/CK
Clock high-level width
Clock low-level width
Clock half period
Clock cycle time
CL = 3
tAC
tDQSCK
tCH
tCL
tHP
tCK
CL = 2
DQ and DM input setup time
fast slew rate
tDS
slow slew rate
DQ and DM input hold time
fast slew rate
tDH
slow slew rate
DQ and DM input pulse width
Address and control input setup time
fast slew rate
tDIPW
tIS
slow slew rate
Address and control input hold time
fast slew rate
tIH
slow slew rate
Address and control input pulse width
DQ & DQS low-impedance time from CK/CK
DQ & DQS high-impedance time from CK/CK
DQS - DQ skew
DQ / DQS output hold time from DQS
Data hold skew factor
Write command to 1st DQS latching transition
DQS input high-level width
DQS input low-level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
MODE REGISTER SET command period
Write preamble setup time
Write postamble
Write preamble
Read preamble
CL = 3
tIPW
tLZ
tHZ
tDQSQ
tQH
tQHS
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRES
tWPST
tWPRE
tRPRE
CL = 2
Read postamble
Rev.1.0, 2007-03
10242006-Y557-TZXW
tRPST
55
- 7.5
max.
min.
Unit Note
max.
1)2)3)4)5)
2.0
5.5
2.0
6.5
ns
2.0
5.5
2.0
6.5
ns
1)2)3)4)5)
tCK
tCK
1)2)3)
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
1)2)3)
min (tCL,tCH)
min (tCL,tCH)
ns
1)2)3)6)7)
6
–
7.5
–
ns
1)2)3)8)
12
–
15
–
0.6
–
0.75
–
ns
1)2)3)9)10)11)
TBD
–
0.85
–
0.6
–
0.75
–
TBD
–
0.85
–
2.1
–
1.7
–
ns
1)2)3)13)
1.1
–
1.3
–
ns
1)2)3)11)14)15)
1.3
–
1.5
–
1.1
–
1.3
–
1.3
–
1.5
–
2.7
–
3.0
–
ns
1)2)3)13)
1.0
–
1.0
–
ns
1)2)3)16)
–
6.0
–
6.5
ns
1)2)3)16)
–
0.6
–
0.6
ns
1)2)3)17)
tHP-tQHS
–
tHP-tQHS
–
ns
1)2)3)7)
–
0.75
–
0.75
ns
1)2)3)7)
0.75
1.25
0.75
1.25
1)2)3)
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.2
–
0.2
–
0.2
–
0.2
–
2
–
2
–
tCK
tCK
tCK
tCK
tCK
tCK
0
–
0
–
ns
1)2)3)18)
tCK
tCK
tCK
tCK
tCK
1)2)3)19)
0.4
0.6
0.4
0.6
0.25
–
0.25
–
0.9
1.1
0.9
1.1
0.7
1.1
0.7
1.1
0.4
0.6
0.4
0.6
1)2)3)9)10)12)
ns
1)2)3)9)10)11)
1)2)3)9)10)12)
1)2)3)12)14)15)
ns
1)2)3)11)14)15)
1)2)3)12)14)15)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)
1)2)3)20)
1)2)3)
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
-6
min.
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
WRITE recovery time
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
CKE minimum high or low time
Refresh period
Average periodic refresh interval (8192 rows)
- 7.5
max.
min.
Unit Note
max.
tRAS
tRC
tRFC
42
70,000
45
70,000
ns
1)2)3)21)
60
–
65
–
ns
1)2)3)21)
72
–
75
–
ns
1)2)3)21)
tRCD
tRP
tRRD
tWR
tDAL
tWTR
tXSR
tXP
tCKE
tREF
tREFI
18
–
22.5
–
ns
1)2)3)21)
18
–
22.5
–
ns
1)2)3)21)
12
–
15
–
ns
1)2)3)21)
15
–
15
–
ns
1)2)3)21)
1)2)3)22)
1
–
1
–
tCK
tCK
120
–
120
–
ns
1)2)3)21)
tCK+ tIS
–
tCK+ tIS
–
ns
1)2)3)
2
–
2
–
tCK
1)2)3)
–
64
–
64
ms
1)2)3)
–
7.8
–
7.8
µs
1)2)3)23)
1)2)3)
1) All parameters assume proper device initialization.
2) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals
other than CK/CK is VDDQ/2.
3) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
4) The output timing reference level is VDDQ/2.
5) Parameters tAC and tDQSCK are specified for full drive strength and a reference load (see Figure 40). This circuit is not intended to be either
a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half
drive strength with a nominal load of 10pF parameters tAC and tDQSCK are expected to be in the same range. However, these parameters
are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation
is suggested.
6) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
7)tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
8) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
9) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between VIH and VIL.
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
17)tDQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
Rev.1.0, 2007-03
10242006-Y557-TZXW
56
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
19) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
20) A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It
is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
21) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
22) tDAL = (tWR / tCK) + (tRP / tCK): for each of the terms above, if not already an integer, round to the next higher integer.
23) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8 * tREFI.
FIGURE 40
Measurement with Reference Load
)/
: /HMS
P&
TABLE 24
Output Slew Rate Characteristics
Parameter
Typical Range
Minimum
Maximum
Unit
Note
Pull-up and Pull-down Slew Rate
(Full Drive Buffer)
TBD
0.7
2.5
V/ns
1)2)
Pull-up and Pull-down Slew Rate
(Half Drive Buffer)
TBD
0.3
1.0
V/ns
1)2)
Output Slew Rate Matching Ratio
(Pull-up to Pull-down)
-
0.7
1.4
-
1)3)
1) Output slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
2) The parameter is measured using a 20pF capacitive load connected to VSSQ.
3) The ratio of the pull-up slew rate to the pull-down slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process
variation.
TABLE 25
AC Overshoot / Undershoot Specification
Parameter
Maximum
Unit
Note
Maximum peak amplitude allowed for overshoot
0.9
V
–
Maximum peak amplitude allowed for undershoot
0.9
V
–
Maximum overshoot area above VDD
3.0
V-ns
–
Maximum undershoot area below VSS
3.0
V-ns
–
Rev.1.0, 2007-03
10242006-Y557-TZXW
57
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
FIGURE 41
AC Overshoot and Undershoot Definition
3.0
Overshoot
2.5
2.0
VDD
Voltage (V)
1.5
1.0
Max. Amplitude = 0.9V
Max. Area = 3V-ns
0.5
0
VSS
-0.5
Undershoot
-1.0
-1.5
0
1
2
3
4
5
6
7
time (ns)
3.3
Operating Currents
TABLE 26
Maximum Operating Currents
Parameter & Test Conditions
Symbol
Values
Values
-6
- 7.5
Unit Note1)2)
3)4)
Operating one bank active-precharge current:
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
STABLE
IDD0
95/90/75
75/65/55
mA
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD2P
1.40
1.40
mA
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD2PS
1.20
1.20
mA
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD2N
36
30
mA
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD2NS
3.0
3.0
mA
Rev.1.0, 2007-03
10242006-Y557-TZXW
58
5)
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter & Test Conditions
Symbol
Values
Values
-6
- 7.5
Unit Note1)2)
3)4)
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD3P
4
4
mA
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD3PS
3.0
3.0
mA
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD3N
50
44
mA
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
IDD3NS
5.0
5.0
mA
Operating burst read current:
one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts;
IOUT = 0 mA; address input are SWITCHING; 50% data change each
burst transfer
IDD4R
130/125/110 100/90/80 mA
5)
Operating burst write current:
IDD4W
one bank active; BL = 4; tCK = tCKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
135/130/115 100/90/80 mA
5)
Auto-Refresh current:
tRC = tRFCmin; tCK = tCKmin; burst refresh; CKE is HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD5
370
270
mA
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are
STABLE; data bus inputs are STABLE
IDD6
see
Table 27
see
Table 27
µA
Deep Power Down current
IDD8
506)
µA
1) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade.
2) Input slew rate is 1.0 V/ns.
3) Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ;
HIGH is defined as VIN ≥ 0.9 * VDDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE
4) All parameters are measured with no output loads.
5) Assuming one of the die is in active RD/WR, whereas the other is in X/Y/Z mode, where X is active non Power-Down standby, Y is
precharge non Power-Down standby, and Z is active Power-Down standby. Note, X/Y scenarios apply to 1CKE or 2CKE options; whereas
Z is only applicable for 2CKE option.
6) IDD8 value shown as typical.
Rev.1.0, 2007-03
10242006-Y557-TZXW
59
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 27
Self Refresh Currents
Parameter & Test Conditions
Max.
Temperature
Symbol
Values
HYE18M1G160BF
Typ.
85 °C
Self Refresh Current:
Self refresh mode,
full array activation
(PASR = 000)
IDD6
Units Note
HYB18M1G160BF
Max.
Typ.
Max.
1520
1800
—
—
70 °C
1020
—
1020
1800
45 °C
640
—
640
—
—
25 °C
560
—
560
Self Refresh Current:
Self refresh mode,
half array activation
(PASR = 001)
85 °C
1080
1560
—
Self Refresh Current:
Self refresh mode,
quarter array activation
(PASR = 010)
70 °C
740
—
740
1560
45 °C
480
—
480
—
25 °C
420
—
420
—
85 °C
840
1340
—
—
70 °C
580
—
580
1340
45 °C
420
—
420
—
25 °C
340
—
340
—
µA
1)
1) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component’s actual temperature with a much
finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for TCSR. At production test the sensor is
calibrated, and IDD6 max. current is measured at 85°C. Typ. values are obtained from device characterization.
3.4
Pull-up and Pull-down Characteristics
Figure 42 shows the characteristics of full and half drive strength. It is specified under best and worst process variation
/condition. Temperature (Tcase): Minimum = 0 °C / -25°C, Maximum = 70°C; VDDQ: Minimum = 1.70 V, Maximum = 1.90 V
FIGURE 42
Full Drive Strength and Half Drive Strength
Half Drive Strength IV Curves
Full Drive Strength IV Curves
30.0
75.0
20.0
50.0
10.0
25.0
PD Min
-25.0
0.0
PD Max
0.0
0.0
0.5
1.0
1.5
PU Min
-10.0
PU Max
-20.0
-50.0
-30.0
-75.0
Rev.1.0, 2007-03
10242006-Y557-TZXW
PD Min
60
0.0
0.5
1.0
1.5
PD Max
PU Min
PU Max
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
4
Package Outline
FIGURE 43
60-ball PG-VFBGA-60-6
Rev.1.0, 2007-03
10242006-Y557-TZXW
61
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inputs Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timing Parameters for ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timing Parameters for READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Timing Parameters for WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timing Parameters for PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timing Parameters for AUTO REFRESH and SELF REFRESH Commands. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Parameters for POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Minimum Number of Required Clock Pulses per Access Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Output Slew Rate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AC Overshoot / Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Maximum Operating Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Rev.1.0, 2007-03
10242006-Y557-TZXW
62
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Standard ballout 1-Gbit DDR Mobile-RAM with 1CKE (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standard ballout 1-Gbit DDR Mobile-RAM with two CKE (CKE0 and CKE1). . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address / Command Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE Burst (min. and max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WRITE to WRITE (min. and max. tDQSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Non-Consecutive WRITE to WRITE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Random WRITE Cycles (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Non-Interrupting WRITE to READ (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupting WRITE to READ (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Non-Interrupting WRITE to PRECHARGE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupting WRITE to PRECHARGE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-Down Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Measurement with Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AC Overshoot and Undershoot Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Full Drive Strength and Half Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
60-ball PG-VFBGA-60-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Rev.1.0, 2007-03
10242006-Y557-TZXW
63
Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Contents
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ball Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.6
2.4.7
2.4.7.1
2.4.7.2
2.4.8
2.4.8.1
2.4.9
2.4.9.1
2.4.9.2
2.4.10
2.4.10.1
2.4.11
2.4.12
2.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . 15
Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DEEP POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CLOCK STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3
3.1
3.2
3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-up and Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Rev.1.0, 2007-03
10242006-Y557-TZXW
64
3
3
5
6
8
52
52
55
58
60
Data Sheet
Edition 2007-03
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com