Cypress CY8CLED16-48PVXIT Ez-colorâ ¢ hb led controller Datasheet

CY8CLED16
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to 16
Independent LED Channels
❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED
Controller plus other Features; Battery
Charging, Motor Control…
■
Visual Embedded Design, PSoC Express
❐ LED Based Express Drivers
• Binning Compensation
• Temperature Feedback
• DMX512
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages down to 1.0V using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to eight Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■
Advanced Peripherals (PSoC Blocks)
❐ 16 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to 2 Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex Peripherals by Combining Blocks
■
Flexible On-Chip Memory
❐ 32K Flash Program Storage 50,000 Erase/Write Cycles
❐ 2K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
• PSoC Express™
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
EZ-Color HB LED Controller
Preliminary Data Sheet
Cypress Semiconductor Corporation
Document Number: 001-13105 Rev. **
•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Revised June 12, 2007
CY8CLED16
Overview
Block Diagram
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Global Analog Interconnect
SROM
Flash 32K
PSoC CORE
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Two
Multiply
Accums.
Analog
Block
Array
POR and LVD
Decimator
I 2C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Document Number: 001-13105 Rev. **
Page 2 of 39
CY8CLED16
EZ-Color Functional Overview
Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family supports up to 16 independent LED
channels with up to 32 bits of resolution per channel, enabling
lighting designers the flexibility to choose the LED array size and
color quality. PSoC Express software, with lighting specific
drivers, can significantly cut development time and simplify
implementation of fixed color points through temperature and
LED binning compensation. EZ-Color's virtually limitless analog
and digital customization allow for simple integration of features
in addition to intelligent lighting, such as Battery Charging, Image
Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.
Target Applications
■
LCD Backlight
■
Large Signs
■
General Lighting
■
Architectural Lighting
■
Camera/Cell Phone Flash
■
Flashlights
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
to 2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the EZ-Color device.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configurations include those listed below.
■
PrISM (8 to 32 bit)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 4)
■
SPI master and slave (up to 4 each)
■
I2C slave and multi-master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 4)
■
Generators (8 to 32 bit)
The M8C CPU core is a powerful processor with speeds up to 48
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Memory encompasses 32 KB of Flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Characteristics on page 4.
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
Document Number: 001-13105 Rev. **
Page 3 of 39
CY8CLED16
The Analog System
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 6
Port 3
Port 4
Port 2
To System Bus
Digital Clocks
From Core
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
Port 1
Port 0
To Analog
System
DIGITAL SYSTEM
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
8
8
Row Input
Configuration
DBB10
DBB11
DCB12
4
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Document Number: 001-13105 Rev. **
GOE[7:0]
Row Output
Configuration
Row 3
Row Output
Configuration
Row Input
Configuration
Row 1
8
Row Output
Configuration
Row Input
Configuration
8
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak Detectors
■
Many other topologies possible
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
GOO[7:0]
Page 4 of 39
CY8CLED16
Additional System Resources
Figure 2. Analog System Block Diagram
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
P0[7]
P2[3]
P2[1]
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Resources include a multiplier, decimator, switch mode pump,
low voltage detection, and power on reset. Statements
describing the merits of each system resource are presented
below.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-13105 Rev. **
Page 5 of 39
CY8CLED16
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table.
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
SRAM
Size
Flash
Size
CapSense
CY8CLED04
4
56
1
4
48
2
2
6
1K
16K
Yes
CY8CLED08
8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
64
4
16
12
4
4
12
2K
32K
No
PSoC Part
Number
Analog
Blocks
LED
Channels
Table 1. EZ-Color Device Characteristics
Getting Started
The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using PSoC Express to create HB
LED applications. This data sheet is an overview of the EZ-Color
integrated circuit and presents specific pin, register, and
electrical specifications.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
Development Kits
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at
http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on EZ-Color to view a current list of available
items.
Application Notes
Technical Training Modules
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date by default.
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog, CapSense, and HB LED. Go to
http://www.cypress.com/techtrain.
Document Number: 001-13105 Rev. **
Page 6 of 39
CY8CLED16
Development Tools
PSoC Express is a high-level design tool for creating embedded
systems with devices using Cypress's PSoC Mixed-Signal
technology. With PSoC Express you create a complete
embedded solution including all necessary on-chip peripherals,
block configuration, interrupt handling and application software
without writing a single line of assembly or C code.
PSoC Express solves design problems the way you think about
the system:
■
Select input and output devices based upon system requirements.
■
Add a communications interface and define its interface to
system (using registers).
■
Define when and how an output device changes state based
upon any and all other system devices.
■
Based upon the design, automatically select one or more PSoC
Mixed-Signal Controllers that match system requirements.
Figure 3. PSoC Express
Most of the files associated with a project are automatically
generated by PSoC Express during the build process, but you
can make changes directly to the custom.c and custom.h files
and also add your own custom code to the project in the Project
Manager.
Application Editor
The Application Editor allows you to edit custom.c and custom.h
as well as any C or assembly language source code that you add
to your project. With PSoC Express you can create application
software without writing a single line of assembly or C code, but
you have a full featured application editor at your finger tips if you
want it.
Build Manager
The Build Manager gives you the ability to build the application
software, assign pins, and generate the data sheet, schematic,
and BOM for your project.
Board Monitor
The Board Monitor is a debugging tool designed to be used
while attached to a prototype board through a communication
interface that allows you to monitor changes in the various
design elements in real time.
The default communication for the board monitor is I2C. It uses
the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit.
Tuners
A Tuner is a visual interface for the Board Monitor that allows
you to view the performance of the HB LED drivers on your test
board while your program is running, and manually override values and see the results.
Hardware Tools
PSoC Express Subsystems
Express Editor
The Express Editor allows you to create designs visually by
dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic
that controls them.
Project Manager
The Project Manager allows you to work with your applications
and projects in PSoC Express. A PSoC Express application is a
top level container for projects and their associated files. Each
project contains a design that uses a single PSoC device. An
application can contain multiple projects so if you are creating an
application that uses multiple PSoC devices you can keep all of
the projects together in a single application.
Document Number: 001-13105 Rev. **
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
I2C to USB Bridge
The I2C to USB Bridge is a quick and easy link from any design
or application’s I2C bus to a PC via USB for design testing,
debugging and communication.
Page 7 of 39
CY8CLED16
Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 15 lists all the abbreviations used to
measure the PSoC devices.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
Numeric Naming
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC™
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SLIMO
slow IMO
SMP
switch mode pump
SRAM
static random access memory
Document Number: 001-13105 Rev. **
Page 8 of 39
CY8CLED16
Pin Information
Pinouts
The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled
with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
IO
IO
I
IO
IO
I
10
11
12
13
IO
IO
IO
IO
14
15
IO
I
I
Power
IO
IO
IO
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Power
16
17
18
19
Pin
Name
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Input
I
I
I
IO
IO
I
Power
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
28-Pin Device
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I,
A, I, P2[3]
P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
Document Number: 001-13105 Rev. **
Page 9 of 39
CY8CLED16
48-Pin Part Pinouts
Table 3. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
1
2
3
4
5
6
7
8
9
10
11
12
13
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
IO
IO
I
14
15
16
17
18
19
20
21
22
23
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
24
25
IO
I
I
Power
IO
IO
IO
IO
IO
IO
IO
IO
IO
36
37
38
39
40
41
42
43
44
45
46
47
48
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Power
26
27
28
29
30
31
32
33
34
35
Pin
Name
Vss
P1[0]
Input
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Power
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
I
IO
IO
I
48-Pin Device
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
Document Number: 001-13105 Rev. **
Page 10 of 39
CY8CLED16
Table 4. 48-Pin Part Pinout (QFN**)
IO
P4[7]
4
IO
P4[5]
5
IO
P4[3]
6
IO
P3[7]
9
IO
P3[5]
10
IO
P3[3]
11
IO
P3[1]
12
IO
P5[3]
13
IO
P5[1]
14
IO
P1[7]
I2C Serial Clock (SCL).
15
IO
P1[5]
I2C Serial Data (SDA).
16
IO
P1[3]
17
IO
P1[1]
18
Power
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Vss
Ground connection.
19
IO
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
20
IO
P1[2]
21
IO
P1[4]
22
IO
P1[6]
23
IO
P5[0]
24
IO
P5[2]
25
IO
P3[0]
26
IO
P3[2]
27
IO
P3[4]
28
IO
29
(Top View)
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
Optional External Clock Input (EXTCLK).
P3[6]
Input
XRES
Active high external reset with internal pull
down.
30
IO
P4[0]
31
IO
P4[2]
32
IO
P4[4]
33
IO
34
IO
I
P2[0]
Direct switched capacitor block input.
35
IO
I
P2[2]
Direct switched capacitor block input.
36
IO
P2[4]
External Analog Ground (AGND).
37
IO
P2[6]
External Voltage Reference (VREF).
38
IO
I
P0[0]
Analog column mux input.
39
IO
IO
P0[2]
Analog column mux input and column output.
40
IO
IO
P0[4]
Analog column mux input and column output.
41
IO
I
P0[6]
Analog column mux input.
42
MLF
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
IO
1
2
3
4
5
6
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
8
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
15
16
Switch Mode Pump (SMP) connection to
external components required.
I2C SDA, P1[5]
P1[3]
SMP
48
47
46
45
44
43
P4[1]
Power
P0[0], A, I
P2[6], External VREF
Direct switched capacitor block input.
3
38
37
Direct switched capacitor block input.
P2[1]
P5[0]
P5[2]
P2[3]
I
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
I
IO
42
41
40
39
IO
2
P2[5]
P2[7]
P0[1], A, I
1
7
48-Pin PSoC Device
Description
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Pin
Name
Analog
13
14
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
Vdd
Supply voltage.
43
IO
I
P0[7]
Analog column mux input.
44
IO
IO
P0[5]
Analog column mux input and column output.
45
IO
IO
P0[3]
Analog column mux input and column output.
Document Number: 001-13105 Rev. **
Page 11 of 39
CY8CLED16
Table 4. 48-Pin Part Pinout (QFN**)
46
IO
47
IO
I
P2[7]
P0[1]
48
IO
P2[5]
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The QFN package has a center pad that must be connected to ground (Vss).
Register Reference
Register Conventions
Register Mapping Tables
Abbreviations Used
This chapter lists the registers of the CY8CLED16 EZ-Color
device.
The register conventions specific to this section are listed in the
following table.
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
The device has a total register address space of 512 bytes. The
register space is referred to as IO space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines
which bank the user is currently in. When the XOI bit is set the
user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DBB20DR0
DBB20DR1
DBB20DR2
DBB20CR0
DBB21DR0
DBB21DR1
DBB21DR2
DBB21CR0
DCB22DR0
DCB22DR1
DCB22DR2
DCB22CR0
DCB23DR0
DCB23DR1
DCB23DR2
DCB23CR0
DBB30DR0
DBB30DR1
DBB30DR2
DBB30CR0
DBB31DR0
DBB31DR1
DBB31DR2
PRT5DM2
17
RW
DBB31CR0
PRT6DR
18
RW
DCB32DR0
PRT6IE
19
RW
DCB32DR1
PRT6GS
1A
RW
DCB32DR2
PRT6DM2
1B
RW
DCB32CR0
PRT7DR
1C
RW
DCB33DR0
PRT7IE
1D
RW
DCB33DR1
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. **
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
57
58
59
5A
5B
5C
5D
#
#
W
RW
#
#
W
ASC21CR3
97
ASD22CR0
98
ASD22CR1
99
ASD22CR2
9A
ASD22CR3
9B
ASC23CR0
9C
ASC23CR1
9D
# Access is bit specific.
Acces
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Acces
RW
RW
RW
RW
RW
RW
RW
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
RW
RW
RW
RW
RW
RW
RW
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
D7
D8
D9
DA
DB
DC
DD
#
RW
#
RW
RW
RW
RW
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 12 of 39
CY8CLED16
Table 5. Register Map Bank 0 Table: User Space (continued)
Name
Addr (0,Hex)
Access
Name
PRT7GS
1E
RW
DCB33DR2
PRT7DM2
1F
RW
DCB33CR0
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Addr (0,Hex)
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
#
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC23CR2
ASC23CR3
Addr (0,Hex)
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Acces
Name
RW
INT_MSK3
RW
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
W
MUL0_X
W
MUL0_Y
R
MUL0_DH
R
MUL0_DL
RW
ACC0_DR1
RW
ACC0_DR0
RW
ACC0_DR3
RW
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Acces
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Table 6. Register Map Bank 1 Table: Configuration Space
PRT0DM0
00
RW
DBB20FN
40
RW
ASC10CR0
80
Acces
s
RW
RDI2RI
C0
Acces
s
RW
PRT0DM1
01
RW
DBB20IN
41
RW
ASC10CR1
81
RW
RDI2SYN
C1
RW
PRT0IC0
02
RW
DBB20OU
42
RW
ASC10CR2
82
RW
RDI2IS
C2
RW
PRT0IC1
03
RW
ASC10CR3
83
RW
RDI2LT0
C3
RW
PRT1DM0
04
RW
DBB21FN
44
RW
ASD11CR0
84
RW
RDI2LT1
C4
RW
PRT1DM1
05
RW
DBB21IN
45
RW
ASD11CR1
85
RW
RDI2RO0
C5
RW
PRT1IC0
06
RW
DBB21OU
46
RW
ASD11CR2
86
RW
RDI2RO1
C6
RW
PRT1IC1
07
RW
ASD11CR3
87
RW
PRT2DM0
08
RW
DCB22FN
48
RW
ASC12CR0
88
RW
RDI3RI
C8
RW
PRT2DM1
09
RW
DCB22IN
49
RW
ASC12CR1
89
RW
RDI3SYN
C9
RW
PRT2IC0
0A
RW
DCB22OU
4A
RW
ASC12CR2
8A
RW
RDI3IS
CA
RW
PRT2IC1
0B
RW
ASC12CR3
8B
RW
RDI3LT0
CB
RW
PRT3DM0
0C
RW
DCB23FN
4C
RW
ASD13CR0
8C
RW
RDI3LT1
CC
RW
PRT3DM1
0D
RW
DCB23IN
4D
RW
ASD13CR1
8D
RW
RDI3RO0
CD
RW
PRT3IC0
0E
RW
DCB23OU
4E
RW
ASD13CR2
8E
RW
RDI3RO1
CE
RW
PRT3IC1
0F
RW
ASD13CR3
8F
RW
PRT4DM0
10
RW
DBB30FN
50
RW
ASD20CR0
90
RW
GDI_O_IN
D0
RW
PRT4DM1
11
RW
DBB30IN
51
RW
ASD20CR1
91
RW
GDI_E_IN
D1
RW
PRT4IC0
12
RW
DBB30OU
52
RW
ASD20CR2
92
RW
GDI_O_OU
D2
RW
PRT4IC1
13
RW
ASD20CR3
93
RW
GDI_E_OU
D3
RW
PRT5DM0
14
RW
DBB31FN
54
RW
ASC21CR0
94
RW
D4
Name
Addr(1,Hex)
Access
Name
Addr(1,Hex)
Access
43
47
4B
4F
53
Name
Addr(1,Hex)
Name
Addr(1,Hex)
C7
CF
PRT5DM1
15
RW
DBB31IN
55
RW
ASC21CR1
95
RW
D5
PRT5IC0
16
RW
DBB31OU
56
RW
ASC21CR2
96
RW
D6
PRT5IC1
17
RW
ASC21CR3
97
RW
D7
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. **
57
# Access is bit specific.
Page 13 of 39
CY8CLED16
Table 6. Register Map Bank 1 Table: Configuration Space (continued)
PRT6DM0
18
RW
DCB32FN
58
RW
ASD22CR0
98
Acces
s
RW
PRT6DM1
19
RW
DCB32IN
59
RW
ASD22CR1
99
RW
D9
PRT6IC0
1A
RW
DCB32OU
5A
RW
ASD22CR2
9A
RW
DA
PRT6IC1
1B
RW
ASD22CR3
9B
RW
DB
PRT7DM0
1C
RW
DCB33FN
5C
RW
ASC23CR0
9C
RW
PRT7DM1
1D
RW
DCB33IN
5D
RW
ASC23CR1
9D
RW
OSC_GO_EN
DD
RW
PRT7IC0
1E
RW
DCB33OU
5E
RW
ASC23CR2
9E
RW
OSC_CR4
DE
RW
PRT7IC1
1F
RW
ASC23CR3
9F
RW
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
Name
Addr(1,Hex)
Access
23
Name
Addr(1,Hex)
Access
5B
5F
Name
Addr(1,Hex)
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
DBB01OU
26
RW
27
Name
Addr(1,Hex)
Acces
s
D8
DC
E5
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
DEC_CR2
E6
E7
RW
DCB02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
W
DCB02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
6B
AB
ECO_TR
EB
W
2B
DCB03FN
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
EF
DBB10FN
30
RW
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10IN
31
RW
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10OU
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
33
DBB11FN
34
RW
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11IN
35
RW
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11OU
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
ACB01CR2
77
RW
37
B7
F6
CPU_F
F7
DCB12FN
38
RW
ACB02CR3
78
RW
RDI1RI
B8
RW
DCB12IN
39
RW
ACB02CR0
79
RW
RDI1SYN
B9
RW
DCB12OU
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
FC
3B
DCB13FN
3C
RW
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DCB13IN
3D
RW
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13OU
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
ACB03CR2
7F
RW
3F
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. **
BF
RL
F8
F9
FLS_PR1
FA
RW
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Page 14 of 39
CY8CLED16
Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8CLED16 EZ-Color device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at
http://www.cypress.com/ez-color.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Refer to Table 23 for the electrical specifications
on the internal main oscillator (IMO) using SLIMO mode.
Figure 4. Voltage versus CPU Frequency, and IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
SLIMO Mode = 0
5.25
3.60
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.00
3.00
93 kHz
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 7. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
oC
degree Celsius
μW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
μA
microampere
pp
peak-to-peak
μF
microfarad
ppm
μH
microhenry
ps
picosecond
μs
microsecond
sps
samples per second
μV
microvolts
σ
sigma: one standard deviation
microvolts root-mean-square
V
volts
μVrms
Document Number: 001-13105 Rev. **
parts per million
Page 15 of 39
CY8CLED16
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
25
+100
o
C
TA
Ambient Temperature with Power Applied
-40
–
+85
o
C
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5 V
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5 V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog
Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
Notes
Higher storage temperatures will reduce data
retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade
reliability.
Human Body Model ESD.
Operating Temperature
Table 9. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
o
TJ
Junction Temperature
-40
–
+100
oC
Document Number: 001-13105 Rev. **
Notes
C
The temperature rise from ambient to junction
is package specific. See “Thermal Impedances
per Package” on page 36. The user must limit
the power consumption to comply with this
requirement.
Page 16 of 39
CY8CLED16
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.00
–
5.25
V
See DC POR and LVD specifications,
Table 3-15 on page 27.
IDD
Supply Current
–
8
14
mA
Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz,
SYSCLK doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
IDD3
Supply Current
–
5
9
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.
IDDP
Supply current when IMO = 6 MHz using SLIMO mode.
–
2
3
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU =
0.75 MHz, SYSCLK doubler disabled, VC1 =
0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active.
–
3
10
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active.
–
4
25
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC.
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
internal slow oscillator, and 32 kHz crystal oscillator active.
–
4
12
μA
Conditions are with properly loaded, 1 μW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and 32 kHz crystal oscillator active.
–
5
27
μA
VREF
Reference Voltage (Bandgap)
1.28
1.3
1.32
V
55 oC.
Conditions are with properly loaded, 1 μW max,
32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85
o
C.
Trimmed for appropriate Vdd.
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RPU
Pull up Resistor
4
5.6
8
kΩ
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
150 mA maximum combined IOL budget.
0.8
V
Vdd = 3.0 to 5.25.
V
Vdd = 3.0 to 5.25.
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
Document Number: 001-13105 Rev. **
Page 17 of 39
CY8CLED16
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 12. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range. All Cases, except highest.
0.0
–
Vdd
V
0.5
–
Vdd - 0.5
V
Power = High, Opamp Bias = High
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (internal signals)
Vdd - .01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal signals)
–
–
0.1
V
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
–
150
200
μA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
67
80
–
dB
PSRROA
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd.
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 oC.
VCMOA
Common Mode Voltage Range
0
–
Vdd
V
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
80
–
–
dB
VOHIGHOA
High Output Voltage Swing (internal signals)
Vdd - .01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal signals)
–
–
.01
V
Document Number: 001-13105 Rev. **
Page 18 of 39
CY8CLED16
Table 13. 3.3V DC Operational Amplifier Specifications (continued)
ISOA
PSRROA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
–
150
200
μA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
–
–
Supply Voltage Rejection Ratio
54
80
–
Not Allowed
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
VREFLPC
Low power comparator (LPC) reference voltage range
0.2
–
Vdd - 1
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Notes
V
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
1
Ω
Power = High
–
–
1
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd
–
–
V
Power = High
+ 1.3
–
–
V
VOHIGHOB
Notes
0.5 x Vdd
+ 1.3
VOLOWOB
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd
V
Power = High
–
–
- 1.3
V
0.5 x Vdd
- 1.3
ISOB
PSRROB
Supply Current Including Bias Cell (No Load)
Power = Low
–
1.1
2
mA
Power = High
–
2.6
5
mA
Supply Voltage Rejection Ratio
40
64
–
dB
Document Number: 001-13105 Rev. **
Page 19 of 39
CY8CLED16
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
–
10
Ω
Power = High
–
–
10
Ω
Power = Low
0.5 x Vdd
–
–
V
Power = High
+ 1.0
–
–
V
VOHIGHOB
Notes
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
0.5 x Vdd
+ 1.0
VOLOWOB
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd
V
Power = High
–
–
- 1.0
V
0.5 x Vdd
- 1.0
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
0.8
1
mA
Power = High
–
2.0
5
mA
Supply Voltage Rejection Ratio
60
64
–
dB
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 17. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5V Output Voltage at Vdd from Pump
4.75
5.0
5.25
V
Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
VPUMP 3V
3V Output Voltage at Vdd from Pump
3.00
3.25
3.60
V
Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
8
–
–
mA
SMP trip voltage is set to 3.25V.
VBAT = 1.8V, VPUMP = 5.0V
5
–
–
mA
SMP trip voltage is set to 5.0V.
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote.a SMP trip voltage is
set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.a SMP trip voltage is
set to 3.25V.
VBATSTART
Minimum Input Voltage from Battery to Start Pump
1.2
–
–
V
Configuration of footnote.a 0oC ≤ TA ≤ 100.
Configuration of footnote.a
1.25V at TA = -40oC.
ΔVPUMP_Line Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote.a VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD Specification,
Table 3-15 on page 27.
ΔVPUMP_Loa
Load Regulation
–
5
–
%VO
Configuration of footnote.a VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD Specification,
Table 3-15 on page 27.
Output Voltage Ripple (depends on capacitor/load)
–
100
–
mVpp
Configuration of footnote.a Load is 5 mA.
Efficiency
35
50
–
%
Configuration of footnote.a Load is 5 mA. SMP
trip voltage is set to 3.25V.
d
ΔVPUMP_Rip
ple
E3
Document Number: 001-13105 Rev. **
Page 20 of 39
CY8CLED16
Table 17. DC Switch Mode Pump (SMP) Specifications (continued)
FPUMP
Switching Frequency
–
1.4
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
a. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode. See Figure 5.
Figure 5. Basic Switch Mode Pump Circuit
DC Analog Reference Specifications
D1
Vdd
V PUMP
L1
V BAT
+
C1
SMP
Battery
PSoC
The following tables list guaranteed maximum and minimum
specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at
25°C and are for design guidance only.
The guaranteed specifications are measured through the Analog
Continuous Time PSoC blocks. The power levels for AGND refer
to the power of the Analog Continuous Time PSoC block. The
power levels for RefHi and RefLo refer to the Analog Reference
Control register. The limits stated for AGND include the offset
error of the AGND buffer local to the Analog Continuous Time
PSoC block. Reference control power is high.
Vss
Table 18. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
VBG5
Bandgap Voltage Reference 5V
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 0.02
Vdd/2
Vdd/2 +
0.02
V
–
AGND = 2 x BandGapa
2.52
2.60
2.72
V
P2[4] 0.013
P2[4]
P2[4] +
0.013
V
–
AGND = P2[4] (P2[4] =
–
AGND = BandGapa
1.27
1.3
1.34
V
–
AGND = 1.6 x BandGapa
2.03
2.08
2.13
V
-0.034
0.000
0.034
V
Vdd/2 +
Vdd/2 +
Vdd/2 +
V
1.21
1.3
1.382
Vdd/2)a
–
AGND Block to Block Variation (AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
a
–
RefHi = 3 x BandGap
3.75
3.9
4.05
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
P2[6] +
2.478
P2[6] +
2.6
P2[6] +
2.722
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] +
1.218
P2[4] +
1.3
P2[4] +
1.382
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] +
P2[6] 0.058
P2[4] +
P2[6]
P2[4] +
P2[6] +
0.058
V
–
RefHi = 2 x BandGap
2.50
2.60
2.70
V
–
RefHi = 3.2 x BandGap
4.02
4.16
4.29
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 -
Vdd/2 -
Vdd/2 -
V
1.369
1.30
1.231
–
RefLo = BandGap
1.20
1.30
1.40
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2.489 P2[6]
2.6 P2[6]
2.711 P2[6]
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] 1.368
P2[4] 1.30
P2[4] 1.232
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] P2[6] 0.042
P2[4] P2[6]
P2[4] P2[6] +
0.042
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Document Number: 001-13105 Rev. **
Page 21 of 39
CY8CLED16
Table 19. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
VBG33
Bandgap Voltage Reference 3.3V
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 0.02
Vdd/2
Vdd/2 +
0.02
V
–
AGND = 2 x BandGapa
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] 0.009
P2[4]
P2[4] +
0.009
V
–
AGND = BandGapa
1.27
1.30
1.34
V
2.03
2.08
2.13
V
-0.034
0.000
0.034
mV
–
a
AGND = 1.6 x BandGap
–
AGND Block to Block Variation (AGND = Vdd/2)
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] +
P2[6] 0.042
P2[4] +
P2[6]
P2[4] +
P2[6] +
0.042
V
–
RefHi = 2 x BandGap
2.50
2.60
2.70
V
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] P2[6] 0.036
P2[4] P2[6] +
0.036
V
a
P2[4] P2[6]
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
Document Number: 001-13105 Rev. **
Notes
Page 22 of 39
CY8CLED16
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. DC POR, SMP, and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
VPPOR1R
PORLEV[1:0] = 01b
VPPOR2R
PORLEV[1:0] = 10b
2.91
–
4.39
V
–
4.55
V
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
2.82
–
4.39
V
–
4.55
V
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
–
92
–
mV
VPH1
PORLEV[1:0] = 01b
–
0
–
mV
VPH2
PORLEV[1:0] = 10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98a
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74b
VLVD6
VM[2:0] = 110b
4.63
4.73
VLVD7
VM[2:0] = 111b
4.72
4.81
V
V
V
V
V
V
V
V
4.82
4.91
Vdd Value for SMP Trip
VPUMP0
VM[2:0] = 000b
2.96
3.02
3.08
VPUMP1
VM[2:0] = 001b
3.03
3.10
3.16
VPUMP2
VM[2:0] = 010b
3.18
3.25
3.32
VPUMP3
VM[2:0] = 011b
4.11
4.19
4.28
VPUMP4
VM[2:0] = 100b
4.55
4.64
4.74
VPUMP5
VM[2:0] = 101b
4.63
4.73
4.82
VPUMP6
VM[2:0] = 110b
4.72
4.82
4.91
VPUMP7
VM[2:0] = 111b
4.90
5.00
5.10
V
V
V
V
V
V
V
V
V
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-13105 Rev. **
Page 23 of 39
CY8CLED16
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply Current During Programming or Verify
–
10
30
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss +
0.75
V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
FlashENT
Flash Endurance (total)a
1,800,00
0
–
–
–
Erase/write cycles.
FlashDR
Flash Data Retention
10
–
–
Years
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13105 Rev. **
Page 24 of 39
CY8CLED16
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 23. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6a,b,c
MHz
Trimmed for 5V or 3.3V operation using factory
trim values. See the figure on page 19. SLIMO
Mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35a,b,c
MHz
Trimmed for 5V or 3.3V operation using factory
trim values. See the figure on page 19. SLIMO
Mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3b,c
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2
F24M
Digital PSoC Block Frequency
0
24
24.6b, d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent. 50%
duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWLOW
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
300
600
ms
Jitter32k
32 kHz Period Jitter
–
100
a,b,d
MHz
Refer to the AC Digital Block Specifications
below.
The crystal oscillator frequency is within 100 ppm of its
final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive
level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC ≤ TA
≤ 85 oC.
ns
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2a,c
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or row out- –
put.
–
12.3
MHz
TRAMP
Supply Ramp Time
–
–
μs
a.
b.
c.
d.
0
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-13105 Rev. **
Page 25 of 39
CY8CLED16
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 001-13105 Rev. **
Page 26 of 39
CY8CLED16
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FGPIO
GPIO Operating Frequency
0
–
12.3
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Figure 11. GPIO Timing Diagram
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum
specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at
25°C and are for design guidance only.
90%
GPIO
Pin
Output
Voltage
Settling times, slew rates, and gain bandwidth are based on the
Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
10%
TRiseF
TRiseS
Document Number: 001-13105 Rev. **
TFallF
TFallS
Page 27 of 39
CY8CLED16
Table 25. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = High, Opamp Bias = High
–
–
0.62
μs
Power = Low, Opamp Bias = Low
–
–
5.9
μs
Power = Medium, Opamp Bias = High
–
–
0.92
μs
Power = High, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.15
–
–
V/μs
Power = Medium, Opamp Bias = High
1.7
–
–
V/μs
Power = High, Opamp Bias = High
6.5
–
–
V/μs
Power = Low, Opamp Bias = Low
0.01
–
–
V/μs
Power = Medium, Opamp Bias = High
0.5
–
–
V/μs
Power = High, Opamp Bias = High
4.0
–
–
V/μs
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time to 0.1% for a 1V Step (10 pF load,
Unity Gain)
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF
load, Unity Gain)
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF
load, Unity Gain)
Gain Bandwidth Product
Table 26. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1% of a 1V Step (10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
–
–
5.41
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.31
–
–
V/μs
Power = Medium, Opamp Bias = High
2.7
–
–
V/μs
Power = Low, Opamp Bias = Low
0.24
–
–
V/μs
Power = Medium, Opamp Bias = High
1.8
–
–
V/μs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time to 0.1% of a 1V Step (10 pF load,
Unity Gain)
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF
load, Unity Gain)
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF
load, Unity Gain)
Gain Bandwidth Product
Document Number: 001-13105 Rev. **
Page 28 of 39
CY8CLED16
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 27. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Document Number: 001-13105 Rev. **
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator reference set
within VREFLPC.
Page 29 of 39
CY8CLED16
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. AC Digital Block Specifications
Function
Description
Min
Typ
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
Timer
Capture Pulse Width
50a
–
Maximum Frequency, No Capture
–
Maximum Frequency, With Capture
–
Enable Pulse Width
Counter
Dead Band
Max
Units
Notes
49.2
MHz
4.75V < Vdd < 5.25V.
24.6
MHz
3.0V < Vdd < 4.75V.
–
ns
–
49.2
MHz
–
24.6
MHz
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
a
50
–
–
ns
Maximum Block Clocking Frequency (< 4.75V)
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Disable Mode
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Maximum Input Clock Frequency
Vdd ≥ 4.75V, 2 Stop Bits
–
–
24.6
MHz
–
–
49.2
MHz
–
–
24.6
MHz
–
–
49.2
MHz
Transmitter
Receiver
Maximum Input Clock Frequency
Vdd ≥ 4.75V, 2 Stop Bits
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
Maximum data rate at 3.08 MHz due to 8 x
over clocking.
Maximum data rate at 6.15 MHz due to 8 x
over clocking.
Maximum data rate at 3.08 MHz due to 8 x
over clocking.
Maximum data rate at 6.15 MHz due to 8 x
over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-13105 Rev. **
Page 30 of 39
CY8CLED16
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4
μs
Power = High
–
–
4
μs
Power = Low
–
–
3.4
μs
Power = High
–
–
3.4
μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.55
–
–
V/μs
Power = High
0.55
–
–
V/μs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 30. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
4.7
μs
Power = High
–
–
4.7
μs
Power = Low
–
–
4
μs
Power = High
–
–
4
μs
Power = Low
.36
–
–
V/μs
Power = High
.36
–
–
V/μs
Power = Low
.4
–
–
V/μs
Power = High
.4
–
–
V/μs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Document Number: 001-13105 Rev. **
Page 31 of 39
CY8CLED16
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 31. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 32. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
–
24.6
MHz
If the frequency of the external clock is greater
than 12 MHz, the CPU clock divider must be
set to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
10
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
Document Number: 001-13105 Rev. **
Page 32 of 39
CY8CLED16
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 34. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Set-up Time
250
–
100a
–
ns
μs
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
Document Number: 001-13105 Rev. **
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Page 33 of 39
CY8CLED16
Packaging Information
This section illustrates the packaging specifications for the CY8CLED16 EZ-Color device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 15. 28-Lead (210-Mil) SSOP
51-85079 *C
Figure 16. 48-Lead (300-Mil) SSOP
51-85061 *C
51 -85061-C
Document Number: 001-13105 Rev. **
Page 34 of 39
CY8CLED16
Figure 17. 48-Lead (7x7 mm) QFN
001-12919 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 001-13105 Rev. **
Page 35 of 39
CY8CLED16
Thermal Impedances
Table 35. Thermal Impedances per Package
Package
Typical
θJA *
28 SSOP
94 oC/W
48 SSOP
69 oC/W
48 QFN**
oC/W
28
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com/psocdesigner.
* TJ = TA + POWER x θJA
** To achieve the thermal impedance specified
for the QFN package, the center thermal pad
should be soldered to the PCB ground plane.
PSoC Programmer
Capacitance on Crystal Pins
Table 36. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 SSOP
2.8 pF
48 SSOP
3.3 pF
48 QFN
1.8 pF
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com/psocprogrammer.
CY3202-C iMAGEcraft C Compiler
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Table 37. Solder Reflow Peak Temperature
Package
Minimum Peak
Temperature*
Maximum Peak
Temperature
28 SSOP
240oC
260oC
48 SSOP
220oC
260oC
48 QFN
220oC
260oC
*Higher temperatures may be required based on the solder
melting point. Typical temperatures for solder are 220 ± 5oC
with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the
solder manufacturer specifications.
Development Tool Selection
Software
This section presents the development tools available for all
current PSoC device families including the CY8CLED16
EZ-Color family.
PSoC Express™
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
Document Number: 001-13105 Rev. **
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3261A-RGB EZ-Color RGB Kit
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Express 3.0 Beta 2, PSoC Programmer, and a suite of
documents, schematics, and firmware examples. The color
selector software application can be installed on a host PC and
is used to control the EZ-Color HB LED controller using the
included USB cable. The application enables you to select colors
via a CIE 1931 chart or by entering coordinates. The kit includes:
■
Training Board (CY8CLED16)
■
One mini-A to mini-B USB Cable
■
PSoC Express CD-ROM
■
Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Express 3.0 you must use
a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
Page 36 of 39
CY8CLED16
CY3210-MiniProg1
■
Getting Started Guide
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
CY3207 Programmer Unit
■
PSoC Designer Software CD
■
PSoC ISSP Software CD
■
Getting Started Guide
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
Accessories (Emulation and Programming)
Table 38. Emulation and Programming Accessories
Part #
Pin
Package
Flex-Pod Kita
Foot Kitb
■
Evaluation Board with LCD Module
CY8CLED16- 28 SSOP
28PVXI
CY3250-29XXX
CY3250-28
SSOP-FK
■
MiniProg Programming Unit
CY3250-29XXX
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
CY8CLED16- 48 SSOP
48PVXI
CY3250-48
SSOP-FK
■
PSoC Designer Software CD
CY8CLED16- 48 QFN
48LFXI
CY3250-29XXX
QFN
CY3250-48
QFN-FK
■
Getting Started Guide
■
USB 2.0 Cable
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
Document Number: 001-13105 Rev. **
Adapterc
Adapters can be
found at
http://www.emulation.com.
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two
flex-pods.
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
c. Programming adapter converts non-DIP package to DIP footprint. Specific
details and ordering information for each of the adapters can be found at
http://www.emulation.com.
3rd-Party Tools
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at
http://www.cypress.com/an2323.
Page 37 of 39
CY8CLED16
Ordering Information
Key Device Features
The following table lists the CY8CLED16 EZ-Color devices’ key package features and ordering codes.
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8CLED16-28PVXI
32K
2K
Yes
-40C to +85C
16
12
24
12
4
Yes
CY8CLED16-28PVXIT
32K
2K
Yes
-40C to +85C
16
12
24
12
4
Yes
CY8CLED16-48PVXI
32K
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
CY8CLED16-48PVXIT
32K
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
CY8CLED16-48LFXI
32K
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
CY8CLED16-48LFXIT
32K
2K
Yes
-40C to +85C
16
12
44
12
4
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 39. Device Key Features and Ordering Information
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
48 Pin (300 Mil) SSOP
48 Pin (300 Mil) SSOP
(Tape and Reel)
48 Pin QFN
48 Pin QFN
(Tape and Reel)
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-13105 Rev. **
Page 38 of 39
CY8CLED16
Document History
Table 40. CY8CLED16 Data Sheet Revision History
Document Title:
CY8CLED16 EZ-Color HB LED Controller
Document Number: 001-13105
Revision
**
ECN #
1148504
Distribution: External/Public
Issue Date
See ECN
Origin of Change
SFVTMP3
Description of Change
New document (revision **).
Posting: None
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works
of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with
a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is
prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13105 Rev. **
Page 39 of 39