Microchip MCP4151T-103E/SL 7/8-bit single/dual spi digital pot with volatile memory Datasheet

MCP413X/415X/423X/425X
7/8-Bit Single/Dual SPI Digital POT with Volatile Memory
Features
Description
• Single or Dual Resistor Network options
• Potentiometer or Rheostat configuration options
• Resistor Network Resolution
- 7-bit: 128 Resistors (129 Steps)
- 8-bit: 256 Resistors (257 Steps)
• RAB Resistances options of:
- 5 kΩ
- 10 kΩ
- 50 kΩ
- 100 kΩ
• Zero Scale to Full-Scale Wiper operation
• Low Wiper Resistance: 75Ω (typical)
• Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• SPI Serial Interface (10 MHz, modes 0,0 & 1,1)
- High-Speed Read/Writes to wiper registers
- SDI/SDO multiplexing (MCP41X1 only)
• Resistor Network Terminal Disconnect Feature
via:
- Shutdown pin (SHDN)
- Terminal Control (TCON) Register
• Brown-out reset protection (1.5V typical)
• Serial Interface Inactive current (2.5 uA typical)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Supports Split Rail Applications
• Internal weak pull-up on all digital inputs
• Wide Operating Voltage:
- 2.7V to 5.5V - Device Characteristics
Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 kΩ device
• Extended temperature range (-40°C to +125°C)
The MCP41XX and MCP42XX devices offer a wide
range of product offerings using an SPI interface. This
family of devices support 7-bit and 8-bit resistor
networks, and Potentiometer and Rheostat pinouts.
Package Types (top view)
MCP41X1
Single Potentiometer
1
2
3
4
CS
SCK
SDI/SDO
VSS
8
7
6
5
MCP41X2
Single Rheostat
CS 1
8 VDD
SCK 2
7 SDO
SDI 3
6 P0B
5 P0W
VSS 4
VDD
P0B
P0W
P0A
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
CS 1
8 VDD
CS 1
7 P0B
SCK 2
6 P0W
SDI 3
5 P0A
VSS 4
EP
9
VSS 4
5 P0W
SDO
12 WP
1
2
11 NC
EP
17
3
10 P0B
9 P0W
5
6
7
8
P0A
4
P1A
PDIP, SOIC, TSSOP
16 15 14 13
P1B
VDD
SDO SCK
SHDN SDI
WP
P0B VSS
P0W V
SS
P0A
P1W
14
13
12
11
10
9
8
VDD
CS
MCP42X1 Dual Potentiometers
1
2
3
4
5
6
7
6 P0B
3x3 DFN*
3x3 DFN*
CS
SCK
SDI
VSS
P1B
P1W
P1A
7 SDO
EP
9
SHDN
SCK 2
SDI/SDO 3
8 VDD
4x4 QFN*
MCP42X2 Dual Rheostat
CS
SCK
SDI
VSS
P1B
1
2
3
4
5
10
9
8
7
6
MSOP, DFN
CS 1
VDD
SDO SCK 2
P0B
P0W SDI 3
P1W VSS 4
10 VDD
EP
11
9 SDO
8 P0B
7 P0W
6 P1W
P1B 5
3x3 DFN*
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2008 Microchip Technology Inc.
DS22060B-page 1
MCP413X/415X/423X/425X
Device Block Diagram
VDD
VSS
CS
SCK
SDI
SDO
NC
SHDN
For Dual Potentiometer
Devices Only
Power-up/
Brown-out
Control
Resistor
Network 0
(Pot 0)
SPI Serial
Interface
Module &
Control
Logic
(WiperLock™
Technology)
Wiper 0
& TCON
Register
P0A
P0W
P0B
P1A
Resistor
Network 1
(Pot 1)
P1W
Wiper 1
& TCON
Register
Memory (4x9)
Wiper0
Wiper1
TCON
STATUS
P1B
For Dual Resistor Network
Devices Only
Device Features
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4132 (3)
1
Rheostat
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4141
1
Potentiometer (1)
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4142
1
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
(3)
1
Potentiometer (1)
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4152 (3)
1
Rheostat
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4161
1
Potentiometer (1)
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
MCP4162
1
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
MCP4231 (3)
2
Potentiometer (1)
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4232 (3)
2
Rheostat
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4151
Wiper
Configuration
(1)
RAB Options (kΩ)
Wiper
- RW
(Ω)
# of Steps
WiperLock
Technology
1 Potentiometer (1) SPI
Device
POR Wiper
Setting
Memory
Type
MCP4131 (3)
# of POTs
Control
Interface
Resistance (typical)
VDD
Operating
Range (2)
MCP4241
2 Potentiometer
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4242
2
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4251 (3)
2
Potentiometer (1)
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4252 (3)
2
Rheostat
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4261
2
Potentiometer (1)
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
MCP4262
2
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
Note 1:
2:
3:
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
Please check Microchip web site for device release and availability.
DS22060B-page 2
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS ............... -0.6V to +7.0V
Voltage on CS, SCK, SDI, SDI/SDO, and
SHDN with respect to VSS ...................................... -0.6V to 12.5V
Voltage on all other pins (PxA, PxW, PxB, and
SDO) with respect to VSS ............................ -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins) ......................±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) ..................................................±20 mA
Maximum output current sunk by any Output pin
......................................................................................25 mA
Maximum output current sourced by any Output pin
......................................................................................25 mA
Maximum current out of VSS pin .................................100 mA
Maximum current into VDD pin ....................................100 mA
Maximum current into PXA, PXW & PXB pins ............±2.5 mA
Storage temperature ....................................-65°C to +150°C
Ambient temperature with power applied
.....................................................................-40°C to +125°C
Total power dissipation (Note 1) ................................400 mW
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins .................................. ≥ 4 kV (HBM),
.......................................................................... ≥ 300V (MM)
Maximum Junction Temperature (TJ) ......................... +150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
© 2008 Microchip Technology Inc.
DS22060B-page 3
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Supply Voltage
VDD
2.7
1.8
—
—
5.5
2.7
V
V
VSS
—
12.5V
V
VSS
—
VDD +
8.0V
V
—
—
1.65
V
CS, SDI, SDO,
SCK, SHDN pin
Voltage Range
VHV
VDD Start Voltage
to ensure Wiper
Reset
VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR
Delay after device
exits the reset
state
(VDD > VBOR)
TBORD
—
10
20
µs
IDD
—
—
450
µA
—
2.5
5
µA
—
0.55
1
mA
Supply Current
(Note 10)
(Note 9)
Conditions
Serial Interface only.
VDD ≥
4.5V
VDD <
4.5V
The CS pin will be at one
of three input levels
(VIL, VIH or VIHH). (Note 6)
RAM retention voltage (VRAM) < VBOR
V/ms
Serial Interface Active,
VDD = 5.5V, CS = VIL, SCK @ 5 MHz,
write all 0’s to volatile Wiper 0 (address
0h)
Serial Interface Inactive,
CS = VIH, VDD = 5.5V
Serial Interface Active,
VDD = 5.5V, CS = VIHH,
SCK @ 5 MHz,
decrement volatile Wiper 0 (address 0h)
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22060B-page 4
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
Resistance
(± 20%)
Resolution
Step Resistance
Nominal
Resistance Match
Wiper Resistance
(Note 3, Note 4)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
RAB
4.0
5
6.0
kΩ
-502 devices (Note 1)
8.0
10
12.0
kΩ
-103 devices (Note 1)
40.0
80.0
50
100
60.0
120.0
kΩ
kΩ
-503 devices (Note 1)
-104 devices (Note 1)
N
RS
|RAB0 - RAB1|
/ RAB
|RBW0 - RBW1|
/ RBW
RW
Nominal
Resistance
Tempco
ΔRAB/ΔT
Ratiometeric
Tempco
Typ
Max
Units
Conditions
257
Taps
8-bit
No Missing Codes
129
Taps
7-bit
No Missing Codes
—
RAB /
(256)
—
Ω
8-bit
Note 6
—
RAB /
(128)
—
Ω
7-bit
Note 6
—
0.2
1.25
%
MCP42X1 devices only
—
0.25
1.5
%
MCP42X2 devices only,
Code = Full-Scale
—
—
75
75
160
300
Ω
Ω
VDD = 5.5 V, IW = 2.0 mA, code = 00h
VDD = 2.7 V, IW = 2.0 mA, code = 00h
—
50
—
ppm/°C TA = -20°C to +70°C
—
100
—
ppm/°C TA = -40°C to +85°C
—
150
—
ppm/°C TA = -40°C to +125°C
ΔVWB/ΔT
—
15
—
ppm/°C Code = Midscale (80h or 40h)
Resistor Terminal
Input Voltage
Range (Terminals
A, B and W)
VA,VW,VB
VSS
—
VDD
V
Maximum current
through A, W or B
IW
—
—
2.5
mA
Leakage current
into A, W or B
IWL
—
100
—
nA
Note 6, Worst case current through
wiper when wiper is either Full-Scale or
Zero Scale.
MCP4XX1 PxA = PxW = PxB = VSS
—
100
—
nA
MCP4XX2 PxB = PxW = VSS
Note 5, Note 6
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2008 Microchip Technology Inc.
DS22060B-page 5
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
Full-Scale Error
(MCP4XX1 only)
(8-bit code =
100h,
7-bit code = 80h)
Zero-Scale Error
(MCP4XX1 only)
(8-bit code = 00h,
7-bit code = 00h)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
VWFSE
-6.0
-0.1
—
LSb
-4.0
-0.1
—
LSb
-3.5
-2.0
-0.1
-0.1
—
—
LSb
LSb
-0.8
-0.1
—
LSb
-0.5
-0.1
—
LSb
-0.5
-0.1
—
LSb
VWZSE
Potentiometer
Integral
Non-linearity
INL
Potentiometer
Differential
Non-linearity
Bandwidth -3 dB
(See Figure 2-64,
load = 30 pF)
DNL
BW
Conditions
8-bit
3.0V ≤ VDD ≤ 5.5V
7-bit
3.0V ≤ VDD ≤ 5.5V
10 kΩ
8-bit
7-bit
3.0V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 5.5V
50 kΩ
8-bit
3.0V ≤ VDD ≤ 5.5V
7-bit
3.0V ≤ VDD ≤ 5.5V
100 kΩ 8-bit
3.0V ≤ VDD ≤ 5.5V
5 kΩ
-0.5
-0.1
—
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
—
—
+0.1
+0.1
+6.0
+3.0
LSb
LSb
5 kΩ
8-bit
7-bit
3.0V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+3.5
LSb
10 kΩ
8-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+2.0
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+0.8
LSb
8-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+0.5
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
—
—
+0.1
+0.1
+0.5
+0.5
LSb
LSb
100 kΩ 8-bit
7-bit
3.0V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 5.5V
-1
±0.5
+1
LSb
8-bit
-0.5
±0.25
+0.5
LSb
7-bit
50 kΩ
3.0V ≤ VDD ≤ 5.5V
MCP4XX1 devices only
(Note 2)
3.0V ≤ VDD ≤ 5.5V
MCP4XX1 devices only
(Note 2)
8-bit Code = 80h
-0.5
±0.25
+0.5
LSb
8-bit
-0.25
±0.125
+0.25
LSb
7-bit
—
2
—
MHz
5 kΩ
—
2
—
MHz
—
1
—
MHz
—
1
—
MHz
—
200
—
kHz
50 kΩ
8-bit
Code = 80h
—
—
200
100
—
—
kHz
kHz
7-bit
100 kΩ 8-bit
Code = 40h
Code = 80h
—
100
—
kHz
7-bit
Code = 40h
7-bit
10 kΩ
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22060B-page 6
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
Rheostat Integral
Non-linearity
MCP41X1
(Note 4, Note 8)
MCP4XX2
devices only
(Note 4)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
R-INL
Min
Typ
Max
Units
-1.5
±0.5
+1.5
LSb
-8.25
+4.5
+8.25
LSb
-1.125
±0.5
+1.125
LSb
-6.0
+4.5
+6.0
LSb
Conditions
5 kΩ
8-bit
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V
7-bit
-1.125
-4.0
±0.5
+2.5
+1.5
+5.5
1.8V
LSb
LSb
Section 2.0
±0.5
+1.125
LSb
+2.5
LSb
+4.0
10 kΩ
8-bit
7-bit
-1.5
±0.5
+1.5
LSb
-2.0
+1
+2.0
LSb
50 kΩ
8-bit
±0.5
+1.125
LSb
-1.5
+1
+1.5
LSb
-1.0
±0.5
+1.0
LSb
-1.5
+0.25
+1.5
LSb
-0.8
±0.5
+0.8
LSb
-1.125
+0.25
+1.125
LSb
1.8V
5.5V, IW = 450 µA
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
1.8V
Section 2.0
-1.125
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
3.0V, IW = 240 µA
(Note 7)
1.8V
Section 2.0
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V
100 kΩ 8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Section 2.0
Section 2.0
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
Section 2.0
-1.5
-5.5
5.5V, IW = 900 µA
1.8V
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
1.8v
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2008 Microchip Technology Inc.
DS22060B-page 7
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
Rheostat
Differential
Non-linearity
MCP41X1
(Note 4, Note 8)
MCP4XX2
devices only
(Note 4)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
R-DNL
-0.5
±0.25
+0.5
LSb
-1.0
+0.5
+1.0
LSb
-0.375
Section 2.0
±0.25
+0.375
LSb
-0.75
+0.5
LSb
+0.75
Conditions
5 kΩ
8-bit
3.0V (Note 7)
7-bit
1.8V
5.5V, IW = 900 µA
3.0V (Note 7)
Section 2.0
1.8V
-0.5
±0.25
+0.5
LSb
-1.0
+0.25
+1.0
LSb
-0.375
Section 2.0
±0.25
+0.375
LSb
-0.75
+0.5
LSb
+0.75
5.5V, IW = 900 µA
10 kΩ
8-bit
5.5V, IW = 450 µA
3.0V (Note 7)
7-bit
1.8V
5.5V, IW = 450 µA
3.0V (Note 7)
Section 2.0
1.8V
±0.25
+0.5
LSb
±0.25
+0.5
LSb
3.0V (Note 7)
-0.375
Section 2.0
±0.25
+0.375
LSb
1.8V
5.5V, IW = 90 µA
-0.375
±0.25
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
-0.375
-0.375
±0.25
±0.25
+0.375
+0.375
LSb
LSb
CAW
—
75
—
pF
f =1 MHz, Code = Full-Scale
Capacitance (Pw)
CW
—
120
—
pF
f =1 MHz, Code = Full-Scale
Capacitance (PB)
CBW
—
75
—
pF
f =1 MHz, Code = Full-Scale
+0.375
50 kΩ
8-bit
5.5V, IW = 90 µA
-0.5
-0.5
7-bit
3.0V (Note 7)
Section 2.0
1.8V
100 kΩ 8-bit
5.5V, IW = 45 µA
3.0V (Note 7)
Section 2.0
1.8V
7-bit
5.5V, IW = 45 µA
3.0V (Note 7)
1.8V
Capacitance (PA)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22060B-page 8
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
Digital Inputs/Outputs (CS, SDI, SDO, SCK, SHDN)
Schmitt Trigger
High Input
Threshold
VIH
0.45 VDD
—
—
V
2.7V ≤ VDD ≤ 5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
0.5 VDD
—
—
V
1.8V ≤ VDD ≤ 2.7V
Schmitt Trigger
Low Input
Threshold
VIL
—
—
0.2VDD
V
Hysteresis of
Schmitt Trigger
Inputs
VHYS
—
0.1VDD
—
V
High Voltage Limit
VMAX
—
—
12.5 (6)
V
Pin can tolerate VMAX or less.
VSS
—
0.3VDD
V
IOL = 5 mA, VDD = 5.5V
VSS
—
0.3VDD
V
IOL = 1 mA, VDD = 1.8V
VOH
0.7VDD
0.7VDD
—
—
VDD
VDD
V
V
IOH = -2.5 mA, VDD = 5.5V
IOL = -1 mA, VDD = 1.8V
IPU
—
—
1.75
mA
Internal VDD pull-up, VIHH pull-down,
VDD = 5.5V, VCS = 12.5V
RCS
—
—
170
16
—
—
µA
kΩ
CS pin, VDD = 5.5V, VCS = 3V
VDD = 5.5V, VCS = 3V
IIL
-1
—
1
µA
VIN = VDD and VIN = VSS
CIN, COUT
—
10
—
pF
fC = 20 MHz
N
0h
—
1FFh
hex
8-bit device
N
0h
—
—
80h
1FFh
—
hex
hex
7-bit device
8-bit device
—
40h
—
hex
7-bit device
Output Low
Voltage (SDO)
VOL
Output High
Voltage (SDO)
Weak Pull-up /
Pull-down Current
CS Pull-up /
Pull-down
Resistance
Input Leakage
Current
Pin Capacitance
RAM (Wiper) Value
Value Range
POR/BOR Value
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2008 Microchip Technology Inc.
DS22060B-page 9
MCP413X/415X/423X/425X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
PSS
—
0.0015
0.0035
%/%
8-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
—
0.0015
0.0035
%/%
7-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
Power Requirements
Power Supply
Sensitivity
(MCP41X2 and
MCP42X2 only)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22060B-page 10
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
1.1
SPI Mode Timing Waveforms and Requirements
VIHH
VIH
CS
VIH
VIL
70
84
72
SCK
83
71
78
79
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
FIGURE 1-1:
TABLE 1-1:
#
SPI Timing Waveform (Mode = 11).
SPI REQUIREMENTS (MODE = 11)
Characteristic
SCK Input Frequency
Symbol
Min
Max Units
FSCK
—
—
60
45
500
45
500
10
20
—
—
10
1
—
—
—
—
—
—
—
50
70
170
—
70
71
CS Active (VIL or VIHH) to SCK↑ input
SCK input high time
72
SCK input low time
73
74
77
80
Setup time of SDI input to SCK↑ edge
Hold time of SDI input from SCK↑ edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK↓ edge
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
83
CS Inactive (VIH) after SCK↑ edge
TscH2csI
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
84
© 2008 Microchip Technology Inc.
TcsA2scH
TscH
TscL
TcsA2csI
100
1
50
—
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Conditions
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
Note 1
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
DS22060B-page 11
MCP413X/415X/423X/425X
VIH
VIHH
CS
SCK
VIH
82
VIL
84
70
83
71
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
73
SDI
80
72
MSb IN
77
BIT6 - - - -1
LSb IN
74
FIGURE 1-2:
TABLE 1-2:
#
SPI Timing Waveform (Mode = 00).
SPI REQUIREMENTS (MODE = 00)
Characteristic
Symbol
Min
Max Units
FSCK
10
1
—
—
—
—
—
—
—
50
70
170
70
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
ms
ns
70
71
CS Active (VIL or VIHH) to SCK↑ input
SCK input high time
72
SCK input low time
73
74
77
80
Setup time of SDI input to SCK↑ edge
Hold time of SDI input from SCK↑ edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK↓ edge
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
—
—
60
45
500
45
500
10
20
—
—
82
SDO data output valid after
CS Active (VIL or VIHH)
CS Inactive (VIH) after SCK↓ edge
TssL2doV
—
TscH2csI
100
1
50
SCK Input Frequency
83
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
84
DS22060B-page 12
TcsA2scH
TscH
TscL
TcsA2csI
—
Conditions
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
Note 1
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
TABLE 1-3:
SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPERATION ONLY) (2)
Characteristic
Symbol
Min
Max Units
Conditions
—
250 kHz VDD = 2.7V to 5.5V
SCK Input Frequency
FSCK
TcsA2scH
60
—
ns
CS Active (VIL or VIHH) to SCK↑ input
SCK input high time
TscH
1.8
—
us
SCK input low time
TscL
1.8
—
ns
40
—
ns
Setup time of SDI input to SCK↑ edge
TDIV2scH
40
—
ns
Hold time of SDI input from SCK↑ edge
TscH2DIL
CS Inactive (VIH) to SDO output hi-impedance
TcsH2DOZ
—
50
ns Note 1
—
1.6
us
SDO data output valid after SCK↓ edge
TscL2DOV
TssL2doV
—
50
ns
SDO data output valid after
CS Active (VIL or VIHH)
TscH2csI
100
—
ns
CS Inactive (VIH) after SCK↓ edge
TcsA2csI
50
—
ns
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
2: This table is for the devices where the SPI’s SDI and SDO pins are multiplexed (SDI/SDO) and a Read
command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write
commands. This data rate can be increased by having external pull-up resistors to increase the rising
edges of each bit.
© 2008 Microchip Technology Inc.
DS22060B-page 13
MCP413X/415X/423X/425X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-DFN (3x3)
θJA
—
84.5
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
211
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
89.3
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 10L-DFN (3x3)
θJA
—
57
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
211
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 16L-QFN
θJA
—
47
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS22060B-page 14
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
200
ICS
150
100
50
RCS
0
2.00
4.00
6.00
8.00
fSCK (MHz)
10.00
12.00
FIGURE 2-1:
Device Current (IDD) vs. SPI
Frequency (fSCK) and Ambient Temperature
(VDD = 2.7V and 5.5V).
2
3
4
5
6
7
VCS (V)
8
9
10
FIGURE 2-3:
CS Pull-up/Pull-down
Resistance (RCS) and Current (ICS) vs. CS Input
Voltage (VCS) (VDD = 5.5V).
3.0
12
2.5
CS V PP Threshold (V)
Standby Current (Istby) (µA)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
250
2.7V -40°C
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
ICS (µA)
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.00
RCS (kOhms)
Operating Current (I DD) (µA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
5.5V
2.0
1.5
1.0
2.7V
0.5
0.0
10
5.5V Entry
8
2.7V Entry
5.5V Exit
6
4
2.7V Exit
2
0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-2:
Device Current (ISHDN) and
VDD. (CS = VDD) vs. Ambient Temperature.
© 2008 Microchip Technology Inc.
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
100
120
FIGURE 2-4:
CS High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
DS22060B-page 15
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
80
0
60
-0.1
125°C
20
0
-0.2
RW
-40°C 25°C
85°C
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
DNL
0.1
180
0
140
RW
100
-0.1
-40°C
20
0
32
25°C
-0.2
85°C
2000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.5
0.2
0.1
0
1000
DNL
RW
0
0
64
128
192
Wiper Setting (decimal)
-0.2
32
-40°C
FIGURE 2-7:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
-0.75
RW
-1.25
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
6
INL
4
2
140
RW
100
0
-40°C
60
125°C
20
0
32
85°C
25°C
DNL
-2
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-9:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
118
98
58
1000
38
500
RW
DNL
0
0
Note:
125C Rw
125C INL
125C DNL
78
1500
-0.3
256
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
DS22060B-page 16
85°C 25°C
2000
-0.1
500
125°C
2500
0.4
0.3
INL
1500
Note:
125C Rw
125C INL
125C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
40
180
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-6:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
2500
-0.25
DNL
220
125°C
60
60
260
INL
220
0.75
0.25
300
0.2
1.25
FIGURE 2-8:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
125C Rw
125C INL
125C DNL
80
0
FIGURE 2-5:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
85C Rw
85C INL
85C DNL
INL
20
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
Wiper Resistance (RW)
(ohms)
40
100
25C Rw
25C INL
25C DNL
Error (LSb)
0.1
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
0.3
125C Rw
125C INL
125C DNL
64
128
192
Wiper Setting (decimal)
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (R W)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
18
-2
256
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
FIGURE 2-10:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
5300
6000
5250
5000
RWB (Ohms)
Nominal Resistance (R
(Ohms)
AB)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.7V
5200
5150
5.5V
5100
1.8V
4000
3000
2000
-40°C
25°C
85°C
125°C
1000
5050
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-11:
5 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
© 2008 Microchip Technology Inc.
0
32
64
96
128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-12:
5 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
DS22060B-page 17
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-13:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-16:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-14:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-17:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-15:
5 kΩ – Power-Up Wiper
Response Time (20 ms/Div).
DS22060B-page 18
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
25°C -40°C
125°C 85°C
100
-0.2
RW
20
-0.3
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
DNL
0.1
180
0
140
100
-0.1
RW
60
25°C
125°C 85°C
20
0
32
-0.2
-40°C
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-19:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
3500
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
3000
125C Rw
125C INL
125C DNL
INL
2500
125°C
0.4
0.3
DNL
0.1
1500
0
1000
-0.1
500
RW
0
0
64
128
192
Wiper Setting (decimal)
-0.2
FIGURE 2-20:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
85°C 25°C
RW
-40°C
DNL
-0.5
-1
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
4
3
INL
220
2
180
1
140
0
100
-40°C
60
DNL
RW
-1
125°C 85°C 25°C
0
-2
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
FIGURE 2-22:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
3500
3000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
2000
1500
1000
500
RW
DNL
0
0
Note:
98
88
78
68
58
48
38
28
18
8
-2
256
125C Rw
125C INL
125C DNL
2500
-0.3
256
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
© 2008 Microchip Technology Inc.
32
4000
0.5
0.2
2000
Note:
40
20
0.6
Error (LSb)
Wiper Resistance
(RW)(ohms)
4000
0.5
0
300
0.2
1
FIGURE 2-21:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
125C Rw
125C INL
125C DNL
60
0
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
85C Rw
85C INL
85C DNL
80
20
FIGURE 2-18:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
Wiper Resistance (R W)
(ohms)
0
Wiper Resistance (R W)
(ohms)
40
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
0.3
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
64
128
192
Wiper Setting (decimal)
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
120
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
FIGURE 2-23:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22060B-page 19
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
12000
AB)
10250
Nominal Resistance (R
(Ohms)
10300
10200
10000
10100
RWB (Ohms)
10150
2.7V
10050
10000
5.5V
9950
1.8V
9900
8000
6000
4000
-40°C
25°C
85°C
125°C
2000
9850
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-24:
10 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS22060B-page 20
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-25:
10 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-26:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-28:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-27:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-29:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
© 2008 Microchip Technology Inc.
DS22060B-page 21
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
-0.1
25°C
85°C
125°C
20
0
-40°C
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.1
180
0
140
32
85C Rw
85C INL
85C DNL
DNL
INL
RW
0
Note:
25C Rw
25C INL
25C DNL
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
256
125C Rw
125C INL
125C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
64
128
192
Wiper Setting (decimal)
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
FIGURE 2-32:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22060B-page 22
32
RW
-0.2
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
1
0.75
0.5
DNL
0.25
0
-0.25
RW
100
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-31:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
85°C 25°C
125°C
140
-0.5
-40°C
60
125°C
20
0
32
-0.75
85°C 25°C
64
-1
96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-34:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Wiper Resistance (Rw)
(ohms)
0
-40°C
180
125°C 85°C 25°C
20
-0.1
40
220
-0.2
-40°C
60
0
260
-0.1
RW
100
0.1
60
300
0.2
INL
DNL
DNL
FIGURE 2-33:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
0.2
80
0
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
0.3
125C Rw
125C INL
125C DNL
INL
20
FIGURE 2-30:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
85C Rw
85C INL
85C DNL
Error (LSb)
0
100
25C Rw
25C INL
25C DNL
Error (LSb)
0.1
-40C Rw
-40C INL
-40C DNL
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
RW
INL
DNL
78.5
73.5
68.5
63.5
58.5
53.5
48.5
43.5
38.5
33.5
28.5
23.5
18.5
13.5
8.5
3.5
-1.5
Error (LSb)
0.2
60
40
120
0.3
125C Rw
125C INL
125C DNL
INL
DNL
80
85C Rw
85C INL
85C DNL
Wiper Resistance (R W)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
120
0 25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
Note:
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
FIGURE 2-35:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60000
52000
50000
51500
1.8V
RWB (Ohms)
Nominal Resistance (R
(Ohms)
AB)
52500
51000
50500
50000
2.7V
49500
40000
30000
20000
-40°C
25°C
85°C
125°C
10000
5.5V
49000
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-36:
50 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
© 2008 Microchip Technology Inc.
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-37:
50 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
DS22060B-page 23
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-38:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-40:
50 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-39:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-41:
50 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
DS22060B-page 24
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
0
-0.1
25°C -40°C
RW
125°C 85°C
32
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
DNL
-0.05
100
RW
60
125°C 85°C 25°C
20
0
32
-0.1
-0.15
-40°C
85C Rw
85C INL
85C DNL
0.25
0.05
15000
-0.05
10000
-0.15
5000
RW
INL
0
64
128
192
Wiper Setting (decimal)
FIGURE 2-44:
100 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
© 2008 Microchip Technology Inc.
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.6
0.4
0.2
0
-0.2
RW
100
60
125°C 85°C 25°C
32
-0.4
-40°C
-0.6
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-46:
100 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
25000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
20000
15000
10000
5000
DNL
0
256
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
25C Rw
25C INL
25C DNL
140
-0.35
0
Note:
-0.25
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
DNL
0.35
0.15
DNL
20000
125C Rw
125C INL
125C DNL
-0.2
180
0
Error (LSb)
Wiper Resistance (R W)
(ohms)
25000
25C Rw
25C INL
25C DNL
RW
INL
20
FIGURE 2-43:
100 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
32
-40C Rw
-40C INL
-40C DNL
220
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
125°C 85°C 25°C
-40°C
FIGURE 2-45:
100 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
260
0
140
-0.1
40
0.15
0.05
180
0.1
0
300
0.1
INL
0.2
60
0.2
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
0.3
125C Rw
125C INL
125C DNL
DNL
80
0
FIGURE 2-42:
100 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
85C Rw
85C INL
85C DNL
INL
20
Wiper Resistance (Rw)
(ohms)
0
Wiper Resistance (R W)
(ohms)
20
25C Rw
25C INL
25C DNL
Error (LSb)
0.1
60
40
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
125C Rw
125C INL
125C DNL
INL
DNL
80
85C Rw
85C INL
85C DNL
0
Note:
64
128
192
Wiper Setting (decimal)
59
54
49
RW
44
39
INL
34
29
24
19
14
9
4
-1
256
125C Rw
125C INL
125C DNL
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
120
Refer to AN1080 for additional information on the characteristics of the wiper
resistance (RW) with respect to device
voltage and wiper setting value.
FIGURE 2-47:
100 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22060B-page 25
MCP413X/415X/423X/425X
120000
103500
103000
102500
102000
101500
101000
100500
100000
99500
99000
98500
100000
Rwb (Ohms)
Nominal Resistance (R
(Ohms)
AB)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.8V
2.7V
80000
60000
40000
-40°C
25°C
85°C
125°C
20000
5.5V
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-48:
100 kΩ – Nominal
Resistance (Ω) vs. Ambient Temperature and
VDD .
DS22060B-page 26
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-49:
100 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-50:
100 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-52:
100 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-51:
100 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-53:
100 kΩ – Power-Up Wiper
Response Time (1 µs/Div).
© 2008 Microchip Technology Inc.
DS22060B-page 27
MCP413X/415X/423X/425X
0.12
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.1
0.08
5.5V
%
%
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.06
0.04
3.0V
0.02
3.0V
0
-40
0
40
80
Temperature (°C)
120
FIGURE 2-54:
Resistor Network 0 to
Resistor Network 1 RAB (5 kΩ) Mismatch vs. VDD
and Temperature.
-40
0.05
0.03
0.04
5.5V
%
0.01
3.0V
0
3.0V
-0.02
120
0.02
0
-0.01
40
80
Temperature (°C)
0.03
5.5V
0.01
0
FIGURE 2-56:
Resistor Network 0 to
Resistor Network 1 RAB (50 kΩ) Mismatch vs.
VDD and Temperature.
0.04
0.02
%
5.5V
-0.01
-0.03
-0.02
-0.04
-40
0
40
80
Temperature (°C)
120
FIGURE 2-55:
Resistor Network 0 to
Resistor Network 1 RAB (10 kΩ) Mismatch vs.
VDD and Temperature.
DS22060B-page 28
-0.03
-40
10
60
Temperature (°C)
110
FIGURE 2-57:
Resistor Network 0 to
Resistor Network 1 RAB (100 kΩ) Mismatch vs.
VDD and Temperature.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.4
0
2.2
-5
IOH (mA)
VIH (V)
-10
5.5V
2
1.8
1.6
1.4
2.7V
2.7V
-15
-20
5.5V
-25
-30
-35
1.2
-40
1
-45
-40
0
40
80
120
-40
0
Temperature (°C)
FIGURE 2-58:
VIH (SDI, SCK, CS, and
SHDN) vs. VDD and Temperature.
1.3
5.5V
IOL (mA)
VIL (V)
1.1
1
0.9
0.8
2.7V
0.7
0.6
-40
0
40
80
120
50
45
40
35
30
25
20
15
10
5
0
120
5.5V
2.7V
-40
Temperature (°C)
FIGURE 2-59:
VIL (SDI, SCK, CS, and
SHDN) vs. VDD and Temperature.
© 2008 Microchip Technology Inc.
80
IOH (SDO) vs. VDD and
FIGURE 2-60:
Temperature.
1.4
1.2
40
Temperature (°C)
0
40
80
120
Temperature (°C)
FIGURE 2-61:
Temperature.
IOL (SDO) vs. VDD and
DS22060B-page 29
MCP413X/415X/423X/425X
2.1
Note: Unless otherwise indicated, TA = +25°C,
VDD = 5V, VSS = 0V.
Test Circuits
1.2
+5V
1
5.5V
VIN
VDD (V)
0.8
0.6
2.7V
Offset
GND
0.4
0.2
A
W
B
+
VOUT
-
2.5V DC
0
-40
0
40
80
120
Temperature (°C)
FIGURE 2-62:
and Temperature.
POR/BOR Trip point vs. VDD
FIGURE 2-64:
Test.
-3 db Gain vs. Frequency
15.0
fsck (MHz)
14.5
5.5V
14.0
2.7V
13.5
13.0
12.5
12.0
-40
0
40
80
120
Temperature (°C)
FIGURE 2-63:
SCK Input Frequency vs.
Voltage and Temperature.
DS22060B-page 30
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP413X/415X/423X/425X
Pin
Single
I/O
Buffer
Type
Weak
Pull-up/
down (2)
Dual
Rheo Pot (1) Rheo
Pot
Symbol
Standard Function
8L
8L
10L
14L
16L
1
1
1
1
16
CS
I
HV w/ST
“smart”
SPI Chip Select Input
2
2
2
2
1
SCK
I
HV w/ST
“smart”
SPI Clock Input
3
—
3
3
2
SDI
I
HV w/ST
“smart”
SPI Serial Data Input
—
3
—
—
—
SDI/SDO
I/O
HV w/ST
“smart”
SPI Serial Data Input/Output
(Note 1, Note 3)
4
4
4
4
3, 4
VSS
—
P
—
Ground
—
—
5
5
5
P1B
A
Analog
No
Potentiometer 1 Terminal B
—
—
6
6
6
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
—
—
7
7
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
5
—
8
8
P0A
A
Analog
No
Potentiometer 0 Terminal A
5
6
7
9
9
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
6
7
8
10
10
P0B
A
Analog
No
—
—
—
12
13
SHDN
I
HV w/ST
“smart”
Hardware Shutdown
7
—
9
13
14
SDO
O
O
No
SPI Serial Data Out
15
VDD
8
8
10
14
—
—
—
11
9
9
11
—
Legend:
Note 1:
2:
3:
4:
11,12 NC
17
EP
Potentiometer 0 Terminal B
—
P
—
Positive Power Supply Input
—
—
—
No Connection
—
—
—
Exposed Pad (Note 4)
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals)
I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin
(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been
requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.
The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and
shutdown current.
The SDO is an open drain output, which uses the internal “smart” pull-up. The SDI input data rate can be
at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up,
customers can increase the rate with external pull-up resistors.
The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively
connected to the die substrate, and therefore should be unconnected or connected to the same ground as
the device’s VSS pin.
© 2008 Microchip Technology Inc.
DS22060B-page 31
MCP413X/415X/423X/425X
3.1
Chip Select (CS)
The CS pin is the serial interface’s chip select input.
Forcing the CS pin to VIL enables the serial commands.
Forcing the CS pin to VIHH enables the high-voltage
serial commands.
3.2
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin.
This pin is connected to the Host Controllers SDO pin.
3.3
Serial Data In / Serial Data Out
(SDI/SDO)
On the MCP41X1 devices, pin-out limitations do not
allow for individual SDI and SDO pins. On these
devices, the SDI and SDO pins are multiplexed.
The MCP41X1 serial interface knows when the pin
needs to change from being an input (SDI) to being an
output (SDO). The Host Controller’s SDO pin must be
properly protected from a drive conflict.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
3.7
Potentiometer Terminal A
The terminal A pin is available on the MCP4XX1
devices, and is connected to the internal
potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full-Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x100 for 8-bit devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP4XX2
devices, and the internally terminal A signal is floating.
MCP42X1 devices have two terminal A pins, one for
each resistor network.
3.8
Shutdown (SHDN)
The SHDN pin is used to force the resistor network
terminals into the hardware shutdown state.
3.9
Serial Data Out (SDO)
The SDO pin is the serial interfaces Serial Data Out pin.
This pin is connected to the Host Controllers SDI pin.
This pin allows the Host Controller to read the digital
potentiometers registers, or monitor the state of the
command error bit.
3.10
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
MCP42XX devices have two terminal B pins, one for
each resistor network.
3.11
3.6
These pins are not internally connected and should be
either connected to VDD or VSS to reduce possible
noise coupling.
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal
potentiometer’s terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminals A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between VSS and
VDD.
MCP42XX devices have two terminal W pins, one for
each resistor network.
DS22060B-page 32
3.12
No Connection (NC)
Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
4.0
FUNCTIONAL OVERVIEW
4.1.2
BROWN-OUT RESET
This Data Sheet covers a family of thirty-two Digital
Potentiometer and Rheostat devices that will be
referred to as MCP4XXX. The MCP4XX1 devices are
the Potentiometer configuration, while the MCP4XX2
devices are the Rheostat configuration.
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage.
As the Device Block Diagram shows, there are four
main functional blocks. These are:
If the VDD voltage decreases below the VRAM voltage
the following happens:
•
•
•
•
• Volatile wiper registers may become corrupted
• TCON register may become corrupted
POR/BOR Operation
Memory Map
Resistor Network
Serial Interface (SPI)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
SPI operation are described in their own sections. The
Device Commands commands are discussed in
Section 7.0.
4.1
POR/BOR Operation
The Power-on Reset is the case where the device is
having power applied to it from VSS. The Brown-out
Reset occurs when a device had power applied to it,
and that power (voltage) drops below the specified
range.
The devices RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less then 1.8V.
When VPOR/VBOR < VDD < 2.7V, the electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
incrementing, decrementing, reading and writing to its
volatile memory if the proper serial command is
executed.
4.1.1
POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage the following happens:
• Volatile wiper register is loaded with the default
wiper value
• The TCON register is loaded it’s default value
• The device is capable of digital operation
© 2008 Microchip Technology Inc.
Once the VDD voltage decreases below the VPOR/VBOR
voltage the following happens:
• Serial Interface is disabled
As the voltage recovers above the VPOR/VBOR voltage
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
4.2
Memory Map
The device memory is 16 locations that are 9-bits wide
(16x9 bits). This memory space contains four volatile
locations (see Table 4-1).
TABLE 4-1:
Address
00h
01h
02h
03h
04h
05h
06h-0Fh
4.2.1
MEMORY MAP
Function
Memory Type
Volatile Wiper 0
Volatile Wiper 1
Reserved
Reserved
Volatile TCON Register
Status Register
Reserved
RAM
RAM
—
—
RAM
RAM
—
VOLATILE MEMORY (RAM)
There are four Volatile Memory locations. These are:
• Volatile Wiper 0
• Volatile Wiper 1
(Dual Resistor Network devices only)
• Status Register
• Terminal Control (TCON) Register
The volatile memory starts functioning at the RAM
retention voltage (VRAM).
DS22060B-page 33
MCP413X/415X/423X/425X
4.2.1.1
Status (STATUS) Register
The STATUS register is placed at Address 05h.
This register contains 5 status bits. These bits show the
state of the Shutdown bit. The STATUS register can be
accessed via the READ commands. Register 4-1
describes each STATUS register bit.
REGISTER 4-1:
R-1
STATUS REGISTER
R-1
R-1
R-1
D8:D5
R-0
R-x
R-x
R-x
R-x
RESV
RESV
RESV
SHDN
RESV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8-5
D8:D5: Reserved. Forced to “1”
bit 4-2
RESV: Reserved
bit 1
SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.3 “Shutdown” for further information)
This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects the
Terminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in Hardware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register may be
read.
1 = MCP4XXX is in the Hardware Shutdown state
0 = MCP4XXX is NOT in the Hardware Shutdown state
bit 0
RESV: Reserved
DS22060B-page 34
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
4.2.1.2
Terminal Control (TCON) Register
This register contains 8 control bits. Four bits are for
Wiper 0, and four bits are for Wiper 1. Register 4-2
describes each bit of the TCON register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
The value that is written to this register will appear on
the resistor network terminals when the serial
command has completed.
On a POR/BOR this register is loaded with 1FFh
(9-bits), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register value.
© 2008 Microchip Technology Inc.
DS22060B-page 35
MCP413X/415X/423X/425X
REGISTER 4-2:
TCON BITS (1, 2)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
D8
R1HW
R1A
R1W
R1B
R0HW
R0A
R0W
R0B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
D8: Reserved. Forced to “1”
bit 7
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
bit 5
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
bit 4
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
bit 3
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1:
2:
The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
These bits do not affect the wiper register values.
DS22060B-page 36
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
5.0
RESISTOR NETWORK
5.1
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full-scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
• Wiper
• Shutdown (Terminal Connections)
Devices have either one or two resistor networks,
These are referred to as Pot 0 and Pot 1.
A
RW
RS
RW
R
RAB S
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see
Figure 5-1). The end points of the resistor ladder are
connected to analog switches which are connected to
the device Terminal A and Terminal B pins. The RAB
(and RS) resistance has small variations over voltage
and temperature.
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 256 resistors thus providing
257 possible settings (including terminal A and
terminal B).
8-Bit
N=
257
(1) (100h)
7-Bit
N=
128
(80h)
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 128 resistors thus providing
129 possible settings (including terminal A and
terminal B).
256
(FFh)
127
(7Fh)
Equation 5-1 shows the calculation for the step
resistance.
255
(FEh)
126
(7Eh)
EQUATION 5-1:
RW (1)
RS
Resistor Ladder Module
(1)
RS CALCULATION
R AB
R S = ------------( 256 )
8-bit Device
R AB
R S = ------------( 128 )
7-bit Device
W
RW
RS
RW
1
(1) (01h)
1
(01h)
0
(00h)
0
(00h)
(1)
Analog Mux
B
Note 1:
The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 kΩ)
compared to larger resistance devices
(100.0 kΩ).
FIGURE 5-1:
Resistor Block Diagram.
© 2008 Microchip Technology Inc.
DS22060B-page 37
MCP413X/415X/423X/425X
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero-scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full-scale connections, connects the Terminal
W (wiper) to Terminal A (wiper setting of 100h or 80h).
In these configurations the only resistance between the
Terminal W and the other Terminal (A or B) is that of the
analog switches.
TABLE 5-2:
DEFAULT FACTORY
SETTINGS SELECTION
Default POR
Wiper Setting
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
A POR/BOR event will load the Volatile Wiper register
value with the default value. Table 5-2 shows the
default values offered. Custom POR/BOR options are
available. Contact the local Microchip Sales Office.
Typical
RAB Value
Wiper
Resistance
Code
5.2
Wiper Code
8-bit
7-bit
-502
5.0 kΩ
Mid-scale
80h
40h
-103
10.0 kΩ
Mid-scale
80h
40h
-503
50.0 kΩ
Mid-scale
80h
40h
-104
100.0 kΩ
Mid-scale
80h
40h
A wiper setting value greater than full-scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a Full-Scale setting (Terminal W (wiper)
connected to Terminal A). Table 5-1 illustrates the full
wiper setting map.
Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.
EQUATION 5-2:
RWB CALCULATION
R AB N
R WB = ------------- + RW
( 256 )
8-bit Device
N = 0 to 256 (decimal)
R AB N
- + RW
R WB = ------------( 128 )
7-bit Device
N = 0 to 128 (decimal)
TABLE 5-1:
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
Wiper Setting
7-bit Pot 8-bit Pot
3FFh
081h
3FFh
101h
080h
100h
07Fh
041h
040h
03Fh
001h
000h
0FFh
081
080h
07Fh
001
000h
DS22060B-page 38
Properties
Reserved (Full-Scale (W = A)),
Increment and Decrement
commands ignored
Full-Scale (W = A),
Increment commands ignored
W=N
W = N (Mid-Scale)
W=N
Zero Scale (W = B)
Decrement command ignored
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
5.3
Shutdown
5.3.2
Shutdown is used to minimize the device’s current
consumption. The MCP4XXX has two methods to
achieve this. These are:
• Hardware Shutdown Pin (SHDN)
• Terminal Control Register (TCON)
The Hardware Shutdown pin is backwards compatible
with the MCP42XXX devices.
5.3.1
HARDWARE SHUTDOWN PIN
(SHDN)
The SHDN pin is available on the dual potentiometer
devices. When the SHDN pin is forced active (VIL):
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor Network. This register is shown in
Register 4-2.
The RxHW bits forces the selected resistor network
into the same state as the SHDN pin. Alternate
low-power configurations may be achieved with the
RxA, RxW, and RxB bits.
Note:
• The P0A and P1A terminals are disconnected
• The P0W and P1W terminals are simultaneously
connect to the P0B and P1B terminals,
respectively (see Figure 5-2)
• The Serial Interface is NOT disabled, and all
Serial Interface activity is executed
The Hardware Shutdown pin mode does NOT corrupt
the values in the Volatile Wiper Registers nor the
TCON register. When the Shutdown mode is exited
(SHDN pin is inactive (VIH)):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The TCON register bits return to controlling the
terminal connection state
Resistor Network
A
TERMINAL CONTROL REGISTER
(TCON)
5.3.3
When the RxHW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON register RxA, RxW,
and RxB bits is overridden (ignored).
When the state of the RxHW bit no longer
forces the resistor network into the hardware SHDN state, the TCON register RxA,
RxW, and RxB bits return to controlling the
terminal connection state. In other words,
the RxHW bit does not corrupt the state of
the RxA, RxW, and RxB bits.
INTERACTION OF SHDN PIN AND
TCON REGISTER
Figure 5-3 shows how the SHDN pin signal and the
RxHW bit signal interact to control the hardware
shutdown of each resistor network (independently).
Using the TCON bits allows each resistor network (Pot
0 and Pot 1) to be individually “shutdown” while the
hardware pin forces both resistor networks to be “shutdown” at the same time.
W
SHDN (from pin)
B
FIGURE 5-2:
Hardware Shutdown
Resistor Network Configuration.
© 2008 Microchip Technology Inc.
RxHW
(from TCON register)
FIGURE 5-3:
Interaction.
To Pot x Hardware
Shutdown Control
RxHW bit and SHDN pin
DS22060B-page 39
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 40
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
6.0
SERIAL INTERFACE (SPI)
The MCP4XXX devices support the SPI serial protocol.
This SPI operates in the slave mode (does not
generate the serial clock).
The SPI interface uses up to four pins. These are:
•
•
•
•
CS - Chip Select
SCK - Serial Clock
SDI - Serial Data In
SDO - Serial Data Out
Typical SPI Interfaces are shown in Figure 6-1. In the
SPI interface, The Master’s Output pin is connected to
the Slave’s Input pin and the Master’s Input pin is
connected to the Slave’s Output pin.
The MCP4XXX SPI’s module supports two (of the four)
standard SPI modes. These are Mode 0,0 and 1,1.
The SPI mode is determined by the state of the SCK
pin (VIH or VIL) on the when the CS pin transitions from
inactive (VIH) to active (VIL or VIHH).
All SPI interface signals are high-voltage tolerant.
Typical SPI Interface Connections
Host
Controller
MCP4XXX
SDO
( Master Out - Slave In (MOSI) )
SDI
SDI
( Master In - Slave Out (MISO) )
SDO
SCK
SCK
I/O (1)
CS
Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI)
Host
Controller
MCP41X1
SDI/SDO
SDO
SDI
SDI
R1(2)
SDO
SCK
SCK
I/O (1)
CS
Alternate MCP41X1 SPI Interface Connections (Host Controller Firmware SPI)
Host
Controller
I/O
(SDO/SDI)
MCP41X1
SDI/SDO
SDI
SDO
I/O
(SCK)
I/O (1)
SCK
CS
Note 1: If High voltage commands are desired, some type of external circuitry needs to be
implemented.
2: R1 must be sized to ensure VIL and VIH of the devices are met.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
© 2008 Microchip Technology Inc.
DS22060B-page 41
MCP413X/415X/423X/425X
6.1
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
•
•
•
•
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
6.1.3
Note:
SDI/SDO
MCP41X1 Devices Only .
For device packages that do not have enough pins for
both an SDI and SDO pin, the SDI and SDO
functionality is multiplexed onto a single I/O pin called
SDI/SDO.
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
The SDO will only be driven for the command error bit
(CMDERR) and during the data bits of a read command
(after the memory address and command has been
received).
6.1.1
6.1.3.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the SDO
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
SDI/SDO Operation
Figure 6-2 shows a block diagram of the SDI/SDO pin.
The SDI signal has an internal “smart” pull-up. The
value of this pull-up determines the frequency that data
can be read from the device. An external pull-up can be
added to the SDI/SDO pin to improve the rise time and
therefore improve the frequency that data can be read.
Note:
To support the High voltage requirement of
the SDI function, the SDO function is an
open drain output.
Data written on the SDI/SDO pin can be at the
maximum SPI frequency.
Note:
Care must be take to ensure that a Drive
conflict does not exist between the Host
Controllers SDO pin (or software SDI/SDO
pin) and the MCP41x1 SDI/SDO pin (see
Figure 6-1).
On the falling edge of the SCK pin during the C0 bit
(see Figure 7-1), the SDI/SDO pin will start outputting
the SDO value. The SDO signal overrides the control of
the smart pull-up, such that whenever the SDI/SDO pin
is outputting data, the smart pull-up is enabled.
The SDI/SDO pin will change from an input (SDI) to an
output (SDO) after the state machine has received the
Address and Command bits of the Command Byte. If
the command is a Read command, then the SDI/SDO
pin will remain an output for the remainder of the
command. For any other command, the SDI/SDO pin
returns to an input.
“smart” pull-up
SDI/SDO
SDI
Open
Drain
Control
Logic
FIGURE 6-2:
Diagram.
DS22060B-page 42
SDO
Serial I/O Mux Block
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
6.1.4
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
6.1.5
THE CS SIGNAL
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL or VIHH).
TABLE 6-1:
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
SCK FREQUENCY
Command
Memory Type Access
Volatile
Memory
Read
SDI, SDO
10 MHz
SDI/SDO (1) 250 kHz (2)
Note 1: MCP41X1 devices only.
Write,
Increment,
Decrement
10 MHz
10 MHz
2: This is the maximum clock frequency
without an external pull-up resistor.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the VIL
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the VIH
level. When the CS pin is driven low (VIL), the
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows
MCP413X/415X/423X/425X devices to be used in
systems previously designed for the MCP414X/416X/
424X/426X devices.
© 2008 Microchip Technology Inc.
DS22060B-page 43
MCP413X/415X/423X/425X
6.2
The SPI Modes
6.3
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.2.1
Figure 6-3 through Figure 6-8 show the different SPI
command waveforms. Figure 6-3 and Figure 6-4 are
read and write commands. Figure 6-5 and Figure 6-6
are read commands when the SDI and SDO pins are
multiplexed on the same pin (SDI/SDO). Figure 6-7
and Figure 6-8 are increment and decrement
commands.
MODE 0,0
In Mode 0,0: SCK idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
6.2.2
SPI Waveforms
MODE 1,1
In Mode 1,1: SCK idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
CS
VIH
VIHH (1)
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO
bit15 bit14 bit13 bit12 bit11
SDI
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
C0
bit1
bit0
D0
bit0
Input
Sample
Note 1: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-3:
VIH
CS
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
VIHH(1)
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
bit15
bit14 bit13 bit12 bit11
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
C0
bit1
bit0
D0
bit0
Input
Sample
Note 1: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-4:
DS22060B-page 44
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
CS
VIH
VIHH (1)
VIL
SCK
Write to
SSPBUF
CMDERR bit
D9
D8
D7
bit9
bit8 bit7
SDO
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
SDI
C1
1
C0
1
(1)
(1)
(1)
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
bit2
D1
bit1
D0
bit0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Input
Sample
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven.
2: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-5:
16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 1,1).
CS
VIH
VIHH (1)
VIL
SCK
Write to
SSPBUF
CMDERR bit
D8
D7
X
SDO
SDI
bit9
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
C0
1
1
(1)
bit8
(1)
D4
D3
bit7
bit6
D6
bit5
D5
bit4
bit3
bit2
D2
bit1
D1
bit0
D0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Input
Sample
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven.
2: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-6:
16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 0,0).
© 2008 Microchip Technology Inc.
DS22060B-page 45
MCP413X/415X/423X/425X
CS
VIH
VIHH (1)
VIL
SCK
Write to
SSPBUF
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
SDO
bit7
SDI
AD3
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
bit7
Input
Sample
Note 1: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-7:
(Mode 1,1).
VIH
CS
8-Bit Commands (Increment, Decrement, Modify - SPI Waveform with PIC MCU
VIHH (1)
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
bit7
AD3
bit7
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
Input
Sample
Note 1: VIHH is supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage
operation.
FIGURE 6-8:
(Mode 0,0).
DS22060B-page 46
8-Bit Commands (Increment, Decrement, Modify - SPI Waveform with PIC MCU
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.0
DEVICE COMMANDS
7.1
Command Byte
The Command Byte has three fields, the Address, the
Command, and 2 Data bits, see Figure 7-1. Currently
only one of the data bits is defined (D8). This is for the
Write command.
The MCP4XXX’s SPI command format supports 16
memory address locations and four commands. Each
command has two modes. These are:
• Normal Serial Commands
• High-Voltage Serial Commands
The device memory is accessed when the master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers.
Normal serial commands are those where the CS pin is
driven to VIL. High Voltage Serial Commands, CS pin is
driven to VIHH, for compatibility with systems that also
support the MCP414X/416X/424X/426X devices. High
Voltage Serial Commands operate identically to their
corresponding Normal Serial Command. In each
mode, there are four possible commands. These
commands are shown in Table 7-1.
The 8-bit commands (Increment Wiper and Decrement Wiper commands) contain a Command Byte,
see Figure 7-1, while 16-bit commands (Read Data
and Write Data commands) contain a Command Byte
and a Data Byte. The Command Byte contains two data
bits, see Figure 7-1.
As the Command Byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first six bits of that
command. On the 7th bit, the SDO pin will output the
CMDERR bit state (see Section 7.3 “Error Condition”). The 8th bit state depends on the the command
selected.
Table 7-2 shows the supported commands for each
memory location and the corresponding values on the
SDI and SDO pins.
TABLE 7-1:
Table 7-3 shows an overview of all the SPI commands
and their interaction with other device features.
C1:C0 Bit
Command
States
11
00
01
10
A A A A C C D D
D D D D 1 0 9 8
3 2 1 0
Memory
Address
Data
Bits
Command
Bits
FIGURE 7-1:
# of Bits
Read Data
16-Bits
Write Data
16-Bits
Increment
8-Bits
Decrement
8-Bits
16-bit Command
8-bit Command
Command Byte
COMMAND BIT OVERVIEW
Command Byte
Data Byte
A A A A C C D D D D D D D D D D
D D D D 1 0 9 8 7 6 5 4 3 2 1 0
3 2 1 0
Data
Bits
Memory
Address
Command
Bits
Command
Bits
CC
1 0
0 0 = Write Data
0 1 = INCR
1 0 = DECR
1 1 = Read Data
General SPI Command Formats.
© 2008 Microchip Technology Inc.
DS22060B-page 47
MCP413X/415X/423X/425X
TABLE 7-2:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Value
00h
01h
MOSI (SDI pin)
Write Data
nn nnnn nnnn
0000 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0000 11nn nnnn nnnn
1111 111n nnnn nnnn
Increment Wiper
—
0000 0100
1111 1111
Decrement Wiper
—
0000 1000
1111 1111
Write Data
nn nnnn nnnn
0001 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0001 11nn nnnn nnnn
1111 111n nnnn nnnn
—
0001 0100
1111 1111
Function
Volatile Wiper 0
Volatile Wiper 1
SPI String (Binary)
Data
(10-bits) (1)
Command
Increment Wiper
MISO (SDO pin) (2)
Decrement Wiper
—
0001 1000
1111 1111
02h
Reserved
—
—
—
—
03h
Reserved
—
—
—
—
04h
Volatile
TCON Register
Write Data
nn nnnn nnnn
0100 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0100 11nn nnnn nnnn
1111 111n nnnn nnnn
05h
Status Register
Read Data
nn nnnn nnnn
0101 11nn nnnn nnnn
1111 111n nnnn nnnn
Reserved
—
—
—
—
06h-0Fh
Note 1:
2:
The Data Memory is only 9-bits wide, so the MSb is ignored by the device.
All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command
combination is a command error state and the CMDERR bit will be clear.
DS22060B-page 48
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.2
Data Byte
Only the Read Command and the Write Command use
the Data Byte, see Figure 7-1. These commands
concatenate the 8-bits of the Data Byte with the one
data bit (D8) contained in the Command Byte to form
9-bits of data (D8:D0). The Command Byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to Full-Scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
Error Condition
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table 4-1). The CMDERR bit is high if the combination
is valid and low if the combination is invalid.
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
© 2008 Microchip Technology Inc.
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. If the CS pin is forced to the inactive
state (VIH) the serial interface is reset. Partial commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP4XXX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (VIH) resets the serial interface. The SPI
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(VIH to VIL or VIH to VIHH).
Note 1: When data is not being received by the
MCP4XXX, It is recommended that the
CS pin be forced to the inactive level (VIL)
2: It is also recommended that long
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
DS22060B-page 49
MCP413X/415X/423X/425X
7.4
Continuous Commands
The device supports the ability to execute commands
continuously. While the CS pin is in the active state
(VIL or VIHH). Any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
2.
3.
4.
5.
6.
7.
8.
CS pin driven active (VIL or VIHH).
Read Command.
Increment Command (Wiper 0).
Increment Command (Wiper 0).
Decrement Command (Wiper 1).
Write Command.
Write Command.
CS pin driven inactive (VIH).
TABLE 7-3:
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is recommended to take the CS pin
inactive then force it back to the active
state.
2: It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
command string.
COMMANDS
# of Bits
High Voltage
(VIHH) on CS
pin?
Write Data
16-Bits
—
Read Data
16-Bits
—
Command Name
Increment Wiper
8-Bits
—
Decrement Wiper
8-Bits
—
High Voltage Write Data
16-Bits
Yes
High Voltage Read Data
16-Bits
Yes
High Voltage Increment Wiper
8-Bits
Yes
High Voltage Decrement Wiper
8-Bits
Yes
DS22060B-page 50
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.5
Write Data
Normal and High Voltage
Note:
7.5.1
The write operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Write Command (Command Byte and
Data Byte) is then clocked in on the SCK and SDI pins.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses. This
protects against system issues from corrupting the
memory locations.
The High Voltage Write Data command is
supported for compatability with system
that also support MCP414X/416X/424X/
426X devices.
The Write command is a 16-bit command. The format
of the command is shown in Figure 7-2.
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command (16-clock) have been received.
COMMAND BYTE
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
SINGLE WRITE
Figure 6-3 and Figure 6-4 show possible waveforms
for a single write.
DATA BYTE
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid Address/Command combination
0 Invalid Address/Command combination (1)
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
Write Command - SDI and SDO States.
© 2008 Microchip Technology Inc.
DS22060B-page 51
MCP413X/415X/423X/425X
7.5.2
CONTINUOUS WRITES
Continuous writes are possible only when writing to the
volatile memory registers (address 00h, 01h, and 04h).
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same volatile
memory address.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
DATA BYTE
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
DS22060B-page 52
Continuous Write Sequence.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.6
Read Data
Normal and High Voltage
Note:
7.6.1
The read operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VILor VIHH). The 16-bit Read Command (Command
Byte and Data Byte) is then clocked in on the SCK and
SDI pins. The SDO pin starts driving data on the 7th bit
(CMDERR bit) and the addressed data comes out on
the 8th through 16th clocks. Figure 6-3 through
Figure 6-6 show possible waveforms for a single read.
The High Voltage Read Data command is
supported for compatability with system
that also support MCP414X/416X/424X/
426X devices.
The Read command is a 16-bit command. The format
of the command is shown in Figure 7-4.
The first 6-bits of the Read command determine the
address and the command. The 7th clock will output
the CMDERR bit on the SDO pin. The remaining
9-clocks the device will transmit the 9 data bits (D8:D0)
of the specified address (AD3:AD0).
Figure 6-5 and Figure 6-6 show the single read
waveforms when the SDI and SDO signals are
multiplexed on the same pin. For additional information
on the multiplexing of these signals, refer to
Section 6.1.3 “SDI/SDO”.
Figure 7-4 shows the SDI and SDO information for a
Read command.
COMMAND BYTE
SDI
SDO
SINGLE READ
DATA BYTE
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
D
8
0
D
7
0
D
6
0
D
5
0
D
4
0
D
3
0
D
2
0
D
1
0
D Valid Address/Command combination
0
0 Attempted Memory Read of Reserved
Memory location.
READ DATA
FIGURE 7-4:
Read Command - SDI and SDO States.
© 2008 Microchip Technology Inc.
DS22060B-page 53
MCP413X/415X/423X/425X
7.6.2
CONTINUOUS READS
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
Continuous reads allows the devices memory to be
read quickly. Continuous reads are possible to all
memory locations.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
DATA BYTE
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
DS22060B-page 54
Continuous Read Sequence.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.7
Increment Wiper
Normal and High Voltage
Note:
The High Voltage Increment Wiper
command is supported for compatability
with system that also support MCP414X/
416X/424X/426X devices.
The Increment Command is an 8-bit command. The
Increment Command can only be issued to wiper
memory locations. The format of the command is
shown in Figure 7-6.
An Increment Command to the wiper memory location
changes that location after a properly formatted
command (8-clocks) have been received.
Increment commands provide a quick and easy
method to modify the value of the wiper location by +1
with minimal overhead.
COMMAND BYTE
(INCR COMMAND (n+1) )
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
0
1
X
X
1
1
1
1
1*
0
1 Note 1, 2
0 Note 1, 3
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-6:
Increment Command SDI and SDO States.
© 2008 Microchip Technology Inc.
7.7.1
SINGLE INCREMENT
Typically, the CS pin starts at the inactive state (VIH),
but may be already be in the active state due to the
completion of another command.
Figure 6-7 through Figure 6-8 show possible
waveforms for a single increment. The increment
operation requires that the CS pin be in the active state
(VILor VIHH). Typically, the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
The 8-bit Increment Command (Command Byte) is
then clocked in on the SDI pin by the SCK pins. The
SDO pin drives the CMDERR bit on the 7th clock.
The wiper value will increment up to 100h on 8-bit
devices and 80h on 7-bit devices. After the wiper value
has reached Full-Scale (8-bit =100h, 7-bit =80h), the
wiper value will not be incremented further. If the Wiper
register has a value between 101h and 1FFh, the
Increment command is disabled. See Table 7-4 for
additional information on the Increment Command
versus the current volatile wiper value.
The Increment operations only require the Increment
command byte while the CS pin is active (VILor VIHH)
for a single increment.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
TABLE 7-4:
Current Wiper
Setting
7-bit
Pot
8-bit
Pot
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
3FFh
101h
100h
0FFh
081
080h
07Fh
001
000h
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
Increment
Command
Operates?
Wiper (W)
Properties
Reserved
(Full-Scale (W = A))
Full-Scale (W = A)
W=N
No
W = N (Mid-Scale)
W=N
Yes
Zero Scale (W = B)
Yes
No
DS22060B-page 55
MCP413X/415X/423X/425X
7.7.2
CONTINUOUS INCREMENTS
Increment commands can be sent repeatedly without
raising CS until a desired condition is met. The value in
the Volatile Wiper register can be read using a Read
Command.
Continuous Increments are possible only when writing
to the wiper registers.
Figure 7-7 shows a Continuous Increment sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
When executing a continuous command string, The
Increment command can be followed by any other valid
command.
When executing an continuous Increment commands,
the selected wiper will be altered from n to n+1 for each
Increment command received. The wiper value will
increment up to 100h on 8-bit devices and 80h on 7-bit
devices. After the wiper value has reached Full-Scale
(8-bit =100h, 7-bit =80h), the wiper value will not be
incremented further. If the Wiper register has a value
between 101h and 1FFh, the Increment command is
disabled.
(INCR COMMAND (n+1) )
A
D
3
1
1
SDO
1
1
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
SDI
The wiper terminal will move after the command has
been received (8th clock).
(INCR COMMAND (n+2) )
0
1
X
X
1
1
1
1
1
1
1
1
1*
0
1
1
1
0
1
1
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
(INCR COMMAND (n+3) )
0
1
X
X
1
0
1
1
1
0
1
1
1*
0
0
1
1
0
0
1
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
0
1
X
X
1
0
0
1
1
0
0
1
1*
0
0
0
1
0
0
0
Note 1, 2
Note 3, 4
Note 3, 4
Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
DS22060B-page 56
Continuous Increment Command - SDI and SDO States.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
7.8
Decrement Wiper
Normal and High Voltage
Note:
The High Voltage Decrement Wiper
command is supported for compatability
with system that also support MCP414X/
416X/424X/426X devices.
The Decrement Command is an 8-bit command. The
Decrement Command can only be issued to wiper
memory locations. The format of the command is
shown in Figure 7-6.
An Decrement Command to the wiper memory location
changes that location after a properly formatted
command (8-clocks) have been received.
Decrement commands provide a quick and easy
method to modify the value of the wiper location by -1
with minimal overhead.
COMMAND BYTE
(DECR COMMAND (n+1))
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
7.8.1
SINGLE DECREMENT
Typically the CS pin starts at the inactive state (VIH), but
may be already be in the active state due to the
completion of another command.
Figure 6-7 through Figure 6-8 show possible
waveforms for a single Decrement. The decrement
operation requires that the CS pin be in the active state
(VILor VIHH). Typically the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
Then the 8-bit Decrement Command (Command Byte)
is clocked in on the SDI pin by the SCK pins. The SDO
pin drives the CMDERR bit on the 7th clock.
The wiper value will decrement from the wipers
Full-Scale value (100h on 8-bit devices and 80h on
7-bit devices). Above the wipers Full-Scale value
(8-bit =101h to 1FFh, 7-bit = 81h to FFh), the
decrement command is disabled. If the Wiper register
has a Zero Scale value (000h), then the wiper value will
not decrement. See Table 7-4 for additional information
on the Decrement Command vs. the current volatile
wiper value.
1
0
X
X
The Decrement commands only require the Decrement
command byte, while the CS pin is active (VILor VIHH)
for a single decrement.
1
1
1
1
1*
0
1 Note 1, 2
0 Note 1, 3
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-8:
Decrement Command SDI and SDO States.
© 2008 Microchip Technology Inc.
TABLE 7-5:
Current Wiper
Setting
7-bit
Pot
8-bit
Pot
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
3FFh
101h
100h
0FFh
081
080h
07Fh
001
000h
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
Decrement
Command
Operates?
Wiper (W)
Properties
Reserved
(Full-Scale (W = A))
Full-Scale (W = A)
W=N
No
Yes
W = N (Mid-Scale)
W=N
Yes
Zero Scale (W = B)
No
DS22060B-page 57
MCP413X/415X/423X/425X
7.8.2
CONTINUOUS DECREMENTS
Decrement commands can be sent repeatedly without
raising CS until a desired condition is met. The value in
the Volatile Wiper register can be read using a Read
Command.
Continuous Decrements are possible only when writing
to the wiper registers.
Figure 7-9 shows a continuous Decrement sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
When executing a continuous command string, The
Decrement command can be followed by any other
valid command.
When executing an continuous Decrement commands,
the selected wiper will be altered from n to n-1 for each
Decrement command received. The wiper value will
decrement from the wipers Full-Scale value (100h on
8-bit devices and 80h on 7-bit devices). Above the
wipers Full-Scale value (8-bit =101h to 1FFh,
7-bit = 81h to FFh), the decrement command is
disabled. If the Wiper register has a Zero Scale value
(000h), then the wiper value will not decrement. See
Table 7-4 for additional information on the Decrement
Command vs. the current volatile wiper value.
(DECR COMMAND (n-1) )
A
D
3
1
1
SDO
1
1
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
SDI
The wiper terminal will move after the command has
been received (8th clock).
1
0
X
X
1
1
1
1
1
1
1
1
1*
0
1
1
1
0
1
1
(DECR COMMAND (n-1) )
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
1
0
X
X
1
0
1
1
1
0
1
1
1*
0
0
1
1
0
0
1
(DECR COMMAND (n-1) )
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
1
0
X
X
1
0
0
1
1
0
0
1
1*
0
0
0
1
0
0
0
Note 1, 2
Note 3, 4
Note 3, 4
Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
DS22060B-page 58
Continuous Decrement Command - SDI and SDO States.
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
8.0
APPLICATIONS EXAMPLES
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP413X/415X/423X/425X
devices can be used to replace the common mechanical trim pot in applications where the operating and
terminal voltages are within CMOS process limitations
(VDD = 2.7V to 5.5V).
8.1
Split Rail Applications
All inputs that would be used to interface to a Host
Controller support High Voltage on their input pin. This
allows the MCP4XXX device to be used in split power
rail applications.
5V
SDI
CS
SCK
Figure 8-1 through Figure 8-2 show three example split
rail systems. In this system, the MCP4XXX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH).
In Example #1 (Figure 8-1), the MCP4XXX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH). If the split rail voltage delta
becomes too large, then the customer may be required
to do some level shifting due to MCP4XXX VOH levels
related to Host Controller VIH levels.
In Example #2 (Figure 8-2), the MCP4XXX interface
input signals need to be able to support the lower
voltage of the PIC MCU output high voltage level (VOH).
Table 8-1 shows an example PIC microcontroller I/O
voltage
specifications
and
the
MCP4XXX
specifications. So this PIC MCU operating at 3.3V will
drive a VOH at 2.64V, and for the MCP4XXX operating
at 5.5V, the VIH is 2.47V. Therefore, the interface
signals meet specifications.
© 2008 Microchip Technology Inc.
SDI
CS
SCK
SHDN
SDO
FIGURE 8-1:
System 1.
SHDN
SDO
Example Split Rail
5V
Voltage
Regulator
3V
MCP4XXX
PIC MCU
SDI
CS
SCK
SDI
CS
SCK
For SPI applications, these inputs are:
CS
SCK
SDI (or SDI/SDO)
SHDN
MCP4XXX
PIC MCU
An example of this is a battery application where the
PIC® MCU is directly powered by the battery supply
(4.8V) and the MCP4XXX device is powered by the
3.3V regulated voltage.
•
•
•
•
3V
Voltage
Regulator
SHDN
SHDN
SDO
SDO
FIGURE 8-2:
System 2.
Example Split Rail
TABLE 8-1:
VOH - VIH COMPARISONS
PIC
VDD
5.5
5.0
4.5
3.3
3.0
2.7
Note
(1)
VIH
MCP4XXX (2)
VOH VDD
VIH
VOH
Comment
4.4
4.4
2.7 1.215 — (3)
4.0
4.0
3.0 1.35 — (3)
3.6
3.6
3.3 1.485 — (3)
2.64 2.64 4.5 2.025 — (3)
2.4
2.4
5.0 2.25 — (3)
2.16 2.16 5.5 2.475 — (3)
1: VOH minimum = 0.8 * VDD;
VOL maximum = 0.6V
VIH minimum = 0.8 * VDD;
VIL maximum = 0.2 * VDD;
2: VOH minimum (SDA only) =;
VOL maximum = 0.2 * VDD
VIH minimum = 0.45 * VDD;
VIL maximum = 0.2 * VDD
3: The only MCP4XXX output pin is SDO,
which is Open-Drain (or Open-Drain with
Internal Pull-up) with High Voltage Support
DS22060B-page 59
MCP413X/415X/423X/425X
8.2
Techniques to force the CS pin to
VIHH
PIC10F206
The circuit in Figure 8-3 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2
pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
PIC MCU
TC1240A
C+
VIN
CSHDN
VOUT
IO1
IO2
C1
MCP402X
R1
CS
C2
FIGURE 8-3:
Using the TC1240A to
generate the VIHH voltage.
The circuit in Figure 8-4 shows the method used on the
MCP402X Non-volatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method
requires that the system voltage be approximately 5V.
This ensures that when the PIC10F206 enters a
brown-out condition, there is an insufficient voltage
level on the CS pin to change the stored value of the
wiper.
The
MCP402X
Non-volatile
Digital
Potentiometer Evaluation Board User’s Guide
(DS51546) contains a complete schematic.
R1
GP0
MCP4XXX
GP2
CS
C1
FIGURE 8-4:
MCP4XXX Non-Volatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
8.3
Using Shutdown Modes
Figure 8-5 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the Bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to VDD and VSS.
Common A
Input
A
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
To base
of Transistor
(or Amplifier)
W
For the serial commands, configure the GP2 pin as an
input (high-impedance). The output state of the GP0
pin will determine the voltage on the CS pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
C2
B
Input
Common B
Balance
Bias
FIGURE 8-5:
Example Application Circuit
using Terminal Disconnects.
DS22060B-page 60
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
8.4
Design Considerations
8.4.2
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
• Power Supply Considerations
• Layout Considerations
8.4.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-6 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
LAYOUT CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-11,
Figure 2-24, Figure 2-36, and Figure 2-48.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
supports two features. These are:
• In-Circuit Accommodation of split rail applications
and power supply sync issues
• Compatability with systems that also support
MCP414X/416X /424X/426X devices
0.1 µF
VDD
W
B
VSS
FIGURE 8-6:
Connections.
U/D
PIC® Microcontroller
A
MCP413X/415X/
423X/425X
0.1 µF
CS
VSS
Typical Microcontroller
© 2008 Microchip Technology Inc.
DS22060B-page 61
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 62
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
Several development tools are available to assist in
your design and evaluation of the MCP4XXX devices.
The currently available tools are shown in Table 9-1.
9.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-2 shows
some of these documents.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 9-1:
DEVELOPMENT TOOLS
Board Name
Part #
Supported Devices
MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS
Board
MCP42XX
MCP4XXX Digital Potentiometer Daughter Board (1)
MCP4XXXDM-DB
MCP42XXX, MCP42XX,
MCP4021, and MCP4011
8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board
SOIC8EV
Any 8-pin device in DIP, SOIC,
MSOP, or TSSOP package
14-pin SOIC/MSOP/DIP Evaluation Board
SOIC14EV
Any 14-pin device in DIP, SOIC, or
MSOP package
Note 1: Requires the use of a PICDEM Demo board (see User’s Guide for details)
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1080
Understanding Digital Potentiometers Resistor Variations
DS01080
AN737
Using Digital Potentiometers to Design Low Pass Adjustable Filters
DS00737
AN692
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
DS00692
AN691
Optimizing the Digital Potentiometer in Precision Circuits
DS00691
AN219
Comparing Digital Potentiometers to Mechanical Potentiometers
DS00219
—
Digital Potentiometer Design Guide
DS22017
—
Signal Chain Design Guide
DS21825
© 2008 Microchip Technology Inc.
DS22060B-page 63
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 64
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
8-Lead DFN (3x3)
XXXX
YYWW
NNN
Part Number
Code
Part Number
Code
MCP4131-502E/MF
DAAE
MCP4132-502E/MF
DAAY
MCP4131-103E/MF
DAAF
MCP4132-103E/MF
DAAZ
MCP4131-104E/MF
DAAH
MCP4132-104E/MF
DABB
MCP4131-503E/MF
DAAG
MCP4132-503E/MF
DABA
MCP4151-502E/MF
DAAP
MCP4152-502E/MF
DAAA
MCP4151-103E/MF
DAAQ
MCP4152-103E/MF
DABD
MCP4151-104E/MF
DAAS
MCP4152-104E/MF
DAAD
MCP4151-503E/MF
DAAR
MCP4152-503E/MF
DAAC
Part Number
Code
Part Number
Code
MCP4131-502E/MS
413152
MCP4132-502E/MS
413252
MCP4131-103E/MS
413113
MCP4132-103E/MS
413213
MCP4131-104E/MS
413114
MCP4132-104E/MS
413214
MCP4131-503E/MS
413153
MCP4132-503E/MS
413253
MCP4151-502E/MS
415152
MCP4152-502E/MS
415252
MCP4151-103E/MS
415113
MCP4152-103E/MS
415213
MCP4151-104E/MS
415114
MCP4152-104E/MS
415214
MCP4151-503E/MS
415153
MCP4152-503E/MS
415253
8-Lead MSOP
XXXXXX
YWWNNN
8-Lead PDIP
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC
Example:
DAAE
0817
256
Example
413152
817256
Example
4131-502
E/P e3 256
0817
Example
XXXXXXXX
XXXXYYWW
4131502E
SN^^^0817
e3
NNN
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS22060B-page 65
MCP413X/415X/423X/425X
Package Marking Information (Continued)
Example:
10-Lead DFN (3x3)
XXXX
YYWW
NNN
Part Number
Code
Part Number
Code
MCP4232-502E/MF
BAEH
MCP4252-502E/MF
BAES
MCP4232-103E/MF
BAEJ
MCP4252-103E/MF
BAET
MCP4232-104E/MF
BAEL
MCP4252-104E/MF
BAEV
MCP4232-503E/MF
BAEK
MCP4252-503E/MF
BAEU
10-Lead MSOP
Example
XXXXXX
Part Number
Code
Part Number
Code
YWWNNN
MCP4232-502E/MS
423252
MCP4252-502E/MS
425252
MCP4232-103E/MS
423213
MCP4252-103E/MS
425213
MCP4232-104E/MS
423214
MCP4252-104E/MS
425214
MCP4232-503E/MS
423253
MCP4252-503E/MS
425253
14-Lead PDIP
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (.150”)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP
XXXXXXXX
YYWW
NNN
16-Lead QFN
XXXXX
XXXXXX
XXXXXX
YWWNNN
DS22060B-page 66
BAEH
0817
256
423252
817256
Example
MCP4251
e3
502E/P^^
0817256
Example
MCP4251
502E/SL^^
e3
0817256
Example
4251502E
0817
256
Example
4251
502
e3
E/ML^^
0817256
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
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© 2008 Microchip Technology Inc.
DS22060B-page 67
MCP413X/415X/423X/425X
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DS22060B-page 69
MCP413X/415X/423X/425X
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DS22060B-page 70
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
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© 2008 Microchip Technology Inc.
DS22060B-page 71
MCP413X/415X/423X/425X
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DS22060B-page 73
MCP413X/415X/423X/425X
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DS22060B-page 75
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© 2008 Microchip Technology Inc.
DS22060B-page 77
MCP413X/415X/423X/425X
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© 2008 Microchip Technology Inc.
DS22060B-page 79
MCP413X/415X/423X/425X
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© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
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© 2008 Microchip Technology Inc.
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DS22060B-page 81
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 82
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision B (December 2008)
The following is the list of modifications:
1.
2.
3.
4.
5.
Updated IPU specifications to specify test
conditions and new limit.
Updated DFN package in “Package Types (top
view)”, including Exposed Thermal Pad sample
(EP).
Added new descriptions in Section 3.0 “Pin
Descriptions”.
Added new Development Tool support items.
Updated Package Outline section.
Revision A (September 2007)
• Original Release of this Document.
MIGRATING FROM
THE MCP41XXX AND
MCP42XXX DEVICES
This is intended to give an overview of some of the
differences to be aware of when migrating from the
MCP41XXX and MCP42XXX devices.
B.1
MCP41XXX to MCP41XX
Differences
Here are some of the differences to be aware of:
1.
2.
3.
4.
5.
6.
7.
8.
9.
B.2
SI pin is now SDI/SDO pin, and the contents of
the device memory can be read.
Need to address the Terminal Connect Feature
(TCON register) of MCP41XX.
MCP41XX supports software Shutdown mode.
New 5 kΩ version.
MCP41XX have 7-bit resolution options.
Alternate pinout versions (for Rheostat
configuration).
Verify device’s electrical specifications.
Interface signals are now high voltage tolerant.
Interface signals now have internal pull-up
resistors.
MCP42XXX to MCP42XX
Differences
Here are some of the differences to be aware of:
1.
Daisy chaining of devices is no longer
supported.
2. SDO pin allows contents of device memory to be
read.
3. Need to address the Terminal Connect Feature
(TCON register) of MCP42XX.
4. MCP42XX supports software Shutdown mode.
5. New 5 kΩ version.
6. MCP42XX have 7-bit resolution options.
7. Alternate package/pinout versions (for Rheostat
configuration).
8. Verify device’s electrical specifications.
9. Interface signals are now high voltage tolerant
10. Interface signals now have internal pull-up
resistors.
© 2008 Microchip Technology Inc.
DS22060B-page 83
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 84
© 2008 Microchip Technology Inc.
MCP413X/415X/423X/425X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device
XXX
X
Resistance Temperature
Version
Range
MCP4131:
MCP4131T:
MCP4132:
MCP4132T:
MCP4151:
MCP4151T:
MCP4152:
MCP4152T:
MCP4231:
MCP4231T:
MCP4232:
MCP4232T:
MCP4251:
MCP4251T:
MCP4252:
MCP4252T:
Resistance Version:
502
103
503
104
Temperature Range
I
E
Package
MF
ML
MS
P
SN
SL
ST
UN
=
=
=
=
/XX
Package
Single Volatile 7-bit Potentiometer
Single Volatile 7-bit Potentiometer
(Tape and Reel)
Single Volatile 7-bit Rheostat
Single Volatile 7-bit Rheostat
(Tape and Reel)
Single Volatile 8-bit Potentiometer
Single Volatile 8-bit Potentiometer
(Tape and Reel)
Single Volatile 8-bit Rheostat
Single Volatile 8-bit Rheostat
(Tape and Reel)
Dual Volatile 7-bit Potentiometer
Dual Volatile 7-bit Potentiometer
(Tape and Reel)
Dual Volatile 7-bit Rheostat
Dual Volatile 7-bit Rheostat
(Tape and Reel)
Dual Volatile 8-bit Potentiometer
Dual Volatile 8-bit Potentiometer
(Tape and Reel)
Dual Volatile 8-bit Rheostat
Dual Volatile 8-bit Rheostat
(Tape and Reel)
5 kΩ
10 kΩ
50 kΩ
100 kΩ
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Extended)
=
=
=
=
=
=
=
=
Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead
Plastic Quad Flat No-lead (QFN), 16-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic Dual In-line (PDIP) (300 mil), 8/14-lead
Plastic Small Outline (SOIC), (150 mil), 8-lead
Plastic Small Outline (SOIC), (150 mil), 14-lead
Plastic Thin Shrink Small Outline (TSSOP), 14-lead
Plastic Micro Small Outline (MSOP), 10-lead
© 2008 Microchip Technology Inc.
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
MCP4131-502E/XX:
MCP4131T-502E/XX:
MCP4131-103E/XX:
MCP4131T-103E/XX:
MCP4131-503E/XX:
MCP4131T-503E/XX:
MCP4131-104E/XX:
MCP4131T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4132-502E/XX:
MCP4132T-502E/XX:
MCP4132-103E/XX:
MCP4132T-103E/XX:
MCP4132-503E/XX:
MCP4132T-503E/XX:
MCP4132-104E/XX:
MCP4132T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4151-502E/XX:
MCP4151T-502E/XX:
MCP4151-103E/XX:
MCP4151T-103E/XX:
MCP4151-503E/XX:
MCP4151T-503E/XX:
MCP4151-104E/XX:
MCP4151T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4152-502E/XX:
MCP4152T-502E/XX:
MCP4152-103E/XX:
MCP4152T-103E/XX:
MCP4152-503E/XX:
MCP4152T-503E/XX:
MCP4152-104E/XX:
MCP4152T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4231-502E/XX:
MCP4231T-502E/XX:
MCP4231-103E/XX:
MCP4231T-103E/XX:
MCP4231-503E/XX:
MCP4231T-503E/XX:
MCP4231-104E/XX:
MCP4231T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4232-502E/XX:
MCP4232T-502E/XX:
MCP4232-103E/XX:
MCP4232T-103E/XX:
MCP4232-503E/XX:
MCP4232T-503E/XX:
MCP4232-104E/XX:
MCP4232T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4251-502E/XX:
MCP4251T-502E/XX:
MCP4251-103E/XX:
MCP4251T-103E/XX:
MCP4251-503E/XX:
MCP4251T-503E/XX:
MCP4251-104E/XX:
MCP4251T-104E/XX:
5 kΩ, 8LD Device
T/R, 5 kΩ, 8LD Device
10 kΩ, 8-LD Device
T/R, 10 kΩ, 8LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 8LD Device
100 kΩ, 8LD Device
T/R, 100 kΩ, 8LD Device
a)
b)
c)
d)
e)
f)
g)
h)
XX
MCP4252-502E/XX: 5 kΩ, 8LD Device
MCP4252T-502E/XX: T/R, 5 kΩ, 8LD Device
MCP4252-103E/XX: 10 kΩ, 8-LD Device
MCP4252T-103E/XX: T/R, 10 kΩ, 8LD Device
MCP4252-503E/XX: 50 kΩ, 8LD Device
MCP4252T-503E/XX: T/R, 50 kΩ, 8LD Device
MCP4252-104E/XX: 100 kΩ, 8LD Device
MCP4252T-104E/XX: T/R, 100 kΩ, 8LD Device
= MF for 8/10-lead 3x3 DFN
= ML for 16-lead QFN
= MS for 8-lead MSOP
= P for 8/14-lead PDIP
= SN for 8-lead SOIC
= SL for 14-lead SOIC
= ST for 14-lead TSSOP
= UN for 10-lead MSOP
DS22060B-page 85
MCP413X/415X/423X/425X
NOTES:
DS22060B-page 86
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS22060B-page 87
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Web Address:
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Tel: 86-756-3210040
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01/02/08
DS22060B-page 88
© 2008 Microchip Technology Inc.