A1 PROs IMP5226CDBT 18--liine pllug and pllay scsii termiinattor Datasheet

IMP5226
1
DATA COMMUNICATIONS
18-Line Plug and Play
SCSI Terminator
Key Features
The 18-channel IMP5226 SCSI terminator is part of IMP's family of highperformance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation
linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator terminator approach. The bandwidth of terminators based on the older
regulator/resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation
capacitor and the need for transient output capacitors while maintaining
pin compatibility with first generation designs. Reduced component
count is inherent with the IMP5226.
The IMP5226 architecture tolerates marginal system designs. A key
improvement offered by the IMP5226 lies in its ability to insure reliable,
error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable
lengths and impedance. Frequently, this situation is not controlled by the
peripheral or host designer.
The IMP5226 can be placed in a sleep mode with a high logic signal. In
the sleep mode the outputs are in a high impedance state. Quiescent current is less than 150µA when disabled.
The IMP5226 is a superior pin-for-pin replacement for the LX5226,
LX5207, UC5601/5602 and the UCC5610.
◆ Ultra-Fast response for Fast-20 SCSI
◆ 35MHz channel bandwidth
◆ Sleep-mode current less than 150µA
— Disconnects terminator from lows
◆ NO external compensation capacitors
◆ Compatible with active negation drivers
◆ Compatible with passive and active terminations
◆ Approved for use with SCSI 1, 2, 3 and
Ultra SCSI
◆ Hot-swap compatible
◆ Pin-for-pin compatible with LX5226, LX5207
and UCC5610
IMP SCSI Terminators
Part
Channels
Type
IMP5111
IMP5112
IMP5115
IMP5121
IMP5218
IMP5219
IMP5225
IMP5226
IMP5241
IMP5242
9
9
9
27
9
9
18
18
8
8
SE
SE
SE
SE
SE
SE
SE
SE
SE/LVD
SE/LVD
5226_t06.eps
Block Diagrams
Term Power
Thermal
Limiting
Circuit
Current
Biasing
Circuit
24mA Current
Limiting Circuit
DATA OUTPUT
PIN DB (0)
VTERM
2.85V
DISCONNECT
–
1 of 18 Channels
+
1.4V
5226_01.eps
IMP5226
1
Pin Configuration
SOWB-28
SSOP-28
DISCONNECT
1
28 GND
T1
2
T2
3
T3
T4
DISCONNECT
1
28 GND
27 T18
T1
2
27 T18
26 T17
T2
3
26 T17
4
25 T16
T3
4
25 T16
5
24 T15
T4
5
24 T15
T5
6
23 T14
T5
6
HEAT SINK / GND
7
22 HEAT SINK / GND
HEAT SINK / GND
7
GND
8
21 HEAT SINK / GND
GND
8
21 HEAT SINK / GND
HEAT SINK / GND
9
20 HEAT SINK / GND
HEAT SINK / GND
9
20 HEAT SINK / GND
IMP5226
IMP5226
23 T14
22 HEAT SINK / GND
T6 10
19 T13
T6 10
19 T13
T7 11
18 T12
T7 11
18 T12
T8 12
17 T11
T8 12
17 T11
T9 13
16 T10
T9 13
16 T10
VTERM 14
15 NC
VTERM 14
15 NC
5226_02a.eps
5226_02b.eps
DWP Package
DB Package
Ordering Information
Part Number
Temperature Range
Package
IMP5226CDWP
0°C to 70°C
28-pin Plastic SOWB
IMP5226CDWPT
0°C to 70°C
Tape and Reel, 28-pin Plastic SOWB
IMP5226CDB
0°C to 70°C
28-pin Plastic SSOP
IMP5226CDBT
0°C to 70°C
Tape and Reel, 28-pin Plastic SSOP
5226_t01.at3
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Operating Junction Temperature . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
DWP Package
Thermal Resistance Junction-to-Leads, θJL . . . . . . . . 18°C/W
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 40°C/W
DB Package
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 117°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
2
408-432-9100/www.impweb.com
© 2000 IMP, Inc.
IMP5226
1
Recommended Operating Conditions
Parameter
Termpwr Voltage
Symbol
Min
VTERM
4.0
Typ
Max
Units
5.5
V
Signal Line Voltage
0
5.0
V
Disconnect Input Voltage
0
VTERM
V
Operating Junction Temperature Range – IMP5226C
0
125
°C
Note:
5226_t02.eps
2. Recommended operating conditions indicate the range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of TA = 25°C. TermPwr = 4.75V. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage
TermPwr Supply Current
Output Current
Symbol Conditions
VOUT
ICC
IOUT
Min
Typ
2.65
2.85
Max
Units
V
All data lines = Open
10
15
All data lines = 0.2V
424
450
DISCONNECT Pins > 2.0V
50
150
µA
–22
–24
mA
–10
µA
1
µA
VOUT = 0.5V
–20
Disconnect Input Current
IIN
DISCONNECT Pins = 0V
Output Leakage Current
IOL
DISCONNECT Pins > 2.0V, VO = 0.2V
Channel Bandwidth
BW
Termination Sink Current, per Channel
ISINK
35
VOUT = 4V
7
mA
MHz
mA
5226_t03.eps
© 2000 IMP, Inc.
Data Communications
3
IMP5226
1
Application Information
Figure 1. Receiving Waveform – 20MHz
Figure 2. Driving Waveform – 20MHz
Receiver
Driver
1 Meter, AWG 28
DISCONNECT
IMP5226
IMP5226
DISCONNECT
5226_03.eps
Figure 3.
4
408-432-9100/www.impweb.com
© 2000 IMP, Inc.
IMP5226
1
Application Information
Cable transmission theory suggests to optimize signal speed and
quality, the termination should act both as an ideal voltage reference when the line is released (deasserted) and as an ideal
current source when the line is active (asserted). Common active
terminators which consist of linear regulators in series with resistors (typically 110Ω) are a compromise. With coventional linear
terminators as the line voltage increases the amount of current
decreases linearly by the equation;
(VREF − VLINE) = I.
R
The IMP5226, with its unique new architecture, applies the maximum amount of current regardless of line voltage until the
termination high threshold (2.85V) is reached.
Acting as a near ideal line terminator, the IMP5226 closely reproduces the optimum case when the device is enabled. To enable
the device the disconnect pin is pulled LOW. During this mode
of operation, quiescent current is 10mA, and the device will
respond to line demands by delivering 24mA on assertion and by
imposing 2.85V on deassertion.
In order to disable the device, the disconnect pin must be driven
HIGH In the disable mode, the device is in a sleep state with
quiescent current less than 150µA. When disabled, all
outputs are in a high impedance state. Sleep mode can be used
for power conservation or to remove the terminator from the
SCSI chain.
An additional feature of the IMP5226 is its compatibility with
active negation drivers.
Table 1. Power Up/ Power Down Function Table
DISCONNECT
Outputs
Maximum Quiescent
Current
L
Enabled
15mA
H
HI Z
150µA
Open
HI Z
150µA
5226_t04.eps
© 2000 IMP, Inc.
Data Communications
5
IMP5226
1
Package Dimensions
SOWB (28-Pin)
Inches
Min
A
Max
Min
Max
SOWB (28-Pin)*
28
15
1
14
B
F
Millimeters
A
B
C
D
F
G
J
K
M
P
P
D
G
L
M
C
SEATING PLANE
K
J
28-Pin (SOWB)DWP.eps
0.698
0.713
0.291
0.299
0.093
0.104
0.013
0.018
0.016
0.050
0.050 BSC
0.009
0.013
0.004
0.012
0°
8°
0.394
0.419
17.70
18.10
7.40
7.60
2.35
2.65
0.33
0.51
0.40
1.27
1.27 BSC
0.23
0.32
0.10
0.30
0°
8°
10.00
10.65
SSOP (28-Pin)
A
0.068
0.078
B
0.009
0.015
C
0.005
0.008
D
0.396
0.407
F
0.205
0.212
G
0.25 BSC
J
0.002
0.008
K
0.064
0.072
L
0.025
0.037
M
0°
8°
P
0.301
0.311
* JEDEC Drawing MO-013AE
SSOP (28-Pin)
E P
1 2 3
D
E
F
A H
SEATING PLANE
B
G
L
C
1.73
1.99
0.25
0.38
0.13
0.22
10.07
10.33
5.20
5.38
0.65 BSC
0.05
0.21
1.63
1.83
0.65
0.95
0°
8°
7.65
7.90
5226_t05.at3
M
28-Pin (SSOP)DB.eps
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Fax: 408-432-1085
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
© 2000 IMP, Inc.
Printed in USA
Publication #: 7009
Revision:
D
Issue Date:
08/19/02
Type:
Preliminary
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