Fairchild FIN1216 Lvds 21-bit serializers/de-serializer Datasheet

Revised March 2005
FIN1217 • FIN1218 •
FIN1215 • FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
Features
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and transmitted.
■ Low power consumption
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
■ Up to 595 Mbps per channel
■ 20 MHz to 85 MHz shift clock support
■ 50% duty cycle on the clock output of receiver
■ r1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 1.785 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
■ Devices are offered in 48-lead TSSOP packages
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Ordering Code:
Order Number
Package
Package Description
Number
FIN1215MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1215MTDX_NL
(Note 1)
MTD48
Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm
Wide
FIN1216MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1216MTDX_NL
(Note 1)
MTD48
Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm
Wide
FIN1217MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1218MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500876
www.fairchildsemi.com
FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers
October 2003
FIN1217 • FIN1218 • FIN1215 • FIN1216
TABLE 1. Serializers/De-Serializers Chip Matrix
Part
CLK Frequency
LVTTL IN
LVDS OUT
FIN1217
85
21
3
FIN1218
85
FIN1215
66
21
3
FIN1216
66
LVDS IN
LVTTL OUT
3
21
3
21
Transmitter Functional Diagram for FIN1217 and FIN1215
Receiver Functional Diagram for FIN1218 and FIN1216
2
48 TSSOP
48 TSSOP
Block Diagrams
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Package
48 TSSOP
48 TSSOP
Pin Descriptions
Pin Names
I/O Type Number of Pins
Description of Signals
TxIn
I
21
LVTTL Level Inputs
TxCLKIn
I
1
LVTTL Level Clock Input
The rising edge is for data strobe.
TxOut
O
3
Positive LVDS Differential Data Output
TxOut
O
3
Negative LVDS Differential Data Output
TxCLKOut
O
1
Positive LVDS Differential Clock Output
TxCLKOut
O
1
Negative LVDS Differential Clock Output
PwrDn
I
1
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in high-impedance state.
Power Supply Pin for PLL
PLL VCC
I
1
PLL GND
I
2
Ground Pins for PLL
LVDS VCC
I
1
Power Supply Pin for LVDS Outputs
LVDS GND
I
3
Ground Pins for LVDS Outputs
VCC
I
4
Power Supply Pins for LVTTL Inputs
GND
I
5
Ground pins for LVTTL Inputs
NC
No Connect
Connection Diagram
FIN1217 and FIN1215 (21:3 Transmitter)
Pin Assignment for TSSOP
3
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FIN1217 • FIN1218 • FIN1215 • FIN1216
Transmitters
FIN1217 • FIN1218 • FIN1215 • FIN1216
Receivers
Pin Descriptions
Pin Names
I/O Type
Number
of
Pins
Description of Signals
RxIn
I
3
Negative LVDS Differential Data Inputs
RxIn
I
3
Positive LVDS Differential Data Inputs
RxCLKIn
I
1
Negative LVDS Differential Clock Input
RxCLKIn
I
1
Positive LVDS Differential Clock Input
RxOut
O
21
LVTTL Level Data Outputs
Goes HIGH for PwrDn LOW
RxCLKOut
O
1
LVTTL Clock Output
PwrDn
I
1
LVTTL Level Input
Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table
PLL VCC
I
1
Power Supply Pin for PLL
PLL GND
I
2
Ground Pins for PLL
LVDS VCC
I
1
Power Supply Pin for LVDS Inputs
LVDS GND
I
3
Ground Pins for LVDS Inputs
VCC
I
4
Power Supply for LVTTL Outputs
GND
I
5
NC
Ground Pins for LVTTL Outputs
No Connect
Connection Diagram
FIN1218 and FIN1216 (3:21 Receiver)
Pin Assignment for TSSOP
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4
Transmitter Truth Table
Inputs
Outputs
TxIn
TxCLKIn
PwrDn (Note 2)
TxOutr
Active
Active
H
L/H
TxCLKOutr
L/H
Active
L/H/Z
H
L/H
X (Note 3)
F
Active
H
L
L/H
F
F
H
L
X (Note 3)
X
X
L
Z
Z
H HIGH Logic Level
L LOW Logic Level
X Don’t Care
Z High Impedance
F Floating
Note 2: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V.
Note 3: TxCLKOutr will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z).
Receiver Truth Table
Inputs
Outputs
RxInr
RxCLKInr
PwrDn (Note 4)
RxOut
RxCLKOut
Active
Active
H
L/H
L/H
Active
F (Note 5)
H
P
H
F (Note 5)
Active
H
H
L/H
F (Note 5)
F (Note 5)
H
P (Note 6)
H
X
X
L
L
H
H HIGH Logic Level
L LOW Logic Level
P Last Valid State
X Don’t Care
Z High Impedance
F Failsafe Condition
Note 4: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V.
Note 5: Failsafe condition is defined as the input being terminated and un-driven (Z) or shorted or open.
Note 6: If RxCLKInr is removed prior to the RxInr data being removed, RxOut will be the last valid state. If RxInr data is removed prior to RxCLKInr being
removed, RxOut will be HIGH.
5
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FIN1217 • FIN1218 • FIN1215 • FIN1216
Truth Tables
FIN1217 • FIN1218 • FIN1215 • FIN1216
Absolute Maximum Ratings(Note 7)
Power Supply Voltage (VCC)
-0.3V to +4.6V
Recommended Operating
Conditions
TTL/CMOS Input/Output Voltage
0.5V to 4.6V
Supply Voltage (VCC)
LVDS Input/Output Voltage
-0.3V to +4.6V
Operating Temperature (TA)(Note 7)
LVDS Output Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
Maximum Junction Temperature (TJ)
Continuous
Maximum Supply Noise Voltage
65qC to 150qC
150 qC
(VCCNPP)
Lead Temperature (TL)
ESD Rating (HBM, 1.5 k:, 100 pF)
!10.0 kV
!6.5 kV
LVDS I/O to GND
All Pins (FIN1215, FIN1217 only)
100 mVP-P (Note 8)
Note 7: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
260 qC
(Soldering, 4 seconds)
3.0V to 3.6V
40°C to 85°C
Note 8: 100mV VCC noise should be tested for frequency at least up to
2 MHz. All the specification below should be met under such a noise.
ESD Rating (MM, 0:, 200 pF)
!400V
(FIN1215, FIN1217 only)
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Transmitter LVTTL Input Characteristics
VIH
Input High Voltage
2.0
VCC
VIL
Input Low Voltage
GND
0.8
V
VIK
Input Clamp Voltage
0.79
1.5
V
IIN
Input Current
1.8
10.0
IIK
18 mA
VIN
0.4V to 4.6V
VIN
GND
10.0
0
PA
Transmitter LVDS Output Characteristics (Note 10)
VOD
Output Differential Voltage
'VOD
VOD Magnitude Change from Differential LOW-to-HIGH
250
VOS
Offset Voltage
'VOS
Offset Magnitude Change from Differential LOW-to-HIGH
IOS
Short Circuit Output Current
VOUT
IOZ
Disabled Output Leakage Current
DO
RL
100 :, See Figure 1
1.125
1.25
450
mV
35.0
mV
1.375
V
mV
3.5
5.0
mA
0V
r1.0
r10.0
PA
33.0 MHz
28.0
46.2
40.0 MHz
29.0
51.7
65.0 MHz
34.0
57.2
85.0 MHz
39.0
62.7
10.0
55.0
0V
0V to 4.6V, PwrDn
Transmitter Supply Current
ICCWT
21:3 Transmitter Power Supply Current
100 :,
for Worst Case Pattern (With Load)
RL
(Note 11), (Note 12)
See Figure 3
(85.0 MHz Specification for FIN1217 only)
ICCPDT
Powered Down Supply Current
Note 9: All Typical values are at TA
25qC and with VCC
PwrDn
0.8V
mA
PA
3.3V.
Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except 'VOD and VOD).
Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 12: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
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6
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
tTCP
Transmit Clock Period
tTCH
Transmit Clock (TxCLKIn) HIGH Time
tTCL
Transmit Clock Low Time
tCLKT
TxCLKIn Transition Time (Rising and Failing)
tJIT
TxCLKIn Cycle-to-Cycle Jitter
tXIT
TxIn Transition Time
Test Conditions
See Figure 6
(10% to 90%) See Figure 7
Min
Typ
Max
Units
11.76
T
50.0
ns
0.35
0.5
0.65
T
0.35
0.5
0.65
T
6.0
ns
1.0
1.5
3.0
ns
6.0
ns
LVDS Transmitter Timing Characteristics
tTLH
Differential Output Rise Time (20% to 80%)
tTHL
Differential Output Fall Time (80% to 20%)
tSTC
TxIn Setup to TxCLNIn
See Figure 6
tHTC
TxIn Holds to TCLKIn
(f
tTPDD
Transmitter Power-Down Delay
See Figure 13, (Note 13)
100
tTCCD
Transmitter Clock Input to Clock Output Delay
See Figure 9
5.5
Transmitter Clock Input to Clock Output Delay
(TA
Transmitter Output Data Jitter (f
See Figure 4
85 MHz) (FIN1217 only)
25qC and with VCC
3.3V)
0.75
1.5
ns
0.75
1.5
ns
2.5
ns
0
ns
2.8
6.8
ns
ns
40 MHz) (Note 14)
0.25
0
0.25
ns
a0.25
a
a0.25
ns
1
2a0.25
2a
2a0.25
ns
fx7
3a0.25
3a
3a0.25
ns
Transmitter Output Pulse Position of Bit 4
4a0.25
4a
4a0.25
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a0.25
5a
5a0.25
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a0.25
6a
6a0.25
ns
ns
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Data Jitter (f
See Figure 16
a
65 MHz) (Note 14)
0.2
0
0.2
a0.2
a
a0.2
ns
1
2a0.2
2a
2a0.2
ns
fx7
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
Transmitter Output Pulse Position of Bit 5
5a0.2
5a
5a0.2
ns
Transmitter Output Pulse Position of Bit 6
6a0.2
6a
6a0.2
ns
ns
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
tTPPB6
Transmitter Output Data Jitter (f
See Figure 16
a
85 MHz) (FIN1217 only) (Note 14)
0.2
0
0.2
a0.2
a
a0.2
ns
1
2a0.2
2a
2a0.2
ns
fx7
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
Transmitter Output Pulse Position of Bit 5
5a0.2
5a
5a0.2
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a0.2
6a
6a0.2
ns
tJCC
FIN1217 Transmitter Clock Out Jitter
40 MHz
350
370
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
tTPLLS
See Figure 16
a
f
(Cycle-to-Cycle)
f
65 MHz
210
230
See Figure 19
f
85 MHz (FIN1217 only)
110
150
Transmitter Phase Lock Loop Set Time (Note 15)
See Figure 11, (Note 14)
10.0
ps
ms
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference (see Figure 15). Figure
16 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
7
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FIN1217 • FIN1218 • FIN1215 • FIN1216
Transmitter AC Electrical Characteristics
FIN1217 • FIN1218 • FIN1215 • FIN1216
Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
LVTTL/CMOS DC Characteristics
VIH
Input High Voltage
2.0
VCC
VIL
Input Low Voltage
GND
0.8
VOH
Output High Voltage
IOH
VOL
Output Low Voltage
IOL
2 mA
0.3
V
VIK
Input Clamp Voltage
IIK
18 mA
1.5
V
10.0
PA
IIN
Input Current
VIN
IOFF
Input/Output Power Off Leakage Current
VCC
IOS
Output Short Circuit Current
0.4 mA
2.7
3.3
10.0
0V to 4.6V
0V,
All LVTTL Inputs/Outputs 0V to 4.6V
VOUT
60.0
0V
V
V
r10.0
PA
120
mA
Receiver LVDS Input Characteristics
VTH
Differential Input Threshold HIGH
Figure 2, Table 2
VTL
Differential Input Threshold LOW
Figure 2, Table 2
VICM
Input Common Mode Range
Figure 2, Table 2
IIN
Input Current
VIN
2.4V, VCC
VIN
0V, VCC
100
100
mV
mV
0.05
3.6V or 0V
3.6V or 0V
2.35
V
r10.0
PA
r10.0
PA
Receiver Supply Current
ICCWR
3:21 Receiver Power Supply Current
33.0 MHz
for Worst Case Pattern (With Load)
CL
8 pF,
(Note 17)
See Figure 3
(85.0 MHz Specification for FIN1218 only)
ICCPDR
Powered Down Supply Current
PwrDn
66.0
40.0 MHz
56.0
74.0
65.0 MHz
75.0
102
85.0 MHz
92.0
125
NA
400
0.8V (RxOut stays LOW)
mA
PA
Note 16: All Typical Values are at TA 25qC and with VCC 3.3V. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD).
Note 17: The power supply current for the receiver can be different with the number of active I/O channels.
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8
Over supply voltage and operating temperatures, unless otherwise specified
Symbol
Parameter
Min
Typ
10.0
11.0
See Figure 8
10.0
12.2
ns
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
6.5
11.6
ns
(f
6.0
11.6
15.0
T
tRCOL
RxCLKOut LOW Time
tRCOH
RxCLKOut HIGH Time
tRSRC
Test Conditions
Max
Units
ns
tRHRC
RxOut Valid After RxCLKOut
tRCOP
Receiver Clock Output (RxCLKOut) Period
tRCOL
RxCLKOut LOW Time
See Figure 8
5.0
7.8
9.0
ns
tRCOH
RxCLKOut HIGH Time
(Rising Edge Strobe)
5.0
7.3
9.0
ns
(f
4.5
7.7
4.0
8.4
11.76
T
40 MHz)
65 MHz)
ns
50.0
ns
tRSRC
RxOut Valid Prior to RxCLKOut
tRHRC
RxOut Valid After RxCLKOut
tRCOP
Receiver Clock Output (RxCLKOut) Period
tRCOL
RxCLKOut LOW Time
See Figure 8
4.0
6.3
6.0
ns
tRCOH
RxCLKOut HIGH Time
(Rising Edge Strobe)
4.5
5.4
6.5
ns
(f
3.5
6.3
3.5
6.5
tRSRC
RxOut Valid Prior to RxCLKOut
tRHRC
RxOut Valid After RxCLKOut
tROLH
Output Rise Time (20% to 80%)
CL
tROHL
Output Fall Time (80% to 20%)
See Figure 5
tRCCD
Receiver Clock Input to Clock Output Delay
See Figure 10 (Note 19)
85 MHz) (FIN1218 only)
8 pF
25qC and VCC
TA
3.3V
3.5
See Figure 14
ns
ns
50.0
ns
ns
ns
2.2
5.0
ns
2.1
5.0
ns
6.9
7.5
ns
1.0
Ps
tRPDD
Receiver Power-Down Delay
tRSPB0
Receiver Input Strobe Position of Bit 0
1.0
2.15
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
4.5
5.8
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
See Figure 17
8.1
9.15
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
(f
11.6
12.6
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
15.1
16.3
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
18.8
19.9
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
22.5
23.6
ns
tRSPB0
Receiver Input Strobe Position of Bit 0
0.7
1.4
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.9
3.6
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
See Figure 17
5.1
5.8
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
(f
7.3
8.0
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
9.5
10.2
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
11.7
12.4
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
13.9
14.6
ns
tRSPB0
Receiver Input Strobe Position of Bit 0
0.49
1.19
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.17
2.87
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
3.85
4.55
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
See Figure 17
5.53
6.23
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
(f
7.21
7.91
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
8.89
9.59
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
10.57
11.27
ns
tRSKM
RxIn Skew Margin
f
40 MHz; See Figure 18
490
(Note 18)
f
65 MHz; See Figure 18
400
f
85 MHz (FIN1218 only);
40 MHz)
65 MHz)
85 MHz) (FIN1218 only)
See Figure 18
tRPLLS
Receiver Phase Lock Loop Set Time
ps
252
See Figure 12
10.0
ms
Note 18: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
Note 19: Total channel latency from serializer to deserializer is (T tTCCD) (2*T tRCCD). There is the clock period.
9
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FIN1217 • FIN1218 • FIN1215 • FIN1216
Receiver AC Electrical Characteristics
FIN1217 • FIN1218 • FIN1215 • FIN1216
FIGURE 1. Differential LVDS Output DC Test Circuit
Note A: For all input pulses, tR or tF 1 ns.
Note B: CL includes all probe and jig capacitance.
FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages
(V)
Resulting Differential Input Voltage Resulting Common Mode Input Voltage
(mV)
(V)
VID
VIC
1.15
100
1.2
1.25
100
1.2
2.4
2.3
100
2.35
2.3
2.4
100
2.35
0.1
0
100
0.05
VIA
VIB
1.25
1.15
0
0.1
100
0.05
1.5
0.9
600
1.2
0.9
1.5
600
1.2
2.4
1.8
600
2.1
1.8
2.4
600
2.1
0.6
0
600
0.3
0
0.6
600
0.3
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10
Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of
transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 3. “Worst Case” Test Pattern
FIGURE 4. Transmitter LVDS Output Load and Transition Times
FIGURE 5. Receiver LVTTL/CMOS Output Load and Transition Times
FIGURE 6. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
FIGURE 7. Transmitter Input Clock Transition Time
11
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FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
(Continued)
FIGURE 8. Receiver Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
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FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
(Continued)
FIGURE 11. Transmitter Phase Lock Loop Set Time
FIGURE 12. Receiver Phase Lock Loop Set Time
FIGURE 13. Transmitter Power-Down Delay
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FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
(Continued)
FIGURE 14. Receiver Power-Down Delay
Note: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference. All the information in this
diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
FIGURE 15. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs
FIGURE 16. Transmitter Output Pulse Bit Position
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FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
(Continued)
FIGURE 17. Receiver Input Strobe Bit Position
Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference).
Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across
PVT (Process, Voltage Supply, and Temperature).
FIGURE 18. Receiver LVDS Input Skew Margin
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FIN1217 • FIN1218 • FIN1215 • FIN1216
AC Loading and Waveforms
(Continued)
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter r3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
•
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right when data is HIGH (by switching between
CLK1 and CLK2 in Figure 11)
•
The r3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency 2 MHz).
FIGURE 19.
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FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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