Rohm BD8LA700EFV-C 8ch low-side switch Datasheet

Datasheet
IPD series for Automotive
8ch Low-side switch
BD8LA700EFV-C
Features
Product Summary
■ Monolithic power IC that has a built-in control part
(CMOS) and a power MOS FET on 1chip
■ 8ch Low-side switch for driving resistive, inductive
load
■ 16bit Serial peripheral interface(SPI) for diagnostics
and control
■ Built-in Open Load Detection circuit in output-off state
■ Built-in Over Current Protection circuit (OCP)
■ Built-in Active Clamp circuit
■ Built-in Thermal shutdown circuit (TSD)
■ Low On resistance of RON=700mΩ(VIN=5V, Tj=25°C,
Io=0.2A, Typ)
■ Surface mount HTSSOP-B24 Package
(Note 1)
■ AEC-Q100 Qualified
Digital part Operating voltage
Analog part Operating voltage
On-state resistance(25°C,Typ)
Over current limit(Typ)
Active clamp energy(25°C)
Package
3.0V to 5.5V
4.0V to 5.5V
700mΩ
1.2A
75mJ
W(Typ) x D(Typ) x H(Max)
7.80mm x 7.60mm x 1.00mm
HTSSOP-B24
(Note 1) Grade1
Overview
BD8LA700EFV is 8ch Low-Side switch for automotive
and industrial equipment. It has a built-in, Open Load
Detection circuit, Over Current Protection circuit, Active
clamp circuit and Thermal Shutdown circuit.
Application
For driving resistive, inductive load
HTSSOP-B24
Basic Application Circuit (Recommendation)
VBAT
0.1µF
0.1µF
VDDA
VDD
CS_B
(IN1)
SI
(IN2)
RST_B
(IN3)
SCLK
(IN4)
DIR
IN1
(IN5)
IN2
(IN6)
IN3
(IN7)
IN4
(IN8)
SO
stand-by
control
RL
OUT 1 ~ 8
POWER ON
RESET
Active
Clamp
POWER ON
RESET
SPI and DIR
Input
Switch from
SPI Mode
To DIR Mode
×8
PRE
DRV
Control
diagnostic
,
protective
factious,
SPI, and DIR Mode
×8
TSD
OCP
OLD
SPI and DIR
Input
×8
diagnostic
output
GND
Product configuration: Silicon monolithic integrated circuit
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○The product is not designed for radiation resistance.
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Datasheet
BD8LA700EFV-C
Pin Descriptions
Pin
Symbol
1
GND
I/O
(Note 1)
Function
-
GND
2
GND
-
GND
3
OUT1
O
Channel 1 output
4
OUT2
O
Channel 2 output
5
OUT3
O
Channel 3 output
6
OUT4
O
Channel 4 output
7
OUT5
O
Channel 5 output
8
OUT6
O
Channel 6 output
9
OUT7
O
Channel 7 output
10
OUT8
O
Channel 8 output
11
GND
-
GND
12
GND
-
GND
13
VDD
-
Digital power supply
14
IN4(IN8)
I
PD
Control input for Channel 4 and 8 (DIR=L) / Control input for Channel 8 (DIR=H)
15
IN3(IN7)
I
PD
Control input for Channel 3 and 7 (DIR=L) / Control input for Channel 7 (DIR=H)
16
IN2(IN6)
I
PD
Control input for Channel 2 and 6 (DIR=L) / Control input for Channel 6 (DIR=H)
17
IN1(IN5)
I
PD
Control input for Channel 1 and 5 (DIR=L) / Control input for Channel 5 (DIR=H)
18
DIR
I
PD
SPI mode, DIR mode change input terminal
19
SO
20
SCLK(IN4)
I
PD
Serial clock (DIR=L) / Control input for Channel 4 (DIR=H)
21
RST_B(IN3)
I
PD
Reset terminal (DIR=L) / Control input for Channel 3 (DIR=H)
22
SI(IN2)
I
PD
Serial data input (DIR=L) / Control input for Channel 2 (DIR=H)
O
23
CS_B(IN1)
24
VDDA
FIN
(Note 2)
PU/PD
(Note 2)
-
FIN
(Note 1)
I
Serial data output terminal
-
SPI enable input (DIR=L) / Control input for Channel 1 (DIR=H)
Analog power supply
Since it has connected with sub of IC, please connect the heat dissipation metal to
external GND potential.
O:Output terminal, I:Input terminal
PD:Pull Down terminal, PU:Pull Up terminal
Pull Up at DIR=Low setting, Pull Down at DIR=High
Pin Configurations
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HTSSOP-B24
(TOP VIEW)
GND
VDDA
GND
CS_B(IN1)
OUT1
SI(IN2)
OUT2
RST_B(IN3)
OUT3
SCLK(IN4)
OUT4
SO
OUT5
DIR
OUT6
IN1(IN5)
OUT7
IN2(IN6)
OUT8
IN3(IN7)
GND
IN4(IN8)
GND
VDD
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Datasheet
BD8LA700EFV-C
Absolute Maximum Ratings
Item
Power supply voltage (Pin No:13,24)
Output voltage (Pin No:3 to 10)
Symbol
Limit values
Unit
V CC
-0.3 to +7
V
V DS1 ~ 8
-0.3 to 45(Internally limited)
V
(Note 1)
A
Output current (Pin No:3 to 10)
I Dn
Diagnostic output voltage (Pin No:19)
V SO
0.5(Internally limited)
-0.3 to +7
V
Input voltage(Pin No:14 to 18,20 to 23)
V IN
-0.3 to +7
V
Junction temperature range
Tj
-40 to +150
°C
Storage temperature range
T stg
-55 to +150
°C
Maximum junction temperature
Active clamp energy (single pulse) (Tj(0)=25°C)
Active clamp energy (single pulse) (Tj(0)=150°C)
T jmax
E S1
E S2
150
75(Note 2)
25(Note 3)
°C
mJ
mJ
Active clamp energy (repetitive) (Tj(0)=105°C)
E AR
20(Note 4)
mJ
(Note 1) However, never exceed Tjmax.
(Note 2) Max Active clamp energy at T j ( 0 ) = 25°C, using single non-repetitive pulse of 0.5A
(Note 3) Max Active clamp energy at T j ( 0 ) =150°C, using single non-repetitive pulse of 0.5A. Not 100% tested.
(Note 4) Max Active clamp energy at T j ( 0 ) =105°C, using repetitive pulse of 0.4A and cycles of 1M times. Not 100% tested.
Operating Voltage Ratings (-40°C ≤Tj ≤+150°C)
Item
Code
Limit values
Unit
Digital part Operating voltage
V DD
3.0 to 5.5
V
Analog part Operating voltage
V DDA
4.0 to 5.5
V
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Datasheet
BD8LA700EFV-C
Electrical Characteristics(unless otherwise specified, VDDA=VDD=5V, -40°C≤Tj ≤+150°C)
Min
Limit values
Typ
Max
IDDAS
-
0
20
μA
IDDS
-
0
20
μA
VDDA Operating current)
IDDA
-
3.0
5.0
mA
VDDA=VDD=5V
VDD Operating current)
IDD
-
0.5
1.0
mA
VDDA=VDD=5V
VPORA
-
-
4.0
V
VPOR
-
-
2.7
V
VINL
0
-
VDD×0.2
V
H level input voltage
VINH
VDD×0.7
-
VDD
V
Input Hysteresis
VHYS
0.1
0.3
0.5
V
L level input current 1
(RST_B,DIR,IN1 to IN4,SCLK,SI)
IINL1
-10
0
10
μA
VRST_B, VDIR, VIN1 to VIN4, VSCLK,
VSI=0V
L level input current 2(CS_B)
IINL2
-100
-50
-25
μA
VCS_B=0V, VDIR=0V
L level input current 3(CS_B)
IINL3
-10
0
10
μA
VCS_B=0V, VDIR=5V
H level input current 1
(RST_B,DIR,IN1 to IN4,SCLK,SI)
IINH1
25
50
100
μA
VRST_B, VDIR, VIN1 to VIN4, VSCLK,
VSI=5V
H level input current 2(CS_B)
IINH2
-10
0
10
μA
VCS_B=5V, VDIR=0V
H level input current 3(CS_B)
IINH3
25
50
100
μA
VCS_B=5V, VDIR=5V
-
0.70
0.87
Ω
-
1.30
1.56
Ω
-
0
1
μA
VDD=VDDA=5V, IDn(Note 1)=0.2A,
Tj=25°C
VDD=VDDA=5V, IDn(note 1)=0.2A,
Tj=150°C
VDS=30V, Tj=25°C, VDIR=0V
-
5
20
μA
VDS=30V, Tj=150°C, VDIR=0V
IOL
15
40
90
μA
VDS =40V, VDIR=5V
tON
-
30
50
μs
tOFF
-
30
50
μs
Slew rate on
dV/dtON
0.3
1.0
3.0
V/μs
Slew rate off
-dV/dtOFF
0.3
1.0
3.0
V/μs
PWM Output range
fPWM
-
-
5
kHz
Output clamp voltage
VCL
45
50
55
V
Item
[Power Supply Block]
VDDA Standby current
(All output on standby mode)
VDD Standby current
(All output on standby mode)
VDDA power on reset
Threshold Voltage
VDD power on reset
Threshold Voltage
[Input PIN]
L level input voltage
Symbol
Unit
Condition
VDDA=VDD=VCS_B=5V
VRST_B=0V
VDDA=VDD=VCS_B=5V
VRST_B=0V
[Power MOS Output]
Output ON resistance
Output leak current
Output leak current
(Open load detected)
RDS(ON)
IL(OFF)
Switching time
VDD=5V, VINn(Note 1)=0V/5V,
RL=60Ω, VBAT=12V, VDIR=5V
VDD=5V, VINn(Note 1)=0V/5V,
RL=60Ω, VBAT=12V, VDIR=5V
(Note 1)
=0V/5V,
VDD=5V, VINn
RL=60Ω, VBAT=12V, VDIR=5V,
80% to 20% of VBAT
(Note 1)
=0V/5V,
VDD=5V, VINn
RL=60Ω, VBAT =12V, VDIR=5V,
20% to 80% of VBAT
VDD=5V, VINn(Note 1)=0V/5V,
RL=60Ω, VDIR=5V, VBAT=12V
IDn
(Note 1)
=1mA(output off state)
(Note 1) ” n” shows the channel number.
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BD8LA700EFV-C
Electrical Characteristics(unless otherwise specified, VDDA=VDD=5V, -40°C≤Tj ≤+150°C)
Item
Symbol
Min
Limit values
Typ
Max
Unit
Condition
[Serial Output]
L level output voltage
VSOL
-
0.3
0.6
V
ISO=1mA
H level output voltage
VSOH
VDD-0.6
VDD-0.3
-
V
ISO=-1mA
ISO(OFF)
-5
0
5
μA
IOCP(ON)
0.5
1.2
2.0
A
tOCP
400
1000
2200
μs
Open load relase voltage
VOLD(OFF)
1.2
2.5
3.5
V
Open load detection voltage
VOLD(ON)
1.0
2.0
3.0
V
tOLD
50
150
600
μs
Tjd
-
175
-
℃
Serial out output leak current
[Protect circuit]
Over current detection current
Over current detection time
Open load detection time
TSD detection temperature
(Note 2)
VINn(Note 1)=0V, VDIR=5V
(Note 1) ” n” shows the channel number.
(Note 2) Not 100% tested..
Definition
Figure 1. Definition
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BD8LA700EFV-C
Measurement Circuit
Figure 2. Output ON Resistance Measuring
Circuit Diagram
Figure 3. Switching Time Measuring Circuit
Diagram
Figure 4. Output Clamp Voltage Measuring
Circuit Diagram
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Figure 5. Open Detection Measuring Circuit
Diagram
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BD8LA700EFV-C
DIR(Direct)mode Diagnostic Output Truth Table
VIN
OUTPUT
TSD
mode
VSO
Output state
ID < 0.5A
Normal
L
ON
ID ≥ 0.5 to 2.0A
Over current
detection
H
OFF
-
-
Thermal shut
down
H
OFF
VDS > 3.0V
-
Normal
L
OFF
VDS ≤ 1.0 to
3.0V
-
Open load
detection
H
OFF
VOUT
OFF
-
H
ON
L
-
IOUT
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BD8LA700EFV-C
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1400
1300
1200
1100
1000
RDS(ON) [mΩ]
RDS(ON) [mΩ]
Characteristic Data (Reference Data) (VDD=5V, VDDA=5V, IN=5V, Tj=25°C unless otherwise is specified)
900
800
700
600
500
400
300
200
100
0
-50 -25
0
25
50
75 100 125 150
3.0
3.5
4.0
Tj [°C]
5.0
5.5
6.0
VDDA ,VDD[V]
Figure 6. Output ON Resistance Characteristic
[Temperature Characteristic]
Figure 7. Output ON Resistance Characteristic
[Source Voltage Characteristic]
10.0
10.0
8.0
8.0
6.0
6.0
IDDAS [μA]
IDDS [μA]
4.5
4.0
2.0
4.0
2.0
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD [V]
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VDDA[V]
Figure 8. Standby Current Characteristic (VDD)
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0.0
Figure 9. Standby Current Characteristic (VDDA)
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70.0
20.0
60.0
10.0
50.0
0.0
40.0
-10.0
ICS_B [μA]
IIN [μA]
BD8LA700EFV-C
30.0
-20.0
20.0
-30.0
10.0
-40.0
0.0
-50.0
0
1
2
3
4
VIN [V]
5
6
7
0
2
3
VCS_B
4
[V]
5
6
7
Figure 11. Input current Characteristic (CS_B)
Figure 10. Input current Characteristic
(Note 1)
)
(IN1~4, DIR, SCLK, SI, RST_B, CS_B
5.0
100.0
90.0
4.5
80.0
4.0
70.0
VINH/VINL [V]
60.0
IIN [μA]
1
50.0
40.0
30.0
VINH
3.5
3.0
2.5
2.0
20.0
VINL
1.5
10.0
0.0
1.0
-50 -25
0
25 50
Tj [°C]
75
100 125 150
-50
-25
0
25 50
Tj [°C]
75
100 125 150
Figure 13. Input Voltage Threshold Characteristic
[Temperature Characteristic]
Figure 12. Input current Characteristic
[Temperature Characteristic]
(Note 1)
, VRST_B=5V)
(VIN1 to 4, VSCLK, VSI, VCS_B
(Note 1)DIRMode
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45.0
45.0
40.0
40.0
35.0
35.0
30.0
30.0
tOFF [μs]
tON [μs]
BD8LA700EFV-C
25.0
20.0
25.0
20.0
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
-50
-25
0
25 50
Tj [°C]
75
100 125 150
-50
-25
25 50
Tj [°C]
75
100 125 150
Figure 15. Switching Time (tOFF)
[Temperature Characteristic]
2.0
2.0
1.5
1.5
-dV/dTOFF [V/μs]
dV/dTON [V/μs]
Figure 14. Switching Time (tON)
[Temperature Characteristic]
0
1.0
1.0
0.5
0.5
0.0
0.0
-50
-25
0
25 50
Tj [°C]
75
100 125 150
Figure 16. Slew Rate (at ON)
[Temperature Characteristic]
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-50
-25
0
25 50
Tj [°C]
75
100 125 150
Figure 17. Slew Rate (at OFF)
[Temperature Characteristic]
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Datasheet
10.0
50.0
8.0
40.0
6.0
30.0
IOL [μA]
IL(OFF) [μA]
BD8LA700EFV-C
4.0
20.0
2.0
10.0
0.0
0.0
-50 -25
0
25 50
Tj [°C]
-50 -25
75 100 125 150
75 100 125 150
Timing Chart with Inductive Load
Figure 21. Timing Chart with inductive Load
Figure 20. Switching Time
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25 50
Tj [°C]
Figure 19. Output Leak Current (Open detect)
[Temperature Characteristic]( VDS =40V)
Figure 18. Output Leak Current
[Temperature Characteristic]( VDS=30V)
Switching Time Measurement
0
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BD8LA700EFV-C
I/O Equivalent Circuits
Pin
Symbol
1,2,
11,12
GND
I/O Equivalent Circuits
x9
3 to 10
OUT1 to OUT8
13
VDD
14 to 17
18
20 to 22
IN4(IN8),
IN3(IN7),
IN2(IN6),
IN1(IN5),
DIR,
SCLK(IN4),
RST_B(IN3),
SI(IN2)
x2
IN4(IN8),
IN3(IN7),
IN2(IN6),
IN1(IN5),
DIR,
SCLK(IN4),
RST_B(IN3),
SI(IN2)
50Ω
100kΩ
50Ω
19
SO
VDD
LOGIC
50Ω
23
CS_B
100kΩ
1kΩ
CS_B
100kΩ
GND
24
VDDA
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Datasheet
BD8LA700EFV-C
SPI mode
When CS_B=H,
SO Terminal become Hi-Z
When CS_B=L,
Internal state (TSD, OCP, OLD) is latched at falling edge of CS_B, and output to SO at rising edge of SCLK.
SI is taken in register at falling edge of SCLK.
Output corresponding to each resister input is controlled at rising edge of CS_B.
Definitions of SI and SO signals are shown below.
SI signals
Initial:0x0000
States of output and protective circuits
OCP
TSD
Bits
CHn
15:14,
13:12,
11:10,
9:8,
7:6,
5:4,
3:2,
1:0
00
OFF
disable
disable
disable
01
ON/OFF (Note 1)
enable/disable
enable/disable
disable/enable
10
ON
enable
enable
disable
11
OFF
disable
disable
enable
Output
OLD
(Note 1) When INn=01, output is controlled by IN terminal.
Output controlled by each input is shown below.
Input
Controlled output
IN1(IN5)
OUT1
IN2(IN6)
OUT2
IN3(IN7)
OUT3
IN4(IN8)
OUT4
IN1(IN5)
OUT5
IN2(IN6)
OUT6
IN3(IN7)
OUT7
IN4(IN8)
OUT8
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BD8LA700EFV-C
SO signals
When CS_B=H,
SO Terminal become Hi-Z
When CS_B=L,
Explanation of each Bit is shown below.
Field
Bits
TER
16(Note 1)
OLn
(n = 8 to1 )
Dn
(n = 8 to1 )
15,13,11
9,7,5
3,1
14,12
10,8,6
4,2,0
Data
STATE
0
Correspondence just after reset and normal operation
1
Correspondence error of last time
0
Normal operation
1
Load open
0
Normal operation
1
OCD or TSD
(Note 1) TER bit outputs logical sums of TER signal and input signal of this device with SI signal in the interval from fall of
CS_B to rise of SCLK as shown below.
Block diagram and timing chart are shown below.
In order to select whether TER signal is output or SPI data output (OLn, Dn) signal is output, “S” signal is generated within IC
and output is switched.
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BD8LA700EFV-C
Seroal Daisy Chain
Plurality of devices can be connected as shown in the diagram below.
CS_B signal and SCLK signal connect common signal.
SI/SO line can connect SO of Device 1 to SI of Device 2 as shown in the diagram below.
Timing chart when 8 devices are connected is shown below.
Figure 22. Timing chart when 8 devices are connected
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BD8LA700EFV-C
Parallel Connection
Plurality of devices can be connected to parallel as shown in the diagram below.
SI signal, SCLK signal and SO signal connect common signal.
Each signal is necessary every each device for the CS_B signal.
Device 1
SI
SCLK
MCS_B1
SO
SPI
CS_B
Device 2
SI
MO
MCLK
MCS_B2
SCLK
SO
SPI
CS_B
MI
Timing chart when 2 devices are connected is shown below.
Figure 23. Timing chart when 2 devices are connected
SPI RST_B releasing sequence
Figure 24. RST_B Releasing Sequence
Item
(Note 1) (Note 2)
RST_B lead time
CS_B enable time(Note 1)
Symbol
Min
Typ
Max
Unit
tRST_B (lead)
tCS_B (en)
1
10
-
-
ms
μs
(Note 1) Not 100% tested
(Note 2) RST_B L time and H time must be over 10μs
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SPI timing chart
Figure 25. SPI Timing Chart
Item
SCLK frequency
SCLK cycle length
SCLK high time
SCLK low time
SCLK setup time
SCLK hold time
CS_B lead time
CS_B lag time
Transfer delay time
Data setup time
Data hold time
SPI Output enable time(Note 1)
SPI Output disable time(Note 1)
SPI Output Data delay time(Note 1), (Note 2)
ERR Output Through delay time (Note 1)
Symbol
Min
Typ
Max
Unit
fSCLK
TSCLK(P)
TSCLK(H)
TSCLK(L)
TSCLK(su)
TSCLK(hd)
TCS_B(lead)
TCS_B(lag)
TCS_B(td)
TSI(su)
TSI(hd)
TSO(en)
TSO(dis)
TSO(dd)
TSO(td)
0
200
50
50
50
50
250
250
250
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
200
250
100
200
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
300
300
250
250
200
200
TSO(dd) [ns]
TSO(dd) [ns]
(Note 1) Not 100% tested.
(Note 2) When SO terminal capacity=10pF, 3.0V ≤ VDD ≤ 5.5V. Refer to Figure 25 and Figure 26.
150
150
100
100
50
50
0
0
0
25
50
75
100
SO terminal capacity [pF]
25
50
75
100
SO terminal capacity [pF]
Figure 26. Max of SPI Output Data delay time
(3.0V ≤ VDD < 4.5V)
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Figure 27. Max of SPI Output Data delay time
(4.5V ≤ VDD ≤ 5.5V)
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DIR (direct) mode
Transition to direct mode is brought about by switching DIR terminal to High.
Output controlled for each input is shown below.
Further, SPI input and RST_B input are not accepted during direct mode.
Input Pin
Controlled Output
CS_B(IN1)
OUT1
SI(IN2)
OUT2
RST_B(IN3)
OUT3
SCLK(IN4)
OUT4
IN1(IN5)
OUT5
IN2(IN6)
OUT6
IN3(IN7)
OUT7
IN4(IN8)
OUT8
DIR (direct) mode timing chart (1)
Figure 28. DIR Mode Timing Chart (1)
Item
DIR lead time(Note 1)
INn enable time(Note 1)
Symbol
Min
Typ
Max
Unit
tDIR(lead)
tINn (en)
1
10
-
-
ms
μs
(Note 1) Not 100% tested.
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DIR (direct) mode timing chart (2)
Figure 29. DIR Mode Timing Chart (2)
Direct mode operation current (IDDA + IDD) state transition
All CH off
1CH on
All CH on
(note 1)
All CH off
Figure 30. Operation Current State Transition Diagram
(Note 1) Sum of P.4 VDDA operation current (when all outputs are on) and VDD operation current (when all outputs are on).
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Power source ON/OFF sequence
VDD(7)
VDDA
tON1(1)
DIR
tOFF1(4)
tON2(2)
INn
tOFF2(5)
tON3(3)
tOFF3(6)
(1) tON1 ≥ 0s
(2) tON2 ≥ 1ms
(3) tON3 ≥ 10us
(4) tOFF1 ≥ 0s
(5) tOFF2 ≥ 0s
(6) tOFF3 ≥ 0s
(7) VDD < VDDA+0.3V
Figure 31. Power Source ON/OFF Sequence
VDD(7)
VDDA
RST_B
tON1(1)
tOFF1(4)
tOFF2(5)
tON2(2)
CS_B
(1) tON1 ≥ 0s
(2) tON2 ≥ 1ms
tON3(3)
tOFF3(6)
(3) tON3 ≥ 10us
(4) tOFF1 ≥ 0s
(5) tOFF2 ≥ 0s
(6) tOFF3 ≥ 0s
(7) VDD < VDDA+0.3V
Figure 32. Power Source ON/OFF Sequence (SPI MODE)
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Detection functions
①
Overcurrent protection
When current of no less than 1.2A (Typ) is flown in output transistor of from OUT1 to OUT8 in 1000μs (Typ),
the error flag is output. The error flag is released by OUTENn(Note 1) becoming L(Note 2).
Figure 33. Overcurrent Protection Timing Chart
(Note 1) OUTENn shows the ON/OFF control signal of the OUT terminals.” n” shows the channel number.
(Note 2) The over current detection latch timer is cleared, and the error flag is not output when OUTENn become L before
Over current detection time(Typ:1000μs Max: 2200μs).
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Overheat protection
When Tj of from OUT1 to OUT8 reaches 175°C (Typ) or above and it passes for 30μs(Typ), output is turned off.
The error flag is released by OUTENn(Note 1) becoming L(Note 2).
②
(Note 1) OUTENn shows the ON/OFF control signal of the OUT terminals. n shows the channel number.
(Note 2) The overheat detection latch timer is cleared, and the error flag is not output when OUTENn become L before
Overheat detection time(Typ:30μs Max: 65μs).
Figure 34. Overheat Protection Timing Chart
Open detection
In case of enable at Open detection function(Note 3), when output voltage of from OUT1 to OUT8 falls below 1.5 V (Typ),
open detection is detected and the error flag is output.
③
(Note 3) As for the DIR mode, OLDENn=H(open detection function becomes effective) in OUTENn =L.
40uA (Typ) is flown from OUT to GND because 60kΩ(Typ) is connected between OUT and GND.
As for the SPI mode, Please refer to Page 13.
“n” shows the channel number.
Figure 35. Open Detection Protection Timing Chart
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Thermal resistance (Note 1)
Item
Symbol
Typ
Unit
Condition
42
°C / W
1s
(Note 2)
30
°C / W
2s
(Note 3)
23
°C / W
2s2p
(Note 4)
4
°C / W
1s
(Note 2)
HTSSOP-B24
Junction-Ambient thermal resistance
Junction-Package upper side
parameter
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
①
(Note5)
θJA
thermal characteristic
ΨJT
Based on JESD51 - 2A (Still-Air), in case of 8ch ON state
Based on JESD51 - 3 FR4 114.3 mm x 76.2 mm x 1.57 mm 1 layer (1s)
(TOP Cupper layer : ROHM original land pattern + wiring for measurement, copper thickness 2oz, copper area 600mm2)
Based on JESD51 -5 FR4 114.3 mm x 76.2 mm x 1.60 mm 2 layer(2s)
(TOP Cupper layer : ROHM original land pattern + wiring for measurement, Bottom Cupper area : 74.2 mm x 74.2 mm,
Cupper thickness (Top and Bottom layers) 2oz )
Based on JESD51 -5 / -7 FR4 114.3 mm x 76.2 mm x 1.60 mm 4 layers (2s2p)
(TOP Cupper layer : ROHM original land pattern + wiring for measurement / 2nd, 3rd, Bottom layer Cupper area : 74.2 mm x 74.2 mm,
Cupper thickness(Top and Bottom layers / Internal layers ) 2oz / 1oz)
TT : The central temperature on the surface of molding is measured.
PCB Layout 1s
100mm2
Footprint
600mm2
1200mm2
Figure 36. PCB Layout 1s
Dimension
Board finish thickness
Board dimension
Board material
Copper thickness (Top/Bottom layers)
Heatsink copper area dimension
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Value
1.57 mm ± 10%
76.2 mm x 114.3 mm
FR4
0.070mm (Cu:2oz)
Footprint / 100mm2 / 600mm2 / 1200mm2
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②
PCB Layout 2s
Top Layer
Bottom Layer
Figure 37. PCB Layout 2s
Dimension
Board finish thickness
Board dimension
Board material
Copper thickness (Top/Bottom layers)
Therml vias separation / diameter
③
Cross section
Value
1.60 mm ± 10%
76.2 mm x 114.3 mm
FR4
0.070mm (Cu + Plating)
1.2mm / 0.3mm
PCB Layout 2s2p
TOP Layer
2nd Layer
3rd Layer
Bottom Layer
Cross section
Figure 38. PCB Layout 2s2p
Dimension
Board finish thickness
Board dimension
Board material
Copper thickness (Top/Bottom layers)
Copper thickness (Inner layers)
Therml vias separation / diameter
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Value
1.60 mm ± 10%
76.2 mm x 114.3 mm
FR4
0.070mm (Cu + Plating)
0.035mm
1.2mm / 0.3mm
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④
Thermal impedance (Single pulse)
Figure 39. Thermal impedance
⑤
Thermal resistance (θJA / ΨJT vs PCB copper area - 1s)
Figure 40. Thermal resistance
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Operational Notes
1)
Absolute Maximum Ratings
Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all
destructive situations such as short-circuit modes or open circuit modes. Therefore, it is important to consider circuit
protection measures, like adding a fuse, in case the IC is expected to be operated in a special mode exceeding the
absolute maximum ratings.
2)
Reverse connection of power supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
3)
Power supply lines
Design the PCB layout pattern to provide low impedance ground and supply lines. Separate the ground and supply
lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting
the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of
temperature and aging on the capacitance value when using electrolytic capacitors.
4)
GND Voltage
The voltage of GND pin must be the lowest voltage of all pins of the IC at all operating conditions. Ensure that no pins
are at a voltage below the ground pin at any time, even during transient condition.
5)
Thermal consideration
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions. Consider Pc that does not exceed Pd in actual operating conditions (Pc≥Pd).
6)
Short between pins and mounting errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
7)
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
8)
Thermal shutdown circuit (TSD)
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn off the IC when the internal
temperature of the IC reaches 175°C (25°C hysteresis). It is not designed to protect the IC from damage or guarantee
its operation. Do not continue to operate the IC after this function is activated. Do not use the IC in conditions where
this function will always be activated.
9)
Over voltage protection (active clamp)
There is a built-in over voltage protection circuit (active clamp) to absorb the induced current when inductive load is off
(Power MOS = off). During active clamp and when IN=0V, TSD will not function so keep IC temperature below 150°C.
10)
Over current protection circuit (OCP)
The IC incorporates an over-current protection circuit that operates in accordance with the rated output capacity. This
circuit protects the IC from damage when the load becomes shorted. It is also designed to limit the output current
(without latching) in the event of more than 1.2A (typ) flow, such as from a large capacitor or other component
connected to the output pin. This protection circuit is effective in preventing damage to the IC in cases of sudden and
unexpected current surges. The IC should not be used in applications where the over current protection circuit will be
activated continuously.
11)
Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
12)
Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
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When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
Pin A
+
N
P
N
+
P
P
N
E
Parasitic
N
P+
N
B
P
P substrate
Parasitic element
GND
P
C
+
N
E
P substrate
GND
Parasitic element
GND
Parasitic
GND
Other adjacent elements
Example of monolithic IC structure
13)
14)
GND wiring pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on
the GND voltage. The power supply and ground lines must be as short and thick as possible to reduce line impedance.
Back electromotive force (BEMF)
There is a possibility that the BEMF is changed by using the operating condition, environment and the individual
characteristics of motor. Please make sure there is no problem when operating the IC even though the BEMF is
changed.
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BD8LA700EFV-C
Ordering Information
B
D
8
L
A
7
0
0
E
F
V
Package
EFV: HTSSOP-B24
-
CE2
Product Rank
C:for Automotive
Packaging Specification
E2:Embossed tape and reel
Marking Diagrams
HTSSOP-B24 (TOP VIEW)
Part Number Marking
BD8LA700
LOT Number
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
HTSSOP-B24
<Tape and Reel information>
Tape
Embossed carrier tape (with dry pack)
Quantity
2000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
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Revision History
Date
Rev
16.Dec.2014
002
18.Aug.2015
003
23.May.2016
004
Changes
New Release
P.1 About “Feature”,add a postscript to explanatory note of AEC-Q100.
P.3 About “Absolute Maximum Ratings”, add a postscript to explanatory note of Active
Clamp Energy(repetitive).
P.4 About “Output Sink Current”, change the limit values of Typ & Max.
P.4 About “Output Sink Current” & “Output Leak Current, add a postscript to VDIR condition.
P.12 About “I/O Equivalent Circuits”, add a postscript to pull-down resistance of input
terminal.
P4 About name of Electrical Characteristics items, correct following name.
Before: Output sink current (IL(OFF)) After: Output leak current(IL(OFF))
About Output leak current (Open load detected), correct the limit values.
P17 About Figure26., correct VDD condition.
P22 About Open detection Note of Detection functions, add an explanatory note.
P26 About Operational Notes, correct No.5.
About Operational Notes, correct No.10.
P27 About Ordering Information, correct Package information.
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Notice
Precaution on using ROHM Products
1.
(Note 1)
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
BD8LA700EFV-C - Web Page
Part Number
Package
Unit Quantity
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
BD8LA700EFV-C
HTSSOP-B24
2000
2000
Taping
inquiry
Yes
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