TI1 CDCM6208V1HRGZR 2:8 clock generator, jitter cleaner with fractional divider Datasheet

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CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
CDCM6208 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
Check for Samples: CDCM6208
1 Features
2 Applications
•
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Superior Performance With Low Power:
– Low Noise Synthesizer (265 fs-rms Typical
Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
Typical Jitter)
– 0.5-W Typical Power Consumption
– High Channel-to-Channel Isolation and
Excellent PSRR
– Device Performance Customizable Through
Flexible 1.8-V, 2.5-V and 3.3-V Power
Supplies, Allowing Mixed Output Voltages
Flexible Frequency Planning:
– 4x Integer Down-Divided Differential Clock
Outputs Supporting LVPECL-Like, CML, or
LVDS-Like Signaling
– 4x Fractional or Integer Divided Differential
Clock Outputs Supporting HCSL, LVDS-Like
Signaling, or Eight CMOS Outputs
– Fractional Output Divider Achieve 0 ppm to < 1
ppm Frequency Error and Eliminates Need for
Crystal Oscillators and Other Clock Generators
– Output Frequencies up to 800 MHz
Two Differential Inputs, XTAL Support, Ability for
Smart Switching
SPI, I2C, and Pin Programmable
Professional User GUI for Quick Design
Turnaround
7 × 7 mm 48-VQFN package (RGZ)
–40°C to 85°C Temperature Range
Base Band Clocking (Wireless Infrastructure)
Networking and Data Communications
Micro and Pico Base Stations
Keystone C66x Multicore DSP Clocking
Storage Server, Portable Test Equipment
Medical Imaging, High End A/V
3 Description
The CDCM6208 is a highly versatile, low jitter low
power frequency synthesizer which can generate
eight low jitter clock outputs, selectable between
LVPECL-like high-swing CML, normal-swing CML,
LVDS-like low-power CML, HCSL, or LVCMOS, from
one of two inputs that can feature a low frequency
crystal or CML, LVPECL, LVDS, or LVCMOS signals
for a variety of wireless infrastructure baseband,
Small Cells, wireline data communication, computing,
low power medical imaging and portable test and
measurement applications. The CDCM6208 also
features an innovative fractional divider architecture
for four of its outputs that can generate any frequency
with better than 1ppm frequency accuracy. The
CDCM6208 can be easily configured through I2C or
SPI programming interface and in the absence of
serial interface, pin mode is also available that can
set the device in 1 of 32 distinct pre-programmed
configurations using control pins.
Device Information
DEVICE NAME
PACKAGE
CDCM6208
VQFN (48)
Simplified Schematic
DR
CDCM6208
Synthesizer
Mode
PCIe
Core
Packet
network
SyncE
e
Eth
rne
t
ALT
CORE
FBADC
GPS receiver
1pps
IEEE1588 timing
extract
1pps
RXADC
TXDAC
DPLL
Ethernet
TMS320TCI6616/18
DSP
AIF
7.00 mm × 7.00 mm
Simplified Schematic
Timing
Packet
Accel
BODY SIZE
Server
1
CDCM6208
APLL
RF LO
RF LO
Pico Cell Clocking
SRIO
Base Band DSP
Clocking
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information, Airflow = 0 LFM....................... 7
Thermal Information, Airflow = 150 LFM................... 8
Thermal Information, Airflow = 250 LFM................... 8
Thermal Information, Airflow = 500 LFM................... 8
Single-Ended Input Characteristics (SI_MODE[1:0],
SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2,
SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR,
PDN, SYNCN, REF_SEL).......................................... 9
6.9 Single-Ended Input Characteristics (PRI_REF,
SEC_REF) ................................................................. 9
6.10 Differential Input Characteristics (PRI_REF,
SEC_REF) ............................................................... 10
6.11 Crystal Input Characteristics (SEC_REF) ............ 10
6.12 Single-Ended Output Characteristics (STATUS1,
STATUS0, SDO, SDA) ............................................ 11
6.13 PLL Characteristics.............................................. 11
6.14 LVCMOS Output Characteristics ......................... 12
6.15 LVPECL (High-Swing CML) Output
Characteristics ......................................................... 13
6.16 CML Output Characteristics................................. 13
6.17 LVDS (Low-Power CML) Output Characteristics. 14
6.18 HCSL Output Characteristics............................... 14
6.19 Output Skew and Sync to Output Propagation Delay
Characteristics ......................................................... 15
6.20 Device Individual Block Current Consumption...... 16
6.21 Worst Case Current Consumption ........................ 17
6.22 Timing Requirements, I2C Timing ......................... 17
6.23 Typical Characteristics .......................................... 19
7
8
Parameter Measurement Information ................ 21
Detailed Description ............................................ 26
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
26
26
26
35
51
52
Application and Implementation ........................ 65
9.1 Application Information............................................ 65
9.2 Typical Applications ................................................ 65
10 Power Supply Recommendations ..................... 74
10.1 Power Rail Sequencing, Power Supply Ramp Rate,
and Mixing Supply Domains .................................... 74
10.2 Device Power-Up Timing ...................................... 75
10.3 Power Down.......................................................... 78
10.4 Power Supply Ripple Rejection (PSRR) versus
Ripple Frequency..................................................... 78
11 Layout................................................................... 79
11.1 Layout Guidelines ................................................. 79
11.2 Reference Schematics .......................................... 81
12 Device and Documentation Support ................. 85
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
85
85
85
85
85
85
13 Mechanical, Packaging, and Orderable
Information ........................................................... 85
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2014) to Revision G
Page
•
Changed Handling Ratings table to ESD Ratings .................................................................................................................. 6
•
Added Table 7 ..................................................................................................................................................................... 38
•
Added Table 10 ................................................................................................................................................................... 43
Changes from Revision E (March 2013) to Revision F
Page
•
Changed layout of data sheet to conform to new TI standards. Added the following sections: Handling Ratings,
Thermal Information, Typical Characteristics, Programming, Register Maps, Layout and Layout Guidelines ..................... 1
•
Changed from zero to one ................................................................................................................................................... 53
•
Added text at the end of the first paragraph in Power Down section .................................................................................. 78
•
Changed fOUT = 122.88 MHz, VDD Supply Noise = 100 mVpp............................................................................................ 78
2
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SCAS931G – MAY 2012 – REVISED JANUARY 2018
Changes from Revision D (March 2013) to Revision E
Page
•
Changed the data sheet layout to the new TI standard ......................................................................................................... 1
•
Added the Handling Ratings table .......................................................................................................................................... 6
•
Changed Pullup and Pulldown value From: MIN = 40 To: 35 kΩ and MAX = 60 To: 65 kΩ ................................................ 9
•
Changed the from Random Jitter, Maximum in Table 2 From: 10k - 20MHZ To: 12k - 20MHZ and From: 0.5 ps-rms
(int div) To: 0.3 ps-rms (int div) ............................................................................................................................................ 27
•
Added new Note 1 to Table 2............................................................................................................................................... 27
Changes from Revision C (September 2012) to Revision D
Page
•
Changed the Description of pin VDD_PRI_REF .................................................................................................................... 4
•
Changed the Description of pin VDD_SEC_REF ................................................................................................................... 4
•
Changed Figure 35............................................................................................................................................................... 33
•
Changed Table 6 - Note 2 and row 10 - 0x1C, PinMode 29-V1, fout(Y7) From: 33.33 To: 44.44....................................... 36
•
Changed Table 8 - Note 2 and row 10 - 0x13, PinMode 20-V2, fout(Y7) From: 25 To: 12.5 .............................................. 40
•
Changed text in the PLL lock detect section From: "1/1000 th of the input reference frequency" To: "1/1000 th of the
PFD update frequency" ........................................................................................................................................................ 45
•
Changed text in the PLL lock detect section From: "approximately 1000 input clock cycles" To: "approximately 1000
PFD update clock cycles" ..................................................................................................................................................... 45
•
Changed Figure 60, From: PDN held Low To: RESETN held low....................................................................................... 76
•
Changed Equation 4............................................................................................................................................................. 78
Changes from Revision B (August 2012) to Revision C
Page
•
Changed Table 39, 2:0 DIE_REVISION Description............................................................................................................ 63
•
Added text "Example: SERDES link with KeyStone™ I DSP" ............................................................................................. 66
Changes from Revision A (June 2012) to Revision B
Page
•
Editorial changes made throughout the data sheet................................................................................................................ 1
•
Changed the Description of pin VDD_PRI_REF .................................................................................................................... 4
•
Changed the Description of pin VDD_SEC_REF ................................................................................................................... 4
•
Added Table Note 1 to the description of pin 44. ................................................................................................................... 6
•
Added Note to the Preventing false output frequencies in SPI/I2C mode at startup: section.............................................. 34
•
Changed the NOTE following Table 12................................................................................................................................ 45
•
Added Note to the I2C SERIAL INTERFACE section........................................................................................................... 49
•
Deleted text "All outputs PECL (Y4:0) and LVDS (Y7:4)." from the Conclusion statement ................................................. 69
•
Changed the text in the OUTPUT MUX on Y4 and Y5 section............................................................................................ 73
•
Changed the text in item 1 of the Staggered CLK output powerup for power sequencing of a DSP section...................... 73
•
Changed the first paragraph in the Power Down section..................................................................................................... 78
•
Changed the first paragraph in the Power Supply Ripple Rejection (PSRR) versus Ripple Frequency section ................. 78
Changes from Original (May 2012) to Revision A
Page
•
Changed the device From: Product Preview To: Production ................................................................................................. 1
•
Section Header From: RESTN, PWR, SYNC To: RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]..................... 9
•
Changed the RPULLUP parametres From: RPULLUP - Input Pullup Resistor To: R - Input Pullup and Pulldown Resistor ......... 9
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SCAS931G – MAY 2012 – REVISED JANUARY 2018
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5 Pin Configuration and Functions
27
VDD_Y4
11
26
Y4_P
12
25
Y4_N
VDD _Y0_Y1
Y2_P
VDD_SECI_REF
SEC_REFN
VDD_Y2_Y3
VDD_Y7
37
10
SEC_REFP
24
Y5_N
VDD_SEC_REF
VDD_Y2_Y3
28
VDD_Y6
VDD_PLL1
38
9
23
Y5_P
PRI_REFN
Y3_P
29
VDD_Y5
VDD_PLL2
39
8
22
VDD_Y5
PRI_REFP
Y3_N
30
Y2_N
7
21
VDD_Y6
VDD_PRI_REF
20
31
19
Y6_P
6
VDD_Y2_Y3
32
REF_SEL
VDD_Y0_Y1
Y6_N
18
33
5
17
4
SCL/PIN4
Y1_P
SCS/AD1/PIN3
16
VDD_Y7
Y0_N
34
Y1_N
3
15
SDO/AD0/PIN2
14
Y7_P
Y0_P
Y7_N
35
13
36
2
VDD_Y0_Y1
1
VDD_PRI_REF
SI_MODE0
SDI/SDA/PIN1
VDD_Y4
REG_CAP
VDD_VCO
40
ELF
41
42
PDN
RESETN/PWR
44
SYNCN
STATUS1/PIN0
45
43
SI_MODE1
STATUS0
46
DVDD
48
DVDD
47
RGZ Package
48-Pin VQFN
(Top View)
Pin Functions
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
PRI_REFP
8
Input
Universal
Primary Reference Input +
PRI_REFN
9
Input
Universal
Primary Reference Input –
VDD_PRI_REF
7
PWR
Analog
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V,
or connected to VDD_SEC_REF.
SEC_REFP
11
Input
Universal
Secondary Reference Input +
SEC_REFN
12
Input
Universal
Secondary Reference Input –
VDD_SEC_REF
10
PWR
Analog
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V,
or connected to VDD_PRI_REF (1).
Manual Reference Selection MUX for PLL. In SPI or I2C mode the
reference selection is also controlled through Register 4 bit
12.REF_SEL = 0 (≤ VIL): selects PRI_REFREF_SEL = 1 (≥ VIH):
selects SEC_REF (when Reg 4.12 = 1). See Table 5 for detail.
REF_SEL
6
Input
LVCMOS
with 50-kΩ pullup
ELF
41
Output
Analog
External loop filter pin for PLL
Y0_P
14
Output
Universal
Output 0 Positive Pin
Y0_N
15
Output
Universal
Output 0 Negative Pin
Y1_P
17
Output
Universal
Output 1 Positive Pin
Y1_N
16
Output
Universal
Output 1 Negative Pin
(1)
4
If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.
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Pin Functions (continued)
PIN
NAME
VDD_Y0_Y1
(2 pins)
I/O
NO.
13, 18
TYPE
DESCRIPTION
PWR
Analog
Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V, or 3.3 V
Y2_P
20
Output
Universal
Output 2 Positive Pin
Y2_N
21
Output
Universal
Output 2 Negative Pin
Y3_P
23
Output
Universal
Output 3 Positive Pin
Y3_N
22
Output
Universal
Output 3 Negative Pin
PWR
Analog
Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V, or 3.3 V
VDD_Y2_Y3
(2 pins)
19, 24
Y4_P
26
Output
Universal
Output 4 Positive Pin
Y4_N
25
Output
Universal
Output 4 Negative Pin
VDD_Y4
27
PWR
Analog
Supply pin for output 4 to set between 1.8 V, 2.5 V, or 3.3 V
Y5_P
29
Output
Universal
Output 5 Positive Pin
Y5_N
28
Output
Universal
Output 5 Negative Pin
VDD_Y5
30
PWR
Analog
Supply pin for output 5 to set between 1.8 V, 2.5 V, or 3.3 V
Y6_P
32
Output
Universal
Output 6 Positive Pin
Y6_N
33
Output
Universal
Output 6 Negative Pin
VDD_Y6
31
PWR
Analog
Supply pin for output 6 to set between 1.8 V, 2.5 V, or 3.3 V
Y7_P
35
Output
Universal
Output 7 Positive Pin
Y7_N
36
Output
Universal
Output 7 Negative Pin
VDD_Y7
34
PWR
Analog
Supply pin for output 7 to set between 1.8 V, 2.5 V, or 3.3 V
VDD_VCO
39
PWR
Analog
Analog power supply for PLL/VCO; This pin is sensitive to power
supply noise; The supply of this pin and the VDD_PLL2 supply pin
can be combined as they are both analog and sensitive supplies;
VDD_PLL1
37
PWR
Analog
Analog Power Supply Connections
VDD_PLL2
38
PWR
Analog
Analog Power Supply Connections; This pin is sensitive to power
supply noise; The supply of VDD_PLL2 and VDD_VCO can be
combined as these pins are both power-sensitive, analog supply pins
DVDD
48
PWR
Analog
Digital Power Supply Connections; This is also the reference supply
voltage for all control inputs and must match the expected input
signal swing of control inputs.
PAD
PWR
Analog
Power Supply Ground and Thermal Pad
GND
STATUS0
46
Output
LVCMOS
Status pin 0 (see Table 12 for details)
STATUS1/PIN0
45
Output and
Input
LVCMOS
no pull resistor
STATUS1: Status pin in SPI/I2C modes. For details, see Table 10 for
pin modes and Table 12 for status mode. PIN0: Control pin 0 in pin
mode.
SI_MODE1
47
Input
LVCMOS
with 50-kΩ pullup
Serial Interface Mode or Pin mode selection. SI_MODE[1:0]=00: SPI
mode; SI_MODE[1:0]=01: I2C mode; SI_MODE[1:0]=10: Pin Mode
(No serial programming); SI_MODE[1:0]=11: RESERVED
SI_MODE0
1
LVCMOS
with 50-kΩ
pulldown
2
I/O
LVCMOS in
Open drain out
LVCMOS in
no pull resistor
SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write
bidirectional), open-drain output; requires a pullup resistor in I2C
mode; PIN1: Control pin 1 in pin mode
SDO/AD0/PIN2
3
LVCMOS out
LVCMOS in
Output/Input
LVCMOS in
no pull resistor
SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 input; PIN2:
Control pin 2 in pin mode
SCS/AD1/PIN 3
4
Input
LVCMOS no pull
resistor
SCS: SPI Latch EnableAD1: I2C Address Offset Bit 1 input; PIN3:
Control pin 3 in pin mode
SCL/PIN4
5
Input
LVCMOS no pull
resistor
SCL: SPI/I2C ClockPIN4: Control pin 4 in pin mode
SDI/SDA/PIN1
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Pin Functions (continued)
PIN
NAME
I/O
NO.
TYPE
DESCRIPTION
RESETN/PWR
44
Input
LVCMOS
with 50-kΩ pullup
In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed
through SPI while RESETN is held low (this is useful to avoid any
false output frequencies at power up). (2)
In Pin mode this pin controls device core and I/O supply voltage
setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power
supply voltage. In pin mode, it is not possible to mix and match the
supplies. All supplies should either be 1.8 V or 2.5/3.3 V.
REG_CAP
40
Output
Analog
Regulator Capacitor; connect a 10-µF cap with ESR below 1 Ω to
GND at frequencies above 100 kHz
PDN
43
Input
LVCMOS
with 50-kΩ pullup
Power Down Active low. When PDN = VIH is normal operation.
When PDN = VIL, the device is disabled and current consumption
minimized. Exiting power down resets the entire device and defaults
all registers. It is recommended to connect a capacitor to GND to
hold the device in power-down until the digital and PLL related
power supplies are stable. See section on power down in the
application section.
SYNCN
42
Input
LVCMOS
with 50-kΩ pullup
Active low. Device outputs are synchronized on a low-to-high
transition on the SYNCN pin. SYNCN held low disables all outputs.
(2)
Note: the device cannot be programmed in I2C while RESETN is held low.
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD_PRI, VDD_SEC,
VDD_Yx_Yy,
Supply voltage
VDD_PLL[2:1], DVDD
–0.5
4.6
V
VIN
–0.5
4.6
AND
V DVDD+ 0.5
V
Input voltage for CMOS control inputs
4.6
AND
Input voltage for PRI/SEC inputs
VOUT
Output voltage
IIN
IOUT
VVDDPRI.SEC+
0.5
VYxYy+ 0.5
V
Input current
20
mA
Output current
50
mA
TJ
Junction temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
–0.5
V
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
VESD (1)
(1)
(2)
(3)
6
Electrostatic discharge
Human Body Model (HBM) ESD Stress Voltage
(2)
Charged Device Model (CDM) ESD Stress Voltage (3)
±2000
±500
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD_Yx_Yy
Output supply voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PLL1,
VDD_PLL2
Core analog supply voltage
1.71
1.8/2.5/3.3
3.465
V
DVDD
Core digital supply voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PRI,
VDD_SEC
Reference input supply voltage
1.71
1.8/2.5/3.3
3.465
V
ΔVDD/Δt
VDD power-up ramp time (0 to 3.3 V) PDN left open,
all VDD tight together PDN low-high is delayed (1)
TA
Ambient Temperature
50 < tPDN
ms
–40
85
°C
DVDD = 1.8 V
–0.5
2.45
V
DVDD = 3.3 V
–0.5
3.965
V
SDA and SCL in I2C Mode (SI_MODE[1:0] = 01)
VI
Input voltage
100
400
dR
Data rate
VIH
High-level input voltage
VIL
Low-level input voltage
CBUS_I2C
Total capacitive load for each bus line
(1)
kbps
0.7 × DVDD
V
0.3 × DVDD
V
400
pF
For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.
For slower power-up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,
VDD_PLLx, and VDD_PRI/SEC reach at least 1.45-V supply voltage. See application section on mixing power supplies and particularly
Figure 59 for details.
6.4 Thermal Information, Airflow = 0 LFM (1) (2) (3) (4)
CDCM6208
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
30.27
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.58
°C/W
RθJB
Junction-to-board thermal resistance
6.83
°C/W
ψJT
Junction-to-top characterization parameter
0.23
°C/W
ψJB
Junction-to-board characterization parameter
6.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.06
°C/W
(1)
(2)
(3)
(4)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3-mm diameter).
θJB (junction to board) is used for the VQFN package, the main heat flow is from the junction to the GND pad of the VQFN.
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6.5 Thermal Information, Airflow = 150 LFM (1) (2) (3) (4)
CDCM6208
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
0.37
°C/W
ψJB
Junction-to-board characterization parameter
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.06
°C/W
(1)
(2)
(3)
(4)
21.8
°C/W
—
°C/W
6.61
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3-mm diameter).
θJB (junction to board) is used for the VQFN package, the main heat flow is from the junction to the GND pad of the VQFN.
6.6 Thermal Information, Airflow = 250 LFM (1) (2) (3) (4)
CDCM6208
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
19.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
°C/W
RθJB
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
0.45
°C/W
ψJB
Junction-to-board characterization parameter
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.06
°C/W
(1)
(2)
(3)
(4)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3-mm diameter).
θJB (junction to board) is used for the VQFN package, the main heat flow is from the junction to the GND pad of the VQFN.
6.7 Thermal Information, Airflow = 500 LFM (1) (2) (3) (4)
CDCM6208
THERMAL METRIC
(1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
ψJT
ψJB
RθJC(bot)
(1)
(2)
(3)
(4)
8
17.7
°C/W
—
°C/W
Junction-to-board thermal resistance
6.58
°C/W
Junction-to-top characterization parameter
0.58
°C/W
Junction-to-board characterization parameter
—
°C/W
Junction-to-case (bottom) thermal resistance
1.05
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3-mm diameter).
θJB (junction to board) is used for the VQFN package, the main heat flow is from the junction to the GND pad of the VQFN.
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6.8
SCAS931G – MAY 2012 – REVISED JANUARY 2018
Single-Ended Input Characteristics (SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4,
SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL)
DVDD = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 ×
DVDD
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
DVDD = 3.465V, VIH = 3.465 V
(pullup resistor excluded)
IIL
Input low current
DVDD = 3.465V, VIL= 0 V
ΔV/ΔT
PDN, RESETN, SYNCN, REF_SEL
input edge rate
20% – 80%
minPulse
PDN, RESETN, SYNCN low pulse
to trigger proper device reset
C IN
Input capacitance
V
0.2 ×
DVDD
V
30
µA
–30
µA
0.75
V/ns
10
ns
2.25
pF
RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]
R
Input pullup and pulldown resistor
SDA and SCL in I
2
35
DVDD = 1.8 V
VHYS_I2C
Input hysteresis
DVDD = 2.5/3.3 V
IH
High-level input current
VI = DVDD
VOL
Output low voltage
IOL= 3 mA
CIN
Input capacitance pin
6.9
50
65
kΩ
C Mode (SI_MODE[1:0]=01)
0.1 VDVDD
V
0.05
V
VDVDD
–5
5
µA
0.2 ×
DVDD
V
5
pF
Single-Ended Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
fIN
Reference and bypass input
frequency
VIH
Input high voltage
VIL
Input low voltage
VHYST
Input hysteresis
IIH
Input high current
IIL
ΔV/ΔT
MAX
UNIT
VDD_PRI/SEC = 1.8 V
TEST CONDITIONS
0.008
MIN
TYP
200
MHz
VDD_PRI/SEC = 3.3 V
0.008
250
MHz
0.8 ×
VDD_PRI/
VDD_SEC
V
0.2 ×
VDD_PRI/
VDD_SEC
150
mV
VDD_PRI/VDD_SEC = 3.465 V, VIH
= 3.465 V
30
µA
Input low current
VDD_PRI/VDD_SEC = 3.465 V, VIL
=0V
–30
µA
Reference input edge rate
20% – 80%
0.75
f PRI ≤ 200 MHz
40%
60%
200 ≤ fPRI ≤ 250 MHz
43%
60%
IDC SE
Reference input duty cycle
C IN
Input capacitance
20
65
V
V/ns
2.25
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9
CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
6.10
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Differential Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.008
250
MHz
fIN
Reference and bypass input
frequency
VI
Differential input voltage swing,
peak-to-peak
VDD_PRI/SEC = 2.5/3.3 V
0.2
1.6
VPP
VDD_PRI/SEC = 1.8 V
0.2
1
VPP
VICM
Input common-mode voltage
CML input signaling, R4[7:6] = 00
VDD_PRI/
VDD_SEC
-0.4
VDD_PRI/
VDD_SEC
-0.1
V
VICM
Input common-mode voltage
LVDS, VDD_PRI/SEC
= 1.8/2.5/3.3 V,
R4[7:6] = 01, R4.1 = d.c.,
R4.0 = d.c.
0.8
1.5
V
VHYST
Input hysteresis
LVDS (Q4[7:6,4:3] = 01)
15
65
mVpp
CML (Q4[7:6,4:3] = 00)
20
85
mVpp
30
µA
IIH
Input high current
VDD_PRI/SEC = 3.465 V,
VIH = 3.465 V
IIL
Input low current
VDD_PRI/SEC = 3.465V, VIL = 0 V
ΔV/ΔT
Reference input edge rate
20% – 80%
IDCDIFF
Reference input duty cycle
CIN
Input capacitance
6.11
1.2
–30
0.75
µA
V/ns
30%
70%
2.7
pF
Crystal Input Characteristics (SEC_REF)
VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
Mode of oscillation
Frequency
Equivalent Series Resistance (ESR)
On-chip load capacitance
Drive level
(1)
(2)
(3)
(4)
(5)
(6)
10
TYP
MAX
UNIT
Fundamental
See note
(1)
10
30.72
MHz
See note
(2)
30.73
50
MHz
10 MHz
150 (3)
25 MHz
70 (4)
50 MHz
30 (5)
1.8-V / 3.3-V SEC_REFP
3.5
4.5
5.5
1.8-V SEC_REFN
5.5
7.25
8.5
3.3-V SEC_REFN
6.5
7.34
8.5
See note
(6)
200
Ω
pF
µW
Verified with crystals specified for a load capacitance of CL = 8 pF, the PCB related capacitive load was estimated to be 2.3 pF, and
completed with a load capacitors of 4 pF on each crystal pin connected to GND. XTALs tested: NX3225GA 10MHz EXS00A-CG02813
CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA 30.72MHz
EXS00A-CG02812 CRG.
For 30.73 MHz to 50 MHz, TI recommends to verify sufficient negative resistance and initial frequency accuracy with the crystal vendor.
The 50-MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the best
choice of the XTAL was one with CL = 7 pF instead of CL = 8 pF.
With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin)
With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin)
With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin)
Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW
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6.12
SCAS931G – MAY 2012 – REVISED JANUARY 2018
Single-Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465
V; TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Output high voltage
Status 1, Status 0, and SDO only;
SDA is open drain and relies on
external pullup for high output; IOH =
1 mA
VOL
Output low voltage
IOL = 1 mA
Vslew
Output slew rate
30% – 70%
IOZH
3-state output high current
DVDD = 3.465 V, VIH = 3.465 V
IOZL
3-state output low current
DVDD = 3.465 V, VIL = 0 V
tLOS
Status loss of signal detection time
LOS_REFfvco
tLOCK
6.13
Status PLL lock detection time
MIN
TYP
MAX
UNIT
0.8 ×
DVDD
V
0.2 ×
DVDD
0.5
V/ns
1
Detect lock
5
µA
–5
µA
2
1/f PFD
2304
Detect unlock
V
1/f PFD
512
PLL Characteristics
VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
fVCO
KVCO
VCO frequency range
VCO gain
fPFD
PFD input frequency
ICP-L
High impedance mode charge pump
leakage
fFOM
Estimated PLL figure of merit (FOM)
tSTARTUP
Start-up time (see Figure 60)
TEST CONDITIONS
MIN
TYP
MAX
V1
2.39
2.55
V2
2.94
3.13
V1, 2.39 GHz
178
V1, 2.50 GHz
204
V1, 2.55 GHz
213
V2, 2.94 GHz
236
V2, 3.00 GHz
250
V2, 3.13 GHz
283
0.008
Measured in-band phase noise at
the VCO output minus 20log(Ndivider) at the flat region
UNIT
GHz
MHz/V
100
MHz
±700
nA
–224
dBc/Hz
12.8
ms
12.85
ms
Power supply ramp time of 1ms from
0 V to 1.7 V, final frequency
accuracy of 10 ppm, fPFD = 25 MHz,
CDCM6208 pin mode use case #2,
CPDN_to_GND = 22 nF
with PRI input signal
with NDK 25 MHz crystal
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CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
6.14
www.ti.com
LVCMOS Output Characteristics
VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
fOUT-F
Output frequency
TEST CONDITIONS
MIN
Fract out divVDD_Yx_Yy = 2.5/3.3 V
0.78
250
Integer out divVDD_Yx_Yy = 2.5/3.3 V
1.55
250
0.78/1.5
200
–1
1
Int or frac out divVDD_Yx_Yy = 1.8 V
(1)
fACC-F
Output frequency error
Fractional output divider
VOH
Output high voltage (normal
mode)
VDD_Yx = min to max,
IOH = -1 mA
VOL
Output low voltage (normal
mode)
VDD_Yx = min to max,
IOL = 100 µA
VOH
Output high voltage (slow
mode)
VDD_Yx = min to max,
IOH = -100 µA
VOL
Output low voltage (slow
mode)
VDD_Yx = min to max,
IOL = 100 µA
IOH
Output high current
TYP
MAX
0.8 ×
VDD_Y
x_Yy
UNIT
MHz
ppm
V
0.2 ×
VDD_Y
x_Yy
0.7 ×
VDD_Y
x_Yy
V
V
0.3 ×
VDD_Y
x_Yy
V
V OUT = VDD_Yx_Yy/2
Normal mode
–50
–8
mA
Slow mode
–45
–5
mA
10
55
mA
5
40
mA
V OUT = VDD_Yx_Yy/2
IOL
Output low current
Normal mode
Slow mode
Output rise/fall slew rate
(normal mode)
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL = 5 pF
5.37
V/ns
Output rise/fall slew rate
(normal mode)
20% to 80%, VDD_Yx_Yy = 1.8 V, CL = 5 pF
2.62
V/ns
Output rise/fall slew rate
(slow mode)
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, CL = 5 pF
4.17
V/ns
Output rise/fall slew rate
(slow mode)
20% to 80%, VDD_Yx_Yy = 1.8 V, CL = 5 pF
1.46
V/ns
PN-floor
Phase noise floor
fOUT = 122.88 MHz
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
V OUT = VDD_Yx/2
tSLEW-RATE-N
tSLEW-RATE-S
(1)
12
–159.5
45%
154 dBc/Hz
55%
Normal mode
30
50
90
Slow mode
45
74
130
Ω
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple 1 over 220, the actual output frequency error is 0.
Note: In LVCMOS Mode, positive and negative outputs are in phase.
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6.15
SCAS931G – MAY 2012 – REVISED JANUARY 2018
LVPECL (High-Swing CML) Output Characteristics
VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625
V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
Integer Output Divider
MIN
TYP
MAX
CDCM6208V1
1.55
800
CDCM6208V2
1.91
800
fOUT-I
Output frequency
VCM-DC
Output DC-coupled common- DC coupled with 50-Ω external termination to
mode voltage
VDD_Yx_Yy
VDD_Yx_Yy – 0.4
UNIT
MHz
V
100-Ω diff load AC coupling (see Figure 12),
fOUT ≤ 250 MHz
1.71 V ≤ VDD_Yx_Yy ≤ 1.89 V
|VOD|
Differential output voltage
2.375 V ≤ VDD_Yx_Yy ≤ 3.465 V
0.45
0.75
1.12
V
0.6
0.8
1.12
V
100-Ω diff load AC coupling (see Figure 12), fOUT ≥
250
1.71 V ≤ VDD_Yx_Yy ≤ 1.89 V
0.73
2.375 V ≤ VDD_Yx_Yy ≤ 3.465 V
VOUT
Differential output peak-topeak voltage
tR/tF
Output rise/fall time
tslew
Output rise/fall slew rate
PN-floor
Phase noise floor
VDD_Yx_Yy = 3.3 V (see Figure 54)
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
Measured from pin to VDD_Yx_Yy
6.16
0.55
0.75
|V
±200 mV around crossing point
2×
OD|
109
20% to 80% VOD
V
1.12
V
217
ps
7.3
V/ns
211
3.7
5.1
–161.4
47.5%
V
ps
–155.8 dBc/Hz
52.5%
50
Ω
CML Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375V to 2.625 V, 3.135 V to 3.465
V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
Integer output divider
MIN
TYP
MAX
V1
1.55
800
V2
1.91
800
UNIT
fOUT-I
Output frequency
VCM-AC
Output AC-coupled commonAC-coupled with 50-Ω receiver termination
mode voltage
VDD_Yx_Yy –
0.46
V
VCM-DC
Output DC-coupled common- DC-coupled with 50-Ω on-chip termination to
mode voltage
VDD_Yx_Yy
VDD_Yx_Yy –
0.2
V
|VOD|
Differential output voltage
VOUT
Differential output peak-topeak voltage
tR/tF
Output rise/fall time
20% to 80%
PN-floor
Phase noise floor at > 5-Hz
offset
fOUT = 122.88 MHz
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
Measured from pin to VDD_Yx_Yy
100-Ω diff load AC coupling (see Figure 12)
0.3
0.45
0.58
2 × |V
OD|
MHz
V
V
VDDYx = 1.8 V
100
151
300
ps
VDDYx = 2.5 V/3.3 V
100
143
200
ps
VDD_Yx_Yy = 1.8 V
–161.2-
–155.8 dBc/Hz
VDD_Yx_Yy = 3.3 V
161.2
–153.8 dBc/Hz
47.5%
52.5%
50
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CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
6.17
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LVDS (Low-Power CML) Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465
V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CDCM6208V1
1.55
400
CDCM6208V2
1.91
400
UNIT
fOUT-I
Output frequency
Integer output divider
fOUT-F
Output frequency
Fractional output divider
0.78
400
MHz
fACC-F
Output frequency error (1)
Fractional output divider
–1
1
ppm
VCM-AC
Output AC-coupled commonAC-coupled with 50-Ω receiver termination
mode voltage
VDD_Yx_Yy –
0.76
V
VCM-DC
Output DC-coupled common- DC-coupled with 50-Ω on-chip termination to
mode voltage
VDD_Yx_Yy
VDD_Yx_Yy –
0.13
V
|VOD|
Differential output voltage
VOUT
Differential output peak-topeak voltage
tR/tF
Output rise/fall time
±100 mV around crossing point
PN-floor
Phase noise floor
fOUT= 122.88 MHz
100-Ω diff load AC coupling (see Figure 12)
0.34
0.454
2×
|V OD|
V
V
300
ps
VDD_Yx = 1.8 V
–159.3
–154.5 dBc/Hz
VDD_Yx = 2.5/3.3 V
–159.1
–154.9 dBc/Hz
Y[3:0]
47.5%
Y[7:4]
45%
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
Measured from pin to VDD_Yx_Yy
(1)
0.247
MHz
52.5%
55%
167
Ω
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple of 1 over 220, the actual output frequency error is 0.
6.18
HCSL Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V,
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V1
1.55
400
V2
1.91
400
UNIT
fOUT-I
Output frequency
Integer output divider
fOUT-F
Output frequency
Fractional output divider
0.78
400
MHz
fACC-F
Output frequency error (1)
Fractional output divider
–1
1
ppm
VCM
Output common-mode
voltage
VDD_Yx_Yy = 2.5/3.3 V
0.2
0.34
0.55
V
VDD_Yx_Yy = 1.8 V
0.2
0.33
0.55
V
|VOD|
Differential output voltage
VDD_Yx_Yy = 2.5/3.3 V;
0.4
0.67
1
V
|VOD|
Differential output voltage
VDD_Yx_Yy = 1.8 V
0.4
0.65
1
V
Differential output peak-topeak voltage
VDD_Yx_Yy = 2.5/3.3 V
2.1
V
Differential output peak-topeak voltage
VDD_Yx_Yy = 1.8 V
tR/tF
Output rise/fall time
Measured from VDIFF= –100 mV to VDIFF = +100mV,
VDD_Yx_Yy = 2.5/3.3 V
100
167
250
ps
tR/tF
Output rise/fall time
Measured from VDIFF= –100 mV to VDIFF= +100 mV,
VDD_Yx_Yy = 1.8 V
120
192
295
ps
PN-floor
Phase noise floor
fOUT = 122.88 MHz
ODC
Output duty cycle
Not in bypass mode
VOUT
(1)
14
1
|V
2×
OD|
MHz
V
VDD_Yx_Yy = 1.8 V
–158.8
–153 dBc/Hz
VDD_Yx = 2.5/3.3 V
–157.6
–153 dBc/Hz
45%
55%
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a ½ 20multiple, the actual output frequency error is 0.
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SCAS931G – MAY 2012 – REVISED JANUARY 2018
6.19 Output Skew and Sync to Output Propagation Delay Characteristics
VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
V1: f VCO= 2.5 GHz
tPD-PS
Propagation delay SYNCN↑
to output toggling high
V2: f VCO= 3 GHz
ΔtPD-PS
Part-to-part propagation
delay variation SYNCN↑ to
output toggling high (1)
MIN
TYP
PS_A=4
9
10.5
11 1/f PS_A
PS_A=5
9
10.2
11 1/f PS_A
PS_A=6
9
10.0
11 1/f PS_A
PS_A=4
10
10.9
12 1/f PS_A
PS_A=5
9
10.5
11 1/f PS_A
PS_A=6
9
10.2
11 1/f PS_A
0
1 1/f PS_A
Fixed supply voltage, temp, and device setting (1)
MAX
UNIT
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OUTDIV = 4
tSK,LVDS
Skew between Y[7:4] LVDS
Y[7:4] = LVDS
40
ps
tSK,LVDS
Skew between Y[3:0] LVDS
Y[3:0] = LVDS
40
ps
tSK,LVDS
Skew between Y[7:0] LVDS
Y[7:0] = LVDS
80
ps
tSK,CML
Skew between Y[3:0] CML
Y[3:0] = CML
40
ps
tSK,PECL
Skew between Y[3:0] PECL
Y[3:0] = LVPECL
40
ps
tSK,HCSL
Skew between Y[7:4] HCSL
Y[7:4] = HCSL
40
ps
tSK,SE
Skew between Y[7:4] CMOS
Y[7:4] = CMOS
50
ps
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OUTDIV = 4
tSK,CMOS-LVDS
Skew between Y[7:4] LVDS
and CMOS mixed
Y[4] = CMOS, Y[7:5] = LVDS
2.5
ns
tSK,CMOS-PECL
Skew between Y[7:0] CMOS
and LVPECL mixed
Y[7:4] = CMOS, Y[3:0] = LVPECL
2.5
ns
tSK,PECL-LVDS
Skew between Y[3:0]
LVPECL and LVDS mixed
Y[0] = LVPECL, Y[3:1] = LVDS
120
ps
tSK,PECL-CML
Skew between Y[3:0]
LVPECL and CML mixed
Y[0] = LVPECL, Y[3:1] = CML
40
ps
tSK,LVDS-PECL
Skew between Y[7:0] LVDS
and LVPECL mixed
Y[7:4] = LVDS, Y[3:0] = LVPECL
180
ps
tSK,LVDS-HCSL
Skew between Y[7:4] LVDS
and HCSL mixed
Y[4] = LVDS, Y[7:5] = HCSL
250
ps
200
ps
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OUTDIV = 3.125
tSK,DIFF, frac
(1)
Skew between Y[7:4] LVDS
using all fractional divider
with the same divider setting
Y[7:4] = LVDS
SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).
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6.20 Device Individual Block Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output
Types = LVPECL/CML/LVDS/LVCMOS/HCSL
BLOCK
CONDITION
Core
TYPICAL CURRENT CONSUMPTION (mA)
CDCM6208 Core, active mode, PS_A = PS_B = 4
75
CML output, AC-coupled with 100-Ω diff load
24.25
LVPECL, AC-coupled with 100-Ω diff load
40
LVCMOS output, transient, 'C L' load, 'f' MHz output
frequency, 'V' output swing
Output Buffer
1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3
LVDS output, AC-coupled with 100-Ω diff load
Output Divide Circuitry
19.7
HCSL output, 50-Ω load to GND on each output pin
31
Integer Divider Bypass (Divide = 1)
3
Integer Divide Enabled, Divide > 1
8
Fractional Divider Enabled
12
additional current when PS_A differs from PS_B
15
Total Device, CDCM6208
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
11. Output divider ratio = 5
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384 MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz,
125 MHz, 50 MHz)
Total Device, CDCM6208
Power Down (PDN = '0')
(excl. I termination_resistors)
(1.8 V: 251 mA
2.5 V: 254 mA
3.3 V: 257 mA)
(incl. I termination_resistors)
(1.8 V: 310 mA
2.5 V: 313 mA
3.3 V: 316 mA)
0.35
Helpful Note: The CDCM6208 User GUI does an excellent job estimating the total device current consumption
based on the actual device configuration. Therefore, TI recommends using the GUI to estimate device power
consumption.
The individual supply pin current consumption for Pin mode P23 was measured to come out the following:
Customer EVM
Table 1. Individual Supplies Measured
16
PWR PIN 39 = GND
VPRI = 1.8 V
VOUT = 1.8 V
Y0-1
Y2-3
Y4
Y5
Y6
Y7
61 mA
40 mA
21 mA
29 mA
30 mA
31 mA
SEC
(VSEC = 1.8V)
SEC
(VSEC = 2.5V)
12 mA
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PRI
PLL1
PLL2
70 mA
VCO
DVDD
Total
1.5 mA
295.5
mA
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6.21 Worst Case Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA = T-40 °C to 85 °C, Output Types =
maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation
BLOCK
Total Device, CDCM6208
CONDITION
CURRENT CONSUMPTION TYP / MAX
All conditions over PVT, AC-coupled outputs with all
outputs terminated, device configuration:
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
11. Output divider ratio = 5
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384
MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100MHz, 66.66
MHz, 125 MHz, 50 MHz)
1.8 V: 310 mA / +21% (excl term)
3.3 V: 318 mA / +21% (excl term)
6.22 Timing Requirements, I2C Timing
PARAMETER
STANDARD MODE
MIN
MAX
0
100
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA
low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL Low-pulse duration
tw(SCLH)
SCL High-pulse duration
4
FAST MODE
MIN
MAX
0
400
UNIT
kHz
4.7
0.6
μs
4
0.6
μs
4.7
1.3
μs
0.6
μs
(1)
th(SDA)
SDA hold time (SDA valid after SCL low)
0
tsu(SDA)
SDA setup time
250
tr-in
SCL / SDA input rise time
1000
300
ns
tf-in
SCL / SDA input fall time
300
300
ns
tf-out
SDA output fall time from VIH min to VIL max
with a bus capacitance from 10 pF to 400 pF
250
250
ns
tsu(STOP)
STOP setup time
tBUS
tglitch_filter
(1)
3.45
0
0.9
100
μs
ns
4
0.6
μs
Bus free time between a STOP and START
condition
4.7
1.3
μs
Pulse width of spikes suppressed by the
input glitch filter
75
300
75
300
ns
The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge
of SCL.
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STOP
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ACK
START
tW(SCLL) tW(SCLH)
tr(SM)
STOP
tf(SM)
~
~
VIH(SM)
SCL
~
~
VIL(SM)
th(START)
tSU(START)
tBUS
tr(SM)
tSU(SDATA)
th(SDATA)
tf(SM)
tSU(STOP)
~
~
~
~
VIH(SM)
SDA
~
~
VIL(SM)
Figure 1. I2C Timing Diagram
For additional information, refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208 meets
the switching characteristics for standard mode and fast mode transfer.
18
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6.23 Typical Characteristics
Figure 2. Typical Device Output Phase Noise and Jitter for
25 MHz
Figure 3. Typical Device Output Phase Noise and Jitter for
312.5 MHz
Figure 4. Fractional Divider Bit Selection Impact on Jitter
(fFRAC = 300 MHz)
Figure 5. Fractional Divider Input Frequency Impact on Jitter
(Using Divide by x.73 Example)
200 ps-pp
200
all zero, (0) typ
MSB, (1/2) typ
180 ps-pp
180
MSB-1, (1/4) typ
160 ps-pp
MSB-9, (1/1024) typ
MSB-3, (1/16) typ
140 ps-pp
MSB-4, (1/32) typ
MSB-6, (1/128) typ
100 ps-pp
MSB-7, (1/256) typ
MSB-9, (1/1024) typ
80 ps-pp
Jitter
MSB-5, (1/54) typ
120 ps-pp
Jitter
MSB-9, (1/1024) max
160
MSB-2, (1/8) typ
140
MSB-4, (1/32) max
120
MSB-13, (1/16384) max
MSB-13, (1/16384) typ
100
LSB, (1/1048576) max
80
LSB, (1/1048576) typ
MSB-13, (1/16384) typ
60 ps-pp
LSB, (1/1048576) typ
0x50A33D (÷x.315) typ
40 ps-pp
60
MSB, (1/2) max
MSB, (1/2) typ
40
0x828F5 (÷x.51) typ
20 ps-pp
0xBAE14 (÷x.73) typ
0 ps-pp
200 220 240 260 280 300 320
340 360 380
all zero, (0) max
20
0
200
400
250
Frequency (MHz)
300
350
400
Frequency (MHz)
Figure 6. Fractional Divider Bit Selection Impact on TJ
(Typical)
Figure 7. Fractional Divider Bit Selection Impact on TJ
(Maximum Jitter Across Process, Voltage and Temperature)
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Typical Characteristics (continued)
0
156.25MHz output using 60Hz Loop
Bandwidth; Clock source is ok to be noisy,
as CDCM6208 filters the jitter out of the
noisy source; RJ=1.2ps-rms (12k-20MHz)
-20
Noise (dB/Hz)
-40
-60
156.25 MHZ
with 60 Hz BW
-80
156.25 MHZ
closed loop
-100
-120
156.25MHz output using 300kHz
bandwidth; Clock source needs to
be clean (e.g. XTAL source)
RJ=265fs-rms
-140
-160
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
Figure 8. Phase Noise Plot for Jitter Cleaning Mode (Blue) and Synthesizer Mode (Green)
20
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7 Parameter Measurement Information
This section describes the characterization test setup of each block in the CDCM6208.
High impedance probe
CDCM6208
LVCMOS
Oscilloscope
5pF
Figure 9. LVCMOS Output AC Configuration During Device Test (VOH, VOL, tSLEW)
High impedance probe
CDCM6208
LVCMOS
Oscilloscope
1mA
High impedance probe
VDD_Yx
1mA
CDCM6208
Oscilloscope
LVCMOS
Figure 10. LVCMOS Output DC Configuration During Device Test
CDCM6208
LVCMOS
50
Phase Noise/
Spectrum
Analyzer
Figure 11. LVCMOS Output AC Configuration During Device Phase Noise Test
50 O
YP
CDCM6208
50
YN
50
Set to one of the following signaling
levels: LVPECL, CML, LVDS
50
Balun
Phase Noise/
Spectrum
Analyzer
Figure 12. LVDS, CML, and LVPECL Output AC Configuration During Device Test
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Parameter Measurement Information (continued)
High impedance differential probe
HCSL
CDCM6208
Oscilloscope
HCSL
50
50
Figure 13. HCSL Output DC Configuration During Device Test
HCSL
CDCM6208
Balun
HCSL
50
Phase Noise/
Spectrum
50
Analyzer
50
Figure 14. HCSL Output AC Configuration During Device Test
Offset = VDD_PRI/SEC/2
LVCMOS
Signal
Generator
CDCM6208
50
Figure 15. LVCMOS Input DC Configuration During Device Test
CML
Signal
Generator
CDCM6208
CML
50
50
VDD_PRI/SEC
Figure 16. CML Input DC Configuration During Device Test
22
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Parameter Measurement Information (continued)
LVDS
Signal
Generator
CDCM6208
100
LVDS
Figure 17. LVDS Input DC Configuration During Device Test
LVPECL
Signal
Generator
CDCM6208
LVPECL
50
50
VDD_PRI/SEC - 2
Figure 18. LVPECL Input DC Configuration During Device Test
VDD_PRI/SEC
100
Signal
Generator
100
CDCM6208
Differential
100
100
Figure 19. Differential Input AC Configuration During Device Test
Crystal
CDCM6208
Figure 20. Crystal Reference Input Configuration During Device Test
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Parameter Measurement Information (continued)
Sine wave
Modulator
Signal
Generator
Reference
Input
CDCM6208
Device Output
50
Balun
Phase Noise/
Spectrum
50
Analyzer
Balun
Phase Noise/
Spectrum
50
Analyzer
50
Figure 21. Jitter Transfer Test Setup
Sine wave
Modulator
Power Supply
Signal
Generator
Reference
Input
CDCM6208
Device Output
50
50
Figure 22. PSNR Test Setup
Yx_P
VOD
Yx_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 23. Differential Output Voltage and Rise and Fall Time
24
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Parameter Measurement Information (continued)
80%
VOUT,SE
OUT_REFx/2
20%
tR
tF
Figure 24. Single-Ended Output Voltage and Rise and Fall Time
VCXO_P
Single Ended
VCXO_P
Differential
VCXO_N
tPD,DIFF
Yx_P
Differential, Integer Divide
Yx_N
tSK,DIFF,INT
Yx_P
Differential, Integer Divide
Yx_N
tSK,DIFF,FRAC
Yx_P
Differential, Fractional Divide
Yx_N
tSK,SE-DIFF,INT
Single Ended, Integer Divide
Yx_P/N
tPD, SE
tSK,SE,INT
Yx_P/N
Single Ended, Integer Divide
tSK,SE,FRAC
Single Ended, Fractional Divide
Yx_P/N
Figure 25. Differential and Single-Ended Output Skew and Propagation Delay
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8 Detailed Description
8.1 Overview
In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp
on output using integer dividers and is between 50 to 220 ps-pp on outputs using fractional dividers depending
on the prescaler output frequency.
In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output
using integer dividers and is less than 70 to 240 ps-pp on outputs using fractional dividers. The CDCM6208 is
packaged in a small 48-pin, 7-mm × 7-mm VQFN package.
8.2 Functional Block Diagram
REF_SEL
ELF
Fractional Div
20-b
Y4
LVDS/
LVCMOS/
HCSL
Y5
Fractional Div
20-b
Smat MUX
Y0
Differential/
LVCMOS PRI_REF
R
4-b
Differential
LVCMOS/ SEC_REF
XTAL
M
14-b
PreScaler PS_A
÷4, ÷5, ÷6
Y2
VCO:
V1: (2.39-2.55) GHz
and V2: (2.94-3.13) GHz
PreScaler PS_B
÷4, ÷5, ÷6
PLL
Control
Status/
Monitoring
Y1
-
N
8-b,10-b
Input
Host
Interface
Integer Div
8-b
LVPECL/
CML/
LVDS
Integer Div
8-b
Y3
Fractional Div
20-b
Y6
Fractional Div
20-b
Y7
LVDS/
LVCMOS/
HCSL
Power
Conditioning
Output
CDCM6208
8.3 Feature Description
Supply Voltage: The CDCM6208 supply is internally regulated. Therefore, each core and I/O supply can be
mixed and matched in any order according to the application needs. The device jitter performance is independent
of supply voltage.
Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and
VCO that operates from 2.39 GHz to 2.55 GHz (CDCM6208V1) and 2.94 GHz to 3.13 GHz (CDCM6208V2).
Reference inputs: The primary and secondary reference inputs support differential and single ended signals
from 8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is
a 4-bit reference divider available on the primary reference input. The input mux between the two references
supports simply switching or can be configured as Smart MUX and supports glitchless input switching.
Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the
output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent
prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then
be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an
output MUX. A total of 2 output MUXes are available.
Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz.
The charge pump gain is programmable and the loop filter consists of internal + partially external passive
components and supports bandwidths from a few Hz up to 400 kHz.
26
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Feature Description (continued)
Phase Noise: The Phase Noise performance of the device can be summarized to:
Table 2. Synthesizer Mode (Loop Filter BW >250 kHz)
RANDOM JITTER (ALL OUTPUTS)
TYPICAL
(1)
(2)
TOTAL JITTER
MAXIMUM
MAXIMUM
10k-20MHz
12k-20MHz
10k-100MHz
0.27 ps-rms (Integer division)
0.7ps-rms (fractional div)
0.3 ps-rms (int div) (1)
0.625 ps-rms (int div)
Integer divider
DJ-unbound
RJ 10k-20MHz
20 ps-pp
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
50-220 ps-pp,
see Figure 30
(2)
Integrated Phase Noise (12kHz - 20 MHz) for 156.25 MHz output clock measured at room temperature using a 25 MHz Low Noise
reference source
TJ = 20 pspp applies for LVPECL, CML, and LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over
PVT.
Table 3. Jitter Cleaner Mode (Loop Filter BW < 1 kHz)
RANDOM JITTER (ALL OUTPUTS)
TYPICAL
TOTAL JITTER
MAXIMUM
MAXIMUM
10k-20MHz
10k-20MHz
10k-100MHz
Integer divider
DJ unbound
RJ 10k-20MHz
1.6 ps-rms (Integer division)
2.3 ps-rms (fractional div) 10k-20MHz
2.1 ps-rms (int div)
2.14 ps-rms (int div)
40 ps-pp
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
70-240 ps-pp,
see Figure 30
Spurious Performance: The spurious performance is as follows:
• Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
• Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential
signaling level operated at 122.88 MHz output frequency in the Nyquist range.
Device outputs:
The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML),
low-swing CML (LVDS like), HCSL, and LVCMOS signaling.
Table 4. Supported Output Formats and Frequency Ranges
Outputs
LVPECL
CML
LVDS
Y[3:0]
X
X
X
Y[7:4]
X
HCSL
X
LVCMOS
X
OUTPUT DIVIDER
FREQUENCY
RANGE
Integer only
1.55 - 800 MHz
Integer
1.55 - 800 MHz
Fractional
1.00 - 400 MHz
Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b
fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is
typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to
control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.
Device Configuration: 32 distinct pin modes are available that cover many common use cases without the need
for any serial programming of the device. For maximum flexibility the device also supports SPI and I2C
programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.
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10G
PHY
DPLL
CDCM6208
Synthesizer
Mode
PCIe
1G
PHY
DDR
4x10G Ethernet ASIC
10G
PHY
10G
PHY
10G
PHY
10G
PHY
10GbE
Figure 26. Typical Use Case: CDCM6208 Example in Wireless Infrastructure Baseband Application
8.3.1 Typical Device Jitter
Figure 27. Typical Device Output Phase Noise and Jitter
for 25 MHz
28
Figure 28. Typical Device Output Phase Noise and Jitter
for 312.5 MHz
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0
156.25MHz output using 60Hz Loop
Bandwidth; Clock source is ok to be noisy,
as CDCM6208 filters the jitter out of the
noisy source; RJ=1.2ps-rms (12k-20MHz)
-20
Noise (dB/Hz)
-40
-60
156.25 MHZ
with 60 Hz BW
-80
156.25 MHZ
closed loop
-100
-120
156.25MHz output using 300kHz
bandwidth; Clock source needs to
be clean (e.g. XTAL source)
RJ=265fs-rms
-140
-160
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
Figure 29. Phase Noise Plot for Jitter Cleaning Mode (Blue) and Synthesizer Mode (Green)
8.3.2 Universal Input Buffer (PRI_REF, SEC_REF)
The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require
external termination schemes. The secondary input buffer also supports crystal inputs and Crystal Input
Characteristics (SEC_REF) provides the characteristics of the crystal that can be used. Both inputs incorporate
hysteresis.
8.3.3 VCO Calibration
The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of
the CDCM6208 must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.
Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.
While transparent to the user, the CDCM6208 and the host system perform the following steps comprising a
VCO calibration sequence:
1. Normal Operation – When the CDCM6208 is in normal (operational) mode, the state of both the power
down pin (PDN) and reset pin (RESETN) is high.
2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset via the PDN pin, through the RESETN pin, or
by removing and restoring device power. Pulling either of these pins low places the device in the reset state.
Holding either pin low holds the device in reset.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated via the host interface. Exiting the reset state occurs automatically after
power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.
Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device
register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device
retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration
for a frequency plan other than the default state (that is, the device calibrates the VCO based on the settings
contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is
low. Writing this bit to a high state and then returning it to the low state invokes a device reset without
restoring device defaults.
4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The CDCM6208 calibrates the VCO. During the calibration routine, the device holds all
outputs in reset so that the CDCM6208 generates no spurious clock signals.
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8.3.4 Reference Divider (R)
The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the
Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets
the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed
as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.
8.3.5 Input Divider (M)
The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is
operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to
the PLL and should be in the range of 8 kHz to 100 MHz.
8.3.6 Feedback Divider (N)
The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider
(1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to
800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to
100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper
operation.
8.3.7 Prescaler Dividers (PS_A, PS_B)
The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to
the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes
the PLL as it also drives the input of the Feedback Divider (N).
8.3.8 Phase Frequency Detector (PFD)
The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output
that is dependent on the phase and frequency difference between the two inputs. The allowable range of
frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.
8.3.9 Charge Pump (CP)
The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or
discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then
converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range
of the charge pump current is from 500 µA to 4 mA.
8.3.10 Fractional Output Divider Jitter Performance
The fractional output divider jitter performance is a function of the fraction output divider input frequency as well
as actual fractional divide setting itself. To minimize the fractional output jitter, TI recommends using the least
number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 30,
the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits
in the middle range of the fractional divider are selected.
30
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Figure 31. Fractional Divider Input Frequency Impact on
Jitter (Using Divide by x.73 Example)
Figure 30. Fractional Divider Bit Selection Impact on Jitter
(fFRAC = 300 MHz)
200 ps-pp
200
all zero, (0) typ
MSB, (1/2) typ
180 ps-pp
180
MSB-1, (1/4) typ
160 ps-pp
MSB-9, (1/1024) typ
MSB-3, (1/16) typ
140 ps-pp
MSB-4, (1/32) typ
MSB-6, (1/128) typ
100 ps-pp
MSB-7, (1/256) typ
MSB-9, (1/1024) typ
80 ps-pp
Jitter
MSB-5, (1/54) typ
120 ps-pp
Jitter
MSB-9, (1/1024) max
160
MSB-2, (1/8) typ
140
MSB-4, (1/32) max
120
MSB-13, (1/16384) max
MSB-13, (1/16384) typ
100
LSB, (1/1048576) max
80
LSB, (1/1048576) typ
MSB-13, (1/16384) typ
60 ps-pp
40 ps-pp
LSB, (1/1048576) typ
60
0x50A33D (÷x.315) typ
40
MSB, (1/2) max
MSB, (1/2) typ
0x828F5 (÷x.51) typ
20 ps-pp
0xBAE14 (÷x.73) typ
0 ps-pp
200 220 240 260 280 300 320
340 360 380
all zero, (0) max
20
0
200
400
250
Frequency (MHz)
300
350
400
Frequency (MHz)
Figure 32. Fractional Divider Bit Selection Impact on TJ
(Typical)
Figure 33. Fractional Divider Bit Selection Impact on TJ
(Maximum Jitter Across Process, Voltage and
Temperature)
Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The RJ impact on TJ is
estimated for a BERT 10(-12) – 1. This measurement result is overly pessimistic, as it does not bandwidth limit the
high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX
PLL bandwidth of typically bit rate divided by 10.
8.3.11 Device Block-Level Description
The CDCM6208 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input
interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider.
Completing the CDCM6208 device are the combination of integer and fractional output dividers, and universal
output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the regulated
supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the
digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the external
power supply rail with a PSNR of better than –50 dB at all frequencies. The regulator capacitor pin REG_CAP
should be connected to ground by a 10 µF capacitor with low ESR (for example, below 1-Ω ESR) to ensure
stability.
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8.3.12 Device Configuration Control
Figure 35 illustrates the relationships between device states, the control pins, device initialization and
configuration, and device operational modes. In pin mode, the state of the control pins determines the
configuration of the device for all device states. In programming mode, the device registers are initialized to their
default state and the host can update the configuration by writing to the device registers.
A system may transition a device from pin mode to host connected mode by changing the state of the SI_MODE
pins and then triggering a device power cycle by toggling the PDN input pin (high-low-high); however, outputs will
be disabled during the transition as the device registers are initialized to the host mode default state.
8.3.13 Configuring the RESETN Pin
Figure 34 shows two typical applications examples of the RESETN pin and usage of the PWR pin in Pin Mode.
DVDD
DVDD
50k
GPO
DVDD
50k
#44 (RESET)
50k
#44 (RESET)
#44 (PWR)
RPD
5k
Host
Controller
CDCM6208
CDCM6208
CDCM6208
if I/O power = 1.8V: RPD=0-Ohm
if I/O power=3.3V: RPD=open
(a) (SPI/I2C Host mode)
(b) (SPI/I2C Host Mode)
(c) (PIN Mode)
Figure 34. RESETN/PWR Pin Configurations
Figure 34 (a) SPI / I2C mode only: shows the RESETN pin connected to a digital device that controls device
reset. The resistor and capacitor combination ensure reset is held low even if the CDCM6208 is powered up
before the host controller output signal is valid.
Figure 34 (b) SPI / I2C mode only: shows a configuration in which the user wishes to introduce a delay between
the time that the system applies power to the device and the device exiting reset. If the user does not use a
capacitor, then the device effectively ignores the state of the RESETN pin.
Figure 34 (c) Pin mode only: shows a configuration useful if the device is used in Pin Mode. Here device pin
number 44 becomes the PWR input. An external pull down resistor can be used to pull this pin down. If the
resistor is not installed, the pin is internally pulled high.
Figure 35 shows how the different possible device configurations and when the VCO becomes calibrated and the
outputs turn on and off.
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Power on
Reset
no
PDN =1?
(all outputs are disabled)
SI_MODE1
SI_MODE0
01
00
I2C Mode
(activate I2C IF)
10
no
RESETN =1?
Pin Mode
SPI Mode
(activate SPI IF)
Decode PIN0 to PIN4,
and PWR input states
Enter Pin Mode specified by
the PINx and PWR
load device registers with defaults; registers
are customer programmable through serial IF
wait for selected reference input
signal (PRI/SEC) to become valid
no
Configure all device settings
wait for selected reference
input signal (PRI/SEC) to
become valid
Calibrate VCO
Calibrate VCO
no
Disable
all
outputs
Disable
all
outputs
RESETN =1?
no
SYNCN =1?
SYNCN =1?
Synchronize outputs
Enable outputs
Synchronize outputs
Enable all outputs
Normal device operation in
PIN mode
Normal device operation in
HOST mode
SYNCN=1?
SYNCN=1?
Disable
all
outputs
no
no
no
yes
yes
RESETN=1?
PDN=1?
PDN=1?
Disable
all
outputs
Figure 35. Device Power Up and Configuration
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8.3.14 Preventing False Output Frequencies in SPI/I2C Mode at Start-Up
Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency.
Holding RESET low at power-up until the device is fully configured keeps all outputs disabled. The device
calibrates automatically after RESET becomes released and starts out with the desired output frequency.
DVDD
Release
RESETGPO
50k
50k
RESET=low
RESET=high
CDCM6208
Step 1
Register
Space
outputs on
SPI or I2C
Master
Register
Space
DVDD
GPO
SPI/I2C
SPI or I2C
Master
outputs off
Configure
Registers
0 to 21
SPI/I2C
NOTE
The RESETN pin cannot be held low during I2C communication. Instead, use the SYNCN
pin to disable the outputs during an I2C write operation, and toggle RESETN pin
afterwards. Alternatively, other options exist such as using the RESETN bit in the register
space to disable outputs until the write operation is complete.
CDCM6208
Step 2
Figure 36. Reset Pin Control During Register Loading
8.3.15 Input MUX and Smart Input MUX
The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register).
The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes
are suppressed at the MUX output.
Table 5. Input MUX Selection
SI_MODE1
PIN NO. 47
REGISTER 4 BIT 13
SMUX_MODE_SEL
REGISTER 4 BIT 12
SMUX_REF_SEL
REF_SEL
PIN NO. 6
0
X
X
0
0 (SPI/I2C mode)
1
1
1
1 (pin mode)
34
not available
1
SELECTED INPUT
Auto Select Priority is given to Primary
Reference input.
Primary input
Secondary input
input select through
SPI/I2C
0
Primary input
1
Secondary input
0
Primary or Auto (see Table 6)
1
Secondary or Auto (see Table 6)
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external pin
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Example 1: An application desired to auto-select the clock reference in SPI/I2C mode. During production testing
however, the system needs to force the device to use the primary followed by the secondary input. The settings
would be as follows:
1. Tie REF_SEL pin always high
2. For primary clock input testing, use R4 [13:12] = 10
3. For secondary clock input testing, set R4 [13:12] = 11.
4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00
Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case,
program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.
SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux
(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.
Switching behavior: The input clocks can have any phase. When switching happens between one input clock to
the other, the phase of the output clock slowly transitions to the phase of the newly selected input clock. There
will be no-phase jump at the output. The phase transition time to the new reference clock signal depends on the
PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF. The
timing diagram of an auto-switch at the input MUX is shown in Figure 37.
Figure 37. Smart Input MUX Auto-Switch Mode Timing Diagram
8.4 Device Functional Modes
8.4.1 Control Pins Definition
In the absence of a host interface, the CDCM6208 can be powered up in one of 32 pre-configured settings when
the pins are SI_MODE[1:0] = 10. The CDCM6208 has 5 control pins identified to achieve commonly used
networking frequencies, and change output types. The Smart Input MUX for the PLL is set in most configurations
to manual mode in pin mode. Based on the control pins settings for the on-chip PLL, the device generates the
appropriate frequencies and appropriate output signaling types at start-up. In the case of the PLL loop filter, "JC"
denotes PLL bandwidths of ≤ 1 kHz and "Synth" denotes PLL bandwidths of ≥ 100 kHz.
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SI_MODE[1:0]
pin[4:0]
UseCase
fin(PRI_REF)
Type
fin(SEC_REF)
Type
REF_SEL (note 2)
f(PFD)
f(VCO)
fout(Y0)
Type
fout(Y1)
Type
fout(Y2)
Type
fout(Y3)
Type
fout(Y4)
Type
fout(Y5)
Type
fout(Y6)
Type
fout(Y7)
Table 6. Pre-Configured Settings of CDCM6208V1 Accessible by PlN[4:0] (1) (2)
Type
00
I/O
SPI Default
25
LVDS
25
Crystal
MANU
25
2500
156.25
CML
156.25
CML
125.00
LVDS
125.00
LVDS
66.66
LVDS
66.66
LVDS
100.00
LVDS
100.00
LVDS
01
I/O
I2C Default
25
LVDS
25
Crystal
MANU
25
2500
156.25
CML
156.25
CML
125.00
LVDS
125.00
LVDS
66.66
LVDS
66.66
LVDS
100.00
LVDS
100.00
LVDS
11
RESERVED
10
0x00
PinMode 1-V1
25
LVDS
25
Crystal
MANU
25
2400
100
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVDS
10
0x01
PinMode 2-V1
25
LVDS
25
Crystal
MANU
25
2400
100
PECL
100
PECL
100
PECL
100
PECL
100
HCSL
100
HCSL
100
HCSL
100
HCSL
10
0x02
PinMode 3-V1
25
LVDS
25
Crystal
MANU
25
2400
100
CML
100
CML
100
CML
100
CML
100
LVDS
100
LVDS
100
LVDS
100
LVDS
10
0x03
PinMode 4-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
10
0x04
PinMode 5-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
PECL
156.25
PECL
156.25
PECL
156.25
PECL
156.25
HCSL
156.25
HCSL
156.25
HCSL
156.25
HCSL
10
0x05
PinMode 6-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
CML
156.25
CML
156.25
CML
156.25
CML
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
10
0x06
PinMode 7-V1
25
LVDS
25
Crystal
MANU
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVDS
10
0x07
PinMode 8-V1
25
LVDS
25
Crystal
MANU
25
2500
125
PECL
125
PECL
125
PECL
125
PECL
125
HCSL
125
HCSL
125
HCSL
125
HCSL
10
0x08
PinMode 9-V1
25
LVDS
25
Crystal
MANU
25
2500
125
CML
125
CML
125
CML
125
CML
125
LVDS
125
LVDS
125
LVDS
125
LVDS
10
0x09
PinMode 10-V1
25
LVDS
25
Crystal
MANU
25
2500
125
LVDS
125
LVDS
156.25
LVDS
156.25
LVDS
100
LVDS
100
LVDS
133.33
LVDS
25
LVDS
10
0x0A
PinMode 11-V1
25
LVDS
25
Crystal
MANU
25
2500
312.5
PECL
312.5
PECL
312.5
PECL
312.5
PECL
312.5
HCSL
312.5
HCSL
312.5
HCSL
312.5
HCSL
10
0x0B
PinMode 12-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
PECL
156.25
PECL
100
PECL
100
PECL
156.25
HCSL
156.25
HCSL
100
HCSL
100
HCSL
10
0x0C
PinMode 13-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
PECL
156.25
PECL
156.25
PECL
156.25
PECL
125
HCSL
125
HCSL
125
HCSL
125
HCSL
10
0x0D
PinMode 14-V1
25
LVDS
25
Crystal
MANU
25
2400
200
PECL
200
PECL
100
PECL
100
PECL
100
HCSL
100
HCSL
200
HCSL
200
HCSL
10
0x0E
PinMode 15-V1
25
LVDS
25
Crystal
MANU
25
2500
500
PECL
500
PECL
250
PECL
250
PECL
125
HCSL
125
HCSL
100
HCSL
25
CMOS
10
0x0F
PinMode 16-V1
25
LVDS
25
Crystal
MANU
25
2500
625
PECL
625
PECL
312.5
PECL
312.5
PECL
156.25
HCSL
156.25
HCSL
125
HCSL
25
CMOS
10
0x10
PinMode 17-V1
30.72
LVDS
30.72
Crystal
MANU
30.72
2457.6
122.88
PECL
122.88
PECL
153.6
PECL
153.6
PECL
30.72
CMOS
153.6
HCSL
61.44
HCSL
122.88
CMOS
10
0x11
PinMode 18-V1
24.8832
LVDS
24.8832
Crystal
MANU
24.8832
2488.32
622.08
CML
622.08
CML
622.08
CML
622.08
CML
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
10
0x12
PinMode 19-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
LVDS
156.25
LVDS
125
LVDS
125
LVDS
66.67
LVDS
25
CMOS
25
LVDS
100
LVDS
10
0x13
PinMode 20-V1
0.008
CMOS
0.008
CMOS
MANU
0.008
2500
156.25
LVDS
156.25
PECL
125
LVDS
125
LVDS
125
CMOS
25
LVDS
100
HCSL
100
HCSL
10
0x14
PinMode 21-V1
25
LVDS
25
Crystal
MANU
25
2500
100
LVDS
100
LVDS
156.25
LVDS
156.25
LVDS
122.88
LVDS
30.72
LVDS
66.67
LVDS
153.6
LVDS
10
0x15
PinMode 22-V1
25
LVDS
25
Crystal
MANU
25
2500
100
PECL
100
PECL
156.25
PECL
156.25
PECL
100
HCSL
100
HCSL
100
HCSL
100
HCSL
10
0x16
PinMode 23-V1
25
LVDS
25
Crystal
MANU
25
2500
100
PECL
100
PECL
156.25
PECL
156.25
PECL
100
HCSL
100
HCSL
156.25
HCSL
100
HCSL
10
0x17
PinMode 24-V1
25
LVDS
25
Crystal
MANU
25
2500
125
PECL
125
PECL
100
PECL
100
PECL
100
HCSL
100
HCSL
100
HCSL
100
HCSL
10
0x18
PinMode 25-V1
25
LVDS
25
Crystal
MANU
25
2500
100
PECL
100
PECL
156.25
PECL
156.25
PECL
100
HCSL
100
HCSL
155.52
HCSL
155.52
HCSL
10
0x19
PinMode 26-V1
25
LVDS
25
Crystal
MANU
25
2500
156.25
PECL
156.25
PECL
100
PECL
100
PECL
125
HCSL
156.26
HCSL
212.5
HCSL
106.25
HCSL
10
0x1A
PinMode 27-V1
25
LVDS
25
Crystal
MANU
25
2500
100
PECL
100
PECL
250
PECL
250
PECL
100
HCSL
100
HCSL
100
HCSL
125
HCSL
(1)
(2)
36
The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be "mixed and matched" as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8 V or 2.5/3.3 V supply. Exception: inputs configured
for LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44.
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: CDCM6208
CDCM6208
www.ti.com
SCAS931G – MAY 2012 – REVISED JANUARY 2018
REF_SEL (note 2)
f(PFD)
f(VCO)
fout(Y0)
Type
fout(Y1)
Type
fout(Y2)
Type
fout(Y3)
Type
25
LVDS
25
Crystal
MANU
25
2500
100
PECL
100
PECL
250
PECL
250
PECL
10
0x1C
PinMode 29-V1
10
CMOS
10
Crystal
AUTO
10
2400
25
LVDS
25
LVDS
80
LVDS
80
LVDS
100
LVDS
10
0x1D
PinMode 30-V1
25
CMOS
25
Crystal
MANU
25
2500
100
LVDS
100
LVDS
125
LVDS
125
LVDS
33.33
CMOS
10
0x1E
PinMode 31-V1
30.72
LVDS
30.72
LVDS
MANU
30.72
2500
156.25
PECL
156.25
PECL
156.25
PECL
156.25
PECL
100
LVDS
10
0x1F
PinMode 32-V1
25
LVDS
off
off
MANU
25
2500
125
CML
125
CML
125
CML
125
CML
100
Type
100
HCSL
Type
fout(Y7)
fin(SEC_REF)
Type
PinMode 28-V1
fout(Y6)
fin(PRI_REF)
Type
0x1B
fout(Y5)
pin[4:0]
UseCase
10
fout(Y4)
SI_MODE[1:0]
Table 6. Pre-Configured Settings of CDCM6208V1 Accessible by PlN[4:0](1)(2) (continued)
Type
100
HCSL
Type
125
HCSL
66.67
HCSL
50
LVDS
66.67
CMOS
66.67
LVDS
44.44
CMOS
50
CMOS
25
100
CMOS
LVDS
25
CMOS
25
LVDS
CMOS
66.67
LVDS
125
LVDS
50
LVDS
Alternative pin mode usage by modifying input frequencies:
10
0x01
PinMode 2-V1
26.5625
LVDS
26.5625
Crystal
MANU
26.5625
2550
106.25
PECL
106.25
PECL
106.25
PECL
106.25
PECL
106.25
HCSL
106.25
HCSL
106.25
HCSL
106.25
HCSL
10
0x02
PinMode 3-V1
26.5625
LVDS
26.5625
Crystal
MANU
26.5625
2550
106.25
CML
106.25
CML
106.25
CML
106.25
CML
106.25
LVDS
106.25
LVDS
106.25
LVDS
106.25
LVDS
10
0x03
PinMode 4-V1
24
LVDS
24
Crystal
MANU
24
2400
150
LVDS
150
LVDS
150
LVDS
150
LVDS
150
LVDS
150
LVDS
150
LVDS
150
LVDS
10
0x03
PinMode 4-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
10
0x03
PinMode 4-V1
24.8832
LVDS
24.8832
Crystal
MANU
24.8832
2488.32
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
10
0x04
PinMode 5-V1
24
LVDS
24
Crystal
MANU
24
2400
150
PECL
150
PECL
150
PECL
150
PECL
150
HCSL
150
HCSL
150
HCSL
150
HCSL
10
0x04
PinMode 5-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
153.6
PECL
153.6
PECL
153.6
PECL
153.6
PECL
153.6
HCSL
153.6
HCSL
153.6
HCSL
153.6
HCSL
10
0x04
PinMode 5-V1
24.8832
LVDS
24.8832
Crystal
MANU
24.8832
2488.32
155.52
PECL
155.52
PECL
155.52
PECL
155.52
PECL
155.52
HCSL
155.52
HCSL
155.52
HCSL
155.52
HCSL
10
0x05
PinMode 6-V1
24
LVDS
24
Crystal
MANU
24
2400
150
CML
150
CML
150
CML
150
CML
150
LVDS
150
LVDS
150
LVDS
150
LVDS
10
0x05
PinMode 6-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
153.6
CML
153.6
CML
153.6
CML
153.6
CML
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
10
0x05
PinMode 6-V1
24.8832
LVDS
24.8832
Crystal
MANU
24.8832
2488.32
155.52
CML
155.52
CML
155.52
CML
155.52
CML
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
10
0x06
PinMode 7-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
10
0x07
PinMode 8-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
122.88
PECL
122.88
PECL
122.88
PECL
122.88
PECL
122.88
HCSL
122.88
HCSL
122.88
HCSL
122.88
HCSL
10
0x08
PinMode 9-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
122.88
CML
122.88
CML
122.88
CML
122.88
CML
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
10
0x0A
PinMode 11-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
307.2
PECL
307.2
PECL
307.2
PECL
307.2
PECL
307.2
HCSL
307.2
HCSL
307.2
HCSL
307.2
HCSL
10
0x0C
PinMode 13-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
153.6
PECL
153.6
PECL
153.6
PECL
153.6
PECL
122.88
HCSL
122.88
HCSL
122.88
HCSL
122.88
HCSL
10
0x0D
PinMode 14-V1
26.5625
LVDS
26.5625
Crystal
MANU
26.5625
2550
212.5
PECL
212.5
PECL
106.25
PECL
106.25
PECL
106.25
HCSL
106.25
HCSL
212.5
HCSL
212.5
HCSL
10
0x0E
PinMode 15-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
491.52
PECL
491.52
PECL
245.76
PECL
245.76
PECL
122.88
HCSL
122.88
HCSL
98.304
HCSL
24.576
CMOS
10
0x0F
PinMode 16-V1
24.576
LVDS
24.576
Crystal
MANU
24.576
2457.6
622.08
PECL
622.08
PECL
307.2
PECL
307.2
PECL
153.6
HCSL
153.6
HCSL
122.88
HCSL
24.576
CMOS
10
0x11
PinMode 18-V1
25
LVDS
25
Crystal
MANU
25
2500
625
CML
625
CML
625
CML
625
CML
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
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Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: CDCM6208
37
CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
www.ti.com
Table 7. Pre-Configured Settings of CDCM6208V1H Accessible by PIN[4:0] (1) (2)
0x0A
10
0x0B
10
0x0C
10
0x0D
10
0x0E
10
0x0F
REF_SEL
(note 2)
UseCase
2550
212.5
LVPECL
Disable
Disable
106.25
LVPECL
Disable
Disable
50
LVCMOS N+P
Disable
Disable
133.33
HCSL
Disable
Disable
25
2500
156.25
LVPECL
156.25
LVPECL
25
LVPECL
25
LVPECL
156.25
HCSL
156.25
HCSL
125
LVCMOS N+P
125
LVCMOS N+P
25
2500
156.25
LVPECL
156.25
LVPECL
156.25
LVPECL
156.25
LVPECL
125
LVCMOS N+P
25
LVCMOS P
125
LVCMOS N+P
125
LVCMOS N+P
25
2500
100
LVPECL
100
LVPECL
100
LVPECL
100
LVPECL
125
LVCMOS N+P
25
LVCMOS N+P
125
LVCMOS N+P
125
LVCMOS N+P
25
2500
156.25
LVPECL
156.25
LVPECL
25
LVPECL
25
LVPECL
100
HCSL
100
HCSL
100
HCSL
100
HCSL
25
2500
156.25
LVPECL
156.25
CML
100
LVPECL
100
CML
125
LVCMOS P
50
LVCMOS P
100
HCSL
100
LVCMOS P
25
2500
156.25
LVPECL
156.25
CML
100
LVPECL
100
CML
125
LVCMOS P
125
HCSL
100
HCSL
100
LVCMOS N+P
25
2500
100
LVPECL
100
LVPECL
100
CML
100
CML
100
LVCMOS P
125
LVCMOS P
25
LVCMOS N+P
25
LVCMOS N+P
25
2500
100
LVPECL
100
LVPECL
156.25
LVPECL
156.25
LVPECL
100
HCSL
100
HCSL
25
LVCMOS P
66.667
LVCMOS P
25
2500
125
LVPECL
125
LVPECL
125
CML
125
CML
125
LVDS
100
LVDS
100
LVCMOS P
24
LVCMOS P
25
2500
156.25
LVPECL
Disable
Disable
100
CML
100
CML
125
LVDS
100
HCSL
100
LVCMOS P
24
LVCMOS P
25
2500
125
LVPECL
125
LVPECL
25
LVPECL
25
LVPECL
156.25
LVDS
156.25
HCSL
100
HCSL
100
LVCMOS P
25
2500
156.25
CML
156.25
LVDS
125
CML
125
LVDS
Disable
Disable
25
LVCMOS P
100
HCSL
66.67
LVCMOS P
25
2500
156.25
LVPECL
156.25
LVPECL
100
LVPECL
100
CML
25
HCSL
25
LVCMOS P
100
LVCMOS P
66.667
LVCMOS P
25
2500
125
LVPECL
125
LVPECL
25
LVPECL
25
LVPECL
100
HCSL
100
LVCMOS P
25
LVCMOS P
66.667
LVCMOS P
25
2500
156.25
LVPECL
156.25
CML
125
CML
125
CML
12
LVCMOS P
25
LVCMOS P
50
LVCMOS P
100
HCSL
38.88
2488.32
622.08
LVPECL
Disable
Disable
155.52
LVPECL
155.52
LVPECL
155.52
LVDS
155.52
LVDS
77.76
LVDS
77.76
LVDS
MANU
Pin Mode 2 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 3 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 4 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 5 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 6 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 7 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 8 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 9 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 10 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 11 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 12 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 13 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 14 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 15 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 16 - V1
38
25
MANU
Pin Mode 1 - V1
(1)
(2)
Type
10
fout(Y7)
0x09
Type
10
fout(Y6)
0x08
Type
10
fout(Y5)
0x07
Type
10
fout(Y4)
0x06
Type
10
fout(Y3)
0x05
XTAL
Type
10
25
fout(Y2)
0x04
LVCMOS
Type
10
25
MANU
fout(Y1)
0x03
XTAL
Type
10
25
fout(Y0)
0x02
LVCMOS
f(VCO)
10
25
f(PFD)
0x01
Type
0x00
10
fin(SEC_REF)
10
SPI/I2C Default
Type
out
fin(PRI_REF)
00
01
pin[4:0]
SI_MODE[1:0]
Pre-Configured Settings of CDCM6208 Accessible by PIN[4:0]
38.88
LVCMOS
38.88
LVCMOS
The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be mixed and matched as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8 V or 2.5/3.3 V supply. Exception: inputs configured for
LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44.
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: CDCM6208
CDCM6208
www.ti.com
SCAS931G – MAY 2012 – REVISED JANUARY 2018
Table 7. Pre-Configured Settings of CDCM6208V1H Accessible by PIN[4:0](1)(2) (continued)
10
0x18
10
0x19
10
0x1A
10
0x1B
10
0x1C
10
0x1D
10
0x1E
10
0x1F
Type
0x17
fout(Y7)
10
Type
0x16
fout(Y6)
10
Type
0x15
fout(Y5)
10
Type
0x14
fout(Y4)
10
Type
0x13
fout(Y3)
10
Type
0x12
fout(Y2)
10
Type
0x11
25
2500
100
CML
100
CML
125
CML
125
CML
83.33
LVCMOS P
25
LVCMOS N+P
100
LVCMOS N+P
125
LVCMOS N+P
25
2400
100
LVPECL
100
LVPECL
100
LVPECL
100
LVPECL
25
LVCMOS P
Disable
Disable
40
LVCMOS P
66.667
LVCMOS P
25
2500
156.25
CML
156.25
LVDS
100
CML
100
LVDS
Disable
Disable
25
LVCMOS N+P
66.67
LVCMOS P
100
HCSL
38.88
2488.32
155.52
LVPECL
155.52
LVPECL
155.52
LVPECL
155.52
LVPECL
77.76
LVDS
Disable
Disable
Disable
Disable
25
LVCMOS N+P
38.88
2488.32
77.76
LVPECL
Disable
Disable
77.76
LVDS
Disable
Disable
77.76
LVCMOS N+P
77.76
LVCMOS N+P
38.88
LVCMOS N+P
25
LVCMOS N+P
0.8
2500
100
LVPECL
Disable
Disable
125
LVPECL
Disable
Disable
125
LVCMOS N+P
25
LVCMOS N+P
66.67
LVCMOS P
2.048
LVCMOS P
25
2500
100
LVPECL
100
LVPECL
125
LVPECL
125
LVPECL
Disable
Disable
25
LVCMOS P
66.667
LVCMOS P
2.048
LVCMOS P
25
2500
125
LVDS
125
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVCMOS N+P
25
LVDS
25
LVCMOS N+P
25
2400
100
LVDS
100
LVDS
100
LVDS
100
LVDS
25
LVDS
25
LVCMOS P
133.33
LVDS
66.67
LVCMOS P
25
2500
156.25
LVPECL
156.25
CML
125
LVPECL
125
CML
Disable
Disable
25
LVCMOS N+P
66.67
LVCMOS P
2.048
LVCMOS P
25
2500
156.25
LVPECL
156.25
LVPECL
125
LVPECL
125
LVPECL
133.33
LVDS
25
LVCMOS P
100
HCSL
100
HCSL
25
2400
100
LVPECL
100
LVPECL
96
LVPECL
Disable
Disable
133.33
HCSL
33.33
LVCMOS P
14.31818
LVCMOS P
48
LVCMOS P
25
2500
156.25
LVPECL
156.25
CML
100
LVPECL
100
CML
25
HCSL
25
LVDS
100
HCSL
100
HCSL
25
2500
156.25
LVPECL
156.25
CML
125
LVPECL
125
CML
25
LVDS
33.33
LVCMOS P
100
HCSL
50
LVCMOS P
25
2500
125
LVPECL
125
LVPECL
25
LVPECL
25
LVPECL
156.25
LVDS
Disable
Disable
100
LVDS
12
LVCMOS P
25
2500
125
LVPECL
125
LVPECL
100
LVPECL
100
LVPECL
156.25
LVDS
Disable
Disable
25
LVCMOS N+P
25
LVCMOS N+P
MANU
0x10
10
fout(Y1)
XTAL
Type
Type
25
fout(Y0)
fin(SEC_REF)
LVCMOS
f(VCO)
Type
25
f(PFD)
fin(PRI_REF)
Pin Mode 17 - V1
REF_SEL
(note 2)
UseCase
10
pin[4:0]
SI_MODE[1:0]
Pre-Configured Settings of CDCM6208 Accessible by PIN[4:0]
MANU
Pin Mode 18 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 19 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 20 - V1
38.88
LVCMOS
38.88
LVCMOS
MANU
Pin Mode 21 - V1
38.88
LVCMOS
38.88
LVCMOS
MANU
Pin Mode 22 - V1
19.2
LVCMOS
19.2
LVCMOS
MANU
Pin Mode 23 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 24 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 25 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 26 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 27 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 28 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 29 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 30 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 31 - V1
25
LVCMOS
25
XTAL
MANU
Pin Mode 32 - V1
25
LVCMOS
25
XTAL
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SI_MODE[1:0]
pin[4:0]
UseCase
fin(PRI_REF)
Type
fin(SEC_REF)
Type
REF_SEL (note 2)
f(PFD)
f(VCO)
fout(Y0)
Type
fout(Y1)
Type
fout(Y2)
Type
fout(Y3)
Type
fout(Y4)
Type
fout(Y5)
Type
fout(Y6)
Type
fout(Y7)
Table 8. Pre-Configured Settings of CDCM6208V2 Accessible by PIN[4:0] (1) (2)
Type
00
I/O
SPI Default
30.72
LVDS
30.72
Crystal
MANU
30.72
3072
153.60
LVDS
153.60
LVDS
122.88
LVDS
122.88
LVDS
61.44
LVDS
61.44
LVDS
30.72
LVDS
30.72
LVDS
01
I/O
I2C Default
30.72
LVDS
30.72
Crystal
MANU
30.72
3072
153.60
LVDS
153.60
LVDS
122.88
LVDS
122.88
LVDS
61.44
LVDS
61.44
LVDS
30.72
LVDS
30.72
LVDS
LVDS
11
RESERVED
10
0x00
PinMode 1-V2
19.44
LVDS
19.44
Crystal
MANU
19.44
3110.4
155.52
PECL
155.52
PECL
155.52
PECL
155.52
PECL
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
10
0x01
PinMode 2-V2
19.44
LVDS
19.44
Crystal
MANU
19.44
3110.4
155.52
PECL
155.52
PECL
155.52
PECL
155.52
PECL
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
10
0x02
PinMode 3-V2
19.44
LVDS
19.44
Crystal
MANU
19.44
3110.4
155.52
PECL
155.52
PECL
155.52
PECL
155.52
PECL
155.52
HCSL
155.52
HCSL
155.52
HCSL
155.52
HCSL
10
0x03
PinMode 4-V2
19.44
LVDS
19.44
Crystal
MANU
19.44
3110.4
622.08
PECL
622.08
PECL
622.08
PECL
622.08
PECL
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
10
0x04
PinMode 5-V2
25
LVDS
25
Crystal
MANU
25
3000
125
PECL
125
PECL
125
PECL
125
PECL
100
HCSL
100
HCSL
100
HCSL
100
HCSL
10
0x05
PinMode 6-V2
25
LVDS
25
Crystal
MANU
25
3000
125
LVDS
125
LVDS
125
LVDS
125
LVDS
100
LVDS
100
LVDS
100
LVDS
100
LVDS
10
0x06
PinMode 7-V2
25
LVDS
25
Crystal
MANU
25
3000
250
LVDS
250
LVDS
250
LVDS
250
LVDS
250
LVDS
250
LVDS
250
LVDS
250
LVDS
10
0x07
PinMode 8-V2
25
LVDS
25
Crystal
MANU
25
3000
200
PECL
200
PECL
200
PECL
200
PECL
200
HCSL
200
HCSL
200
HCSL
200
HCSL
10
0x08
PinMode 9-V2
25
LVDS
25
Crystal
MANU
25
3000
187.5
PECL
187.5
PECL
187.5
PECL
187.5
PECL
187.5
HCSL
187.5
HCSL
187.5
HCSL
187.5
HCSL
10
0x09
PinMode 10-V2
38.4
LVDS
38.4
Crystal
MANU
38.4
3072
153.6
LVDS
153.6
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
153.6
LVDS
153.6
LVDS
10
0x0A
PinMode 11-V2
38.4
LVDS
38.4
Crystal
MANU
9.6
3072
153.6
LVDS
153.6
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
153.6
LVDS
153.6
LVDS
10
0x0B
PinMode 12-V2
25
LVDS
25
Crystal
MANU
25
3000
100
LVDS
x
x
x
x
x
x
100
HCSL
25
CMOS
24
CMOS
27
CMOS
10
0x0C
PinMode 13-V2
122.88
LVDS
122.88
LVDS
MANU
3.072
3072
153.6
LVDS
153.6
LVDS
122.88
LVDS
122.88
LVDS
30.72
LVDS
30.72
LVDS
61.44
LVDS
61.44
LVDS
10
0x0D
PinMode 14-V2
153.6
LVDS
153.6
LVDS
MANU
0.384
3072
153.6
LVDS
153.6
LVDS
122.88
LVDS
122.88
LVDS
30.72
LVDS
30.72
LVDS
61.44
LVDS
61.44
LVDS
10
0x0E
PinMode 15-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
2949.12
491.52
PECL
491.52
PECL
245.76
PECL
245.76
PECL
122.88
LVDS
122.88
LVDS
61.44
LVDS
30.72
LVDS
10
0x0F
PinMode 16-V2
19.44
LVDS
19.44
Crystal
MANU
19.44
3110.4
155.52
LVDS
155.52
LVDS
155.52
LVDS
155.52
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
10
0x10
PinMode 17-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
2949.12
245.76
LVDS
245.76
LVDS
245.76
LVDS
245.76
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
122.88
LVDS
10
0x11
PinMode 18-V2
25
LVDS
25
Crystal
MANU
6.25
3125
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
106.25
LVDS
106.25
LVDS
106.25
LVDS
106.25
LVDS
10
0x12
PinMode 19-V2
25
LVDS
25
Crystal
MANU
25
3000
125
LVDS
125
LVDS
125
LVDS
125
LVDS
106.25
LVDS
106.25
LVDS
106.25
LVDS
106.25
LVDS
10
0x13
PinMode 20-V2
25
LVDS
25
Crystal
MANU
25
3125
156.25
PECL
156.25
PECL
125
PECL
125
PECL
66.67
CMOS
33.33
CMOS
50
CMOS
12.5
CMOS
10
0x14
PinMode 21-V2
25
CMOS
25
Crystal
MANU
25
3125
125
LVDS
125
LVDS
125
LVDS
125
LVDS
66.67
LVDS
156.25
LVDS
125
LVDS
100
LVDS
10
0x15
PinMode 22-V2
25
LVDS
25
Crystal
MANU
1
3072
153.6
LVDS
153.6
LVDS
122.88
LVDS
122.88
LVDS
66.67
LVDS
156.25
LVDS
30.72
LVDS
100
LVDS
10
0x16
PinMode 23-V2
19.2
LVDS
19.2
Crystal
MANU
3.84
2949.12
122.88
LVDS
122.88
PECL
122.88
LVDS
122.88
LVDS
30.72
LVDS
66.67
LVDS
153.6
LVDS
250
LVDS
10
0x17
PinMode 24-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
2949.12
122.88
LVDS
122.88
LVDS
30.72
LVDS
30.72
LVDS
66.67
LVDS
100
LVDS
156.25
LVDS
156.25
LVDS
10
0x18
PinMode 25-V2
25
LVDS
25
Crystal
MANU
25
3000
125
LVDS
125
LVDS
125
LVDS
125
LVDS
68.75
LVDS
68.75
LVDS
68.75
LVDS
68.75
LVDS
10
0x19
PinMode 26-V2
10
LVDS
10
Crystal
MANU
0.08
2949.12
245.76
PECL
245.76
PECL
122.88
PECL
122.88
PECL
125
LVDS
100
LVDS
307.2
LVDS
307.2
LVDS
10
0x1A
PinMode 27-V2
30.72
LVDS
30.72
LVDS
MANU
30.72
2949.12
122.88
LVDS
x
x
30.72
LVDS
30.72
LVDS
156.25
LVDS
156.25
LVDS
100
LVDS
66.67
LVDS
10
0x1B
PinMode 28-V2
10
CMOS
10
LVDS
MANU
0.08
2949.12
245.76
CML
245.76
CML
122.88
CML
122.88
CML
30.72
LVDS
66.67
LVDS
156.25
LVDS
307.2
LVDS
(1)
(2)
40
The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be mixed and matched as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8-V or 2.5/3.3-V supply.
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Product Folder Links: CDCM6208
CDCM6208
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SCAS931G – MAY 2012 – REVISED JANUARY 2018
SI_MODE[1:0]
pin[4:0]
UseCase
fin(PRI_REF)
Type
fin(SEC_REF)
Type
REF_SEL (note 2)
f(PFD)
f(VCO)
fout(Y0)
Type
fout(Y1)
Type
fout(Y2)
Type
fout(Y3)
Type
fout(Y4)
Type
fout(Y5)
Type
fout(Y6)
Type
fout(Y7)
Table 8. Pre-Configured Settings of CDCM6208V2 Accessible by PIN[4:0]()() (continued)
Type
10
0x1C
PinMode 29-V2
19.44
LVDS
19.44
Crystal
MANU
0.01
3125
156.25
LVDS
156.25
LVDS
125
LVDS
125
LVDS
66.67
LVDS
100
LVDS
25
LVDS
25
LVDS
10
0x1D
PinMode 30-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
2949.12
737.28
PECL
737.28
PECL
491.52
PECL
491.52
PECL
122.88
HCSL
122.88
HCSL
122.88
LVDS
122.88
LVDS
10
0x1E
PinMode 31-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
3072
614.4
PECL
614.4
PECL
307.2
PECL
307.2
PECL
153.6
HCSL
153.6
HCSL
153.6
LVDS
153.6
LVDS
10
0x1F
PinMode 32-V2
30.72
LVDS
30.72
Crystal
MANU
30.72
3072
153.6
CML
153.6
CML
153.6
CML
153.6
CML
100
LVDS
66.67
LVDS
125
LVDS
50
LVDS
Alternative PinMode usage by modifying input frequencies:
10
0x00
PinMode 1-V2
19.2
LVDS
19.2
Crystal
MANU
19.2
3072
153.6
PECL
153.6
PECL
153.6
PECL
153.6
PECL
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
10
0x01
PinMode 2-V2
19.2
LVDS
19.2
Crystal
MANU
19.2
3072
153.6
PECL
153.6
PECL
153.6
PECL
153.6
PECL
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
10
0x03
PinMode 4-V2
19.2
LVDS
19.2
Crystal
MANU
19.2
3072
614.4
PECL
614.4
PECL
614.4
PECL
614.4
PECL
153.6
LVDS
153.6
LVDS
153.6
LVDS
153.6
LVDS
10
0x11
PinMode 18-V1
25
LVDS
25
Crystal
MANU
25
2500
625
CML
625
CML
625
CML
625
CML
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
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8.4.2 Loop Filter Recommendations for Pin Modes
The following two tables provide the internal charge pump and R3/C3 settings for pin modes. The designer can either design their own optimized loop
filter, or use the suggested loop filter in the Table 10.
Table 9. CDCM6208V1 Loop Filter Recommendation for Pin Mode
SI_MODE [1:0]
PIN[4:0]
USECASE
f(PFD)
[MHz]
ICP
[mA]
SUGGESTED LOOP FILTER
C1/R2/C2
INTERNAL LPF COMPONENTS
R3
C3
00
out
SPI Default
25
2.5
100 Ω
242.5 pF
10
0x00
Pin Mode 1 - V1
25
2.5
100 Ω
242.5 pF
10
0x01
Pin Mode 2 - V1
25
2.5
100 Ω
242.5 pF
10
0x02
Pin Mode 3 - V1
25
2.5
100 Ω
242.5 pF
10
0x03
Pin Mode 4 - V1
25
2.5
100 Ω
242.5 pF
10
0x04
Pin Mode 5 - V1
25
2.5
100 Ω
242.5 pF
10
0x05
Pin Mode 6 - V1
25
2.5
100 Ω
242.5 pF
10
0x06
Pin Mode 7 - V1
25
2.5
100 Ω
242.5 pF
10
0x07
Pin Mode 8 - V1
25
2.5
100 Ω
242.5 pF
10
0x08
Pin Mode 9 - V1
25
2.5
100 Ω
242.5 pF
10
0x09
Pin Mode 10 - V1
25
2.5
100 Ω
242.5 pF
10
0x0A
Pin Mode 11 - V1
25
2.5
100 Ω
242.5 pF
10
0x0B
Pin Mode 12 - V1
25
2.5
100 Ω
242.5 pF
10
0x0C
Pin Mode 13 - V1
25
2.5
100 Ω
242.5 pF
10
0x0D
Pin Mode 14 - V1
25
2.5
100 Ω
242.5 pF
10
0x0E
Pin Mode 15 - V1
25
2.5
100 Ω
242.5 pF
10
0x0F
Pin Mode 16 - V1
25
2.5
100 Ω
242.5 pF
10
0x10
Pin Mode 17 - V1
30.72
2.5
100 Ω
242.5 pF
10
0x11
Pin Mode 18 - V1
24.8832
2.5
100 Ω
242.5 pF
10
0x12
Pin Mode 19 - V1
25
2.5
100 Ω
242.5 pF
10
0x13
Pin Mode 20 - V1
0.008
0.5
4010 Ω
562.5 pF
10
0x14
Pin Mode 21 - V1
25
2.5
100 Ω
242.5 pF
10
0x15
Pin Mode 22 - V1
25
2.5
100 Ω
242.5 pF
10
0x16
Pin Mode 23 - V1
25
2.5
100 Ω
242.5 pF
10
0x17
Pin Mode 24 - V1
25
2.5
100 Ω
242.5 pF
10
0x18
Pin Mode 25 - V1
25
2.5
100 Ω
242.5 pF
10
0x19
Pin Mode 26 - V1
25
2.5
100 Ω
242.5 pF
10
0x1A
Pin Mode 27 - V1
25
2.5
10 Ω
30.0 pF
10
0x1B
Pin Mode 28 - V1
25
2.5
100 Ω
242.5 pF
10
0x1C
Pin Mode 29 - V1
10
2.5
20pF/1210/68nF
100 Ω
242.5 pF
10
0x1D
Pin Mode 30 - V1
25
2.5
100pF/500R/22nF
100 Ω
242.5 pF
10
0x1E
Pin Mode 31 - V1
0.04
0.5
4.7uF/250/47uF
4010 Ω
562.5 pF
10
0x1F
Pin Mode 32 - V1
25
2.5
100pF/500R/22nF
100 Ω
242.5 pF
100pF/500R/22nF
220pF/400/22nF
100pF/500R/22nF
1uF/1.3k/22uF
100pF/500R/22nF
42
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CDCM6208
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SCAS931G – MAY 2012 – REVISED JANUARY 2018
UseCase
00
01
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
ICP
suggested loop Filter
[MHz]
[mA]
C1/R2/C2
Internal LPF
components
pin[4:0]
SI_MODE
[1:0]
Table 10. CDCM6208V1H Loop Filter Recommendation for Pin Mode
f(PFD)
out
SPI/I2C Default
25
2.5
10 Ohm
35 pF
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Pin Mode 1 - V1
Pin Mode 2 - V1
Pin Mode 3 - V1
Pin Mode 4 - V1
Pin Mode 5 - V1
Pin Mode 6 - V1
Pin Mode 7 - V1
Pin Mode 8 - V1
Pin Mode 9 - V1
Pin Mode 10 - V1
Pin Mode 11 - V1
Pin Mode 12 - V1
Pin Mode 13 - V1
Pin Mode 14 - V1
Pin Mode 15 - V1
Pin Mode 16 - V1
Pin Mode 17 - V1
Pin Mode 18 - V1
Pin Mode 19 - V1
Pin Mode 20 - V1
Pin Mode 21 - V1
Pin Mode 22 - V1
Pin Mode 23 - V1
Pin Mode 24 - V1
Pin Mode 25 - V1
Pin Mode 26 - V1
Pin Mode 27 - V1
Pin Mode 28 - V1
Pin Mode 29 - V1
Pin Mode 30 - V1
Pin Mode 31 - V1
Pin Mode 32 - V1
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
38.88
25
25
25
38.88
38.88
0.8
25
25
25
25
25
25
25
25
25
25
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.0
2.5
2.5
2.5
2.0
2.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
10 Ohm
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
35 pF
100pF/500/22nF
10pF/2.8k/4.7nF
100pF/500/22nF
R3
C3
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Table 11. CDCM6208V2 Loop Filter Recommendation for Pin Mode
SI_MODE [1:0]
PIN[4:0]
USECASE
f(PFD)
[MHz]
ICP
[mA]
SUGGESTED LOOP FILTER
C1/R2/C2
INTERNAL LPF COMPONENTS
R3
C3
100 Ω
242.5 pF
00
out
SPI Default
30.72
2.5
470pF/560R/100nF
10
0x00
Pin Mode 1 - V1
19.44
2.5
330pF/530R/22nF
100 Ω
242.5 pF
10
0x01
Pin Mode 2 - V1
19.44
0.5
4.7uF/10R/100uF
4010 Ω
562.5 pF
10
0x02
Pin Mode 3 - V1
19.44
2.5
100 Ω
242.5 pF
10
0x03
Pin Mode 4 - V1
19.44
2.5
100 Ω
242.5 pF
10
0x04
Pin Mode 5 - V1
25
2.5
100 Ω
242.5 pF
10
0x05
Pin Mode 6 - V1
25
2.5
100 Ω
242.5 pF
10
0x06
Pin Mode 7 - V1
25
2.5
100 Ω
242.5 pF
10
0x07
Pin Mode 8 - V1
25
2.5
100 Ω
242.5 pF
10
0x08
Pin Mode 9 - V1
25
2.5
100 Ω
242.5 pF
10
0x09
Pin Mode 10 - V1
38.4
2.5
220p/280R/22n
100 Ω
242.5 pF
10
0x0A
Pin Mode 11 - V1
9.6
0.5
4.7uF/10R/100uF
4010 Ω
562.5 pF
10
0x0B
Pin Mode 12 - V1
25
2.5
200pF/400R/22nF
100 Ω
242.5 pF
10
0x0C
Pin Mode 13 - V1
3.072
0.5
10uF/15R/100uF
4010 Ω
562.5 pF
10
0x0D
Pin Mode 14 - V1
0.384
0.5
10uF/42R/100uF
4010 Ω
562.5 pF
10
0x0E
Pin Mode 15 - V1
30.72
2.5
470pF/560R/100nF
100 Ω
242.5 pF
10
0x0F
Pin Mode 16 - V1
19.44
2.5
330pF/530R/22nF
100 Ω
242.5 pF
10
0x10
Pin Mode 17 - V1
30.72
2.5
470pF/560R/100nF
100 Ω
242.5 pF
10
0x11
Pin Mode 18 - V1
6.25
2.5
100p/1.1k/10n
530 Ω
310.0 pF
10
0x12
Pin Mode 19 - V1
25
2.5
100 Ω
242.5 pF
10
0x13
Pin Mode 20 - V1
25
2.5
100 Ω
242.5 pF
10
0x14
Pin Mode 21 - V1
25
2.5
100 Ω
242.5 pF
10
0x15
Pin Mode 22 - V1
1
2.5
100p/1.5k/100n
4010 Ω
562.5 pF
10
0x16
Pin Mode 23 - V1
3.84
1.5
22nF/220R/1uF
1050 Ω
562.5 pF
10
0x17
Pin Mode 24 - V1
30.72
2.5
470pF/560R/100nF
100 Ω
242.5 pF
10
0x18
Pin Mode 25 - V1
25
2.5
200pF/400R/22nF
100 Ω
242.5 pF
10
0x19
Pin Mode 26 - V1
0.08
1
5uF/100/100uF
4010 Ω
562.5 pF
10
0x1A
Pin Mode 27 - V1
30.72
2.5
470pF/560R/100nF
10 Ω
242.5 pF
10
0x1B
Pin Mode 28 - V1
0.08
1
5uF/100/100uF
4010 Ω
562.5 pF
10
0x1C
Pin Mode 29 - V1
0.01
1.5
5uF/200/100uF
4010 Ω
562.5 pF
10
0x1D
Pin Mode 30 - V1
30.72
2.5
100 Ω
242.5 pF
10
0x1E
Pin Mode 31 - V1
30.72
2.5
100 Ω
242.5 pF
10
0x1F
Pin Mode 32 - V1
30.72
2.5
100 Ω
242.5 pF
330pF/530R/22nF
44
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200pF/400R/22nF
200pF/400R/22nF
470pF/560R/100nF
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8.4.3 Status Pins Definition
The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by
reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization
of which vitals are mapped to these two pins. Table 12 lists the three events that can be mapped to each status
pin and which can also be read in the register space.
Table 12. CDCM6208 Status Pin Definition List
STATUS
SIGNAL NAME
SIGNAL TYPE
SIGNAL NAME
SEL_REF
LVCMOS
STATUS0, 1
Reg 3.12
Reg 3.9
Indicates Reference Selected for PLL:
0 → Primary input selected to drive PLL
1 → Secondary input selected to drive PLL
LOS_REF
LVCMOS
STATUS0, 1
Reg 3.11
Reg 3.8
Loss of selected reference input observed at active input:
0 → Reference input present
1 → Loss of reference input
Important Note 1: For LOS_REF to operate properly, the secondary
input SEC_IN must be enabled. Set register Q4.5=1. If register
Q4.5 is set to zero, LOS_REF will output a static high signal
regardless of the actual input signal status on PRI_IN.
PLL_UNLOCK
LVCMOS
STATUS0, 1
Reg 3.10
Reg 3.7
Indicates unlock status for PLL (digital):
PLL locked → Q21.02 = 0 and VSTATUS0/1= VIH
PLL unlocked → Q21.2 = 1 and VSTATUS0/1= VILSee note (1)
Note 2: I f the smartmux is enabled and both reference clocks stall,
the STATUSx output signal will 98% of the time indicate the LOS
condition with a static high signal. However, in 2% of the cases, the
LOS detection engine erroneously stalls at a state where the
STATUSx output PLL lock indicator will signalize high for 511 out of
every 512 PFD clock cycles.
(1)
REGISTER BIT DESCRIPTION
NO.
The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.
NOTE
It is recommended to assert only one out of the three register bits for each of the status
pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference
clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 =
1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to
set the according 3 register bits to zero (for example, Q3[12:9] = 0 for STATUS0 = 0). If
more than one bit is enabled for each STATUS signal, the function becomes OR'ed. For
example, if Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if
the device goes out of lock or the selected reference clock signal is lost.
8.4.4 PLL Lock Detect
The PLL lock detection circuit is a digital detection circuit which detects any frequency error, even a single cycle
slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the
counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as
toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 th of the PFD update frequency to the
device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000 PFD
update clock cycles. If the system plans using PLL lock to toggle a system reset, then consider adding an RC
filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system
reset.
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8.4.5 Interface and Control
The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208 through the SPI or I2C port.
The host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block
is controlled and monitored via a specific grouping of bits located within the register file. The host controls and
monitors certain device-wide critical parameters directly, through control/status pins. In the absence of a host, the
CDCM6208 can be configured to operate in pin mode where the control pins [PIN0-PIN4] can be set
appropriately to generate the necessary clock outputs out of the device.
STATUS1/PIN0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
PDN
Reg 23
15 14 13 12 11 10 9
Reg 22
15 14 13 12 11 10 9
RESETN/PWR
Device
Control
And
Status
SCL/PIN4
SPI/I2C
Port
SDI/SDA/PIN1
Reg 21
15 14 13 12 11 10 9
Reg 20
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDO/AD0/PIN2
Reg3
15 14
Reg2
15 14
Reg1
15 14
Reg 0
15 14
SCS/AD1/PIN3
SI_MODE0
Comm
Select
SI_MODE1
SPI: SI_MODE[1:0]=00;
I2C: SI_MODE[1:0]=01;
Device
Hardware
User Space
Reg31
15 14 13 12 11 10 9
Reg30
15 14 13 12 11 10 9
STATUS0
Control/
Status Pins
TI only space
REGISTER SPACE
Pin Mode: SI_MODE[1:0]=10
Figure 38. CDCM6208 Interface and Control Block
Within this register space, there are certain bits that have read/write access. Other bits are read-only (an attempt
to write to a read only bit will not change the state of the bit).
8.4.5.1 Register File Reference Convention
Figure 39 shows the method this document employs to refer to an individual register bit or a grouping of register
bits. If a drawing or text references an individual bit, the format is to specify the register number first and the bit
number second. The CDCM6208 contains 21 registers that are 16 bits wide. The register addresses and the bit
positions both begin with the number zero (0). A period separates the register address and bit address. The first
bit in the register file is address 'R0.0' meaning that it is located in Register 0 and is bit position 0. The last bit in
the register file is address R31.15 referring to the 16thbit of register address 31 (the 32ndregister in the device
Reg05
Register Number (s)
5
4
Bit Number(s)
3
2
R05 .2
Figure 39. CDCM6208 Register Reference Format
46
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8.4.5.2 SPI - Serial Peripheral Interface
To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave
protocol in which the host system is always the master; therefore, the host always initiates communication
to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000.
Table 13. Serial Port Signals in SPI Mode
PIN
NAME
NUMBER
DESCRIPTION
I/O
SDI/SDA/PIN1
2
Input
SDO/AD0/PIN2
3
Output
SDI: SPI Serial Data Input
SCS/AD1/PIN3
4
Input
SCS: SPI Latch Enable
SCL/PIN4
5
Input
SCL: SPI/I2C Clock
SDO: SPI Serial Data
The host must present data to the device MSB first. A message includes a transfer direction bit, an address field,
and a data field as depicted in Figure 40
Examples:
3
4
5
6
7
0
0
0
0
A
10
A
9
R/W
First Out
MSB
1 2
Fixed (4 bits)
LSB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Order of Transmission
A A A A A A A A A D D D D D D D D D D D D D D D D
Bit Definition
8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register Address (11 bits)
Data Payload (16 bits)
Message Field Definition
8
9
Read Register 4:
1|000 0|000 0000 0100| xxxx xxxx xxxx xxxx
Write 0xF0F1 to Register 5:
0|000 0|000 0000 0101| 1111 0000 1111 0001
Figure 40. CDCM6208 SPI Message Format
8.4.5.2.1 Writing to the CDCM6208
To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the
clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208. This bit signals if a read (first bit
high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208 with each rising edge of
SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the target register in
the register file. The 16 bits that follow are the data payload. If the host sends an incomplete message, (i.e. the
host de-asserts the SCS pin high prior to a complete message transmission), then the CDCM6208 aborts the
transfer, and device makes no changes to the register file or the hardware. Figure 42 shows the format of a write
transaction on the CDCM6208 SPI port. The host signals the CDCM6208 of the completed transfer and disables
the SPI port by de-asserting the SCS pin high.
8.4.5.2.2 Reading From the CDCM6208
As with the write operation, the host first initiates a SPI transfer by asserting the SCS pin low. The host signals a
read operation by shifting a logical high in the first bit position, signaling the CDCM6208 that the host is imitating
a read data transfer from the device. During the portion of the message in which the host specifies the
CDCM6208 register address, the host presents this information on the SDI pin of the device (for the first 15 clock
cycles after the W/R bit). During the 16 clock cycles that follow, the CDCM6208 presents the data from the
register specified in the first half of the message on the SDO pin. The SDO output is 3-stated anytime SCS is
high, so that multiple SPI slave devices can be connected to the same serial bus. The host signals the
CDCM6208 that the transfer is complete by de-asserting the SCS pin high.
SCS (#37)
0
&
0
SDO internal
enable signal
Data out
0
LVCMOS
SDO
(#34)
CDCM6208
Figure 41. Reading From the CDCM6208
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8.4.5.2.3 Block Write/Read Operation
The device supports a block write and block read operation. The host need only specify the lowest address of the
sequence of addresses that the host needs to access. The CDCM6208 will automatically increment the internal
register address pointer if the SCS pin remains low after the SPI port finishes the initial 32-bit transmission
sequence. Each transmission of 16 bits (a data payload width) results in the device automatically incrementing
the address pointer (provided the SCS pin remains active low for all sequences).
SCS
SCL
WRITE
SCI
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 D15 D14 D13 D12 D11 D10
SCI
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16
D9
D8
D7
D6
D5
D4
D5
D4
D3
D2
D1
D0
D1
D0
'21¶7 &$5(
READ
HI-Z
SCO
D15 D14 D13 D12 D11 D10
16-BIT COMMAND
D9
D7
D8
D6
D3
D2
16-BIT DATA
Figure 42. CDCM6208 SPI Port Message Sequencing
t4
t1
t5
SCL
t2
SDI
A31
t3
A30
D1
D0
'21¶7 &$5(
t6
SDO
D15
'21¶7 &$5(
D1
tri-state
D0
t7
SCS
t8
Figure 43. CDCM6208 SPI Port Timing
Table 14. SPI Timing
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
fClock
Clock Frequency for the SCL
t1
SPI_LE to SCL setup time
10
ns
t2
SDI to SCL setup time
10
ns
t3
SDO to SCL hold time
10
ns
t4
SCL high duration
25
ns
t5
SCL low duration
25
ns
t6
SCL to SCS Setup time
10
ns
t7
SCS Pulse Width
20
ns
t8
SDI to SCL Data Valid (First Valid Bit after SCS)
10
ns
48
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8.4.5.2.4 I2C Serial Interface
With SI_MODE1=0 and SI_MODE0=1 the CDCM6208 enters I 2C mode. The I2C port on the CDCM6208 works
as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode operations. Fast mode
imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less
than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger at the SDA and SCL inputs to
provide receiver input hysteresis for increased noise robustness.
NOTE
Communication through I2C is not possible while RESETN is held low.
In an I2C bus system, the CDCM6208 acts as a slave device and is connected to the serial bus (data bus SDA
and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices to be
connected to the same serial bus. The CDCM6208 allows up to four unique CDCM6208 slave devices to occupy
the I2C bus in addition to any other I2C slave device with a different I2C address. These slave devices are
accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave
address responds to subsequent I2C commands. The device slave address is 10101xx (the two LSBs are
determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set through pins
on device power up.
SDA
Data out
Data in
CDCM6208
Figure 44. I2C Serial Interface
During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred.
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data
line can change only when the clock signal on the SCL line is low. The start data transfer condition is
characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is
characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are
always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed
by an acknowledge bit and bytes are sent MSB first.
The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A
= 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA
line high during the 9thclock pulse.
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The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master. The CDCM6208 slave address bytes are given in below
table.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10 thclock pulse following the acknowledge bit for the last data byte from
the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during
the 9thclock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave
knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the
low period before the 10 thclock pulse, and high during the 10 thclock pulse to assert a stop condition.
For "Register Write/Read" operations, the I2C master can individually access addressed registers, that are made
of two 8-bit data bytes.
Table 15. I2C Slave Address Byte
50
A6
A5
A4
A3
A2
AD1
AD0
R/W
1
0
1
0
1
0
0
1/0
1
0
1
0
1
0
1
1/0
1
0
1
0
1
1
0
1/0
1
0
1
0
1
1
1
1/0
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8.5 Programming
Table 16. Generic Programming Sequence
S
Start Condition
Sr
Repeated Condition
R/W
1 = Read (Rd) from slave; 0 = Write (Wr) to slave
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 45. Register Write Programming Sequence
1
7
S
SLAVE
Address
1
Wr
1
8
A
Register
Address
1
8
A
Register
Address
1
8
A
Data
Byte
1
8
1
1
A
Data
Byte
A
P
Figure 46. Register Read Programming Sequence
1
7
S
SLAVE
Address
1
Wr
1
8
A
Register
Address
1
8
A
Register
Address
1
A
1
1
S
Slave
Address
1
Rd
1
8
A
Data
Byte
1
8
1
1
A
Data
Byte
A
P
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8.6 Register Maps
Y0
In SPI/I2C mode the device can be configured through twenty registers. Register 4 configures the input, Reg 0-3
the PLL and dividers, and Register 5 - 20 configures the 8 different outputs.
CDCM6208 Register programming
INT
DIV
REG 5
Y1
REG 6
REG 4
PSB
M
I
REG 1
Charge Pump
and
Loop Filter
VCO
PSA
Y2
REG 4
R
INMUX
PRI
REG 4
REG 3
SEC
INT
DIV
REG 0
REG 7
N
REG 8
PRI
SEC
Y4
REG 9,10,11
FRAC
DIV
OUTMUX
Y3
REG 2 / REG1
OUTMUX
PRI
SEC
Y5
REG 9
REG 12,13,14
FRAC
DIV
REG 12
Y6
FRAC
DIV
FRAC
DIV
Y7
REG 15,16,17
REG 18,19, 20
Figure 47. Device Register Map
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Register Maps (continued)
Table 17. Register 0
BIT
BIT NAME
15:10
RESERVED
These bits must be set to 0
LF_C3[2:0]
PLL Internal Loop Filter
(C3)
PLL Internal Loop Filter Capacitor (C3) Selection
000 → 35 pF
001→ 112.5 pF
010 → 177.5 pF
011 → 242.5 pF
100 → 310 pF
101 → 377.5 pF
110 → 445 pF
111 → 562.5 pF
PLL Internal Loop Filter
(R3)
PLL Internal Loop Filter Resistor (R3) Selection
000 → 10 Ω
001 → 30 Ω
010 → 60 Ω
011 → 100 Ω
100 → 530 Ω
101→ 1050 Ω
110 → 2080 Ω
111 → 4010 Ω
9:7
6:4
LF_R3[2:0]
3:1
PLL_ICP[2:0]
0
RESERVED
RELATED BLOCK
PLL Charge Pump
DESCRIPTION/FUNCTION
PLL Charge Pump Current Setting
000 → 500 µA
001 → 1.0 mA
010 → 1.5 mA
011 → 2.0 mA
100 → 2.5 mA
101 → 3.0 mA
110 → 3.5 mA
111→ 4.0 mA
This bit is tied to one statically, and it is recommended to set to 1
when writing to register.
Table 18. Register 1
BIT
BIT NAME
RELATED BLOCK
15:2
PLL_REFDIV[13:0]
PLL Reference Divider
1:0
PLL_FBDIV1[9:8]
DESCRIPTION/FUNCTION
PLL Reference 14-b Divider Selection
(Divider value is register value +1)
PLL Feedback Divider 1 PLL Feedback 10-b Divider Selection, Bits 9:8
Table 19. Register 2
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:8
PLL_FBDIV1[7:0]
PLL Feedback Divider 1
PLL Feedback 10-b Divider Selection, Bits 7:0
(Divider value is register value +1)
7:0
PLL_FBDIV0[7:0]
PLL Feedback Divider 0
PLL Feedback 8-b Divider Selection
(Divider value is register value +1)
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Table 20. Register 3
BIT
BIT NAME
15:13
RESERVED
RELATED BLOCK
12
ST1_SEL_REFCLK
Reference clock status enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
11
ST1_LOR_EN
Loss-of-reference Enable on Status 1 pin:
0 → Disable"
1 → Enable (See Table 12 for full description)
10
ST1_PLLLOCK_EN
PLL Lock Indication Enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
These bits must be set to 0
Device Status
9
ST0_SEL_REFCLK
Reference clock status enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
8
ST0_LOR_EN
Loss-of-reference Enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
7
ST0_PLLLOCK_EN
PLL Lock Indication Enable on Status 0 pin:"
0 → Disable
1 → Enable (See Table 12 for full description)
6
RSTN
Device Reset
Device Reset Selection:
0 → Device In Reset (retains register values)
1 → Normal Operation
5
SYNCN
Output Divider
Output Channel Dividers Synchronization Enable:
0 → Forces synchronization
1 → Exits synchronization
4
ENCAL
PLL/VCO
3:2
1:0
54
DESCRIPTION/FUNCTION
PLL/VCO Calibration Enable:
0 → Disable
1 → Enable
PS_B[1:0]
PLL Prescaler 1 Integer Divider Selection:
00 → Divide-by-4
01→ Divide-by-5
PLL Prescaler Divider B
10 → Divide-by-6
11 → RESERVED
used for Y2, Y3, Y6, and Y7
PS_A[1:0]
PLL Prescaler 0 Integer Divider Selection:
00 → Divide-by-4
01 → Divide-by-5
PLL Prescaler Divider A
10 → Divide-by-6
11 → RESERVED
used in PLL feedback, Y0, Y1, Y4, and Y5
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Table 21. Register 4
BIT
15:14
13
BIT NAME
RELATED BLOCK
12
SMUX_REF_SEL
11:8
CLK_PRI_DIV[3:0]
7:6
Smart MUX Pulse Width Selection. This bit controls the Smart MUX
delay and waveform reshaping.
00 → PLL Smart MUX Clock Delay and Reshape Disabled (default
in all pin modes)
01 → PLL Smart MUX Clock Delay Enable
10 → PLL Smart MUX Clock Reshape Enable
11 → PLL Smart MUX Clock Delay and Reshape Enable
SMUX_PW[1:0]
SMUX_MODE_SEL
Reference Input Smart
MUX
4:3
Primary Input Divider
SEC_SELBUF[1:0]
(1)
(2)
Primary Input (R) Divider Selection:
0000 → Divide by 1
1111 → Divide by 16
Secondary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → Crystal
Secondary input enable:
0 → Disable
1 → Enable
EN_SEC_CLK
PRI_SELBUF[1:0]
Primary Input
2
Smart MUX Mode Selection:
0 → Auto select
1 → Manual select
Note: in Auto select mode, both input buffers must be enabled. Set
R4.5 = 1 and R4.2 = 1
Smart MUX Selection for PLL Reference:
0 → Primary
1 → Secondary (only if REF_SEL pin is high)
This bit is ignored when smartmux is set to auto select (for example,
R4.13 = 0). See Table 12 for details.
Secondary Input
5
DESCRIPTION/FUNCTION
Primary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → LVCMOS
Primary input enable:
0 → Disable
1 → Enable
EN_PRI_CLK
1
SEC_SUPPLY
(1)
Secondary Input
0
PRI_SUPPLY
(2)
Primary Input
Supply voltage for secondary input:
0 → 1.8 V
1 → 2.5/3.3 V
Supply voltage for primary input:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_SEC supply voltage used.
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_PRI supply voltage used.
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Table 22. Register 5
BIT
BIT NAME
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8:7
RELATED BLOCK
Output Channel 1 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
SEL_DRVR_CH1[1:0]
Output Channel 1
6:5
EN _CH1[1:0]
4:3
SEL_DRVR_CH0[1:0]
0
(1)
56
EN_CH0[1:0]
SUPPLY_CH0_1
(1)
Output channel 1 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channel 0 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
Output Channel 0
2:1
DESCRIPTION/FUNCTION
Output Channels 0
and 1
Output channel 0 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channels 0 and 1 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 23. Register 6
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8
RESERVED
This bit must be set to 0
7:0
OUTDIV0_1[7:0]
Output Channels 0
and 1
DESCRIPTION/FUNCTION
Output channels 0 and 1 8-b output integer divider setting
(Divider value is register value +1)
Table 24. Register 7
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8:7
SEL_DRVR_CH3[1:0]
Output Channel 3 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
Output Channel 3
6:5
EN_CH3[1:0]
4:3
SEL_DRVR_CH2[1:0]
0
(1)
EN_CH2[1:0]
SUPPLY_CH2_3
(1)
Output channel 3 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channel 2 Type Selection:
00, 01 → LVDS
10 → CML"
11 → PECL
Output Channel 2
2:1
DESCRIPTION/FUNCTION
Output Channels 2
and 3
Output channel 2 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channels 2 and 3 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 25. Register 8
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8
RESERVED
This bit must be set to 0
7:0
OUTDIV2_3[7:0]
Output Channels 2
and 3
DESCRIPTION/FUNCTION
Output channels 2 and 3 8-b output integer divider setting
(Divider value is register value +1)
Table 26. Register 9
BIT
BIT NAME
15
RESERVED
14:13
OUTMUX_CH4[1:0]
Output MUX setting for output channel 4:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10
PRE_DIV_CH4[2:0]
Output channel 4 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q9.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1 (only for CDCM6208 with fVCO ≤ 2.4 GHz)
All other combinations reserved
9
EN_FRACDIV_CH4
Output channel 4 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH4
Output channel 4 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH4
Output channel 4 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH4
5
RESERVED
4:3
SEL_DRVR_CH4[2:0]
2:1
0
(1)
58
RELATED BLOCK
This bit must be set to 0
Output Channel 4
Output channel 4 positive-side LVCMOS enable:
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 4 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
Output channel 4 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH4[1:0]
SUPPLY_CH4
DESCRIPTION/FUNCTION
(1)
Output channel 4 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 27. Register 10
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV4[7:0]
3:0
FRACDIV4[19:16]
Output Channel 4
DESCRIPTION/FUNCTION
Output channel 4 8-b integer divider setting
(Divider value is register value +1)
Output channel 4 20-b fractional divider setting, bits 19 - 16
Table 28. Register 11
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV4[15:0]
Output Channel 4
DESCRIPTION/FUNCTION
Output channel 4 20-b fractional divider setting, bits 15 - 0
Table 29. Register 12
BIT
BIT NAME
15
RESERVED
DESCRIPTION/FUNCTION
This bit must be set to 0
OUTMUX_CH5[1:0]
Output MUX setting for output channel 5:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10
PRE_DIV_CH5[2:0]
Output channel 5 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q12.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208 with fVCO ≤ 2.4GHz)
All other combinations reserved
9
EN_FRACDIV_CH5
Output channel 5 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH5
Output channel 5 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH5
Output channel 5 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH5
5
RESERVED
4:3
SEL_DRVR_CH5[2:0]
14:13
2:1
0
(1)
RELATED BLOCK
Output Channel 5
This bit must be set to 0
Output channel 5 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
Output channel 5 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH5[1:0]
SUPPLY_CH5
Output channel 5 positive-side LVCMOS enable:
0 → Disable
1 → Enable
(1)
Output channel 5Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 30. Register 13
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV5[7:0]
3:0
FRACDIV5[19:16]
Output Channel 5
DESCRIPTION/FUNCTION
Output channel 5 8-b integer divider setting
(Divider value is register value +1)
Output channel 5 20-b fractional divider setting, bits 19-16
Table 31. Register 14
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV5[15:0]
Output Channel 5
DESCRIPTION/FUNCTION
Output channel 5 20-b fractional divider setting, bits 15-0
Table 32. Register 15
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12:10
PRE_DIV_CH6[2:0]
Output channel 6 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q15.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208V1 with fVCO ≤ 2.4GHz)
All other combinations reserved
9
EN_FRACDIV_CH6
Output channel 6 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH6
Output channel 6 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH6
Output channel 6 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH6
5
RESERVED
Output Channel 6
4:3
2:1
0
(1)
60
DESCRIPTION/FUNCTION
This bit must be set to 0
SEL_DRVR_CH6[1:0]
Output channel 6 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
Output channel 6 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH6[1:0]
SUPPLY_CH6
Output channel 6 positive-side LVCMOS enable:
0 → Disable
1 → Enable
(1)
Output channel 6 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 33. Register 16
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV6[7:0]
3:0
FRACDIV6[19:16]
Output Channel 6
DESCRIPTION/FUNCTION
Output channel 6 8-b integer divider setting
(Divider value is register value +1)
Output channel 6 20-b fractional divider setting, bits 19-16
Table 34. Register 17
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV6[15:0]
Output Channel 6
DESCRIPTION/FUNCTION
Output channel 6 20-b fractional divider setting, bits 15-0
Table 35. Register 18
BIT
BIT NAME
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
DESCRIPTION/FUNCTION
12:10
PRE_DIV_CH7[2:0]
Output channel 7 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q18.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208 with f VCO ≤ 2.4 GHz)
All other combinations reserved
9
EN_FRACDIV_CH7
Output channel 7 fractional divider enable: 0 → Disable, 1 →
Enable
8
LVCMOS_SLEW_CH7
Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow
7
EN_LVCMOS_N_CH7
Output channel 7 negative-side LVCMOS enable: 0 → Disable, 1 →
Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH7
5
RESERVED
4:3
SEL_DRVR_CH7[2:0]
Output channel 7 type selection:00 or 01 → LVDS, 10 → LVCMOS,
11 → HCSL
2:1
EN_CH7[1:0]
Output channel 7 enable: 00 → Disable, 01 → Enable, 10 → Drive
static low, 11 → Drive static high
0
(1)
RELATED BLOCK
SUPPLY_CH7
Output Channel 7
Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 →
Enable
This bit must be set to 0
(1)
Output channel 7 Supply Voltage Selection: 0 → 1.8 V, 1 → 2.5/3.3
V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 36. Register 19
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV7[7:0]
3:0
FRACDIV7[19:16]
Output Channel 7
DESCRIPTION/FUNCTION
Output channel 7 8-b integer divider setting
(Divider value is register value +1)
Output channel 7 20-b fractional divider setting, bits 19-16
Table 37. Register 20
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV7[15:0]
Output Channel 7
DESCRIPTION/FUNCTION
Output channel 7 20-b fractional divider setting, bits 15-0
Table 38. Register 21 (Read Only)
BIT
BIT NAME
15
RESERVED
This bit will read a 0
14
RESERVED
This bit will read a 0
13
RESERVED
This bit will read a 0
12
RESERVED
This bit will read a 0
11
RESERVED
This bit will read a 0
10
RESERVED
This bit will read a 0
9
RESERVED
This bit will read a 0
8
RESERVED
This bit will read a 0
7
RESERVED
This bit will read a 0
6
RESERVED
This bit will read a 0
5
RESERVED
This bit will read a 0
4
RESERVED
This bit will read a 0
3
RESERVED
This bit will read a 0
2
RELATED BLOCK
Indicates unlock status for PLL (digital):
0 → PLL locked
1 → PLL unlocked
Note: the external output signal on Status 0 or Status 1 uses a
reversed logic, and indicates "lock" with a VOH signal and unlock
with a VOL signaling level.
PLL_UNLOCK
Device Status
Monitoring
62
DESCRIPTION/FUNCTION
1
LOS_REF
Loss of reference input observed at input Smart MUX output in
observation window for PLL:
0 → Reference input present
1 → Loss of reference input
0
SEL_REF
Indicates Reference Selected for PLL:
0 → Primary
1 → Secondary
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Table 39. Register 40 (Read Only)
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
Ignore
14
RESERVED
Ignore
13
RESERVED
Ignore
12
RESERVED
Ignore
11
RESERVED
Ignore
10
RESERVED
Ignore
9
RESERVED
Ignore
8
RESERVED
Ignore
7
RESERVED
Ignore
6
RESERVED
Ignore
5:3
VCO_VERSION
Device Information
2:0
DIE_REVISION
DESCRIPTION/FUNCTION
Indicates the device version (Read only):
000 → CDCM6208V1
001 → CDCM6208V2
Indicates the silicon die revision (Read only):
00X --> Engineering Prototypes
010 --> Production Material
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Table 40. Default Register Setting for SPI/I2C Modes
64
Register
CDCM6208V1
CDCM6208V2
0
0x01B9
0x01B9
1
0x0000
0x0000
2
0x0018
0x0013
3
0x08F4
0x08F5
4
0x30EC
0x30EC
5
0x0132
0x0022
6
0x0003
0x0003
7
0x0022
0x0022
8
0x0003
0x0004
9
0x0202
0x0002
10
0x003B
0x0090
11
0x01EC
0x0000
12
0x0202
0x0002
13
0x003B
0x0090
14
0x01EC
0x0000
15
0x0002
0x0002
16
0x0040
0x0090
17
0x0000
0x0000
18
0x0002
0x0002
19
0x0040
0x0130
20
0x0000
0x0000
:
:
:
40
0xXX01
0xXX09
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output
clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers.
Timing
Packet
Accel
DR
PCIe
Core
Packet
network
SyncE
Eth
ern
et
TMS320TCI6616/18
DSP
AIF
ALT
CORE
FBADC
GPS receiver
1pps
IEEE1588 timing
extract
1pps
RXADC
TXDAC
DPLL
Ethernet
CDCM6208
Synthesizer
Mode
Server
9.2 Typical Applications
RF LO
CDCM6208
APLL
RF LO
Pico Cell Clocking
SRIO
Base Band DSP
Clocking
Figure 48. Typical Application Circuit
Figure 49. Typical Application Circuit
9.2.1 Design Requirements
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, a 10 GigEthernet). Fully estimating the clock jitter
impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR
bandwidth.
9.2.2 Detailed Design Procedures
9.2.2.1 Jitter Considerations in SERDES Systems
As shown in Figure 50, the bandwidth of TX and RX is the frequency range in which clock jitter adds without any
attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock
jitter with a 20 dB/dec or even steeper roll-off.
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Typical Applications (continued)
Parallel out
De-Serializer
Parallel in
Serializer
serial data with
embedded clock
TX PLL
RX PLL
c
/de
/ de
dB
c
flow=BWRX PLL
HTransfer(f) = HTXPLL * ( 1 - HRXPLL)
c
20
/de
dB
dB
/de
c
20
HTransfer(f)
fhigh=BWTX PLL
flow
flow=1.875MHz for 10GbE
RX REF
CLOCK
20
dB
1-HRXPLL(f)
20
TX REF
CLOCK
HTXPLL(f)
CDR
fhigh
fhigh=20MHz for 10GbE
Figure 50. Serial Link Jitter Budget Explanation
Example: SERDES link with KeyStone™ I DSP
The SERDES TX PLL of the TI KeyStone™ I DSP family (see Hardware Design Guide for KeyStone Devices
(SPRABI2)) for the SRIO interface has a 13-MHz PLL bandwidth (Low Pass Characteristic, see Figure 50). The
CDCM6208V2, pin-mode 27, was characterized in this example over Process, Voltage and Temperature (PVT)
with a low-pass filter of 13 MHz to simulate the TX PLL. The attenuation is higher or equal to 20 dB/dec;
therefore, the characterization used 20 dB/dec as worst case.
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Typical Applications (continued)
Table 41 shows the maximum total jitter over PVT with and without a low-pass filter.
Table 41. Maximum Total Jitter (1) Over PVT With and Without Low-Pass Filter
(1)
OUTPUT
FREQUENCY
[MHz]
MAX TJ [ps]
DSP SPEC
MAX TJ [ps]
WITHOUT LOW-PASS FILTER
MAX TJ [ps]
WITH 13-MHZ LOW-PASS
FILTER
Y0
122.88
56
9.43
8.19
Y2
30.72
56
9.60
7.36
Y3
30.72
56
9.47
7.42
Y4
156.25
(6 bit fraction)
56
57.66
17.48
Y5
156.25
(20 bit fraction)
56
76.87
32.32
Y6
100.00
56
86.30
33.86
Y7
66.667
300
81.71
35.77
Input signal: 250-fs RMS (Integration Range 12 kHz to 5 MHz)
Figure 51 shows the maximum Total Jitter with and without low-pass filter characteristic and the maximum TI
KeyStone™ I specification.
Figure 51. Maximum Jitter Over PVT
NOTE
Due to the damping characteristic of the DSP SERDES PLLs, the actual TJ data can be
worse.
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9.2.2.2 Jitter Considerations in ADC and DAC Systems
A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular
frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity.
The following test results were achieved connecting the CDCM6208 to ADC and DACs:
Figure 52. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49
Figure 53. IF = 60 MHz Fclk = 122.88 MHz CDCM6208 Driving ADC
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Observation: Up to an IF = 100 MHz, the ADC performance when driven by the CDCM6208 (Figure 53) is
similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering
(Figure 52).
Conclusion: Therefore, the CDCM6208 is usable for applications up to 100 MHz IF. For IF above 100 MHz, the
SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and other
outputs running at different integer frequencies.
NOTE
For crosstalk, TI highly recommends configuring both pre-dividers identically, otherwise
the SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.
245.76MHz DAC
driven from ³LGHDO VRXUFH´
(Wenzel oscillator buffered by HP8133A)
Ref -14.1 dBm
-20
* At t 5 dB
245.76MHz DAC
driven from CDCM6208
(no performance degradation observed)
* RBW 30 kHz
* VBW 300 kHz
* SWT 1 s
Ref -14.1 dBm
-20
-30
* RBW 30 kHz
* VBW 300 kHz
* SWT 1 s
-3 0
A
A
-4 0
-40
1 RM *
* At t 5 dB
1 RM *
CL R W R
-50
CLRWR
-5 0
-6 0
-60
-7 0
-70
-8 0
-80
NOR
NOR
-90
-9 0
-100
-1 0 0
-1 1 0
-110
Center 245.76 MHz
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spac ing
Al ternate Channel
Bandwidth
Spac ing
2.55 MHz/
3.84 MHz
3.84 MHz
5 MHz
3.84 MHz
10 MHz
W-CDMA 3GPP FWD
Powe r
Span 25.5 MHz PRN
- 9 . 39
d Bm
L owe r
- 72 . 81
dB
Up p e r
- 72 . 40
dB
L owe r
- 77 . 79
dB
Up p e r
- 78 . 31
dB
Center 245.76 MHz
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spac ing
Al ternate Channel
Bandwidth
Spac ing
Span 25.5 MHz PRN
3.84 MHz
2.55 MHz/
W-CDMA 3GPP FWD
Powe r
3.84 MHz
5 MHz
L owe r
- 73 . 12
Up p e r
- 73 . 06
dB
L owe r
- 79 . 22
dB
Up p e r
- 79 . 19
dB
3.84 MHz
10 MHz
- 9 . 40
d Bm
dB
Figure 54. DAC Driven by Lab Source and CDCM6208 in Comparison (Performance Identical)
Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208 compared to
driving the DAC with a perfect lab source. Therefore, the CDCM6208 provides sufficient low noise to drive a
245.76 MHz DAC.
9.2.2.3 Configuring the PLL
The CDCM6208 allows configuring the PLL to accommodate various input and output frequencies either through
an I2C or SPI programming interface or in the absence of programming, the PLL can be configured through
control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop Filter,
Feedback Divider, Prescaler Divider, and Output Dividers.
For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met when using
primary input for the reference clock, and the condition in Equation 2 has to be met when using secondary input
for the reference clock.
f
f
PRI_REF =
VCO
(M × R)
(N × PS_A)
(1)
f
f
SEC_REF =
VCO
M
(N × PS_A)
(2)
In Equation 1 and Equation 2, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the
reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the
feedback divider, and PS_A the prescaler divider A.
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The output frequency, ƒOUT, is a function of ƒVCO, the prescaler A, and the output divider (O), and is given by
Equation 3. (Use PS_B in for outputs 2, 3, 6, and 7).
f
OSC
=
f
OUT (O × PS_A)
(3)
When the output frequency plan calls for the use of some output dividers as fractional values, the following steps
are needed to calculate the closest achievable frequencies for those using fractional output dividers and the
frequency errors (difference between the desired frequency and the closest achievable frequency).
• Based on system needs, decide the frequencies that need to have best possible jitter performance.
• Once decided, these frequencies need to be placed on integer output dividers.
• Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the
common divisor algorithm.
• Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider,
input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the
prescaler divider.
• Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support
the output frequencies that are not part of the common frequency plan from the common divisor algorithm
already worked out.
• For each fractional divider value, try to represent the fractional portion in a 20-bit binary scheme, where the
first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is
represented as 0.125 and so on. Continue this process until the entire 20-bit fractional binary word is
exhausted.
• Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of
the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the
mathematical function of the frequency out of the prescaler divider divided by the achievable fractional
divider.
• The frequency error can then be calculated as the difference between the desired frequency and the closest
achievable frequency.
9.2.2.4 Programmable Loop Filter
The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop
bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in
Figure 55 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.
R2
C2
C1
ELF
R3
C3
Figure 55. CDCM6208 PLL Loop Filter Topology
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9.2.2.5 Loop filter Component Selection
The loop filter setting and external resistor selection is important to set the PLL to best possible bandwidth and to
minimize jitter. A high bandwidth (≥ 100 kHz) provides best input signal tracking and is therefore desired with a
clean input reference (synthesizer mode). A low bandwidth (≤ 1 kHz) is desired if the input signal quality is
unknown (jitter cleaner mode). TI provides a software tool that makes it easy to select the right loop filter
components. C1, R2, and C2 are external loop filter components, connected to the ELF pin. The 3 rd pole of the
loop filter is device internal with R3 and C3 register selectable.
9.2.2.6 Device Output Signaling
LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and
drives a signal swing identical to LVDS (approximately 350 mV). The output slew rate is faster than standard
LVDS for best jitter performance. The LVDS-like outputs should be AC-coupled when interfacing to a LVDS
receiver. See reference schematic Figure 69 for an example. The supply voltage for outputs configured LVDS
can be selected freely between 1.8 V and 3.3 V.
LVPECL-like: Outputs Y[3:0] support LVPECL-like signaling. The actual output stage uses a CML structure but
drives the same signal amplitude and rise time as true emitter coupled logic output stages. The LVPECL-like
outputs should be AC-coupled, and contrary to standard PECL designs, no external termination resistor to VCC2V is used (fewer components for lowest BOM cost). See reference schematic Figure 69 for an example. The
supply voltage for outputs configured LVPECL-like is recommended to be 3.3 V, though even 1.8 V provides
nearly the same output swing and performance at much lower power consumption.
CML: Outputs Y[3:0] support standard CML signaling. The supply voltage for outputs configured CML can be
selected freely between 1.8 V and 3.3 V. A true CML receiver can be driven DC coupled. All other differential
receiver should connected using AC coupling. See reference schematic Figure 69 for a circuit example.
HCSL: Outputs Y[7:4] support HCSL signaling. The supply voltage for outputs configured HCSL can be selected
freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50-Ω termination to GND.
See the reference schematic for an example.
CMOS: Outputs Y[7:4] support 1.8-V, 2.5-V, and 3.3-V CMOS signaling. A fast or reduced slew rate can be
selected through register programming. Each differential output port can drive one or two CMOS output signals.
Both signals are in-phase, meaning their phase offset is zero degrees, and not 180˚. The output swing is set by
providing the according supply voltage (for example, if VDD_Y4=2.5 V, the output swing on Y4 will be 2.5-V
CMOS). Outputs configured for CMOS should only be terminated with a series-resistor near the device output to
preserve the full signal swing. Terminating CMOS signals with a 50-Ω resistor to GND would reduce the output
signal swing significantly.
9.2.2.7 Integer Output Divider (IO)
Each integer output divider is made up of a continuous 10-b counter. The output buffer itself contributes only little
to the total device output jitter due to a low output buffer phase noise floor. The typical output phase noise floor
at an output frequency of 122.88 MHz, 20-MHz offset from the carrier measures as follows: LVCMOS: –157.8
dBc/Hz, LVDS: –158 dBc/Hz, LVPECL: –158.25 dBc/Hz, HCSL: –160 dBc/Hz. Therefore, the overall contribution
of the output buffer to the total jitter is approximately 50 fs-rms (12 k – 20 MHz). An actual measurement of
phase noise floor with different output frequencies for one nominal yielded the results in Table 42:
Table 42. Output Noise Floor
fOUT
LVDS (Y0)
PECL (Y0)
CML (Y0)
HCSL (Y4)
CMOS 3p3V (Y7)
737.28 MHz
–154.0 dBc/Hz
–154.8 dBc/Hz
–154.4 dBc/Hz
–153.1 dBc/Hz
–150.9 dBc/Hz
368.64 MHz
–157.0 dBc/Hz
–155.8 dBc/Hz
–156.4 dBc/Hz
–153.9 dBc/Hz
–153.1 dBc/Hz
184.32 MHz
–157.3 dBc/Hz
–158.6 dBc/Hz
158.1 dBc/Hz
–154.7 dBc/Hz
–156.2 dBc/Hz
92.16 MHz
–161.2 dBc/Hz
–161.6 dBc/Hz
–161.4 dBc/Hz
–155.2 dBc/Hz
–159.4 dBc/Hz
46.08 MHz
–162.2 dBc/Hz
–165.0 dBc/Hz
–163.0 dBc/Hz
–154.0 dBc/Hz
–162.8 dBc/Hz
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9.2.2.8 Fractional Output Divider (FOD)
The CDCM6208 incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer
output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated
frequencies. The fractional output divider architecture is shown in Figure 56.
Pre-Scaler PS_A or PS_B
VCO
2.39-2.55GHz
2.94-3.13GHz
÷ 4, 5 or 6
Pre-Scaler
output clock
398-800MHz
Reg 3.4:0
FracDiv Pre Divider
÷ 1, 2 or 3
Limit: 200-400MHz
Reg 9.12:10
Reg 12.12:10
Reg 15.12:10
Reg 18.12:10
Integer Divider
÷ 1 to 256
Reg 10.11:4
Reg 13.11:4
Reg 16.11:4
Reg 19.11:4
Fractional division
.xxx
Reg 10.3:0 + Reg 11
Reg 13.3:0 + Reg 14
Reg 16.3:0 + Reg 17
Reg 19.3:0 + Reg 20
Fractional Divider (simplified)
Figure 56. Fractional Output Divider Principle Architecture (Simplified Graphic, not Showing Output
Divider Bypass Options)
The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any
frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider
block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep
enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency
in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The
fractional values available are all possible 20-b representations of fractions within the following range:
• 1.0 ≤ ƒracDIV ≤ 1.9375
• 2.0 ≤ ƒracDIV ≤ 3.875
• 4.0 ≤ ƒracDIV ≤ 5.875
• x.0 ≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254
• 254.0 ≤ ƒracDIV ≤ 255.875
• 256.0 ≤ ƒracDIV ≤ 256.99999
The CDCM6208 user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend
frequency planning is recommended.
The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on
which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than
exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from
50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths
(approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (<
1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer
mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional
divider enable bit, which engages the higher performing integer divider.
9.2.2.9 Output Synchronization
Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208, this signal
comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output
synchronization is to toggle the SYNCN pin. When SYNC is asserted (VSYNCN ≤ VIL), all outputs are disabled
(high-impedance) and the output dividers are reset. When SYNC is de-asserted (VSYNCN ≥ VIH), the device first
internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on
simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the
SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles.
For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.
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The SYNC feature is particularly helpful in systems with multiple CDCM6208. If SYNC is released simultaneously
for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to
identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew uncertainty
due to sync remains ±2 clock cycles.
Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with
the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values
(PS_A=PS_B).
PS_A
1
2
3
4
5
6
7
8
9
10
11
12
One pre-scaler clock cycle
uncertainty, of when the
output turns on for one
device in one particular
configuration
SYNCN
Outputs tristates
Y0
Possibility (A)
Y0
Outputs turned on
Possibility (B)
Figure 57. SYNCN to Output Delay Uncertainty
9.2.2.10 Output Mux on Y4 and Y5
The CDCM6208 device outputs Y4 and Y5 can either be used as independent fractional outputs or allow
bypassing of the PLL in order to output the primary or secondary input signal directly.
9.2.2.11 Staggered CLK Output Power Up for Power Sequencing of a DSP
DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term
reliability problems, TI recommends avoiding any clock signal to the DSP until the DSP power rail is also
powered up. This can be achieved in two ways using the CDCM6208:
1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on
outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power
supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208 output will
remain disabled until the DSP rails ramps up as well. Figure 58 shows the turnon behavior.
Figure 58. Sequencing the Output Turnon Through Sequencing the Output Supplies
Output Y2 Powers Up While Output Y0 is Already Running
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10 Power Supply Recommendations
10.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
10.1.1 Mixing Supplies
The CDCM6208 incorporates a very flexible power supply architecture. Each building block has its own power
supply domain, and can be driven independently with 1.8 V, 2.5 V, or 3.3 V. This is especially of advantage to
minimize total system cost by deploying multiple low-cost LDOs instead of one, more-expensive LDO. This also
allows mixed IO supply voltages (for example, one CMOS output with 1.8 V, another with 3.3 V) or interfacing to
a SPI/I2C controller with 3.3-V supply while other blocks are driven from a lower supply voltage to minimize
power consumption. The CDCM6208 current consumption is practically independent of the supply voltage, and
therefore a lower supply voltage consumes lower device power. Also note that outputs Y3:0 if used for PECL
swing will provide higher output swing if the according output domains are connected to 2.5 V or 3.3 V.
10.1.2 Power-On Reset
The CDCM6208 integrates a built-in POR circuit, that holds the device in power down until all input, digital, and
PLL supplies have reached at least 1.06 V (minimum) to 1.24 V (maximum). After this power-on release, device
internal counters start (see Device Power-Up Timing) followed by device calibration. While the device digital
circuit resets properly at this supply voltage level, the device is not ready to calibrate at such a low voltage.
Therefore, for slow power-up ramps, the counters expire before the supply voltage reaches the minimum voltage
of 1.71 V. Hence for slow power-supply ramp rates, it is necessary to delay calibration further using the PDN
input.
10.1.3 Slow Power-Up Supply Ramp
No particular power supply sequence is required for the CDCM6208. However, it is necessary to ensure that
device calibration occurs AFTER the DVDD supply as well as the VDD_PLL1, VDD_PLL2, VDD_PRI, and
VDD_SEC supply are all operational, and the voltage on each supply is higher than 1.45. This is best realized by
delaying the PDN low-to-high transition. The PDN input incorporates a 50-kΩ resistor to DVDD. Assuming the
DVDD supply ramp has a fixed time relationship to the slowest of all PLL and input power supplies, a capacitor
from PDN to GND can delay the PDN input signal sufficiently to toggle PDN low-to-high AFTER all other supplies
are stable. However, if the DVDD supply ramps much sooner than the PLL or input supplies, additional means
are necessary to prevent PDN from toggling too early. A premature toggling of PDN would possibly result in
failed PLL calibration, which can only be corrected by re-calibrating the PLL by either toggling PDN or RESET
high-low-high.
VDVDD
PDN
1.8V ,
2.5V , or
3.3V
1.3V
50k
0V
VDD_PLL 1, VDD_ PLL2, VDD_PRI,
VDD_SEC all must rise before PDN toggles high
VDVDD
t? 0
CPDN
VDVDD
CDCM6208
VIH( min)
VPDN
0V
Figure 59. PDN Delay When Using Slow Ramping Power Supplies (Supply Ramp > 50 ms)
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Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued)
10.1.4 Fast Power-Up Supply Ramp
If the supply ramp time for DVDD, VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC are faster than 50 ms from
0 V to 1.8 V, no special provisions are necessary on PDN; the PDN pin can be left floating. Even an external
capacitor to GND can be omitted in this circumstance, as the device delays calibration sufficiently by internal
means.
10.1.5 Delaying VDD_Yx_Yy to Protect DSP IOs
DSPs and other highly integrated processors sometimes do not permit any clock signal to be present until the
DSP power supply for the corresponding IO is also present. The CDCM6208 allows to either sequence output
clock signals by writing to the corresponding output enable bit through SPI/I2C, or alternatively it is possible to
connect the DSP IO supply and the CDCM6208 output supply together, in which case the CDCM6208 output will
not turn on until the DSP supply is also valid. This second implementation avoids SPI/I2C programming.
10.2 Device Power-Up Timing
Before the device outputs turn on after power up, the device goes through the following initialization routine:
Table 43. Power-Up Timing Procedure
STEP
DURATION
COMMENTS
Step 1: Power up ramp
Depends on customer supply
ramp time
The POR monitor holds the device in power-down or reset until the
VDD supply voltage reaches 1.06 V (min) to 1.26 V (max)
Step 2: XO startup (if crystal is
used)
Depends on XTAL. Could be
several ms;
For NX3225GA 25 MHz typical
XTAL startup time measures 200
µs.
This step assumes RESETN = 1 and PDN = 1.The XTAL startup
time is the time it takes for the XTAL to oscillate with sufficient
amplitude. The CDCM6208 has a built-in amplitude detection circuit,
and holds the device in reset until the XTAL stage has sufficient
swing.
Step 3: Ref Clock Counter
64k Reference clock cycles at
PFD input
This counter of 64 k clock cycles needs to expire before any further
power-up step is done inside the device. This counter ensures that
the input to the PFD from PRI or SEC input has stabilized in
frequency. The duration of this step can range from 640 µs (fPFD=
100 MHz) to 8 sec (8 kHz PFD).
Step 4: FBCLK counter
64k FBCLK cycles with CW=32;
The duration is similar to Step 3,
or can be more accurately
estimated as:
V1: approximately 64k x PS_A x
N/2.48 GHz
V2: approximately 64k x PS_A x
N/3.05 GHz
The Feedback counter delays the startup by another 64k PFD clock
cycles. This is so that all counters are well initialized and also ensure
additional timing margin for the reference clock to settle. This step
can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz).
Step 5: VCO calibration
128k PFD reference clock cycles
This step calibrates the VCO to the exact frequency range, and
takes exactly 128k PFD clock cycles. The duration can therefore
range from 1280 µs (fPFD= 100 MHz) to 16 sec (f PFD= 8 KHz).
Step 6: PLL lock time
approximately 3 x LBW
The Outputs turn on immediately after calibration. A small frequency
error remains for the duration of approximately 3 x LBW (so in
synthesizer mode typically 10 µs). The initial output frequency will be
lower than the target output frequency, as the loop filter starts out
initially discharged.
Step 7: PLL Lock indicator high
approximately 2305 PFD clock
cycles
The PLL lock indicator if selected on output STATUS0 or STATUS1
will go high after approximately 2048 to 2560 PFD clock cycles to
indicate PLL is now locked.
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Y4n
Device outputs held static low
( YxP=low, Yxn=high)
Y 4 ( HCSL)
Outputs tristated
Y4p
Step5
VCO CAL
Step2
XO startup
Step3
Ref Clk Cntr
Step4
FBCLK Cntr
Step6 : PLL lock time
From here
on Device
is locked
RESETN held low
1.8V
1.05V
Step1 : Pwr up
Figure 60. Power-Up Time
Figure 61. XTAL Start-Up Using NX3225GA 25 MHz (Step 2)
76
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Step 7
Time from PLL Lock
to LOCK signal asserting high on STATUS0 = 78…s
4=3.5%
140ns
250ns
Figure 62. PLL Lock Behavior (Step 6)
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10.3 Power Down
When the PDN pin = 0, the device enters a complete power down mode with a current consumption of no more
than 1 mA from the entire device. Exiting power down resets the entire device and defaults all registers. It is
recommended to connect a capacitor between the PDN pin and GND to implement a RC time delay and ensure
the digital and PLL related power supplies are stable before the device calibration sequences is initiated. Refer to
Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains for more details.
10.4 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
Many system designs become increasingly more sensitive to power supply noise rejection. To simplify design
and cost, the CDCM6208 has built-in internal voltage regulation, which improves the power supply noise
rejection over designs with no regulators. As a result, the following output rejection is achieved:
-50
-55
9.2 ps
-60
2.9 ps
-70
-75
0.92 ps
Jitter
PSRR (dBc)
-65
-80
0.29 ps
-85
-90
0.092 ps
-95
-100
100
1000
10K
100k
1M
10M
Frequency (Hz)
Figure 63. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format
fOUT = 122.88 MHz
VDD Supply Noise = 100 mVpp
The DJ due to PSRR can be estimated using Equation 4:
(4)
Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the
according output jitter for a 122.88-MHz output signal with LVDS signaling could be estimated with DJ = 0.7 ps.
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11 Layout
11.1 Layout Guidelines
Employing the thermally enhanced printed-circuit board layout shown in Figure 64 insures good thermal
performance of the solution. Observing good thermal layout practices enables the thermal pad on the backside of
the VQFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
Figure 64 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via pattern facilitates both considerations.
Figure 64. Recommended PCB Layout of CDCM6208
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Layout Guidelines (continued)
Figure 65 shows the conceptual layout detailing the recommended placement of power supply bypass
capacitors. If the capacitors are mounted on the back side, 0402 components can be employed; however,
soldering to the Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size
capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply
on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to
the ground plane.
Figure 65. PCB Conceptual Layouts
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11.2 Reference Schematics
5
4
STATUS1_PIN0
REG_CAP
C82
3
SDI_SDA_PIN1
SDO_AD0_PIN2 SCS_AD1_PIN3
2
Place 10uF close to
device pin to
minimize series
resistance
10uF/6.3V
General Power supply related note:
Place all 0.1uF bypass caps as close as possible to device pins.
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
BLM15HD102SN1D
1 L1
2
DNI
D
DVDD
PWR_MONITO
R
1
SCL_PIN4
DVDD
DVDD
DVDD
VDD_PLL_A
DVDD
C298 C283
100p
0.1uF F
C281
1uF
10uF
C288
C279
VDD_OUT01
C295
0.1uF
C275
0.1uF
1uF
C289
VDD_PLL
VDD_PLL_A
REG_CAP
ELF
PDN
SYNCN
VDD_OUT23
RESET_PWR
STATUS1_PIN0
STATUS0
DVDD
SI_MODE1
0.1uF
C284
0.1uF
C276
0.1uF
1uF
VDD_OUT4
C
37
VDD_PLL1
VDD_PLL2
38
39
REG_CAP
ELF
VDD_VCO
40
41
42
SYNCN
43
44
RESETN/PWR
STATUS1/PIN0
STATUS0
45
46
47
SI_MODE1
DVDD
PDN
Y5_P
VDD2_Y2_Y3
VDD_Y4
Y4_P
Y4_N
36
0.1uF
35
0.1uF
34
33
0.1uF
32
0.1uF
31
30
DSP_CLK7N
C291
VDD_OUT7
0.1uF
DSP_CLK6N
0.1uF
28
0.1uF
27
C286
0.1uF
1uF
C292
VDD_OUT6
0.1uF
C299
C300
0.1uF
1uF
B
VDD_OUT7
DSP_CLK5N
C301
DSP_CLK5P
C303
0.1uF
C302
0.1uF
1uF
VDD_OUT4
26
0.1uF
25
0.1uF
DSP_CLK4N
VDD_PRI_IN
DSP_CLK4P
C304
C305
0.1uF
1uF
VDD_SEC_IN
DVDD
VDD_OUT23
DSP_CLK3N
DSP_CLK3P
DSP_CLK2N
DSP_CLK2P
VDD_OUT23
VDD_OUT01
DSP_CLK1P
DSP_CLK1N
DSP_CLK0N
DSP_CLK0P
VDD_OUT01
C287
VDD_OUT6
DSP_CLK6P
C274
0.1uF
C307
C293
C308
0.1uF
1uF
Rev
01
CDCM6208 Reference Schematic
3
December, 2011
2
A
1uF
Title
Date:
4
1uF
VDD_OUT5
29
C
VDD_OUT5
DSP_CLK7P
A
5
C277
0.1uF
24
Y3_P
23
0.1uF
Y3_N
22
0.1uF
Y2_N
21
0.1uF
Y2_P
20
0.1uF
VDD1_Y2_Y3
19
SEC_REFN
VDD2_Y0_Y1
SEC_REFP
18
VDD_SEC_REF
Y5_N
Y1_P
PRI_REFN
13
SEC_REFN
U1
PRI_REFP
Y1_N
12
VDD_Y5
17
11
SEC_REFP
CDCM6208
VDD_PRI_REF
0.1uF
10
VDD_SEC_IN
VDD_Y6
Y0_N
9
PRI_REFN
REF_SEL
16
8
PRI_REFP
Y6_P
0.1uF
7
VDD_PRI_IN
VDD_Y7
SCL/PIN4
15
6
REF_SEL
Y7_P
Y6_N
0.1uF
5
SCL_PIN4
C285
0.1uF
Y7_N
SCS/AD1/PIN3
Y0_P
4
SCS_AD1_PIN3
SDO/AD0/PIN2
14
3
SDO_AD0_PIN2
SDI/SDA/PIN1
0.1uF
2
SDI_SDA_PIN1
SI_MODE0
VDD1_Y0_Y1
1
POWER_PAD
49
48
C290
SI_MODE0
B
C282
D
0.1uF
RESET_PWR
Device Reset can connect to
power monitor or left
unconnected; pin has internal
150k pullup
VDD_PLL
C280
Sheet
of
1
3
1
Figure 66. Schematic Page 1
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Reference Schematics (continued)
5
4
3
2
1
PRIMARY REFERENCE INPUT
LOOP FILTER
C_PRI
_P
CLKIN_PRIP
PRI_REFP
1uF
D
49.9
C2
R2
R_PRI_PUP
ELF
VDD_PRI_ IN
D
R 83
C296
49.9
C_PRI_N
C1
1uF
R_PRI_PDN
R 84
CLKIN_PRIN
PRI_REFN
1uF
Loop Filter
The following input biasing is recommended :
Examples
AC coupled differential signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]= 01 and/or Reg4[4:3]= 01 (LVDS),
C
target VBIAS=1.2V , therefore
set R_PRI_PUP=5.5k , RPRI_PDN=3.14k
for VDD_PRI/SEC=1.8V:
DC coupled LVDS signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]= 01 and/or Reg4[4:3]= 01 (LVDS),
R _PRI_PUP=5.5k , RPRI_PDN=3.14k
replace C_PRI_P=C_PRI_N =0
for VDD_PRI/SEC=1.8V:
DC coupled 3.3V CMOS signals
:
Connect VDD_SEC_IN=3.3V,
select Reg4[7:6]= 10 and/or Reg 4[4:3]= 10 (CMOS),
R 83,R84,R85 , & R 86=DNI , replace C_PRI_P=C_PRI_N =0
for 1.8V CMOS signals
:
Connect VDD_SEC_IN =1.8V :
CDCM6208V 2:
With C1=470pF , R 2=560 , C2=100nF and
Internal components R3=100 , C3=242.5pF,
PF
C
f =30.72MHz,and I =2.5mA:
D bandwidth~ ( 300
PkHz )
Loop
target V BIAS =0.9 V, therefore
set R_PRI_PUP=5.5k, RPRI_PDN=5.5k
R _PRI_PUP=5.5k , RPRI_PDN=3.14k
25MHz
4
1
GND0
3
1
GND1
3
CDCM6208V 2:
With C1=5 F, R 2=100 , C2=100 F and
Internal components R3=4.01k , C 3=662.5pF,
PF
C
f =80kHz , and I =500 A:
D bandwidth~P( 100Hz)
Loop
2
NX3225GA
Use of Crystal on secondary reference input (VDD_SEC_,1 YROWDJH LV GRQ¶W FDUH):
select Reg4[7:6]= 11( XTAL),
set R87=DNI , R89=DNI , R72=0 , R 73=0
C
Jitter cleaner mode( low loop bandwidth):
CDCM6208V 1:
With C1=4.7 F, R 2=145 , C2=47 F and
Internal components R3=4.01k , C 3=662.5pF,
fPF=40kHz , and IC =500 A:
D bandwidth~P( 40Hz)
Loop
Y1
DC coupled CML only (VDD _PRI/ 6(& YROWDJH LV GRQ¶W FDUH)
:
select Reg4[7:6]= 00 and/or Reg4[4:3]= 00 (CML),
set R_PRI_PUP=0 , RPRI_PDN=DNI ,
Replace CPRI_ P=0 , C _PRI_N=0
B
:
Synthesizer mode(high loop bandwidth)
CDCM6208V 1:
With C1=100pF , R 2=500 , C2=22nF and
Internal components R3=100 , C3=242.5pF,
PF
C
f =25MHz, and I =2.5mA:
D bandwidth~ (P300kHz )
Loop
B
C27
4pF
C 28
4pF
R73
DNI
R72
SECONDARY REFERENCE INPUT
DNI
C29
0.0
CLKIN_SECP
SEC_REFP
R87
1uF
R_SEC_PUP
49.9
VDD_SEC_IN
R 85
C297
49.9
A
C30
A
R_SEC_PDN
1uF
R86
0.0
CLKIN_SECN
SEC_REFN
R 89
Title
1uF
Rev
CDCM
Date:
5
4
3
December , 2011
2
6208
01
Reference Schematic
Sheet
of
2
3
1
Figure 67. Schematic Page 2
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5
4
2
3
1
3.3V Power Supply
C37
510pF
D
OUT2
NR
6
3
FB
R41
10k
4
GND
IN2 7
IN1 8
VDD_PLL
R2p5
DNI
R3p3
DNI
2
0
2p5V
2
DNI
3p3V
2
DNI
1p8V
VDD_OUT6
1p8V
2p5V
1
R1p8
0
R40
30.9k
9 GND_PAD
5
2
2
1
2 1
3p3V
TPS7A8001
OUT1
EN
+5V
D
10uF/6.3V
C38
0.01uF
U6
C34
C39
10uF/6.3V
3p3V
MANY VIAS with Heat Sink
VDD_OUT01
2
0
2
DNI
2
DNI
2
0
2
0
1p8V
2p5V
2
DNI
2p5V
3p3V
2
DNI
3p3V
1p8V VDD_PRI_IN
2
0
1p8V
1p8V
VDD_OUT7
2.5V Power Supply
2p5V
B
DNI
2
DNI
2
0
2
DNI
2
DNI
3p3V
DNI
1p8VVDD_SEC_IN
2
0
2p5V
2
DNI
3p3V
2
DNI
2
0
2p5V
2
DNI
3p3V
2
DNI
1p8V
DVDD
VDD_OUT4, 5, 6, and VDD_OUT7 supply setting
reflect the CMOS signal output swing
C50
750pF
2p5V
3p3V
1p8V
R55
21k
1
5
2
OUT2
6
3
FB
R54
10k
4
GND
GND_PAD
2
DNI
2
9
0
2
2 1
2
2p5V
1
DNI
2p5V
NR
IN2 7
IN1 8
+5V
C35
10uF/6.3V
C48
0.01uF
U7
C
C49
10uF/6.3V
MANY VIAS with Heat Sink
3p3V
1p8V
B
2p5V
1.8V Power Supply
3p3V
If SPI or I2C is used, set DVDD to the same
supply voltage (e.g. 1.8V, 2.5V, or 3.3V)
2
VDD_OUT5
DNI
2
C53
1300pF
R58
12.5k
2 1
VDD_OUT4
2
TPS7A8001
OUT1
EN
Every supply can individually be connected to either 1.8V, 2.5V, or 3.3V. It is also possible to run all
IO from one single supply at 1.8V, 2.5V, or 3.3V.
3 FB
4 GND
1
R56
10k
1p8V
TPS7A8001
1 OUT1
5
EN
2 OUT2
NR 6
9 GND_PAD
VDD_OUT23
2
C
IN2 7
IN1 8
U8
+5V
C36
10uF/6.3V
C51
0.01uF
C52
10uF/6.3V
MANY VIAS with Heat Sink
A
A
Title
5
4
3
2
Date:
Rev
01
CDCM6208 Reference Schematic
December, 2011
Sheet
1
3
of
3
Figure 68. Schematic Page 3
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5
4
3
HCSL connection example (DC coupled)
2
1
LVDS or LVPECL connection example (AC coupled)
RS(P)
D
Y4-7_HCSL_P
0
TX-line 50
PCIe_PHY_P
TX-line 50
PCIe_PHY_N
TX-line 50
Y0-7 LVDS_P
RS(N)
Y4-7_HCSL_N
0
49.9
Diff_in_P
1uF
D
DSP with receiver input
termination and self-biasing
TX-line 50
Y0-7 LVDS_N
49.9
Diff_in_N
1uF
PICe phy
Outputs 4 to 7 have option for HCSL, LVCMOS, LPCML
For HCSL, install 50 ohm termination resistors and adjust
C
series resistor between 0 and 33 ohms to improve ringing.
LVDS or LVPECL connection example (AC coupled)
TX-line 50
Y0-7 LVDS_P
Diff_in_P
1uF
DSP without receiver input
termination and self-biasing
B
TX-line 50
Y0-7 LVDS_N
B
Diff_in_N
1uF
49.9
49.9
Vbias
100n
A
A
Title
CDCM6208 Reference Schematic (Extra: output termination)
Date:
5
4
3
December, 2011
2
Sheet
extra
Rev
01
of
1
Figure 69. Schematic Page 4
84
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Hardware Design Guide for KeyStone Devices (SPRABI2)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
KeyStone, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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85
PACKAGE OPTION ADDENDUM
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16-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCM6208V1HRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CM6208V1H
CDCM6208V1RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCM6208V1
CDCM6208V1RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCM6208V1
CDCM6208V2RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCM6208V2
CDCM6208V2RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCM6208V2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jan-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCM6208V1HRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
CDCM6208V1RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CDCM6208V1RGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CDCM6208V2RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CDCM6208V2RGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCM6208V1HRGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
CDCM6208V1RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
CDCM6208V1RGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
CDCM6208V2RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
CDCM6208V2RGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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