PD - 95488
AUTOMOTIVE MOSFET
Features
O
O
O
O
O
O
O
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
IRF2807ZPbF
IRF2807ZSPbF
IRF2807ZLPbF
HEXFET® Power MOSFET
D
VDSS = 75V
RDS(on) = 9.4mΩ
G
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety of other applications.
ID = 75A
S
TO-220AB
IRF2807Z
D2Pak
IRF2807ZS
TO-262
IRF2807ZL
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
89
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
63
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
75
IDM
Pulsed Drain Current
350
PD @TC = 25°C
Maximum Power Dissipation
170
W
VGS
Linear Derating Factor
Gate-to-Source Voltage
1.1
± 20
W/°C
V
160
mJ
EAS
c
EAS (tested)
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
i
c
d
200
See Fig.12a,12b,15,16
h
A
mJ
°C
-55 to + 175
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient (PCB Mount, steady state)
j
Typ.
Max.
Units
–––
0.90
°C/W
0.50
–––
–––
62
–––
40
HEXFET® is a registered trademark of International Rectifier.
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1
06/30/04
IRF2807Z/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
Min. Typ. Max. Units
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
75
–––
–––
2.0
67
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.073
7.5
–––
–––
–––
–––
–––
–––
71
19
28
18
79
40
45
4.5
–––
–––
9.4
4.0
–––
20
250
200
-200
110
29
42
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
3270
420
240
1590
280
440
–––
–––
–––
–––
–––
–––
gfs
IDSS
IGSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 53A
V VDS = VGS, ID = 250µA
S VDS = 25V, ID = 53A
µA VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
nC ID = 53A
VDS = 60V
VGS = 10V
ns VDD = 38V
ID = 53A
RG = 6.2Ω
VGS = 10V
nH Between lead,
D
f
f
f
6mm (0.25in.)
from package
pF
G
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
89
ISM
(Body Diode)
Pulsed Source Current
–––
–––
350
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
46
80
1.3
69
120
c
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.12mH,
RG = 25Ω, IAS = 53A, VGS =10V. Part not
recommended for use above this value.
ISD ≤ 53A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
2
Conditions
MOSFET symbol
A
V
ns
nC
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 53A, VGS = 0V
TJ = 25°C, IF = 53A, VDD = 25V
di/dt = 100A/µs
f
S
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
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IRF2807Z/S/LPbF
1000
1000
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
1
4.5V
0.1
100
BOTTOM
10
4.5V
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
0.01
0.1
1
10
100
0.1
1000
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
150
Gfs, Forward Transconductance (S)
1000
ID, Drain-to-Source Current (Α)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
T J = 175°C
100
10
T J = 25°C
1
VDS = 25V
20µs PULSE WIDTH
125
T J = 25°C
100
75
T J = 175°C
50
25
0
0.1
4
6
8
10
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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12
0
25
50
75
100
125
150
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRF2807Z/S/LPbF
100000
VGS, Gate-to-Source Voltage (V)
ID= 53A
C oss = C ds + C gd
10000
C, Capacitance(pF)
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
Ciss
Coss
Crss
1000
100
VDS= 60V
VDS= 38V
10.0
VDS= 15V
8.0
6.0
4.0
2.0
0.0
10
1
10
0
100
20
30
40
50
60
70
80
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
10000
ID, Drain-to-Source Current (A)
1000
ISD, Reverse Drain Current (A)
10
TJ = 175°C
100
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100
10
T J = 25°C
1
100µsec
10
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10msec
1.8
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF2807Z/S/LPbF
100
90
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.5
Limited By Package
ID, Drain Current (A)
80
70
60
50
40
30
20
10
0
ID = 53A
VGS = 10V
2.0
1.5
1.0
0.5
25
50
75
100
125
150
175
-60 -40 -20 0
T C , Case Temperature (°C)
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF2807Z/S/LPbF
300
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
15V
ID
22A
38A
BOTTOM 53A
TOP
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
5.0
4.0
ID = 250µA
3.0
2.0
1.0
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRF2807Z/S/LPbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
0.05
0.10
10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 53A
150
100
50
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
www.irf.com
175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF2807Z/S/LPbF
D.U.T
Driver Gate Drive
+
-
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
P.W.
+
V DD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF2807Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
IGBTs, CoPACK
2 - DRAIN
1- GATE
3 - SOURCE
2- DRAIN
3- SOURCE
4 - DRAIN
4- DRAIN
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
HEXFET
1 - GATE
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T HE AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
www.irf.com
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
9
IRF2807Z/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMB LE D ON WW 02, 2000
IN THE AS S E MB LY LINE "L "
INT ERNAT IONAL
RE CT IFIER
L OGO
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
PART NUMBE R
F 530S
AS S E MBL Y
LOT CODE
DAT E CODE
YE AR 0 = 2000
WE EK 02
LINE L
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMB LY
LOT CODE
10
PART NUMB ER
F530S
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMB LY S IT E CODE
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IRF2807Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in assembly line
pos ition indicates "Lead-F ree"
INTERNATIONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IF IER
LOGO
ASS EMBLY
LOT CODE
www.irf.com
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASS EMBLY SIT E CODE
11
IRF2807Z/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
12
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