NSC LMH6550MMNOPB Lmh6550 differential, high speed op amp Datasheet

LMH6550
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SNOSAK0H – DECEMBER 2004 – REVISED MARCH 2013
LMH6550 Differential, High Speed Op Amp
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FEATURES
DESCRIPTION
1
•
•
•
•
•
•
23
The LMH™6550 is a high performance voltage
feedback differential amplifier. The LMH6550 has the
high speed and low distortion necessary for driving
high performance ADCs as well as the current
handling capability to drive signals over balanced
transmission lines like CAT 5 data cables. The
LMH6550 can handle a wide range of video and data
formats.
400 MHz −3 dB Bandwidth (VOUT = 0.5 VPP)
90 MHz 0.1 dB Bandwidth
3000 V/µs Slew Rate
8 ns Settling Time to 0.1%
−92/−103 dB HD2/HD3 @ 5 MHz
10 ns Shutdown/Enable
With external gain set resistors, the LMH6550 can be
used at any desired gain. Gain flexibility coupled with
high speed makes the LMH6550 suitable for use as
an IF amplifier in high performance communications
equipment.
APPLICATIONS
•
•
•
•
•
•
•
Differential AD Driver
Video Over Twisted Pair
Differential Line Driver
Single End to Differential Converter
High Speed Differential Signaling
IF/RF Amplifier
SAW Filter Buffer/Driver
The LMH6550 is available in the space saving SOIC
and VSSOP packages.
Typical Application
RF
AV, RIN
RS
VS
a
+
V
RO
RG
VI
+
-
VCM
RT
RG
ADC
+
RM
IN-
VO
IN+
RO
-
V
RF
For R M
Av
RIN #
RG :
DesignTarget :
VO RF
#
VI R G
1) Set R T
2R G (1 A v )
2 Av
2) Set RM
1
1
RS
1
RIN
R T || R S
Figure 1. Single Ended to Differential ADC Driver
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LMH6550
SNOSAK0H – DECEMBER 2004 – REVISED MARCH 2013
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Connection Diagram
1
8
+IN
-IN
2
VCM
-
+
7
3
6
4
5
V+
+OUT
EN
V-
-OUT
Figure 2. 8-Pin SOIC & VSSOP - Top View
See Package Number D0008A & DGK0008A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1) (2)
(3)
Human Body Model
2000V
Machine Model
200V
Supply Voltage
13.2V
Common Mode Input Voltage
±VS
Maximum Input Current (pins 1, 2, 7, 8)
30 mA
(4)
Maximum Output Current (pins 4, 5)
Maximum Junction Temperature
150°C
Soldering Information:
See Product Folder at www.ti.com and SNOA549C
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the
Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200pF.
The maximum output current (IOUT) is determined by device power dissipation limitations.
Operating Ratings
(1)
−40°C to +85°C
Operating Temperature Range
−65°C to +150°C
Storage Temperature Range
Total Supply Voltage
Package Thermal Resistance (θJA)
(1)
(2)
2
4.5V to 12V
(2)
8-Pin SOIC
150°C/W
8-Pin VSSOP
235°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the
Electrical Characteristics tables.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is P D= (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
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±5V Electrical Characteristics
(1)
Single ended in differential out, TA = 25°C, VS = ±5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω; Unless specified. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
AC Performance (Differential)
SSBW
Small Signal −3 dB Bandwidth
VOUT = 0.5 VPP
400
MHz
LSBW
Large Signal −3 dB Bandwidth
VOUT = 2 VPP
380
MHz
Large Signal −3 dB Bandwidth
VOUT = 4 VPP
320
MHz
0.1 dB Bandwidth
VOUT = 0.5 VPP
90
MHz
(4)
Slew Rate
4V Step
3000
V/μs
Rise/Fall Time
2V Step
2000
1
ns
Settling Time
2V Step, 0.1%
8
ns
VCM Pin AC Performance (Common Mode Feedback Amplifier)
Common Mode Small Signal
Bandwidth
VCM Bypass Capacitor Removed
210
MHz
Slew Rate
VCM Bypass Capacitor Removed
200
V/µs
VO = 2 VPP, f = 5 MHz, RL = 800Ω
−92
VO = 2 VPP, f = 20 MHz, RL = 800Ω
−78
Distortion and Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 70 MHz, RL = 800Ω
−59
VO = 2 VPP, f = 5 MHz, RL = 800Ω
−103
VO = 2 VPP, f = 20 MHz, RL = 800Ω
−88
dBc
dBc
VO = 2 VPP, f = 70 MHz, RL = 800Ω
−50
en
Input Referred Voltage Noise
f ≥ 1 MHz
6.0
nV/√Hz
in
Input Referred Noise Current
f ≥ 1 MHz
1.5
pA/√Hz
Input Characteristics (Differential)
VOSD
IBI
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
Input Offset Voltage Average
Temperature Drift
(5)
Input Bias Current
(6)
Input Bias Current Average
Temperature Drift
(5)
1
±4
±6
1.6
0
-8
mV
µV/°C
−16
µA
9.6
nA/°C
0.3
µA
82
dBc
Input Bias Difference
Difference in Bias Currents Between the
Two Inputs
CMRR
Common Mode Rejection Ratio
DC, VCM = 0V, VID = 0V
RIN
Input Resistance
Differential
5
MΩ
CIN
Input Capacitance
Differential
1
pF
CMVR
Input Common Mode Voltage Range
CMRR > 53 dB
+3.2
−4.7
V
72
+3.1
−4.6
VCM Pin Input Characteristics (Common Mode Feedback Amplifier)
VOSC
(1)
(2)
(3)
(4)
(5)
(6)
Input Offset Voltage
Common Mode, VID = 0
1
±5
±8
mV
Input Offset Voltage Average
Temperature Drift
(5)
25
µV/°C
Input Bias Current
(6)
−2
μA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
Typical numbers are the most likely parametric norm.
Slew Rate is the average of the rising and falling edges.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Negative input current implies current flowing out of the device.
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±5V Electrical Characteristics (1) (continued)
Single ended in differential out, TA = 25°C, VS = ±5V, VCM = 0V, RF = RG = 365Ω, RL = 500Ω; Unless specified. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VCM CMRR
Min
VID = 0V, 1V Step on VCM Pin, Measure
VOD
(2)
Typ
(3)
Max
(2)
Units
70
75
ΔVO,CM/ΔVCM
0.995
0.997
Output Voltage Swing
Peak to Peak, Differential
7.38
7.18
7.8
V
Output Common Mode Voltage
Range
VID = 0 V,
±3.69
±3.8
V
IOUT
Linear Output Current
VOUT = 0V
±63
±75
mA
ISC
Short Circuit Current
Output Shorted to Ground
VIN = 3V Single Ended (7)
±200
mA
Output Balance Error
ΔVOUT Common Mode /ΔVOUT
Differential, VOUT = 1 VPP Differential, f =
10 MHz
−68
dB
Input Resistance
dB
25
Common Mode Gain
kΩ
1.005
V/V
Output Performance
Miscellaneous Performance
Enable Voltage Threshold
Pin 7
Disable Voltage Threshold
Pin 7
2.0
V
Enable Pin Current
VEN =0V
(8)
-250
VEN =4V
(8)
55
1.5
Enable/Disable Time
V
µA
10
ns
70
dB
AVOL
Open Loop Gain
Differential
PSRR
Power Supply Rejection Ratio
DC, ΔVS = ±1V
74
90
Supply Current
RL = ∞
18
20
24
27
mA
1
1.2
mA
Disabled Supply Current
(7)
(8)
dB
The maximum output current (IOUT) is determined by device power dissipation limitations.
Negative input current implies current flowing out of the device.
5V Electrical Characteristics
(1)
Single ended in differential out, TA = 25°C, AV = +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; Unless specified.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
SSBW
Small Signal −3 dB Bandwidth
RL = 500Ω, VOUT = 0.5 VPP
350
MHz
LSBW
Large Signal −3 dB Bandwidth
RL = 500Ω, VOUT = 2 VPP
330
MHz
60
MHz
1500
V/μs
0.1 dB Bandwidth
(4)
Slew Rate
2V Step
Rise/Fall Time, 10% to 90%
1V Step
1
ns
Settling Time
1V Step, 0.05%
12
ns
Common Mode Small Signal
Bandwidth
185
MHz
Slew Rate
180
V/μs
VCM Pin AC Performance (Common Mode Feedback Amplifier)
(1)
(2)
(3)
(4)
4
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
Typical numbers are the most likely parametric norm.
Slew Rate is the average of the rising and falling edges.
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SNOSAK0H – DECEMBER 2004 – REVISED MARCH 2013
5V Electrical Characteristics (1) (continued)
Single ended in differential out, TA = 25°C, AV = +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; Unless specified.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Distortion and Noise Response
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL = 800Ω
−89
VO = 2 VPP, f = 20 MHz, RL = 800Ω
−88
VO = 2 VPP, f = 5 MHz, RL = 800Ω
−85
VO = 2 VPP, f = 20 MHz, RL = 800Ω
−70
dBc
dBc
en
Input Referred Noise Voltage
f ≥ 1 MHz
6.0
nV/√Hz
in
Input Referred Noise Current
f ≥ 1 MHz
1.5
pA/√Hz
Input Characteristics (Differential)
VOSD
IBIAS
CMRR
VICM
Input Offset Voltage
Differential Mode, VID = 0, VCM = 0
Input Offset Voltage Average
Temperature Drift
(5)
Input Bias Current
(6)
Input Bias Current Average
Temperature Drift
(5)
Input Bias Current Difference
Difference in Bias Currents Between the
Two Inputs
Common-Mode Rejection Ratio
DC, VID = 0V
Input Resistance
Differential
Input Capacitance
Differential
Input Common Mode Range
CMRR > 53 dB
1
±4
±6
1.6
0
70
+3.1
+0.4
−8
mV
µV/°C
−16
μA
9.5
nA/°C
0.3
µA
80
dBc
5
MΩ
1
pF
+3.2
+0.3
VCM Pin Input Characteristics (Common Mode Feedback Amplifier)
Input Offset Voltage
Common Mode, VID = 0
1
Input Offset Voltage Average
Temperature Drift
Input Bias Current
VCM CMRR
VID = 0,
1V Step on VCM Pin, Measure VOD
Input Resistance
VCM Pin to Ground
Common Mode Gain
ΔVO,CM/ΔVCM
70
±5
±8
mV
18.6
µV/°C
3
μA
75
dB
25
kΩ
0.991
V/V
Output Performance
VOUT
Output Voltage Swing
Peak to Peak, Differential,
VS = ±2.5V, VCM = 0V
2.4
2.8
V
IOUT
Linear Output Current
VOUT = 0V Differential
±54
±70
mA
ISC
Output Short Circuit Current
Output Shorted to Ground
VIN = 3V Single Ended (7)
250
mA
CMVR
Common Mode Voltage Range
VID = 0, VCM Pin = 1.2V and 3.8V
3.8
1.2
V
Output Balance Error
ΔVOUT Common Mode /ΔVOUT
DIfferential, VOUT = 1 VPP Differential, f =
10 MHz
−65
dB
3.72
1.23
Miscellaneous Performance
(5)
(6)
(7)
Enable Voltage Threshold
Pin 7
Disable Voltage Threshold
Pin 7
2.0
V
1.5
V
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Negative input current implies current flowing out of the device.
The maximum output current (IOUT) is determined by device power dissipation limitations.
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5V Electrical Characteristics (1) (continued)
Single ended in differential out, TA = 25°C, AV = +1, VS = 5V, VCM = 2.5V, RF = RG = 365Ω, RL = 500Ω; Unless specified.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Enable Pin Current
Conditions
Min
(2)
-250
VEN =4V
(8)
55
Open Loop Gain
DC, Differential
PSRR
Power Supply Rejection Ratio
DC, ΔVS = ±0.5V
IS
Supply Current
RL = ∞
ISD
Disabled Supply Current
6
(3)
VEN =0V
Enable/Disable Time
(8)
Typ
(8)
Max
(2)
Units
µA
10
ns
70
dB
72
77
dB
16.5
19
23.5
26.5
mA
1
1.2
mA
Negative input current implies current flowing out of the device.
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Typical Performance Characteristics
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
Frequency Response
vs.
Supply Voltage
Frequency Response
1
1
0
0
VS = 5V
-1
-2
VS = ±5V
GAIN (dB)
GAIN (dB)
-2
-3
-4
-5
VS = ±5V
-3
-4
-5
-6
-6
VOD = 0.5VPP
-7
VOD = 1VPP
-7
AV = 1
-8
AV = 1
-8
DIFFERENTIAL INPUT
SINGLE ENDED INPUT
-9
-9
1
10
100
1
1000
Figure 4.
Frequency Response
vs.
VOUT
Frequency Response
vs.
Gain
0
NORMALIZED GAIN (dB)
1
VOD = 4.0VPP
-2
-3
VOD = 0.5VPP
-4
-5
VOD = 2.0VPP
-6
Vs = ±5V
AV = 1
GAIN = 2
-1
-2
-3
GAIN = 4
-4
-5
GAIN = 6
-6
-7
VOUT = 0.5 VPP
SINGLE ENDED INPUT
-8
SINGLE ENDED INPUT
-9
-9
1
10
100
1
1000
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5.
Figure 6.
Frequency Response
vs.
Capacitive Load
Suggested ROUT
vs.
Cap Load
2
1
1000
Figure 3.
0
-8
100
FREQUENCY (MHz)
1
-7
10
FREQUENCY (MHz)
-1
GAIN (dB)
VS = 5V
-1
CL = 5.7 pF, ROUT = 40:
1000
70
VS = ±5V
60
-1
CL = 10 pF, ROUT = 30:
-2
CL = 22 pF, ROUT = 22:
-3
-4
SUGGESTED RO (:)
GAIN (dB)
0
CL = 47 pF, ROUT = 13:
-5
VOD = 210 mVPP
-6 A = 1
V
-7 LOAD = (CL || 1 k:) IN
SERIES WITH 2 ROUTS
-8
1
10
100
50
40
30
20
LOAD = 1 k: || CAP LOAD
10
VS = ±5V
0
1000
FREQUENCY (MHz)
1
10
100
CAPACITIVE LOAD (pF)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
1 VPP Pulse Response Single Ended Input
70
0.8
60
0.6
50
0.4
VOUT (V)
SUGGESTED RO (:)
Suggested ROUT
vs.
Cap Load
40
30
20
0
-0.2
-0.4
LOAD = 1 k: || CAP LOAD
10
VS = 5V
RL = 500:
-0.6
VS = 5V
0
0.2
RF = 360:
-0.8
1
10
100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
CAPACITIVE LOAD (pF)
Figure 9.
Figure 10.
2 VPP Pulse Response Single Ended Input
Large Signal Pulse Response
1.5
2.5
2
1
1.5
1
VOUT (V)
VOUT (V)
0.5
0
-0.5
VS = ±5
-1
RL = 500:
0.5
0
-0.5
-1
RL = 500:
-1.5
RF = 360:
SINGLE ENDED
INPUT
-2
RF = 360:
-1.5
-2.5
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
TIME (ns)
Figure 11.
Figure 12.
Output Common Mode Pulse Response
Distortion
vs.
Frequency Single Ended Input
-30
40
-40
20
HD3
DISTORTION (dBc)
COMMON MODE VOUT (mV)
30
10
0
-10
-20
-30
RL = 500:
-40
-70
VS = 5V
-80
RL = 800:
VOD = 2 VPP
-90
VOD = 4 VPP
VOCM = 2.5V
-100
-60
0
10 20 30 40 50 60 70 80 90 100
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
TIME (ns)
Figure 13.
8
-60
HD2
RF = 360:
-50
-50
Figure 14.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
Distortion
vs.
Frequency Single Ended Input
Maximum VOUT
vs.
IOUT
4
-40
3.9
-50
3.8
MAXIMUM VOUT (V)
DISTORTION (dBc)
HD3
-60
-70
-80
HD2
VS = ±5V
-90
RL = 800:
3.6
3.5
3.4
AV = 2
RF = 730:
3.1
VOCM = 0V
-110
VIN = 3.88V SINGLE ENDED
3
10
0
20
30
40
50
60
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
70
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
Figure 15.
Figure 16.
Minimum VOUT
vs.
IOUT
Closed Loop Output Impedance
100
-3
VS = ±5V
VS = ±5V
-3.1
VIN = 0V
AV = 2
-3.2
RF = 730:
-3.3
VIN = 3.88V SINGLE ENDED
10
-3.4
|Z| (:)
MINIMUM VOUT (V)
VS = ±5V
3.3
3.2
VOD = 2 VPP
-100
3.7
-3.5
AV = 1
1
-3.6
-3.7
0.1
-3.8
-3.9
0.01
-4
0.01
10 20 30 40 50 60 70 80 90 100
0
1
0.1
Figure 17.
Closed Loop Output Impedance
1000
PSRR
100
VS = 5V
90
VIN = 0V
PSRR -
PSRR (dBc DIFFERENTIAL)
|Z| (:)
100
Figure 18.
100
10
10
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
AV = 1
1
0.1
80
70
PSRR +
60
50
40
30
20
10
0.01
0.01
0.1
1
10
100
1000
VS = ±5V
RL = 500:
AV = 1
VIN = 0V
0
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19.
Figure 20.
100
1000
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 500Ω, RF = RG = 365Ω; Unless Specified).
PSRR
CMRR
100
85
80
PSRR 75
70
CMRR (dB)
PSRR (dBc DIFFERENTIAL)
90
80
PSRR +
60
50
40
60
VS = 5V
55
20
RL = 500:
50
AV = 1
45
VIN = 2.5V
0
0.01
0.1
1
10
100
40
0.1
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21.
Figure 22.
Balance Error
3rd Order Intermodulation Products
vs.
VOUT
-40
-25
-30
RL = 500:
-35
-40
-45
-50
RF = 360:
VS = 5V
AV = 1
-55
IMD 3 (dBc)
BALANCE ERROR (dBc)
65
30
10
VS = ±5V
-60
-65
-70
-75
VS = ±5V
-45
AV = 2 V/V
-50
RL = 200:
f = 40 MHz
-55
f = 20 MHz
-60
-65
-70
f = 5 MHz
-75
-80
-85
-90
-80
-85
1
10
100
1000
FREQUENCY (MHz)
0
1
2
3
4
5
6
7
DIFFERENTIAL VOUT (VPP)
Figure 23.
10
70
Figure 24.
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APPLICATION SECTION
The LMH6550 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6550, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common mode feedback circuit allows single ended to differential operation.
The LMH6550 is a voltage feedback amplifier with gain set by external resistors. Output common mode voltage
is set by the VCM pin. This pin should be driven by a low impedance reference and should be bypassed to ground
with a 0.1 µF ceramic capacitor. Any signal coupling into the VCM will be passed along to the output and will
reduce the dynamic range of the amplifier.
The LMH6550 is equipped with a ENABLE pin to reduce power consumption when not in use. The ENABLE pin
floats to logic high. If this pin is not used it can be left floating. The amplifier output stage goes into a high
impedance state when the amplifier is disabled. The feedback and gain set resistors will then set the impedance
of the circuit. For this reason input to output isolation will be poor in the disabled state.
FULLY DIFFERENTIAL OPERATION
The LMH6550 will perform best when used with split supplies and in a fully differential configuration. See
Figure 25 and Figure 26 for recommend circuits.
RF1
RO
RG1
+
VI
a
CL
VCM
RL
VO
RG2
RO
RF2
ENABLE
Figure 25. Typical Application
The circuit shown in Figure 25 is a typical fully differential application as might be used to drive an ADC. In this
circuit closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the applications in this data sheet VIN is presumed to be
the voltage presented to the circuit by the signal source. For differential signals this will be the difference of the
signals on each input (which will be double the magnitude of each individual signal), while in single ended inputs
it will just be the driven input signal.
The resistors RO help keep the amplifier stable when presented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the LMH6550 provides excellent distortion, balance and
common mode rejection provided the resistors RF, RG and RO are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80 dB, the DC and low frequency CMRR of most circuits will be
dominated by the external resistors and board trace resistance. At higher frequencies board layout symmetry
becomes a factor as well. Precision resistors of at least 0.1% accuracy are recommended and careful board
layout will also be required.
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500
50:
100:
TWISTED PAIR
250
+
2 VPP
a
VCM
250
2 VPP
50:
500
GAIN = 2
ENABLE
Figure 26. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6550 makes an
excellent cable driver as shown in Figure 26. The LMH6550 is also suitable for driving differential cables from a
single ended source.
The LMH6550 requires supply bypassing capacitors as shown in Figure 27 and Figure 28. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. The SMT capacitors should be connected directly to a ground plane. Thin traces or small vias will reduce
the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM pin to ground. The
VCM pin is a high impedance input to a buffer which sets the output common mode voltage. Any noise on this
input is transferred directly to the output. Output common mode noise will result in loss of dynamic range,
degraded CMRR, degraded Balance and higher distortion. The VCM pin should be bypassed even if the pin in not
used. There is an internal resistive divider on chip to set the output common mode voltage to the mid point of the
supply pins. The impedance looking into this pin is approximately 25 kΩ. If a different output common mode
voltage is desired drive this pin with a clean, accurate voltage reference.
+
V
V
+
0.01 PF 0.01 PF
10 PF
10 PF
0.01 PF
+
+
VCM
0.1 PF
0.1 PF
VCM
-
0.1 PF
0.01 PF
10 PF
V
-
Figure 27. Split Supply Bypassing Capacitors
12
Figure 28. Single Supply Bypassing Capacitors
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SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
The LMH6550 provides excellent performance as an active balun transformer. Figure 29 shows a typical
application where an LMH6550 is used to produce a differential signal from a single ended source.
In single ended input operation the output common mode voltage is set by the VCM pin as in fully differential
mode. Also, in this mode the common mode feedback circuit must recreate the signal that is not present on the
unused differential input pin. Figure 23 is the measurement of the effectiveness of this process. The common
mode feedback circuit is responsible for ensuring balanced output with a single ended input. Balance error is
defined as the amount of input signal that couples into the output common mode. It is measured as a the
undesired output common mode swing divided by the signal on the input. Balance error can be caused by either
a channel to channel gain error, or phase error. Either condition will produce a common mode shift. Figure 23
measures the balance error with a single ended input as that is the most demanding mode of operation for the
amplifier.
Supply and VCM pin bypassing are also critical in this mode of operation. See the above section on for bypassing
recommendations and also see Figure 27 and Figure 28 for recommended supply bypassing configurations.
RF
AV, RIN
RS
VS
a
+
V
RG
VI
VI1
-
VCM
RT
RM
IN-
ADC
VO
+
-
VI2
RG
RO
VO1
+
VO2
IN+
RO
-
+-
V
RF
Definitions :
Conditions :
R S R T || RIN
RM
Av
RIN
1
RG
R G RF
2
R G RM
R G RM RF
RT || RS
VO
VI
2(1
1
1
)
2R G RM (1
1 2
VOCM
VICM
VCM
VI1
2
RF
for R M
RG
VO2
2
VOCM .
RG
2
RG (1
)
)
1
1
VO1
VI2
2
#
2
2
#
2R G (1 A v )
for RM
2 Av
RG
(by design)
2
#
VOCM
1 Av
for R M
RG
Figure 29. Single Ended In to Differential Out
SINGLE SUPPLY OPERATION
The input stage of the LMH6550 has a built in offset of 0.7V towards the lower supply to accommodate single
supply operation with single ended inputs. As shown in Figure 29, the input common mode voltage is less than
the output common voltage. It is set by current flowing through the feedback network from the device output. The
input common mode range of 0.4V to 3.2V places constraints on gain settings. Possible solutions to this
limitation include AC coupling the input signal, using split power supplies and limiting stage gain. AC coupling
with single supply is shown in Figure 30.
In Figure 29 closed loop gain = VO / VI ≊ RF / RG, where VI =VS / 2, as long as RM << RG. Note that in single
ended to differential operation VI is measured single ended while VO is measured differentially. This means that
gain is really 1/2 or 6 dB less when measured on either of the output pins separately. Additionally, note that the
input signal at RT (labeled as VI) is 1/2 of VS when RT is chosen to match RS to RIN.
VICM = Input common mode voltage = (VI1+VI2) / 2.
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RF
RO
VO1
VI1
RG
RS
+
VI
a
RT
RL
CL
VCM
VO
RG
VI2
RM
VO2
RO
RF
ENABLE
*VCM =
VO1 + VO2
VICM = VOCM
2
*BY DESIGN
VICM =
VI1 + VI2
2
Figure 30. AC Coupled for Single Supply Operation
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load conditions. They typically have high impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 31 shows a typical circuit for driving an ADC. The two
56Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In
addition, the resistors form part of a low pass filter which helps to provide anti alias and noise reduction
functions. The two 39 pF capacitors help to smooth the current spikes associated with the internal switching
circuits of the ADC and also are a key component in the low pass filtering of the ADC input. In the circuit of
Figure 31 the cutoff frequency of the filter is 1/ (2*π*56Ω *(39 pF + 14 pF)) = 53 MHz (which is slightly less than
the sampling frequency). Note that the ADC input capacitance must be factored into the frequency response of
the input filter, and that being a differential input the effective input capacitance is double. Also as shown in
Figure 31 the input capacitance to many ADCs is variable based on the clock cycle. See the data sheet for your
particular ADC for details.
RF1
56
RG1
ADC12LO66
39 pF
+
VI
a
VCM
-
7 - 8 pF
39 pF
RG2
56
VREF
RF2
ENABLE
1V LOW IMPEDANCE
VOLTAGE REFERENCE
Figure 31. Driving an ADC
14
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The amplifier and ADC should be located as closely together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 for more details on the subsampling process and the requirements this imposes on the filtering
necessary in your system.
USING TRANSFORMERS
Transformers are useful for impedance transformation as well as for single to differential, and differential to single
ended conversion. A transformer can be used to step up the output voltage of the amplifier to drive very high
impedance loads as shown in Figure 32. Figure 34 shows the opposite case where the output voltage is stepped
down to drive a low impedance load.
Transformers have limitations that must be considered before choosing to use one. Compared to a differential
amplifier, the most serious limitations of a transformer are the inability to pass DC and balance error (which
causes distortion and gain errors). For most applications the LMH6550 will have adequate output swing and drive
current and a transformer will not be desirable. Transformers are used primarily to interface differential circuits to
50Ω single ended test equipment to simplify diagnostic testing.
300: TWISTED PAIR
500
37.5:
1:2 (TURNS)
250
4 VPP
a
+
VCM
VCM
250
37.5:
8 VPP
RL = 300:
500
ENABLE
AV = 2
Figure 32. Transformer Out High Impedance Load
VIN * AV * N
§
¨
¨
©
VL =
§ 2 ROUT * N2
¨
+1
¨
RL
©
WHERE VIN = DIFFERENTIAL INPUT VOLTAGE
§ SECONDARY
¨
¨ PRIMARY
©
§
¨
¨
©
N = TRANSFORMER TURNS RATIO =
AV = CLOSED LOOP AMPLIFIER GAIN
ROUT = SERIES OUTPUT MATCHING RESISTOR
RL = LOAD RESISTOR
VL = VOLTAGE ACROSS LOAD RESISTOR
Figure 33. Calculating Transformer Circuit Net Gain
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100: TWISTED PAIR
375
200:
2:1 (TURNS)
375
4 VPP
a
+
VCM
VCM
375
1 VPP
RL = 100:
200:
375
ENABLE
AV = 1
Figure 34. Transformer Out Low Impedance Load
50: COAX
375
100:
2:1 (TURNS)
375
4 VPP
a
+
VCM
C1
375
1 VPP
100:
375
ENABLE
GAIN = 1
C1 IS NOT REQUIRED IF VCM = GROUND
Figure 35. Driving 50Ω Test Equipment
CAPACITIVE DRIVE
As noted in DRIVING ANALOG TO DIGITAL CONVERTERS, capacitive loads should be isolated from the
amplifier output with small valued resistors. This is particularly the case when the load has a resistive component
that is 500Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component
could be 1000Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using
matching resistors will be sufficient to isolate any subsequent capacitance. For other applications see Figure 8
and Figure 9 in Typical Performance Characteristics.
POWER DISSIPATION
The LMH6550 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance,
thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX of 150°C is
never exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6550:
16
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1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V−. (Be sure to include any
current through the feedback network if VOCM is not mid rail.)
2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms
((VS − V−OUT) * I−OUT), where VOUT and IOUT are the voltage and the current measured at the output pins of
the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage.
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMH6550 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
•
•
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
For the SOIC package θJA is 150°C/W
For the VSSOP package θJA is 235°C/W
(1)
NOTE
If VCM is not 0V then there will be quiescent current flowing in the feedback network. This
current should be included in the thermal calculations and added into the quiescent power
dissipation of the amplifier.
ESD PROTECTION
The LMH6550 is protected against electrostatic discharge (ESD) on all pins. The LMH6550 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6550 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
BOARD LAYOUT
The LMH6550 is a very high performance amplifier. In order to get maximum benefit from the differential circuit
architecture board layout and component selection is very critical. The circuit board should have low a
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as
should the supply bypass capacitors. The LMH730154 evaluation board is an example of good layout
techniques.
The LMH6550 is sensitive to parasitic capacitances on the amplifier inputs and to a lesser extent on the outputs
as well. Ground and power plane metal should be removed from beneath the amplifier and from beneath RF and
RG.
With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors.
EVALUATION BOARD
National Semiconductor offers evaluation board(s) to aid in device testing and characterization and as a guide for
proper layout. Generally, a good high frequency layout will keep power supply and ground traces away from the
inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response
peaking and possible circuit oscillations (see Application Note OA-15 for more information).
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REVISION HISTORY
Changes from Revision G (March 2013) to Revision H
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6550MA
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LMH65
50MA
LMH6550MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
50MA
LMH6550MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
50MA
LMH6550MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
AL1A
LMH6550MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
AL1A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMH6550MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMH6550MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMH6550MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6550MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMH6550MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMH6550MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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