Analogic AAT3603IIH-T1 Total power solution for portable application Datasheet

PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
General Description
Features
The AAT3603 is a member of AnalogicTech’s Total Power
Management ICTM (TPMICTM) product family. It contains a
single-cell Lithium Ion/Polymer battery charger, a fully
integrated step-down converter and 5 low dropout (LDO)
regulators. The device is ideal for low cost handheld portable GSM or CDMA mobile telephones.
All six voltage regulators operate with low quiescent current. The total no load current when the step-down converter and 2 LDOs are enabled is only 170μA.
• Voltage Regulator VIN Range: 4.5V to 6V
• Low Cost Power Integration
• Low Standby Current
▪ 170μA (typ) w/ Buck (Core), LDO1 (PowerDigital),
and LDO2 (PowerAnalog) Active, No Load
• One Step-Down Buck Converter (Core)
▪ 1.8V, 300mA Output
▪ 1.5MHz Switching Frequency
▪ Fast Turn-On Time (120μs typ)
• Five LDOs Programmable with I2C
▪ LDO1: 3.0V, 300mA (PowerDigital)
▪ LDO2: 3.0V, 150mA (PowerAnalog or PLL)
▪ LDO3: 3.0V, 150mA (TCXO)
▪ LDO4: 3.0V, 150mA (TX)
▪ LDO5: 3.0V, 150mA (RX)
▪ PSRR: 60dB@10kHz
▪ Noise: 50μVrms for LDO3, LDO4, and LDO5
• One Battery Charger
▪ Digitized Thermal Regulation
▪ Charge Current Programming up to 1.4A
▪ Charge Current Termination Programming
▪ Automatic Trickle Charge for Battery Preconditioning
(2.8V Cutoff)
• Adapter OK (ADPP) and Reset (RESET) Timer Outputs
• Separate Enable Pins for Supply Outputs
• Over-Current Protection
• Over-Temperature Protection
• 5x5mm TQFN55-36 Package
The AAT3603 is available in a thermally enhanced low
profile 5x5x0.8mm 36-pin TQFN package.
Applications
The battery charger is a complete thermally regulated
constant current/constant voltage linear charger. It
includes an integrated pass device, reverse blocking protection, high accuracy current and voltage regulation,
charge status, and charge termination. The charging
current, charge termination current, and recharge voltage are programmable with an external resistor and/or
by a standard I2C interface.
The step-down DC/DC converter is integrated with internal
compensation and operates at a switching frequency of
1.5MHz, thus minimizing the size of external components
while keeping switching losses low and efficiency greater
than 95%. All LDO output voltages are programmable
using the I2C interface.
The five LDOs offer 60dB power supply rejection ratio
(PSRR) and low noise operation making them suitable for
powering noise-sensitive loads.
•
•
•
•
•
3603.2008.06.1.0
Digital Cameras
GSM or CDMA Cellular Phones
Handheld Instruments
PDAs and Handheld Computers
Portable Media Players
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1
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Application
BAT
CHGIN
5V from
AC Adapter or USB Port
+
10μF
To BAT
-
22μF
1 cell
Li+
battery
100k
ADPP
Charger
Control
STAT
ISET
TS
CT
ENBAT
Ref
To
BAT
100k
To
BAT
100k
10kΩ
NTC
For BAT
Temp sense
1.24k
0.1μF
SDA
SCL
To BAT
EN_TEST
PVIN
μC
UVLO
EN_HOLD
I 2C
and
Enable
Control
EN_KEY
LX
VIN
3.3μH
Step-down
BUCK
Ref
ON_KEY
Core : 1.8V
300mA
10μF
4.7μF
OUTBUCK
PGND
Enable
RESET
To OUT1
100k
EN2
EN3
EN4
EN5
VIN
REF
CNOISE
AVIN2
AVIN1
VIN
Ref
To BAT
0.01μF
LDO1
LDO2
Enable
VIN
Ref
LDO3
Enable
VIN
Ref
LDO4
LDO5
Enable
VIN
Ref
Enable
Ref
VIN
Enable
To BAT
AGND
OUT5
RX
3.0V
150mA
OUT4
TX
3.0V
150mA
4.7μF
2
OUT3
TCXO
3.0V
150mA
4.7μF
OUT2
OUT1
PowerAnalog
3.0V
150mA
PowerDigital
3.0V
300mA
4.7μF
4.7μF
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22μF
3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Pin Descriptions
Pin #
Symbol
1
EN_TEST
2
EN_HOLD
3
EN_KEY
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ON_KEY
EN2
EN3
EN4
EN5
OUT5
OUT4
AVIN2
OUT3
OUT2
AVIN1
OUT1
AGND
CNOISE
18
RESET
19
ADPP
20
21
22
23
LX
PGND
PVIN
OUTBUCK
24, 25
N/C
26, 27
28, 29
30
BAT
CHGIN
ENBAT
31
TS
32
ISET
33
CT
34
STAT
35
36
SDA
SCL
EP
EP
3603.2008.06.1.0
Function
Similar to EN_HOLD but intended for use with the automatic tester or as a hands free enable input pin indicating hands free phone operation with a headset. It is also internally pulled to GND when floating.
Enable for the system. EN_HOLD must be held high by the processor to maintain core power. It is internally
pulled to GND when floating.
Enable for the system. An internal pull-up resistor keeps the pin pulled up to an internal supply to keep the
system off when there is no CHGIN input. Connect a normally-open pushbutton switch from this pin to GND.
There is an internal 300ms debounce delay circuit to filter noise.
Buffered logic output of the EN_KEY pin with a logic signal from ground to OUT1.
Enable for LDO2 (PowerAnalog or PLL). (Internally pulled low when floating)
Enable for LDO3 (TCXO). (Internally pulled low when floating)
Enable for LDO4 (TX) (Internally pulled low when floating)
Enable for LDO5 (RX) (Internally pulled low when floating)
Output for LDO5 (RX) (when shut down, pulled down with 10kΩ)
Output for LDO4 (TX) (when shut down, pulled down with 10kΩ)
Analog voltage input. Must be tied to BAT on the PCB.
Output for LDO3 (TCXO)
Output for LDO2 (PowerAnalog)
Analog voltage input. Must be tied to BAT on the PCB.
Output for LDO1 (PowerDigital)
Signal ground
Noise Bypass pin for the internal reference voltage. Connect a 0.01μF capacitor to AGND.
RESET is the open drain output of a 50ms reset timer. RESET is released after the 50ms timer times out.
RESET is active low and is held low during shutdown. RESET should be tied to a 10K or larger pullup to
OUTBUCK.
Open Drain output. Will pull low when VCHGIN > 4.5V. When this happens, depending on the status of the
USE_USB pin, the charge current will be reset to the default values (see Battery Charger and I2C Serial
Interface and Programmability section)
Step-down Buck converter (Core) switching node. Connect an inductor between this pin and the output.
Power Ground for step-down Buck converter (Core)
Input power for step-down Buck converter (Core). Must be tied to BAT.
Feedback input for the step-down Buck converter (Core)
No Connect; do not connect anything to these pins.
Connect to a Lithium Ion battery.
Power input from either external adapter or USB port.
Active low enable for the battery charger (Internally pulled low when floating)
Battery Temperature Sense pin with 75μA output current. Connect the battery’s NTC resistor to this pin and
ground.
Charge current programming input pin (Tie a 1k to GND for maximum fast charge current). Can be used to
monitor charge current.
Charger Safety Timer Pin. A 0.1μF ceramic capacitor should be connected between this pin and GND. Connect directly to GND to disable the timer function.
Battery charging status pin output. Connected internally between GND and OUT1 (PowerDigital). Used to
monitor battery charge status.
I2C serial data pin, open drain; requires a pullup resistor.
I2C serial clock pin, open drain; requires a pullup resistor.
The exposed thermal pad (EP) must be connected to board ground plane and pins 16 and 21. The ground
plane should include a large exposed copper pad under the package for thermal dissipation (see package
outline).
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3
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Pin Configuration
SCL
SDA
STAT
CT
ISET
TS
ENBAT
CHGIN
CHGIN
TQFN55-36
(Top View)
36
EN_TEST
EN_HOLD
EN_KEY
ON_KEY
EN2
EN3
EN4
EN5
OUT5
35
34
33
32
31
30
29
28
1
27
2
26
3
25
4
24
5
23
6
22
7
21
8
20
9
19
11
12
13
14
15
16
17
18
OUT4
AVIN2
OUT3
OUT2
AVIN1
OUT1
AGND
CNOISE
RESET
10
BAT
BAT
N/C
N/C
OUTBUCK
PVIN
PGND
LX
ADPP
4
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Absolute Maximum Ratings1
TA = 25°C unless otherwise noted.
Symbol
VIN
Power and logic pins
TJ
TS
TLEAD
Description
Input Voltage, CHGIN, BAT
Maximum Rating
Operating Junction Temperature Range
Storage Temperature Range
Maximum Soldering Temperature (at leads, 10 sec)
Value
Units
-0.3 to 6.5
VIN + 0.3
-40 to 85
-65 to 150
300
V
V
°C
°C
°C
Value
Units
25
4
°C/W
W
Recommended Operating Conditions2
Symbol
θJA
PD
Description
Thermal Resistance
Maximum Power Dissipation
1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions
specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
2. Thermal Resistance was measured with the AAT3603 device on the 4-layer FR4 evaluation board in a thermal oven. The amount of power dissipation which will cause the
thermal shutdown to activate will depend on the ambient temperature and the PC board layout ability to dissipate the heat. See Figures 11-14.
3603.2008.06.1.0
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Electrical Characteristics1
VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.
Symbol
Description
Conditions
Power Supply
VIN
CHGIN Input Voltage
IQ
Battery Standby Current
ISHDN
Typ
Max
Units
6
V
μA
10.0
μA
4.5
V
5
V
V
V
μA
4.5
Buck, LDO1 + LDO2, no load
EN_TEST, EN_HOLD, EN2, EN3, EN4, EN5
= GND, EN_KEY floating
CHGIN rising
CHGIN falling
BAT rising
BAT falling
VBAT = 4V, VCHGIN = 0V
Battery Shutdown Current
Under-Voltage Lockout for CHGIN
UVLO
Battery Under-Voltage Lockout
Leakage Current from BAT Pin
IBAT
Startup Timers
RESET
Reset Timer
Charger Voltage Regulation
VBAT_REG
Output Charge Voltage Regulation
VMIN
Preconditioning Voltage Threshold
VRCH
Min
Initiated when OUT1 = 90% of final value
0°C ≤ TA ≤ +70°C
(No trickle charge option available)
I2C Recharge Code = 00 (default)
I2C Recharge Code = 01
I2C Recharge Code = 10
I2C Recharge Code = 11
Battery Recharge Voltage Threshold
170
4.25
4.15
2.6
2.35
2
35
ms
4.158
2.6
4.200
2.8
4.00
4.05
4.10
4.15
4.242
3.0
864
960
1056
85
100
800
115
V
V
V
V
V
V
Charger Current Regulation
ICH_CC
KI_SET
ICH_PRE
ICH_TERM
Constant-Current Mode Charge Current
Charge Current Set Factor: ICH_CC/IISET
Preconditioning Charge Current
Charge Termination Threshold Current
Charging Devices
Charging Transistor ON Resistance
RDS(ON)
Logic Control / Protection
VEN_HOLD,
Input High Threshold
VEN_KEY,
Input Low Threshold
VEN_TEST
VADPP
IADPP
VSTAT
ISTAT
VOVP
Output Low Voltage
Output Pin Current Sink Capability
Output High Voltage
Output Pin Current Source Capability
Over-Voltage Protection Threshold
RISET = 1.24k (for 0.8A), I2C ISET code =
100, VBAT = 3.6V, VCHGIN = 5.0V
I2C ISET Code = 000, VBAT = 3.6V
Constant Current Mode, VBAT = 3.6V
RISET = 1.24kΩ
12
I2C
I2C
I2C
I2C
I2C
50
5
10
15
20
ISET Code = 000
Term Code = 00 (default)
Term Code = 01
Term Code = 10
Term Code = 11
VIN = 5V
0.6
mA
mA
%
ICH_CC
mA
%
ICH_CC
0.9
1.4
Ω
V
Pin Sinks 4mA
0.4
V
0.4
8
VOUT1
1.5
V
mA
V
mA
V
4.3
1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.
6
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Electrical Characteristics1
VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.
Symbol
Description
Conditions
Logic Control / Protection (continued)
VOCP
Over Current Protection Threshold
TC
Constant Current Mode Time Out
TK
Trickle Charge Time Out
TV
Constant Voltage Mode Time Out
ITS
Current Source from TS Pin
TS1
TS Hot Temperature Fault
TS2
TS Cold Temperature Fault
TLOOP_IN
TLOOP_OUT
TREG
Step-Down Buck
VOUTBUCK
ILIMOUTBUCK
RDS(ON)L
RDS(ON)H
FOSC
TS
Start-Up Time
LDO1 (PowerDigital)
VOUT1
Output Voltage Accuracy
IOUT1
Output Current
ILIM1
Output Current Limit
VDO1
Dropout Voltage
ΔVOUT1(VOUT1ΔVIN1) Line Regulation
Load Regulation
ΔVOUT1
PSRR
Power Supply Rejection Ratio
TS
Start Up Time
CCT = 100nF, VCHGIN = 5V
Falling Threshold
Hysteresis
Rising Threshold
Hysteresis
Thermal Loop Entering Threshold
Thermal Loop Exiting Threshold
Thermal Loop Regulation
Converter (Core)
Output Voltage Accuracy
P-Channel Current Limit
High Side Switch On-Resistance
Low Side Switch On-Resistance
Oscillator Frequency
Min
IOUTBUCK = 0 ~ 300mA; VIN = 2.7V ~ 5.5V
71
318
2.30
1.71
TA = 25°C
From Enable to Regulation; COUTBUCK =
4.7μF, CNOISE = On
IOUT1 = 0~300mA
IOUT1 = 300mA
IOUT1 = 100mA
IOUT1 = 0.5mA ~ 150mA
IOUT1 = 10mA, COUT1=22μF, 100Hz ~ 10KHz
From Enable to Regulation; C OUT1 = 22μF,
CNOISE = On
Typ
105
3
TC/8
3
75
331
25
2.39
25
115
85
100
1.80
0.8
0.8
0.8
1.5
Max
79
346
Units
%VCS
Hours
Hours
Hours
μA
mV
2.48
V
mV
°C
°C
°C
1.89
V
A
Ω
Ω
MHz
100
μs
-3
300
+3
40
60
%
mA
mA
mV
%/V
mV
dB
175
μs
1000
160
320
0.07
1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.
3603.2008.06.1.0
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7
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Electrical Characteristics1
VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.
Symbol
Description
LDO2 (PowerAnalog)
VOUT2
Output Voltage Accuracy
IOUT2
Output Current
ILIM2
Output Current Limit
VDO2
Dropout Voltage
ΔVOUT2/
Line Regulation
(VOUT2ΔVIN2)
ΔVOUT2
Load Regulation
PSRR
Power Supply Rejection Ratio
Ts
Min
IOUT2 = 0 ~ 150mA
-3
150
Typ
IOUT2 = 100mA
Load: 0.5mA~150mA
IOUT2 = 10mA, COUT2 = 4.7μF, 10 ~ 10KHz
From Enable to Regulation; COUT2 = 4.7μF,
CNOISE = On
Start Up Time
IOUTX = 0 ~ 150mA
%
mA
mA
mV
0.07
%/V
mV
dB
65
μs
+3
%
mA
mA
mV
0.07
%/V
1000
165
IOUTX = 0.5mA ~ 150mA
IOUTX = 10mA, COUTx = 4.7μF, 10 ~ 10KHz
IOUTX = 10mA, Power BW: 10kHz ~ 100KHz
From Enable to Regulation; COUTX = 4.7μF,
CNOISE = On
For EN2, EN3, EN4 and EN5
+3
40
60
IOUTX = 100mA
Logic Control
VIH
Enable Pin Logic High Level
Enable Pin Logic Low Level
VIL
Thermal
TSD
Over Temperature Shutdown Threshold
THYS
Over Temperature Shutdown Hysteresis
SCL, SDA (I2C Interface)
FSCL
Clock Frequency
TLOW
Clock Low Period
Clock High Period
THIGH
THD_STA
Hold Time START Condition
TSU_STA
Setup Time for Repeat START
TSU_DTA
Data Setup Time
TSU_STO
Setup Time for STOP Condition
Bus Free Time Between STOP and
TBUF
START Condition
VIL
Input Threshold Low
Input Threshold High
VIH
II
Input Current
VOL
Output Logic Low (SDA)
Units
-3
150
IOUTX = 150mA
Start Up Time
Max
1000
165
IOUT2 = 150mA
LDO3 (TCXO), LDO4 (TX) and LDO5 (RX)
VOUTx
Output Voltage Accuracy
IOUTx
Output Current
ILIMx
Output Current Limit
VDOx
Dropout Voltage
ΔVOUTx/
Line Regulation
(VOUTxΔVINx)
ΔVOUTx
Load Regulation
PSRR
Power Supply Rejection Ratio
eN
Output Noise Voltage
Ts
Conditions
40
60
40
mV
dB
μVrms
65
μs
1.4
V
0.4
140
15
0
1.3
0.6
0.6
0.6
100
0.6
˚C
˚C
400
1.3
2.7V ≤ VIN ≤ 5.5V
2.7V ≤ VIN ≤ 5.5V
V
KHz
μs
μs
μs
μs
ns
μs
μs
0.4
1.0
0.4
1.4
-1.0
IPULLUP = 3mA
V
V
μA
V
1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.
8
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Basic I2C Timing Diagram
SDA
TSU_DAT
TLOW
THD_STA
TBUF
SCL
THD_STA
3603.2008.06.1.0
THD_DAT
THIGH
TSU_STA
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TSU_STO
9
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—Charger
Preconditioning Threshold Voltage
vs. Temperature
Preconditioning Charge Current vs. Temperature
(VBAT = 2.5V, RSET = 1.24kΩ)
2.810
115
2.808
2.802
VCHGIN = 5.5V
ICH_PRE (mA)
VMIN (V)
2.804
VCHGIN = 6.0V
2.800
2.798
2.796
VCHGIN = 5.0V
2.794
VCHGIN = 4.5V
105
100
VCHGIN = 5.5V
VCHGIN = 5.0V
95
VCHGIN = 4.5V
90
85
2.792
2.790
-50
VCHGIN = 6.0V
110
2.806
-25
0
25
50
75
80
-50
100
-25
0
Recharge Voltage Threshold vs. Temperature
(VRCH set to 4.0V)
4.25
4.05
4.24
4.04
4.23
VCHGIN = 5.5V
VBAT_REG (V)
VRCH (V)
4.03
4.01
VCHGIN = 6.0V
4.00
3.99
VCHGIN = 5.0V
VCHGIN = 4.5V
3.98
3.97
3.96
-50
-25
0
25
50
75
4.20
4.19
VCHGIN = 5.0V
4.18
4.16
100
-50
-25
50
40
VCHGIN = 5.5V
600
VCHGIN = 5.0V
500
400
VCHGIN = 4.5V
300
100
-25
0
25
50
75
100
0
2.5
2.9
3.3
3.7
4.1
4.5
Battery Voltage (V)
Temperature (°C)
10
100
200
VCHGIN = 4.5V
10
-50
75
VCHGIN = 6.0V
700
VCHGIN = 6.0V
ICH (mA)
ICH_TERM (mA)
80
0
50
(RISET = 1.24kΩ
Ω)
800
VCHGIN = 5.0V
25
Charging Current vs. Battery Voltage
900
20
0
Temperature (°C)
90
30
VCHGIN = 4.5V
4.17
100
60
100
4.21
Charge Termination Threshold Current
vs. Temperature
VCHGIN = 5.5V
75
VCHGIN = 6.0V
VCHGIN = 5.5V
4.22
Temperature (°C)
70
50
Output Charge Voltage Regulation vs. Temperature
(End of Charge Voltage)
4.06
4.02
25
Temperature (°C)
Temperature (°C)
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—Charger (continued)
Constant Current Mode Charge Current
vs. Temperature
Constant Current Mode Charge Current
vs. Input Voltage
(VBAT = 3.6V; RISET = 1.24kΩ
Ω)
900
VCHGIN = 6.0V
VCHGIN = 4.5V
880
860
700
ICH_CC (mA)
ICH_CC (mA)
800
VCHGIN = 5.5V
600
VCHGIN = 5.0V
500
840
VBAT = 3.3V
820
800
780
VBAT = 3.6V
VBAT = 4.1V
760
740
400
300
(RSET = 1.24kΩ
Ω)
900
720
-50
-25
0
25
50
75
100
700
Temperature (°C)
3603.2008.06.1.0
4.5
4.75
5
5.25
5.5
5.75
6
CHGIN Voltage (V)
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—Step-Down Buck Converter
Step-Down Buck Load Regulation
vs. Output Current
Step-Down Buck Efficiency vs. Output Current
(VOUT = 1.8V; L = 3.3µH)
90
VBAT = 3.6V
Efficiency (%)
80
(VOUT = 1.8V; L = 3.3µH)
VBAT = 2.7V
0.5
Load Regulation (%)
100
VBAT = 4.2V
70
60
50
40
VCHGIN = 4.5V
VCHGIN = 5.5V
30
VCHGIN = 6.0V
20
VCHGIN = 5.0V
10
0
1
10
100
0.4
0.0
-0.1
VBAT = 2.7V
-0.2
-0.3
1
-0.2
-0.3
1.815
IOUT = 200mA
IOUT = 10mA
IOUT = 1mA
-0.4
-0.5
2.5
IOUT = 50mA
VBAT
3
4 4.2
3.5
VCHGIN
4.5
1000
VCHGIN = 5.0V
1.820
VOUT (V)
Line Regulation (%)
0
-0.1
100
(IOUT = 10mA)
IOUT = 300mA
0.1
10
1.825
0.5
IOUT = 0.01mA
VCHGIN = 5.0V
Step-Down Buck Output Voltage vs. Temperature
(VOUT = 1.8V; L = 3.3µH)
0.2
VBAT = 3.6V
-0.4
Output Current (mA)
Step-Down Buck Line Regulation
vs. CHGIN and Battery Input Voltage
0.3
VCHGIN = 6.0V
0.1
Output Current (mA)
0.4
VCHGIN = 5.5V
VBAT = 4.2V
0.2
-0.5
1000
VCHGIN = 4.5V
0.3
1.810
1.805
1.800
VBAT = 3.6V
VCHGIN = 5.5V
VBAT = 2.7V
VCHGIN = 4.5V
VCHGIN = 6.0V
1.795
1.790
IOUT = 100mA
1.785
5
1.780
-50
5.5
6
VBAT = 4.2V
-25
0
25
50
75
100
Temperature (°C)
Input VBAT, VCHGIN (V)
VBAT Line Transient Response Step-Down Buck
VCHGIN Line Transient Response Step-Down Buck
(VBAT = 3.5V to 4.2V; IOUT = 300mA; VOUT = 1.8V; COUT = 4.7µF)
(VCHGIN = 4.5V to 5.5V; IOUT = 300mA; VOUT = 1.8V; COUT = 4.7µF)
VO
1.80
1.76
4.5
4.0
VBAT
3.5
3.0
Output Voltage (top) (V)
Output Voltage (top) (V)
1.84
1.86
1.84
1.82
1.78
6.0
1.76
5.5
Time (100µs/div)
12
VO
1.80
VCHGIN
5.0
4.5
4.0
Input Voltage (bottom) (V)
1.88
Input Voltage (bottom) (V)
1.92
Time (100µs/div)
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—Step-Down Buck Converter (continued)
(IOUTBUCK = 100mA to 300mA; VBAT = 3.6V;
VOUTBUCK = 1.8V; COUT = 4.7µF)
2.00
1.90
1.60
100
IO
50
0
2.00
1.90
1.70
300
1.60
200
IO
100
0
Time (100µs/div)
Time (100µs/div)
3603.2008.06.1.0
VO
1.80
Output Current
(bottom) (mA)
1.70
Output Current
(bottom) (mA)
VO
1.80
Output Voltage (top) (V)
Load Transient Response Step-Down Buck
(IOUTBUCK = 10mA to 100mA; VBAT = 3.6V;
VOUTBUCK = 1.8V; COUT = 4.7µF)
Output Voltage (top) (V)
Load Transient Response Step-Down Buck
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13
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—LDO1
LDO1 Load Regulation vs. Output Current
LDO1 Line Regulation vs. Battery
and CHGIN Input Voltage
(VOUT1 = 3.0V)
(VOUT1 = 3.0V)
0.8
Line Regulation (%)
Load Regulation (%)
1.0
0.6
0.4
0.2
VBAT = 4.2V
0.0
-0.2
-0.4
VBAT = 3.6V
-0.6
VBAT = 3.3V
-0.8
-1.0
0.1
1
10
0.05
0.03
0.01
-0.01
-0.03
-0.07
-0.09
-0.11
-0.13
100
VBAT
-0.15
3
1000
3.5
Output Current (mA)
VCHGIN
4.5
5
5.5
(VOUT1 = 3.0V)
3.10
Output Voltage VOUT1 (V)
3.004
3.002
3.000
2.998
VCHGIN = 6.0V
VCHGIN = 5.5V
VCHGIN = 5.0V
VCHGIN = 4.5V
VBAT = 4.2V
VBAT = 3.6V
VBAT = 3.1V
2.996
2.994
-25
0
25
50
75
3.05
3.00
IOUT = 1mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
IOUT = 200mA
IOUT = 250mA
IOUT = 300mA
2.95
2.90
2.85
2.80
100
3.0
3.1
3.2
Temperature (°C)
3.3
3.4
3.5
VBAT Line Transient Response LDO1
(VOUT1 = 3.0V)
(VBAT = 3.5V to 4.2V; IOUT1 = 300mA; VOUT1 = 3V)
Output Voltage (top) (V)
Dropout Voltage (mV)
3.02
180
160
140
120
100
80
60
-40°C
25°C
85°C
40
20
0
50
100
150
200
250
3.01
VO
3.00
2.99
2.98
4.5
4.0
VBAT
3.5
3.0
Input Voltage (bottom) (V)
200
300
Output Current (mA)
14
3.6
Input Voltage (V)
LDO1 Dropout Voltage vs. Output Current
0
6
LDO1 Dropout Characteristics vs. Input Voltage
(IOUT1 = 10mA)
Output Voltage VOUT1 (V)
4.2
4
Input Voltage VBAT, VCHGIN (V)
LDO1 Output Voltage vs. Temperature
2.992
-50
IOUT = 0.01mA
IOUT = 1mA
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
-0.05
Time (100µs/div)
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—LDO1 (continued)
VCHGIN Line Transient Response LDO1
Load Transient Response LDO1
(VCHGIN = 4.5V to 5.5V; IOUT = 300mA; VOUT = 3V)
(IOUT1 = 10mA to 100mA; VBAT = 3.6V; VOUT1 = 3V)
3.00
2.99
2.98
6.0
5.5
5.0
VCHGIN
4.5
4.0
Output Voltage (top) (V)
VO
3.04
3.02
VO
3.00
2.98
2.96
Time (100µs/div)
100
IO
50
Output Current
(bottom) (mA)
Output Voltage (top) (V)
3.01
Input Voltage (bottom) (V)
3.02
0
Time (100µs/div)
Load Transient Response LDO1
(IOUT1 = 100mA to 300mA; VBAT = 3.6V; VOUT1 = 3V)
3.02
VO
3.00
2.98
2.96
300
200
IO
100
Output Current
(bottom) (mA)
Output Voltage (top) (V)
3.04
0
Time (100µs/div)
3603.2008.06.1.0
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15
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—LDO4
LDO4 Load Regulation vs. Output Current
LDO4 Load Regulation vs. Output Current
(VOUT4 = 3.0V)
(VOUT4 = 3.0V)
1.0
1.0
VCHGIN = 4.5V
VCHGIN = 5.0V
VCHGIN = 5.5V
VCHGIN = 6.0V
0.6
0.4
Load Regulation (%)
Load Regulation (%)
0.8
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.1
1
10
100
VBAT = 4.2V
VBAT = 3.6V
VBAT = 3.3V
VBAT = 3.1V
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.1
1000
1
Output Current (mA)
LDO4 Output Voltage vs. Temperature
100
1000
LDO4 Line Regulation vs. Battery
and CHGIN Input Voltage
(IOUT4 = 10mA)
(VOUT4 = 3.0V)
3.008
3.006
Line Regulation (%)
Output Voltage VOUT4 (V)
10
Output Current (mA)
3.004
3.002
3.000
VCHGIN = 6.0V
VCHGIN = 5.5V
VCHGIN = 5.0V
VCHGIN = 4.5V
VBAT = 4.2V
VBAT = 3.6V
VBAT = 3.1V
2.998
2.996
2.994
2.992
2.990
-50
-25
0
25
50
75
0.06
0.04
0.02
0
-0.02
-0.04
-0.08
-0.1
-0.12
-0.14
100
IOUT = 0.01mA
IOUT = 1mA
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
-0.06
VBAT
3
3.5
Temperature (°C)
4
4.2
VCHGIN
4.5
5
5.5
Input Voltage VBAT, VCHGIN (V)
LDO4 Dropout Characteristics vs. Input Voltage
LDO4 Dropout Voltage vs. Output Current
(VOUT4 = 3.0V)
(VOUT4 = 3.0V)
200
Dropout Voltage (mV)
Output Voltage (V)
3.10
3.05
3.00
2.95
2.90
IOUT = 1mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
2.85
2.80
3.0
3.1
3.2
3.3
3.4
3.5
3.6
180
160
140
120
100
80
60
-40°C
25°C
85°C
40
20
0
0
25
50
75
100
125
150
Output Current (mA)
Input Voltage (V)
16
6
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3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—LDO4 (continued)
VBAT Line Transient Response LDO4
VCHGIN Line Transient Response LDO4
(VBAT = 3.5V to 4.2V; IOUT4 = 150mA; VOUT4 = 3V)
(VCHGIN = 4.5V to 5.5V; IOUT4 = 150mA; VOUT4 = 3V)
3.00
2.99
2.98
4.5
4.0
VBAT
3.5
3.0
Output Voltage (top) (V)
Output Voltage (top) (V)
VO
3.02
3.01
VO
3.00
2.99
6.0
2.98
5.5
4.5
4.0
Time (100µs/div)
Time (100µs/div)
Load Transient Response LDO4
(IOUT4 = 10mA to 75mA; VBAT = 3.6V;
VOUT4 = 3V; COUT = 4.7µF)
(IOUT4 = 75mA to 150mA; VBAT = 3.6V;
VOUT4 = 3V; COUT = 4.7µF)
3.04
3.02
2.98
2.96
100
IO
50
0
3.04
3.02
2.98
2.96
Time (100µs/div)
3603.2008.06.1.0
VO
3.00
150
IO
100
50
Output Current
(bottom) (mA)
VO
3.00
Output Voltage (top) (V)
Load Transient Response LDO4
Output Current
(bottom) (mA)
Output Voltage (top) (V)
5.0
VCHGIN
Input Voltage (bottom) (V)
3.01
Input Voltage (bottom) (V)
3.02
0
Time (100µs/div)
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17
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Typical Characteristics—General
Quiescent Current vs. Input Voltage
Start-up Sequence
(VOUT = 1.8V; L = 3.3µH)
(VCHGIN = 5.0V)
450
Output Voltage (2V/div)
Quiescent Current (µA)
500
400
350
300
250
200
150
-40°C
25°C
85°C
100
50
0
VBAT
2.7
3.2
3.7
4.2
VCHGIN
4.7
5.2
Buck
LDO1
LDO2
LDO3
LDO4
LDO5
5.7
Time (50µs/div)
LDO Output Voltage Noise
LDO Output Voltage Noise
(No Load; Power BW: 100~100KHz)
(IOUT3 = 10mA, Power BW = 100~100KHz)
6.00
6.00
5.40
5.40
4.80
4.80
Noise (µVRMS)
Noise (µVRMS)
Input VBAT, VCHGIN (V)
4.20
3.60
3.00
2.40
1.80
4.20
3.60
3.00
2.40
1.80
1.20
1.20
0.60
0.60
0.00
100
1000
10000
100000
0.00
100
Frequency (Hz)
1000
10000
100000
Frequency (Hz)
LDO Power Supply Rejection Ratio, PSRR
(IOUT3 = 10mA, BW = 100~100KHz)
150
Magnitude (dB)
135
120
105
90
75
60
45
30
15
0
100
1000
10000
100000
Frequency (Hz)
18
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Functional Block Diagram
CHGIN
BAT
ADPP
Charger
Control
ENBAT
STAT
ISET
TS
CT
Ref
RESET
SDA
SCL
PVIN
UVLO
EN_TEST
I 2C
and
Enable
Control
EN_HOLD
EN_KEY
ON_KEY
LX
VIN
BUCK
Ref
OUTBUCK
Enable
PGND
EN2
EN3
EN4
VIN
REF
CNOISE
EN5
AVIN2
AVIN1
VIN
Ref
LDO1
LDO2
Enable
VIN
Ref
LDO3
Enable
VIN
Ref
LDO4
Enable
VIN
Ref
LDO5
Enable
Ref
VIN
Enable
AGND
OUT1
OUT2
OUT3
OUT4
OUT5
Functional Description
Typical Power Up Sequence
The AAT3603 is a complete power management solution.
It seamlessly integrates an intelligent, stand-alone CC/
CV (Constant Current/Constant Voltage), linear-mode
single-cell battery charger with one step-down Buck converter and five low-dropout (LDO) regulators to provide
power from either a wall adapter or a single-cell Lithium
Ion/Polymer battery.
The AAT3603 supports a variety of push-button or
enable/disable schemes. A typical startup and shutdown
process proceeds as follows (referring to Figures 1 and
2): System startup is initiated whenever one of the following conditions occurs:
If only the battery is available, then the voltage regulators and converter are powered directly from the battery.
(The charger is put into sleep mode and draws less than
1μA quiescent current.)
3603.2008.06.1.0
1) A push-button is used to assert EN_KEY low.
2) A valid supply (>CHGIN UVLO) is connected to the
charger input CHGIN.
3) A hands free device or headset is connected, asserting EN_TEST high.
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
The startup sequence for the AAT3603 core (Buck and
LDO1) is typically initiated by pulling the EN_KEY pin low
with a pushbutton switch, see Figure 1. The Buck (Core)
is the first block to be turned on. When the output of the
Buck reaches 90% of its final value, then LDO1 is
enabled. When LDO1 (PowerDigital) reaches 90% of its
final value, the 65ms RESET timer is initiated holding the
microprocessor in reset. When the RESET pin goes High,
the μP can begin a power up sequence. After the startup
sequence has commenced, LDO2 (PowerAnalog), LDO3
(TCXO), LDO4 (TX) and LDO5 (RX) can be enabled and
disabled as desired using their independent enable pins,
even while the Buck and LDO1 are still starting up.
However, if they are shut down, then LDO2, LDO3,
LDO4, and LDO5 cannot be enabled. The μP must pull
the EN_HOLD signal high before the EN_KEY signal can
be released by the push-button. This procedure requires
that the push-button be held until the μP assumes control of EN_HOLD, providing protection against inadvertent momentary assertions of the pushbutton. Once
EN_HOLD is high the startup sequence is complete. If
the μP is unable to complete its power-up routine successfully before the user lets go of the push-button, the
AAT3603 will automatically shut itself down. (EN_KEY
and EN_HOLD are OR’d internally to enable the two core
converters.)
Alternatively, the startup sequence is automatically
started without the pushbutton switch when the CHGIN
pin rises above its UVLO threshold. The system cannot
20
be disabled until the voltage at the CHGIN pin drops
below the falling UVLO threshold. Thirdly, the EN_TEST
pin can be used to startup the device for test purposes
or for hands free operation such as when connecting a
headset to the system.
Typical Power Down Sequence
If only the battery is connected and the voltage level is
above the BAT UVLO , then the EN_KEY pin can be held
low in order to power down AAT3603. The user can initiate a shutdown process by pressing the push-button a
second time. Upon detecting a second assertion of EN_
KEY (by depressing the push-button), the AAT3603
asserts ON_KEY to interrupt the microprocessor which
initiates an interrupt service routine that the user
pressed the push-button. If EN_TEST and CHGIN are
both low, the microprocessor then initiates a powerdown routine, the final step of which will be to de-assert
EN_HOLD, disabling LDO2, LDO3, LDO4, and LDO5.
When the voltage at the CHGIN pin is above the CHGIN
UVLO, the device cannot be powered down. If the voltage
at the CHGIN pin is below the CHGIN UVLO, both the
EN_KEY and EN_HOLD pins must be held low in order to
power down AAT3603. If LDO2, LDO3, LDO4, and LDO5
have not been disabled individually prior to global power
down, then they will be turned off simultaneously with the
Buck. The outputs of LDO4 and LDO5 are internally pulled
to ground with 10k during shutdown to discharge the output capacitors and ensure a fast turn-off response time.
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
CHGIN
UVLO
Debounce
BAT
EN_KEY
Push-button
On Switch
Enable
for BAT
Regulators
OUT1
ON_KEY
Micro
EN_HOLD
Processor
μP
EN_BAT
Automatic
Tester or
Handsfree
Operation
Enable for
Battery Charger
EN_TEST
Figure 1: Enable Function Detailed Schematic.
Power Up Sequence
Power Down Sequence
300ms
debounce
delay
EN_KEY
ON_KEY
EN_HOLD must be held high
before EN _KEY can be released .
EN_HOLD
OUTBuck
(Core)
OUT1
(PowerDigital)
90% Regulation
90% Regulation
65ms
RESET
Figure 2: Typical Power Up/Down Sequence.
3603.2008.06.1.0
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21
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Battery Charger
Figure 3 illustrates the entire battery charging profile
which consists of three phases.
1.
2.
3.
Preconditioning Current Mode (Trickle) Charge
Constant Current Mode Charge
Constant Voltage Mode Charge
Trickle charge is a safety precaution for a deeply discharged cell. It also reduces the power dissipation in the
internal series pass MOSFET when the input-output voltage differential is at its highest.
Constant Current Mode Charge Current
Preconditioning Trickle Charge
Battery charging commences only after the AAT3603
battery charger checks several conditions in order to
maintain a safe charging environment. The system
operation flow chart for the battery charger operation is
shown in Figure 4. The input supply must be above the
minimum operating voltage (UVLO) and the enable pin
(ENBAT) must be low (it is internally pulled down). When
the battery is connected to the BAT pin, the battery
charger checks the condition of the battery and determines which charging mode to apply.
Preconditioning Current Mode
Charge Current
If the battery voltage is below the preconditioning voltage threshold VMIN, then the battery charger initiates
precondition trickle charge mode and charges the battery at 12% of the programmed constant-current magnitude. For example, if the programmed current is
500mA, then the trickle charge current will be 60mA.
Trickle charge continues until the battery voltage reaches VMIN. At this point the battery charger begins constant-current charging. The current level default for this
mode is programmed using a resistor from the ISET pin
to ground. Once that resistor has been selected for the
default charge current, then the current can be adjusted
through I2C from a range of 40% to 180% of the programmed default charge current. Programmed current
can be set at a minimum of 100mA and up to a maximum of 1A. When the ADPP signal goes high, the default
I2C setting of 100% is reset.
Constant Voltage Mode Charge
Constant current charging will continue until the battery
voltage reaches the Output Charge Voltage Regulation
point VBAT_REG. When the battery voltage reaches the regulation voltage (VBAT_REG), the battery charger will transition
to constant-voltage mode. VBAT_REG is factory programmed
to 4.2V (nominal). Charging in constant-voltage mode will
continue until the charge current has reduced to the end
of charge termination current programmed using the I2C
interface (5%, 10%, 15%, or 20%).
I (mA)
V (V)
Preconditioning
Trickle Charge
Phase
Constant Current
Charge Phase
Constant Voltage
Charge Phase
FAST-CHARGE to
TOP-OFF Charge
Threshold
Constant-Current Mode
Charge Current (ICH_CC)
Battery End of Charge
Voltage Regulation (VBAT_REG)
Charge Voltage
Preconditioning Threshold
Voltage (VMiN)
Charge Current
Preconditioning Charge
Current (ICH_PRE)
Charge Termination
Threshold Current
(ICH_TERM)
T (s)
Trickle Charge
Timeout
(TK)
Constant Current Timeout
(TC)
Constant Voltage Timeout
(TV)
Figure 3: Current vs. Voltage and Charger Time Profile.
22
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Enable
No
Power On Reset
Yes
Power Input
Voltage
VCHGIN > VUVLO
Enable
Expired
Yes
Shut Down
Yes
Charge Timer
Control
Fault
Conditions Monitoring
OV, OT,
VTS1 < VTS < V TS2
No
Preconditioning
Test
VBAT < VMIN
Yes
Preconditioning
(Trickle Charge)
Thermal
Loop
Thermal
Loop
Current
Current
ReductionininADP
Reduction
C.C. ModeMode
Charging
Yes
No
No
No
Recharge Test
VBAT < VRCH
Yes
Current Phase Test
VBAT < VBAT_REG
Yes
Constant
Current Charge
Mode
Yes
Constant
Voltage Charge
Mode
Device Thermal
Loop Monitor
TJ > 115°C
No
Voltage Phase Test
ICH > ICH_TERM
No
Charge Completed
Figure 4: System Operation Flow Chart for the Battery Charger.
3603.2008.06.1.0
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PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Power Saving Mode
After the charge cycle is complete, the battery charger
turns off the series pass device and automatically goes into
a power saving sleep mode. During this time, the series
pass device will block current in both directions to prevent
the battery from discharging through the battery charger.
The battery charger will remain in sleep mode even if the
charger source is disconnected. It will come out of sleep
mode if either the battery terminal voltage drops below
the VRCH threshold, the charger EN pin is recycled, or the
charging source is reconnected. In all cases, the battery
charger will monitor all parameters and resume charging
in the most appropriate mode.
Temperature Sense (TS)
The TS pin is available to monitor the battery temperature. Connect a 10k NTC resistor from the TS pin to
ground. The TS pin outputs a 75μA constant current into
the resistor and monitors the voltage to ensure that the
battery temperature does not fall outside the limits
depending on the temperature coefficient of the resistor
used. When the voltage goes above 2.39V or goes below
0.331V, the charging current will be suspended.
small, and this pin is susceptible to noise and changes in
capacitance value. Therefore, the timing capacitor should
be physically located on the printed circuit board layout
as close as possible to the CT pin. Since the accuracy of
the internal timer is dominated by the capacitance value,
a 10% tolerance or better ceramic capacitor is recommended. Ceramic capacitor materials, such as X7R and
X5R types, are a good choice for this application.
Programming Charge Current (ISET)
At initial power-on, the charge current is always set to
100mA. The constant current mode charge level is user
programmed with the I2C interface and a set resistor
placed between the ISET pin and ground. The accuracy of
the constant charge current, as well as the preconditioning trickle charge current, is dominated by the tolerance
of the set resistor. For this reason, a 1% tolerance metal
film resistor is recommended for the set resistor function.
The programmable constant charge current levels from
100mA to 1A may be set by selecting the appropriate
resistor value from Table 1, Figure 5, and Table 3. The
ISET pin current to charging current ratio is 1 to 800. It
is regulated to 1.25V during constant current mode
unless changed using I2C commands. It can be used as a
charging current monitor, based on the equation:
Charge Safety Timer (CT)
While monitoring the charge cycle, the AAT3603 utilizes a
charge safety timer to help identify damaged cells and to
ensure that the cell is charged safely. Operation is as follows: upon initiating a charging cycle, the AAT3603 charges the cell at 12% of the programmed maximum charge
until VBAT >2.8V. If the cell voltage fails to reach the preconditioning threshold of 2.8V (typ) before the safety
timer expires, the cell is assumed to be damaged and the
charge cycle terminates. If the cell voltage exceeds 2.8V
prior to the expiration of the timer, the charge cycle proceeds into fast charge. There are three timeout periods: 1
hour for Trickle Charge mode, 3 hours for Constant
Current mode, and 3 hours for Constant Voltage mode.
The CT pin is driven by a constant current source and will
provide a linear response to increases in the timing
capacitor value. Thus, if the timing capacitor were to be
doubled from the nominal 0.1μF value, the time-out
periods would be doubled. If the programmable watchdog timer function is not needed, it can be disabled by
terminating the CT pin to ground. The CT pin should not
be left floating or unterminated, as this will cause errors
in the internal timing control circuit. The constant current provided to charge the timing capacitor is very
24
ICH = 800 ⋅
⎛ VISET⎞
⎝ RISET⎠
During preconditioning charge, the ISET pin is regulated
to 12% of the fast charge current ISET voltage level
(Figure 5), but the equation stays the same. During constant voltage charge mode, the ISET pin voltage will
slew down and be directly proportional to the battery
current at all times.
Constant Charging
Current ICH_CC (mA)
Set Resistor
Value (kΩ)
100
200
300
400
500
600
700
800
900
1000
10
4.99
3.32
2.49
2
1.65
1.43
1.24
1.1
1
Table 1: Constant Current Charge vs.
ISET Resistor Value.
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Constant Current Mode Charge Current
vs. ISET Resistor
ISET Voltage vs. Battery Voltage
(CHGIN = 5.0V, RISET = 1.24kΩ
Ω)
(VIN = 5V; VBAT = 3.6V)
1.4
1400
1.2
1
1000
VISET (V)
ICH_CC (mA)
1200
800
600
0.8
0.6
400
0.4
200
0.2
0
0.1
1
10
0
2.5
100
ISET Resistor (kΩ
Ω)
2.9
3.3
3.7
4.1
4.5
Battery Voltage (V)
Figure 5: Constant Current Mode Charge ICH_CC Setting vs. ISET Resistor
and ISET Voltage vs. Battery Voltage.
Reverse Battery Leakage
CHGIN Bypass Capacitor Selection
The AAT3603 includes internal circuitry that eliminates
the need for series blocking diodes, reducing solution
size and cost as well as dropout voltage relative to conventional battery chargers. When the input supply is
removed or when CHGIN goes below the AAT3603’s
under voltage-lockout (UVLO) voltage, or when CHGIN
drops below VBAT, the AAT3603 automatically reconfigures its power switches to minimize current drain from
the battery.
CHGIN is the power input for the AAT3603 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on CHGIN. In most applications, CHGIN is connected to either a wall adapter or
USB port. Under normal operation, the input of the charger will often be “hot-plugged” directly to a powered USB
or wall adapter cable, and supply voltage ringing and
overshoot may appear at the CHGIN pin. A high quality
capacitor connected from CHGIN to G, placed as close as
possible to the IC, is sufficient to absorb the energy.
Wall-adapter powered applications provide flexibility in
input capacitor selection, but the USB specification presents limitations to input capacitance selection. In order
to meet both the USB 2.0 and USB OTG (On The Go)
specifications while avoiding USB supply under-voltage
conditions resulting from the current limit slew rate
(100mA/μs) limitations of the USB bus, the CHGIN
bypass capacitance value must be between 1μF and
4.7μF. Ceramic capacitors are often preferred for bypassing due to their small size and good surge current ratings, but care must be taken in applications that can
encounter hot plug conditions as their very low ESR, in
combination with the inductance of the cable, can create
a high-Q filter that induces excessive ringing at the
CHGIN pin. This ringing can couple to the output and be
mistaken as loop instability, or the ringing may be large
enough to damage the input itself. Although the CHGIN
pin is designed for maximum robustness and an absolute
Adapter Power Indicator (ADPP)
This is an open drain output which will pull low when
VCHGIN > 4.5V. When this happens the charge current will
be reset to the default ISET values or I2C programmed
values.
Charge Status Output (STAT)
The AAT3603 provides battery charging status via a status pin. This pin is a buffered output with a supply level
up to the LDO1 output (PowerDigital). The status pin can
indicate the following conditions:
Event Description
STAT
No battery charging activity
Battery charging
Charging completed
Low (to GND)
High (to VOUT1)
Low (to GND)
Table 2: Charge Status Output (STAT).
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PRODUCT DATASHEET
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maximum voltage rating of +6.5V for transients, attention must be given to bypass techniques to ensure safe
operation. As a result, design of the CHGIN bypass must
take care to “de-Q” the filter. This can be accomplished
by connecting a 1Ω resistor in series with a ceramic
capacitor (as shown in Figure 6A), or by bypassing with
a tantalum or electrolytic capacitor to utilize its higher
ESR to dampen the ringing (as shown in Figure 6A). For
additional protection, Zener diodes with 6V clamp voltages may also be used. In any case, it is always critical
to evaluate voltage transients at the CHGIN pin with an
oscilloscope to ensure safe operation.
Thermal Considerations
The actual maximum charging current is a function of
charge adapter input voltage, the state of charge of the
battery at the moment of charge, and the ambient temperature and the thermal impedance of the package and
printed circuit board. The maximum programmable current may not be achievable under all operating parameters. One issue to consider is the amount of current being
sourced to the supply channels while the battery is being
charged.
The AAT3603 is offered in a TQFN55-36 package which
can provide up to 4W of power dissipation when it is
properly bonded to a printed circuit board and has a
maximum thermal resistance of 25°C/W. Many considerations should be taken into account when designing the
printed circuit board layout, as well as the placement of
the charger IC package in proximity to other heat generating devices in a given application design. The ambient temperature around the charger IC will also have an
effect on the thermal limits of a battery charging application. The maximum limits that can be expected for a
given ambient condition can be estimated by the following discussion. First, the maximum power dissipation for
a given situation should be calculated:
PD(MAX) =
(TJ(MAX) - TA)
θJA
Where:
PD(MAX) = Maximum Power Dissipation (W)
θJA = Package Thermal Resistance (°C/W)
TJ(MAX) = Maximum Device Junction Temperature (°C)
[150°C]
TA = Ambient Temperature (°C)
CHGIN
To USB Port or
Wall Adapter
To USB Port or
Wall Adapter
1Ω
CHGIN
4.7μF
ESR > 1Ω
1μF Ceramic
(XR5/XR7)
(A)
(B)
Figure 6: Hot Plug Requirements.
26
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Next, the power dissipation for the charger can be calculated by the following equation:
PD = (VCHGIN - VBAT) · ICH_CC + (VCHGIN · IOP) + (VCHGIN - VBAT) · IBAT
+ (VBAT - VOUT1) · IOUT1 + (VBAT - VOUT2) · IOUT2
+ (VBAT - VOUT3) · IOUT3 + (VBAT - VOUT4) · IOUT4
+ (VBAT - VOUT5) · IOUT5
+ IOUTBUCK2 · RDS(ON)L ·
VOUTBUCK
RDS(ON)H · [VBAT - VOUTBUCK]
VBAT +
VBAT
Where:
PD = Total Power Dissipation by the Device
VCHGIN = CHGIN Input Voltage
VBAT = Battery Voltage at the BAT Pin
ICH_CC = Constant Charge Current Programmed for the
Application
IOP = Quiescent Current Consumed by the IC for Normal
Operation [0.5mA]
VBAT = Load current from the BAT pin for the system
LDOs and step-down converter
RDS(ON)H and RDS(ON)L = On-resistance of step-down high
and low side MOSFETs [0.8Ω each]
VOUTX and IOUTX = Output voltage and load currents for
the LDOs and step-down converter [3V out for each
LDO]
By substitution, we can derive the maximum charge current before reaching the thermal limit condition (TREG =
100°C, Thermal Loop Regulation). The maximum charge
current is the key factor when designing battery charger
applications.
ICH_CC(MAX) =
(TREG - TA) - (V
CHGIN · IOP) - (VCHGIN - VBAT) · IBAT
θJA
- [(VBAT - VOUT1) · IOUT1] - (VBAT - VOUT2) · IOUT2
- [(VBAT - VOUT3) · IOUT3] - (VBAT - VOUT4) · IOUT4
- (VBAT - VOUT5) · IOUT5
VOUTBUCK
- IOUTBUCK2 · RDS(ON)L · V
+
BAT
RDS(ON)H · (VBAT - VOUTBUCK)
VBAT
VCHGIN - VBAT
3603.2008.06.1.0
In general, the worst condition is when there is the
greatest voltage drop across the charger, when battery
voltage is charged up to just past the preconditioning
voltage threshold and the LDOs and step-down converter are sourcing full output current.
For example, if 977mA is being sourced from the BAT pin
to the LDOs and Buck channels (300mA to LDO1, 100mA
to LDO2-5, and 277mA to the Buck; see buck efficiency
graph for 300mA output current) with a CHGIN supply of
5V, and the battery is being charged at 3.0V with 800mA
charge current, then the power dissipated will be 3.64W.
A reduction in the charge current (through I2C) may be
necessary in addition to the reduction provided by the
internal thermal loop of the charger itself.
For the above example at TA = 30°C, the ICH_CC(MAX) =
386mA.
Thermal Overload Protection
The AAT3603 integrates thermal overload protection
circuitry to prevent damage resulting from excessive
thermal stress that may be encountered under fault conditions, for example. This circuitry disables all regulators
if the AAT3603 die temperature exceeds 140°C, and
prevents the regulators from being enable until the die
temperature drops by 15°C (typ).
Synchronous Step-Down
Converter (Buck)
The AAT3603 contains a high performance 300mA,
1.5MHz synchronous step-down converter. The stepdown converter operates to ensure high efficiency performance over all load conditions. It requires only three
external power components (CIN, COUT, and L). A high DC
gain error amplifier with internal compensation controls
the output. It provides excellent transient response and
load/line regulation. Transient response time is typically
less than 20μs. The converter has soft start control to
limit inrush current and transitions to 100% duty cycle
at drop out.
The step-down converter input pin PVIN should be connected to the BAT output pin. The output voltage is
internally fixed at 1.8V. Power devices are sized for
300mA current capability while maintaining over 90%
efficiency at full load.
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Input/Output Capacitor and Inductor
Apart from the input capacitor that is shared with the LDO
inputs, only a small L-C filter is required at the output side
for the step-down converter to operate properly. Typically,
a 3.3μH inductor such as the Sumida CDRH2D11NP3R3NC and a 4.7μF ceramic output capacitor are recommended for low output voltage ripple and small component size. Ceramic capacitors with X5R or X7R dielectrics
are highly recommended because of their low ESR and
small temperature coefficients. A 10μF ceramic input
capacitor is sufficient for most applications.
Control Loop
The converter is a peak current mode step-down converter. The inner, wide bandwidth loop controls the
inductor peak current. The inductor current is sensed
through the P-channel MOSFET (high side) which is also
used for short circuit and overload protection. A fixed
slope compensation signal is added to the sensed current to maintain stability for duty cycles greater than
50%. The peak current mode loop appears as a voltage
programmed current source in parallel with the output
capacitor.
The output of the voltage error amplifier programs the
current mode loop for the necessary peak inductor current to force a constant output voltage for all load and
line conditions. The voltage feedback resistive divider is
internal and the error amplifier reference voltage is
0.45V. The voltage loop has a high DC gain making for
excellent DC load and line regulation. The internal voltage loop compensation is located at the output of the
transconductance voltage error amplifier.
Soft Start
Soft start slowly increases the internal reference voltage
when the input voltage or enable input is initially applied.
It limits the current surge seen at the input and eliminates output voltage overshoot.
Current Limit and
Over-Temperature Protection
For overload conditions the peak input current is limited.
As load impedance decreases and the output voltage
falls closer to zero, more power is dissipated internally,
28
raising the device temperature. Thermal protection completely disables switching when internal dissipation
becomes excessive, protecting the device from damage.
The junction over-temperature threshold is 140°C with
15°C of hysteresis.
Linear LDO Regulators (OUT1-5)
The advanced circuit design of the linear regulators has
been specifically optimized for very fast start-up and
shutdown timing. These proprietary LDOs are tailored for
superior transient response characteristics. These traits
are particularly important for applications which require
fast power supply timing.
There are two LDO input pins, AVIN1/2, which should be
connected to the BAT output pin. All LDO outputs are
initially fixed at 3.0V. The user can program the output
voltages for the LDOs to 2.8V, 2.85V, or 2.9V using I2C.
The high-speed turn-on capability is enabled through the
implementation of a fast start control circuit, which
accelerates the power up behavior of fundamental control and feedback circuits within the LDO regulator. For
LDO4 and LDO5, fast turn-off time response is achieved
by an active output pull down circuit, which is enabled
when the LDO regulator is placed in the shutdown mode.
This active fast shutdown circuit has no adverse effect on
normal device operation.
Input/Output Capacitors
The LDO regulator output has been specifically optimized
to function with low cost, low ESR ceramic capacitors.
However, the design will allow for operation over a wide
range of capacitor types. The input capacitor is shared
with all LDO inputs and the step-down converter. A 10μF
is sufficient. A 4.7μF ceramic output capacitor is recommended for LDO2-5 and a 22μF output capacitor for
LDO1.
Current Limit and
Over-Temperature Protection
The regulator comes with complete short circuit and
thermal protection. The combination of these two internal
protection circuits gives a comprehensive safety system
to guard against extreme adverse operating conditions.
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I2C Serial Interface
and Programmability
The timing diagram in Figure 7 depicts the transmission
protocol.
START and STOP Conditions
Serial Interface
Many of the features of the AAT3603 can be controlled via
the I2C serial interface. The I2C serial interface is a widely used interface where it requires a master to initiate all
the communications with the slave devices. The I2C protocol consists of 2 active wire SDA (serial data line) and
SCL (serial clock line). Both wires are open drain and
require an external pull up resistor to VCC (BAT may be
used as VCC). The SDA pin serves I/O function, and the
SCL pin controls and references the I2C bus. I2C protocol
is a bidirectional bus which allows both read and write
actions to take place, but the AAT3603 supports the write
protocol only. Since the protocol has a dedicated bit for
Read or Write access (R/W), when communicating with
AAT3603, this bit must be set to “0”.
ACK from slave
START
MSB
Chip
Address
1
0
LSB
W
ACK MSB
START and STOP conditions are always generated by the
master. Prior to initiating a START condition, both the
SDA and SCL pin are idle mode (idle mode is when there
is no activity on the bus and SDA and SCL are pulled to
VCC via external resistor). As depicted in Figure 7, a
START condition is defined to be when the master pulls
the SDA line low and after a short period pulls the SCL
line low. A START condition acts as a signal to all IC’s
that something is about to be transmitted on the BUS.
A STOP condition, also shown in Figure 7, is when the
master releases the bus and SCL changes from low to
high followed by SDA low to high transition. The master
does not issue an ACKNOWLEGE and releases the SCL
and SDA pins.
ACK from slave
Register
Address
LSB ACK MSB
ACK from slave
Data
LSB ACK STOP
SCL
SDA
0
1
1
0
0
0
including R/W bit,
Chip Address = 0x98
Figure 7: I2C Timing Diagram.
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Transferring Data
Every byte on the bus must be 8 bits long. A byte is
always sent with a most significant bit first (see Figure
8).
LSB
MSB
R/W
Figure 8: Bit Order.
The address is embedded in the first seven bits of the
byte. The eighth bit is reserved for the direction of the
information flow for the next byte of information. For
the AAT3603, this bit must be set to “0”. The full 8-bit
address including the R/W bit is 0x98 (hex) or
10011000 in binary.
Acknowledge Bit
The acknowledge bit is the ninth bit of data. It is used
to send back a confirmation to the master that the
data has been received properly. For acknowledge to
take place, the MASTER must first release the SDA
line, then the SLAVE will pull the data line low as
shown in Figure 7.
Serial Programming Code
After sending the chip address, the master should send
an 8-bit data stream to select which register to program
and then the codes that the user wishes to enter.
Register 0x00:
Timer
RCHG1
RCHG0
CHG2
CHG1
CHG0
Term1
Term0
Not used
Not used
Not used
Not used
SYS
LDO11
LDO10
LDO50
LDO41
LDO40
LDO31
LDO30
LDO21
LDO20
Register 0x01:
Not used
Register 0x02:
LDO51
Figure 9: Serial Programming Register Codes.
CHG2
CHG1
CHG0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Constant Current Charge
ICH_CC
100mA
(fixed internally)
640mA
480mA
320mA
960mA
1120mA
1280mA
1440mA
Constant Current Charge
as % of ISET Current
(default)
80%
60%
40%
120%
140%
160%
180%
Table 3: CHG Bit Setting for the Constant Current Charge Level
(assuming ISET resistor is set to default 800mA charge current).
30
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Notes concerning the operation of the CHG2, CHG1 and
CHG0 bits or ISET code:
• Once the part is turned on using the EN_KEY pin (and
there is a BAT and/or CHGIN supply), and data is sent
through I2C, the I2C codes in the registers will always
be preserved until the part is shut down using the
EN_HOLD (going low) or if the BAT and CHGIN supply
are removed.
• If the part is turned on by connecting supply CHGIN
(and not through EN_KEY), then when the CHGIN is
removed, the part will shut down and all I2C registers
will be cleared.
• ISET Code 000 in Register 0x00, bits 2,3,4 = 100mA.
• If the part has been turned on by EN_KEY and CHGIN
is disconnected then reconnected, the ISET code will
be forced to 000 and the current will be set to
100mA.
• The next time any I2C register is programmed (even if
it is not for the ISET code), the ISET code will revert
back to what it was before. For example, if the ISET
code is set to 010 and the part was turned on with
EN_KEY, then when CHGIN is disconnected then
reconnected, the charger will be set to 100mA. Then
if any other command is sent, the ISET code will
remain 010.
Term1
Term0
Termination Current (as % of Constant Current Charge)
0
0
1
1
0
1
0
1
5% (default)
10%
15%
20%
Table 4: Term Bit Setting for the Termination Current Level.
RCHG1
RCHG0
Recharge Threshold
0
0
1
1
0
1
0
1
4.00V (default)
4.05V
4.10V
4.15V
Table 5: RCHG Bit Setting for the Battery Charger Recharge Voltage Level.
Timer
Charger Watchdog Timer
0
1
ON (default)
OFF (and reset to zero)
Table 6: Timer Bit Setting for the Charger Watchdog Timer.
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LDO11
LDO10
LDO1 Output Voltage
0
0
1
1
0
1
0
1
3.00V (default)
2.90V
2.85V
2.80V
LDO21
LDO20
LDO2 Output Voltage
0
0
1
1
0
1
0
1
3.00V (default)
2.90V
2.85V
2.80V
LDO31
LDO30
LDO3 Output Voltage
0
0
1
1
0
1
0
1
3.00V (default)
2.90V
2.85V
2.80V
LDO41
LDO40
LDO4 Output Voltage
0
0
1
1
0
1
0
1
3.00V (default)
2.90V
2.85V
2.80V
LDO51
LDO50
LDO5 Output Voltage
0
0
1
1
0
1
0
1
3.00V (default)
2.90V
2.85V
2.80V
Layout Guidance
Figure 10 is the schematic for the evaluation board. The
evaluation board has extra components for easy evaluation; the actual BOM need for a system is shown in Table
9. When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT3603:
1.
2.
3.
4.
5.
Table 7: LDO Bit Setting for
LDO Output Voltage Level.
6.
7.
The exposed pad EP must be reliably soldered to
PGND/AGND and multilayer GND. The exposed thermal pad should be connected to board ground plane
and pins 2 and 16. The ground plane should include
a large exposed copper pad under the package with
VIAs to all board layers for thermal dissipation.
The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connection to the LX pins should be as short as possible.
Use several via pads when routing between layers.
The input capacitors (C1 and C2) should be connected as close as possible to CHGIN (Pin 28) and
PGND (Pin 2) to get good power filtering.
Keep the switching node LX away from the sensitive
OUTBUCK feedback node.
The feedback trace for the OUTBUCK pin should be
separate from any power trace and connected as
closely as possible to the load point. Sensing along a
high current load trace will degrade DC load regulation.
The output capacitor C4 and L1 should be connected
as close as possible and there should not be any
signal lines under the inductor.
The resistance of the trace from the load return to
the PGND (Pin 2) should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
Quantity
Value
Designator
Footprint
Description
5
2
4
3
1
1
9
8
1
10μF
22μF
4.7μF
0.1μF
0.01μF
3.3μH
100K
10K
1.24K
C1, C2, C3, C14, C15
C9
C4, C5, C6, C7, C8
C10, C11, C12
C13
L1
R5, R8, R20, R21, R22, R23, R25, R26, R27
R17, R19, R24, R29, R31, R32, R33, R37
R18
0603
0805
0603
0402
0402
CDRH2D
0402
0402
0402
Capacitor, Ceramic, X5R, 6.3V, ±20%
Capacitor, Ceramic, 20%, 6.3V, X5R
Capacitor, Ceramic, 20%, 6.3V, X5R
Capacitor, Ceramic, 16V, 10%, X5R
Capacitor, Ceramic, 16V, 10%, X7R
Inductor, Sumida CDRH2D11NP-3R3NC
Resistor, 5%
Resistor, 5%
Resistor, 1%
Table 8: Minimum AAT3603 Bill of Materials.
32
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Total Power Solution for Portable Applications
D1
NP1K
STAT
0
VDIG
PON_N
VANA
VTCXO
ACOK_N
EXT PWR
J12
INT/EXT PWR
2
BAT_ID
2
4
6
8
10
12
14
16
18
20
22
24
26
1
1
3
5
7
9
11
13
15
17
19
21
23
25
R32 NP 10k
R1
TP11
BAT
J1
STAT
3
R30
J10
R31
RESET_N
1
SDA
2 SCL
3
GND
4
10K
R33
TX_EN
PWR_HOLD
10K
DATA HEADER
VCORE
VBAT
TP1
VBAT
Header 13X2H
TP2
CHGIN
CHG_EN
J11
J3
VBAT
U1
3
2
CHGIN
1
C1
10μF
VBUS/VCHG
R2
28 CHGIN
30
0
29
C16
R4
0
R7
R6
0
VDIG
0.001μF
R5
100K
R8
J2
VTX
SDA
SCL
TCXO_EN
VRX
ANA_EN
100K
VBUS
VBATT
VCHG
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
ENBAT
R9
0
R10
0
R12
0
R14
0
N/C
N/C
AVIN1
AVIN2
PVIN
CHGIN
3
EN _KEY
2
1 EN_HOLD
EN_TEST
DNP
5
EN2
6 EN3
7
EN4
8
EN5
AAT3603
OUT1
OUT2
OUT3
OUT4
OUT5
LX
OUTBUCK
32
BAT_ID
31
CT
R28
Q1
CMPT3904
4.75K
R34 0
R35 0
R36 0
15
13
12
10
9
20
23
ISET
C12
0.1μF
VDIG
R19
10K
VDIG
R20
100K
R21
100K
J13
SW1
PWR_ON
RX_EN
PWR_ON
1
2
3
RX_EN
BAT
VDIG
R 24
10K
0 ACOK_N
0 PON_N
1
2
3
R25
100K
R22
100K
C5
4.7μF
C6
4.7μF
C7
4.7μF
C8
4.7μF
R15
0 RESET_N
17
R16
0 STAT
16
AGND
PGND 21
37
GND_SLUG
R29
10K
R37
NP
10K
ACOK_N RESET_N
TP3
TP5
C13
0.01μF
C9
22μF
VDIG
VCORE
STAT
TP6
R23
100K
J15
J16
1
1
TCXO_EN 2
ANA_EN 2
3
3
TX_EN
TCXO_EN
R 27
100K
J18
ANA_EN
CHG_EN
3
PWR_HOLD
TP7
GND
TP8
GND
TP12
GND
J20
1
PWR_HOLD 2
HF_PWR
C4
4.7μF
CHGIN
J17
HF_PWR
1
2
3
J9
OUT1
VDIG
J14
TX_EN
J8
OUT2
LX
R13
R39 0
VDIG
J7
OUT 3
22μF
PON_N
TP4
BAT
J6
OUT4
buckout
R38 0
C10
C11
0.1μF 0.1μF
J5
OUT5
L1 3.3μH
R17
10K
Header 13X2H
VTX VTCXO VANA VDIG
C15
OUT1
OUT2
OUT3
OUT4
OUT5
R11
TS
R18
1.24K
J4
BUCK
19
ADPP 4
ON-KEY
18
RESET 34
STAT
CNOISE
PWR_ON
RX_EN
HF_PWR
25
24
14
11
22
TP9
33
VCORE VRX
BAT
C3
22μF
35
36 SDA
SCL
VBATT
0.001μF
C17
BAT 27
26
BAT
1
2
3
CHG_EN
Figure 10: AAT3603 Evaluation Kit Schematic.
3603.2008.06.1.0
www.analogictech.com
33
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Ordering Information
Package
Part Marking1
Part Number (Tape and Reel)2
TQFN55-36
3YXYY
AAT3603IIH-T1
All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means semiconductor
products that are in compliance with current RoHS standards, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. For more information, please visit our website at
http://www.analogictech.com/about/quality.aspx.
Packaging Information
TQFN55-36
R = 0.1
3.600 ± 0.050
5.000 ± 0.050
Index Area
(D/2 x E/2)
C = 0.3
5.000 ± 0.050
Detail "A"
3.600 ± 0.050
Bottom View
Top View
0.750 ± 0.050
0.450 ± 0.050
0.200 ± 0.050
0.203 REF
+ 0.050
0.000 - 0.000
Side View
0.40 BSC
Detail "A"
All dimensions in millimeters.
1. XYY = assembly and date code.
2. Sample stock is generally held on part numbers listed in BOLD.
3. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing
process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection.
34
www.analogictech.com
3603.2008.06.1.0
PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
Advanced Analogic Technologies, Inc.
3230 Scott Boulevard, Santa Clara, CA 95054
Phone (408) 737-4600
Fax (408) 737-4611
© Advanced Analogic Technologies, Inc.
AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual
property rights are implied. AnalogicTech reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in AnalogicTech’s terms and
conditions of sale, AnalogicTech assumes no liability whatsoever, and AnalogicTech disclaims any express or implied warranty relating to the sale and/or use of AnalogicTech products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate
design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to
support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other
brand and product names appearing in this document are registered trademarks or trademarks of their respective holders.
3603.2008.06.1.0
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35