CY8C20111, CY8C20121 CapSense® Express™ – One Button and Two Button Capacitive Controllers CapSense® Express™ – One Button and Two Button Capacitive Controllers Features ■ ■ Capacitive button input tied to a configurable output ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, and sizes ■ Target Applications ❐ Printers ❐ Cellular handsets ❐ LCD monitors ❐ Portable DVD players ■ Industry's best configurability ❐ ❐ ❐ ❐ Custom sensor tuning Output supports strong 20 mA sink current Output state can be controlled through I2C or directly from CapSense input state Run time reconfigurable over I2C ■ Advanced features ❐ Plug-and-play with factory defaults – tuned to support up to 1 mm overlay ❐ Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool ■ Wide range of operating voltages ❐ 2.45 V to 2.9 V ❐ 3.10 V to 3.6 V ❐ 4.75 V to 5.25 V Cypress Semiconductor Corporation Document Number: 001-53516 Rev. *H • I2C communication ❐ Supported from 1.8 V ❐ Internal pull-up resistor support option ❐ Data rate up to 400 kbps. 2 ❐ Configurable I C addressing ■ Industrial temperature range: –40 °C to +85 °C ■ Available in 8-pin SOIC package Overview The CapSense® Express™ controllers support two capacitive sensing (CapSense) buttons and two general purpose outputs in CY8C20121 and one CapSense button and one general purpose output in CY8C20111. The device functionality is configured through the I2C port and can be stored in on-board nonvolatile memory for automatic loading at power on. The digital outputs are controlled from CapSense inputs in factory default settings, but are user configurable for direct control through I2C. The four key blocks that make up the CY8C20111 and CY8C20121 controllers are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and I2C communications. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs and permanently store the settings. The standard I2C serial communication interface allows the host to configure the device and read sensor information in real time. I2C address is fully configurable without any external hardware strapping. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 31, 2012 CY8C20111, CY8C20121 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Pinouts .............................................................................. 4 Pin Definitions .................................................................. 4 Typical Circuits ................................................................. 5 Operating Modes .............................................................. 8 Normal Mode ............................................................... 8 Setup Mode ................................................................. 8 I2C Interface ...................................................................... 8 I2C Device Addressing ................................................ 8 I2C Clock Stretching .................................................... 8 Format for Register Write and Read ........................... 9 Registers ........................................................................... 9 Register Conventions .................................................. 9 Register Map ............................................................. 10 CapSense Express Commands ................................ 11 OUTPUT_STATUS ................................................... 12 OUTPUT_PORT ........................................................ 12 CS_ENABLE ............................................................. 12 DIG_ENABLE ............................................................ 13 SET_STRONG_DM .................................................. 13 OP_SEL_x ................................................................. 15 LOGICAL_OPR_INPUTx .......................................... 15 CS_NOISE_TH ......................................................... 16 CS_BL_UPD_TH ....................................................... 16 CS_SETL_TIME ........................................................ 16 CS_OTH_SET ........................................................... 17 CS_HYSTERISIS ...................................................... 17 CS_DEBOUNCE ....................................................... 18 CS_NEG_NOISE_TH ................................................ 18 CS_LOW_BL_RST .................................................... 18 CS_FILTERING ......................................................... 19 CS_SCAN_POS_x .................................................... 19 CS_FINGER_TH_x ................................................... 20 CS_IDAC_x ............................................................... 20 I2C_ADDR_LOCK ..................................................... 20 DEVICE_ID ............................................................... 21 Document Number: 001-53516 Rev. *H DEVICE_STATUS ..................................................... 21 I2C_ADDR_DM ......................................................... 22 CS_READ_BUTTON ................................................. 22 CS_READ_BLx ......................................................... 23 CS_READ_DIFFx ...................................................... 23 CS_READ_RAWx ..................................................... 23 CS_READ_STATUS ................................................. 24 COMMAND_REG ...................................................... 24 Layout Guidelines and Best Practices ......................... 26 Example PCB Layout Design with Two CapSense Buttons and Two LEDs .................... 28 Operating Voltages ......................................................... 29 CapSense Constraints ................................................... 29 Absolute Maximum Ratings .......................................... 30 Operating Temperature .................................................. 30 Electrical Specifications ................................................ 31 DC Electrical Specifications ...................................... 31 CapSense Electrical Characteristics ......................... 33 AC Electrical Specifications ....................................... 33 Appendix ......................................................................... 35 Examples of Frequently Used I2C Commands ......... 35 Ordering Information ...................................................... 36 Ordering Code Definitions ......................................... 36 Thermal Impedances ...................................................... 36 Solder Reflow Specifications ........................................ 36 Package Diagram ............................................................ 37 Acronyms ........................................................................ 38 Document Conventions ................................................. 38 Units of Measure ....................................................... 38 Numeric Conventions ................................................ 38 Glossary .......................................................................... 39 Document History Page ................................................. 43 Sales, Solutions, and Legal Information ...................... 44 Worldwide Sales and Design Support ....................... 44 Products .................................................................... 44 PSoC Solutions ......................................................... 44 Page 2 of 44 CY8C20111, CY8C20121 Pinouts Figure 1. 8-pin SOIC (150 Mils) pinout CY8C20111 (1 Button) Pin Definitions 8-pin SOIC CY8C20111 (1 Button) Pin No Name 1 VSS Description 2 I2C SCL I2C Clock 3 I2C SDA I2C Data 4 CS0 CapSense Input 5 NC No Connect 6 DIG0 7 NC No Connect 8 VDD Supply Voltage Ground Digital Output Document Number: 001-53516 Rev. *H Page 3 of 44 CY8C20111, CY8C20121 Pinouts Figure 2. 8-pin SOIC (150 Mils) pinout CY8C20121 (2 Button) Pin Definitions 8-pin SOIC CY8C20121 (2 Button) Pin No Name 1 VSS Description 2 I2C SCL I2C Clock 3 I2C SDA I2C Data 4 CS0 CapSense Input 5 CS1 CapSense Input 6 DIG0 Digital Output 7 DIG1 Digital Output 8 VDD Ground Supply Voltage Document Number: 001-53516 Rev. *H Page 4 of 44 CY8C20111, CY8C20121 Typical Circuits Figure 3. Circuit-1: One Button and One LED [1] Figure 4. Circuit-2: One Button and One LED with I2C Interface Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. *H Page 5 of 44 CY8C20111, CY8C20121 Typical Circuits (continued) Figure 5. Circuit-3: Two Buttons and Two LEDs with I2C Interface Figure 6. Circuit-4: Compatibility with 1.8 V I2C Signaling [2, 3] Note 2. 1.8 V VDD_I2C VDD_CE and 2.4 V VDD_CE 5.25 V. 3. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM register and its factory setting. Document Number: 001-53516 Rev. *H Page 6 of 44 CY8C20111, CY8C20121 Typical Circuits (continued) Figure 7. Circuit-5: Powering Down CapSense Express Device for Low Power Requirements [4] Output enable LDO Output VDD LED Master Or Host CapSense Express I2C Pull UPs SDA I2C BUS SCL Note 4. For low power requirements, if VDD is to be turned off, the above concept can be used. The VDDs of CapSense Express, I2C pull-ups, and LEDs must be from the same source. Turning off the VDD ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins can cater to the power supply requirement of the circuit, the LDO can be avoided. Document Number: 001-53516 Rev. *H Page 7 of 44 CY8C20111, CY8C20121 Operating Modes I2C Interface Normal Mode The CapSense Express devices support the industry standard I2C protocol, which can be used to: In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to these registers can be done only in setup mode. Setup Mode All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. ■ Configure the device ■ Read the status and data registers of the device ■ Control device operation ■ Execute commands The I2C address can be modified during configuration. I2C Device Addressing The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending one byte address; first 7-bit contains address and LSb indicates the data transfer direction. Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different I2C addresses. Table 1. I2C Addresses 7-bit Slave Address (in Dec) D7 D6 D5 D4 D3 D2 D1 D0 8-bit Slave Address (in Hex) 1 0 0 0 0 0 0 1 0(W) 02 1 0 0 0 0 0 0 1 1(R) 03 75 1 0 0 1 0 1 1 0(W) 96 75 1 0 0 1 0 1 1 1(W) 97 I2C Clock Stretching “Clock stretching” or “bus stalling” in I2C communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master is expected to wait until the SCL is released by the slave. When an I2C master communicates with the CapSense Express device, the CapSense Express stalls the I2C bus after the reception of each byte (that is, just before the ACK/NAK bit) until processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate with the CapSense Express device. An I2C master which does not support clock stretching (a bit banged software I2C Master) must wait for a specific amount of time specified (as shown in the section Format for Register Write and Read) for each register write and read operation before the next bit is transmitted. It is mandatory to check the SCL status (it should be high) before I2C master initiates any data transfer with CapSense Express. If the master fails to do so and continues to communicate, the communication is erroneous. The following diagrams represent the ACK time delays shown in the Register Map on page 7. Figure 8. Write ACK Time Representation Document Number: 001-53516 Rev. *H Page 8 of 44 CY8C20111, CY8C20121 Figure 9. Read ACK Time Representation Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr A Data Register read format Start Slave Addr + W Start Slave Addr + R A A Reg Addr Data A A Stop Data Legends Master Slave A A Data ..... A ..... Data Data N A Stop Stop A – ACK N – NAK Registers Register Conventions Convention RW R WPR FD Description Register have both read and write access Register have only read access Write register with pass code Factory defaults Document Number: 001-53516 Rev. *H Page 9 of 44 CY8C20111, CY8C20121 Register Map Factory Default Writable I2C Max ACK I2C Max ACK Only in Values of Registers Time in in Setup Page No. (in Hex) Setup Normal Mode Time Mode (ms) [6] [5] [6] Mode (ms) 1 Button 2 Button Register Address (in Hex) Access OUTPUT_PORT 04 W – 01 03 0.10 – 12 CS_ENABLE 07 RW Yes 01 03 – 11 12 DIG_ENABLE 08 RW Yes 01 03 – 11 13 SET_STRONG_DM 11 RW Yes 01 03 – 11 13 OP_SEL_0 1C RW – 82 82 0.12 11 15 LOGICAL_OPR_INPUT0 1E RW – 01 01 0.12 11 15 OP_SEL_1 [7] 21 RW – 82 0.12 11 15 23 RW – 02 0.12 11 15 CS_NOISE_TH 4E RW – 28 0.11 11 16 CS_BL_UPD_TH 4F RW – 64 64 0.11 11 16 CS_SETL_TIME 50 RW Yes A0 A0 – 35 16 CS_OTH_SET 51 RW Yes 00 00 – 35 17 CS_HYSTERISIS 52 RW – 0A 0A 0.11 11 17 CS_DEBOUNCE 53 RW – 03 03 0.11 11 18 CS_NEG_NOISE_TH 54 RW – 14 14 0.11 11 18 CS_LOW_BL_RST 55 RW – 14 14 0.11 11 18 CS_FILTERING 56 RW – 20 20 0.11 11 19 CS_SCAN_POS_0 5C RW Yes 00 00 – 11 19 CS_SCAN_POS_1 [7] 5D RW Yes 01 – 11 19 CS_FINGER_TH_0 66 RW – 64 0.14 11 20 67 RW – 64 0.14 11 20 CS_IDAC_0 70 RW – 0A 0.14 11 20 CS_IDAC_1 [7] 71 RW – 0A 0.14 11 20 I2C_ADDR_LOCK 79 RW – 01 01 0.11 11 20 DEVICE_ID 7A R – 11 21 0.11 11 21 Name LOGICAL_OPR_INPUT1 CS_FINGER_TH_1 [7] [7] 28 64 0A DEVICE_STATUS 7B R – 03 03 0.11 11 21 I2C_ADDR_DM 7C RW – 80 80 0.11 11 22 CS_READ_BUTTON 81 RW – 81 81 0.12 11 22 CS_READ_BLM 82 R – NA NA 0.12 11 23 CS_READ_BLL 83 R – NA NA 0.12 11 23 CS_READ_DIFFM 84 R – NA NA 0.12 11 23 CS_READ_DIFFL 85 R – NA NA 0.12 11 23 CS_READ_RAWM 86 R – NA NA 0.12 11 23 CS_READ_RAWL 87 R – NA NA 0.12 11 23 Notes 5. These registers are writable only after entering into setup mode. All other registers are available for read and write in normal and setup mode. 6. The Ack times specified are 1x I2C Ack times. 7. These registers are available only in CY8C20121 device. Document Number: 001-53516 Rev. *H Page 10 of 44 CY8C20111, CY8C20121 Register Map (continued) Factory Default Writable I2C Max ACK I2C Max ACK Only in Values of Registers Time in in Setup Page No. (in Hex) Setup Normal Mode Time Mode (ms) [6] [5] [6] Mode (ms) 1 Button 2 Button Register Address (in Hex) Access CS_READ_STATUS 88 R – NA NA 0.12 11 24 COMMAND_REG A0 W – 00 00 0.10 11 24 Name CapSense Express Commands Command [8] Description Executable Mode Duration the Device is NOT Accessible after ACK (in ms) [9] W 00 A0 00 Get firmware revision Setup/Normal 0 W 00 A0 01 Store current configuration to NVM Setup/Normal 120 W 00 A0 02 Restore factory configuration Setup/Normal 120 W 00 A0 03 Write NVM POR defaults Setup/Normal 120 W 00 A0 04 Read NVM POR defaults Setup/Normal 5 W 00 A0 05 Read current configurations (RAM) Setup/Normal 5 W 00 A0 06 Reconfigure device (POR) Setup 5 W 00 A0 07 Set Normal mode of operation Setup/Normal 0 W 00 A0 08 Set Setup mode of operation Setup/Normal 0 W 00 A0 09 Start scan Setup/Normal 10 W 00 A0 0A Stop scan Setup/Normal 5 W 00 A0 0B Get CapSense scan status Setup/Normal 0 Notes 8. ‘W’ indicates the write transfer. The next byte of data represents the 7-bit I2C address. 9. The Ack times specified are 1x I2C Ack times. Document Number: 001-53516 Rev. *H Page 11 of 44 CY8C20111, CY8C20121 OUTPUT_STATUS Output Status Register OUTPUT_STATUS: 00h 1 Button 7 6 5 4 3 2 1 0 Access: FD R:01 Bit Name STS[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD R:03 Bit Name STS[1:0] The Output Status register represents the actual logical levels on the output pins. Bit 1:0 Name STS [1:0] Description Used to represent the output status 0 Output low 1 Output high OUTPUT_PORT Output Port Register OUTPUT_PORT: 04h 1 Button 7 6 5 4 3 2 1 0 Access: FD W:01 Bit Name DIG[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD W:03 Bit Name DIG[1:0] This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be changed using this register. Bit 1:0 Name DIG [1:0] Description A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ CS_ENABLE Select CapSense Input Register CS_ENABLE: 07h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name CS[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name CS[1:0] Document Number: 001-53516 Rev. *H Page 12 of 44 CY8C20111, CY8C20121 This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit 1:0 Name CS [1:0] Description These bits are used to enable CapSense inputs. 0 Disable CapSense input 1 Enable CapSense input DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name DIG[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name DIG [1:0] This register is used to enable DIG (Digital) outputs. If DIG output is enabled, the strong drive mode register (11h) should also be set. If DIG output is disabled the drive mode of these pins is High Z. Bit 1:0 Name DIG [1:0] Description These bits are used to enable DIG outputs. 0 Disable DIG output 1 Enable DIG output SET_STRONG_DM Sets Strong Drive Mode for DIG Outputs. SET_STRONG_DM: 11h (Writable only in Setup mode) 1 Button 7 6 5 4 3 2 1 0 Access: FD RW:01 Bit Name DM [0] 2 Button 7 6 5 4 3 2 1 0 Access: FD RW:03 Bit Name DM [1:0] This register sets strong drive mode for DIG (Digital) outputs. To set strong drive mode the pin should be enabled as GP output. Bit 1:0 Name DM [1:0] Document Number: 001-53516 Rev. *H Description These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set Page 13 of 44 CY8C20111, CY8C20121 Figure 10. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] LOGICAL_OPR_INPUT0 [0] A INVERSION LOGIC ENB DIG0 AND / OR Logic selection CS0 B S OP_SEL_0 [0] OP_SEL_0 [7] OP_SEL_0 [1] Figure 11. CY8C20121 Digital Logic Diagram LOGICAL_OPR_INPUTx [0] OUTPUT_PORT [x] ENB CS0 LOGICAL_OPR_INPUTx [1] ENB CS1 A A INVERSION LOGIC AND / OR Logic selection B AND / OR Logic selection B DIGx S S OP_SEL_x [7] OP_SEL_x [0] OP_SEL_x [1] INPUT SELECTION LOGIC Document Number: 001-53516 Rev. *H Page 14 of 44 CY8C20111, CY8C20121 OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch OP_SEL_1: 21h (Not available for 1 Button) 1/2Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW: 0 RW: 0 RW: 0 Op_En InvOp Operator This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not have any effect. The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output of logic operation can also be inverted. Bit 7 Name Op_En 1 InvOp 0 Operator Description This bit enables or disables logic operation. 0 Disable logic operation 1 Enable logic operation This bit enables or disables logic operation output inversion. 0 Logic operation output not inverted 1 Logic operation output inverted This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs LOGICAL_OPR_INPUTx Selects Input for Logic Operation LOGICAL_OPR_INPUT0: 1Eh LOGICAL_OPR_INPUT0 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 LOGICAL_OPR_INPUT1: 23h (Not available for 1 button) 6 5 4 3 2 1 6 5 4 3 2 1 0 RW:01 CSL[0] 0 RW:01 CSL [1:0] LOGICAL_OPR_INPUT1 2 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:02 CSL [1:0] These registers are used to give the input to logic operation block. The inputs can be only CapSense input status. Bit Name Description 1:0 CSL [1:0] These bits selects the input for logic operation block. Document Number: 001-53516 Rev. *H Page 15 of 44 CY8C20111, CY8C20121 CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 6 5 4 3 Access: FD RW:28 Bit Name NT[7:0] 2 1 0 This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to baseline. This parameter is common for all sensors. The range is 3 to 255 and it should satisfy the equation NT < Min (Finger Threshold – Hysteresis – 5). Recommended value is 40% of finger threshold. Bit Name Description 7:0 NT [7:0] These bits are used to set the noise threshold value. CS_BL_UPD_TH Baseline Update Threshold Register CS_BL_UPD_TH: 4Fh 1/2 Button 7 6 5 4 3 Access: FD RW:64 Bit Name BLUT[7:0] 2 1 0 When the new raw count value is above the current baseline and the difference is below the noise threshold, the difference between the current baseline and the raw count is accumulated into a “bucket.” When the bucket fills, the baseline increments and the bucket is emptied. This parameter sets the threshold that the bucket must reach for the baseline to increment. In other words, lower value provides faster baseline update rate and vice versa. This parameter is common for all sensors. The range is 0 to 255. Bit 7:0 Name BLUT [7:0] Description These bits set the threshold that the bucket must reach for baseline to increment. CS_SETL_TIME Settling Time Register CS_SETL_TIME: 50h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 5 4 3 RW:A0 STLNG_TM[7:0] 2 1 0 The settling time parameter controls the duration of the capacitance-to-voltage conversion phase. The parameter setting controls a software delay that allows the voltage on the integrating capacitor to stabilize. This parameter is common for all sensors. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. The range is 2 to 255. Bit 7:0 Name STLNG_TM [7:0] Document Number: 001-53516 Rev. *H Description These bits are used to set the settling time value. Page 16 of 44 CY8C20111, CY8C20121 CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 6 5 4 3 Access: FD RW: 00 RW: 0 Bit Name CS_CLK[1:0] Sns_Ar 2 1 0 The registers set the CapSense module frequency of operation and enables or disables the sensor auto reset. CS_CLK bits provides option to select variable clock input for the CapSense block. A sensor design having higher paratactic requires lower clock for better performance and vice versa. Sensor Auto Reset determines whether the baseline is updated at all times or only when the signal difference is below the noise threshold. When set to ‘1’ (enabled), the baseline is updated constantly. This setting limits the maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count suddenly rises without anything touching the sensor. This sudden rise can be caused by a large power supply voltage fluctuation, a high energy RF noise source, or a very quick temperature change. When the parameter is set to ‘0’ (disabled), the baseline is updated only when raw count and baseline difference is below the noise threshold parameter. This parameter may be enabled unless there is a demand to keep the sensors in the on state for a long time. This parameter is common for all sensors. Bit 6:5 Name CS_CLK[1:0] 3 Description These bits selects the CapSense clock. CS_CLK[1:0] Frequency of Operation 00 IMO 01 IMO/2 10 IMO/4 11 IMO/8 This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset Sns_Ar CS_HYSTERISIS Hysteresis Register CS_HYSTERISIS: 52h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name HYS[7:0] 2 1 0 The Hysteresis parameter adds to or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. If the sensor is off, the difference count must overcome the ‘finger threshold + hysteresis’. If the sensor is on, the difference count must go below the ‘finger threshold – hysteresis’. It is used to add debouncing and “stickiness” to the finger detection algorithm. This parameter is common for all sensors. Possible values are 0 to 255. However, the setting must be lower than the finger threshold parameter setting. Recommended value for hysteresis is 15 percent of finger threshold. Bit Name Description 7:0 HYS [7:0] These bits are used to set the hysteresis value. Document Number: 001-53516 Rev. *H Page 17 of 44 CY8C20111, CY8C20121 CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name DB[7:0] 2 1 0 The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference count value must stay above the ‘finger threshold + hysteresis’ for the number specified. This parameter is common for all sensors. Possible values are 1 to 255. A setting of ‘1’ provides no debouncing. Bit Name 7:0 DB [7:0] Description These bits are used to set the debounce value. CS_NEG_NOISE_TH Negative Noise Threshold Register CS_NEG_NOISE_TH: 54h 1/2 Button 7 6 5 4 3 Access: FD RW:0A Bit Name NNT[7:0] 2 1 0 This parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline is not updated. However, if the current raw count stays in the low state (difference greater than the threshold) for the number of samples specified by the Low Baseline Reset parameter, the baseline is reset. This parameter is common for all sensors. Bit Name Description 7:0 NNT [7:0] These bits are used to set the negative noise value. CS_LOW_BL_RST Low Baseline Reset Register CS_LOW_BL_RST: 55h 1/2 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:0A LBR[7:0] This parameter works together with the Negative Noise Threshold parameter. If the sample count values are below the baseline minus the negative noise threshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct the finger-on-at-startup condition. This parameter is common for all sensors. Bit 7:0 Name LBR [7:0] Document Number: 001-53516 Rev. *H Description These bits are used to set the Low Baseline Reset value. Page 18 of 44 CY8C20111, CY8C20121 CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 RW: 0 Access: FD RstBl Bit Name 6 5 RW: 1 I2C_DS 4 RW: 0 Avg_En 3 2 1 0 RW: 00 Avg_Order[1:0] This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit 7 Name RstBl 5 I2C_DS 4 Avg_En [1:0] Description This bit resets all the baselines and it is auto cleared to ‘0’. 0 All Baselines are not reset 1 All baselines are reset When this bit is set to ‘1’ the CapSense scan sample is dropped if I2C communication was active during scanning. 0 Disable the I2C drop sample filer 1 Enable the I2C drop sample filter This bit enables average filter on raw counts. 0 Disable the average filter 1 Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] Avg_Order[1:0] in Hex 00 01 10 11 Samples to Average 2 4 8 16 CS_SCAN_POS_x Scan Position Registers CS_SCAN_POS_0: 5Ch (Writable only in Setup mode) 1/2 Button 7 6 5 4 3 2 1 0 Access: FD RW: 0 Bit Name Scan_Pstn CS_SCAN_POS_1: 5Dh (Not available for 1 Button) (Writable only in Setup mode) 2 Button 7 6 5 4 3 2 1 0 Access: FD RW: 1 Bit Name Scan_Pstn This register is used to set the position of the sensors in the switch table for proper scanning sequence because the CapSense sensors are scanned in sequence. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name Description 0 Scan_Pstn This bit sets the scan position. Document Number: 001-53516 Rev. *H Page 19 of 44 CY8C20111, CY8C20121 CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h 1/2 Button 7 CS_FINGER_TH_1: 67h (Not available in 1 Button) 6 5 4 3 Access: FD RW: 64 Bit Name FT[7:0] 2 1 0 This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter should be configured individually for each CapSense inputs. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name Description [7:0] FT [7:0] These bit set the finger threshold for CapSense inputs. CS_IDAC_x IDAC Setting Registers CS_IDAC_0: 70h CS_IDAC_1: 71h (Not available in 1 Button) 1/2 Button 7 6 5 4 3 Access: FD RW: 0A Bit Name IDAC[7:0] 2 1 0 The IDAC register controls the sensitivity of the CapSense algorithm. This register is used to tune the CapSense input for specific design or overlays. Decreasing the value of this register increases the sensitivity of the CapSense buttons and vice versa. Decreasing the value of IDAC increases noise and vice versa. Possible values are 1 to 255. If the value is set to 0 then the value is reset to default value 10. The recommended value is greater than 4. Setting value 4 creates excessive amount of noise. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit Name Description [7:0] IDAC [7:0] These bit set the IDAC values. I2C_ADDR_LOCK I2C Address Lock Registers I2C_ADDR_LOCK: 79h 1/2 Button 7 6 5 4 3 2 1 0 WPR: 0 Access: FD I2CAL Bit Name I2 2 This register is used to unlock and lock the C address register (7Ch) access. The device I C address should be modified by writing new address to register 7Ch after unlocking the access using this register. Write to the 7C register during the locked state does not have any effect and the new address take effect only after the access is locked. To lock or unlock the I2C AL bit, the following three bytes must be written to register 79h: ■ unlock I2CAL: 3Ch A5h 69h ■ lock I2CAL: 96h 5Ah C3h Reading the I2CAL bit from register 79h indicates the current access state. Bit 0 Name I2CAL Document Number: 001-53516 Rev. *H Description This bit gives the lock/unlock status of I2C address. 0 Unlocked 1 Locked Page 20 of 44 CY8C20111, CY8C20121 DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button Access: FD Bit Name 7 6 5 4 3 2 1 0 3 2 1 0 R: 11 DEV_ID[7:0] 2 Button Access: FD Bit Name 7 6 5 4 R: 21 DEV_ID[7:0] This register contains the device and product ID. The device and product ID corresponds to “xx” in CY8C201xx. Bit 7:0 Name DEV_ID [7:0] Description These bits contain the device and product ID. Part No CY8C20111 CY8C20121 Device/Product ID 11 21 DEVICE_STATUS Device Status Register DEVICE_STATUS: 7Bh 1/2 Button 7 6 Access: FD R : 00 Ip_Volt[1:0] Bit Name 5 R: 0 IRES 4 R:0 Load_FD 3 R: 0 No_NVM_Wr 2 1 R: 0 CSE 0 R: 0 DIGE This register contains the device status. Bit 7:6 Name Ip_Volt [1:0] Description Supply voltage is automatically detected and these bits are set accordingly. Ip_Volt[1:0] 00 01 10 11 5 IRES 4 Load_FD 3 No_NVM_Wr 1 CSE 0 DIGE Document Number: 001-53516 Rev. *H Supply Voltage 5 3.3 2.7 Reserved When set to ‘1’, this bit indicates that an internal reset occurred. 0 indicates the last system reset was not internal reset 1 indicates the last system reset was internal reset This bit indicates whether factory defaults are loaded during power-up. 0 User default configuration is loaded during power-up 1 Factory default configuration is loaded during power-up When set to ‘1’, this bit indicates that the supply voltage applied to the device Is too low for a write to nonvolatile memory operation, and no write is performed. This bit must be checked before any Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled Page 21 of 44 CY8C20111, CY8C20121 I2C_ADDR_DM Device I2C Address and I2C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 6 5 4 3 2 Access: FD RW: 0 RW: 00 Bit Name I2CIP_EN I2C_ADDR[6:0] 1 0 This register sets the drive mode of I2C pins and I2C slave address. To write to this register, register 79h must first be unlocked. The value written to register 7Ch is applied only after locking register 79h again. Bit 7 Name I2CIP_EN 6:0 I2C_ADDR [6:0] Description This bit is used to set the I2C pins drive mode. 0 Internal pull-up enabled 1 Internal pull-up disabled Used to set the device I2C address. CS_READ_BUTTON Button Select Register I2C_ADDR_DM: 81h 1 Button 7 6 5 4 3 2 1 0 Access: FD RW: 0 RW: 0 Bit Name RD_EN CSBN[0] 2 Button 7 Access: FD RW: 0 RW: 00 Bit Name RD_EN CSBN[1:0] 6 5 4 3 2 1 0 The scan result of a CapSense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h–87h registers. This register is used to select a CapSense input to read the raw count, difference count, and baseline. Only the pins defined as CapSense inputs in register 07h can be used with this register. Trying to select other pins not defined as CapSense does not have any change. Bit 7 Name RD_EN 1:0 CSBN [1:0] Description This bit enables the CapSense raw data reading. 0 Disable CapSense scan result reading 1 Enable CapSense scan result reading These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] 01 10 Document Number: 001-53516 Rev. *H CapSense Button No 1 2 Page 22 of 44 CY8C20111, CY8C20121 CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h 1/2 Button 7 CS_READ_BLL: 83h 6 5 4 3 Access: FD R: 00 Bit Name BL [7:0] 2 1 0 1 0 1 0 Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit Name Description 7:0 BL [7:0] These bits represent the baseline value. CS_READ_DIFFx Difference Count Value MSB/LSB Registers CS_READ_DIFFM: 82h 1/2 Button 7 CS_READ_DIFFL: 83h 6 5 4 3 Access: FD R: 00 Bit Name DIF [7:0] 2 Reading from this register returns the 2-byte current difference count for the selected CapSense input. Bit Name Description 7:0 DIF [7:0] These bits represent the sensor difference count. CS_READ_RAWx Difference Count Value MSB/LSB Registers CS_READ_RAWM: 82h 1/2 Button 7 CS_READ_RAWL: 83h 6 5 4 3 Access: FD R: 00 Bit Name RC [7:0] 2 Reading from this register returns the 2-byte current raw count value for the selected CapSense input. Bit Name Description 7:0 RC [7:0] These bits represent the raw count value. Document Number: 001-53516 Rev. *H Page 23 of 44 CY8C20111, CY8C20121 CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 6 5 4 3 2 1 0 Access: FD R: 0 Bit Name BT_ST[0] 2 Button 7 6 5 4 3 2 1 0 Access: FD R: 00 Bit Name BT_ST[1:0] This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ indicates sensor is OFF. Bit 1:0 Name BT_ST [1:0] Description These bits used to represent sensor status. 0 Sensor OFF 1 Sensor ON COMMAND_REG Command Register COMMAND_REG: A0h 1/2 Button 7 6 5 4 3 Access: FD W: 00 Bit Name Cmnd [7:0] 2 1 0 Commands are executed by writing the command code to the command register. Bit Name Description 7:0 Cmnd [7:0] Refer to the following table for command register opcodes. Command Code Name Description 00h Get Firmware Revision The I2C buffer is loaded with the one byte firmware revision value. Reading one byte after writing this command returns the firmware revision. The upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. 01h Store Current Configuration to NVM The current register settings are saved in nonvolatile memory (flash). This setting is automatically loaded after the next device reset/power-up or if the Reconfigure Device (06h) command is issued. 02h Restore Factory Configuration Replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings are loaded after the next device reset/power-up or if the 06h command is issued. 03h Write POR Defaults Sends new power-up defaults to the CapSense controller without changing current settings unless the 06h command is issued afterwards. This command is followed by 123 data bytes according to the POR Default Data Structure table. The CRC is calculated as the XOR of the 122 data bytes (00h-79h). If the CRC check fails or an incomplete block is sent, the slave responds with an ACK and the data is NOT saved to flash. To define new POR defaults: Document Number: 001-53516 Rev. *H ■ Write command 03h ■ Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) ■ Write one CRC byte calculated as XOR of previous 122 data bytes Page 24 of 44 CY8C20111, CY8C20121 Command Code 04h 05h Name Read POR Defaults Read Device Configuration (RAM) Description Reads the POR settings stored in the nonvolatile memory. To read POR defaults: ■ Write command 04h ■ Read 122 data bytes ■ Read one CRC byte Reads the current device configuration. Gives the user “flat-address-space” access to all device settings. To read device configuration: ■ Write command 05h ■ Read 122 data bytes ■ Read one CRC byte 06h Reconfigure Device (POR) Immediately reconfigures the device with actual POR defaults from flash. Has the same effect on the registers as a POR. This command can only be executed in setup operation mode (command code 08). 07h Set Normal Operation Mode Sets the device in normal operation mode. In this mode, CapSense pin assignments cannot be modified; settling time, IDAC setting, external capacitor, and sensor auto-reset also cannot be modified. 08h Set Setup Operation Mode Sets the device in setup operation mode. In this mode, CapSense pin assignments can be changed along with other parameters. 09h Start CapSense Scanning Allows the user to start CSA scanning after it has been stopped using command 0x0A. Note that at POR, scanning is enabled and started by default if one or more sensors are enabled. 0Ah Stop CapSense Scanning Allows the user to stop CSA scanning. A system host controller might initiate this command before powering down the device to make sure that during power-down no CapSense touches are detected. When CSA scanning is stopped by the user and the device is still in the valid VCC operating range, the following behavior is supported: 0Bh Returns CapSense Scanning Status Document Number: 001-53516 Rev. *H ■ Any change to configuration can still be done (as long as VCC is in operating range). ■ Command code 0x06 overrides the status of stop/scan by enabling and starting CSA scanning if one or more sensors are enabled. ■ CapSense read-back values return 0x00. The I2C buffer is loaded with the one-byte CSA scanning status value. After writing the value 0Bh to the A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because VCC is outside the valid operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. Page 25 of 44 CY8C20111, CY8C20121 Layout Guidelines and Best Practices Table 2. Layout Guidelines and Best Practices Sl. No. Category Min Max Recommendations/Remarks – – Solid round pattern, round with LED hole, rectangle with round corners 5 mm 15 mm 10 mm = Button Ground Clearance – 8 mm 0.5 mm 2 mm 1 Button Shape 2 Button Size 3 Button Button Spacing 4 Button Ground Clearance 5 Ground Flood – Top Layer – – Hatched ground 7 mil trace and 45 mil grid (15% filling) 6 Ground Flood – Bottom Layer – – Hatched ground 7 mil trace and 70 mil grid (10% filling) 7 Trace Length from Sensor to PSoC - Buttons – 200 mm < 100 mm. 8 Trace Width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 Trace Routing – – Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. 10 Via Position for the Sensors – – Via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 11 Via Hole Size for Sensor Traces – – 10 mil 12 No. of Via on Sensor Trace 1 2 1 13 CapSense Series Resistor Placement – 10mm Place CapSense series resistors close to PSoC for noise suppression.CapSense resistors have highest priority place them first. 14 Distance between any CapSense Trace to Ground Flood 10 mil 20 mil 20 mil 15 Device Placement – – Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum 16 Placement of Components in 2 Layer PCB – – Top layer-sensor pads and bottom layer-PSoC, other components and traces. 17 Placement of Components in 4 Layer PCB – – Top layer-sensor pads, second layer – CapSense traces, third layer-hatched ground, bottom layer- PSoC, other components and non CapSense traces 18 Overlay Material – – Should to be non conductive material. Glass, ABS Plastic, Formica 19 Overlay Adhesives – – Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended. 20 LED Back Lighting – – Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs on page 28. 21 Board Thickness – – Standard board thickness for CapSense FR4 based designs is 1.6 mm. Button ground clearance = Overlay Thickness The Recommended maximum overlay thickness is 2 mm. For more details refer to the section “The Integrating Capacitor (Cint)” in AN53490. Document Number: 001-53516 Rev. *H Page 26 of 44 CY8C20111, CY8C20121 Figure 12. Button Shapes Figure 13. Button Layout Design X: Button to ground clearance Y: Button to button clearance Figure 14. Recommended Via-hole Placement Document Number: 001-53516 Rev. *H Page 27 of 44 CY8C20111, CY8C20121 Example PCB Layout Design with Two CapSense Buttons and Two LEDs Figure 15. Top Layer Figure 16. Bottom Layer Document Number: 001-53516 Rev. *H Page 28 of 44 CY8C20111, CY8C20121 Operating Voltages For details on I2C 1x Ack time, refer Table on page 10 and Table on page 11. I2C 4x Ack time is approximately four times the values mentioned in these tables. CapSense Constraints Parameter Min Typ Max Units Parasitic Capacitance (CP) of the CapSense Sensor – – 30 pF Supply Voltage Variation (VDD) – – ± 5% Document Number: 001-53516 Rev. *H Notes Page 29 of 44 CY8C20111, CY8C20121 Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes –55 25 +100 °C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C (0 °C to 50 °C). Extended duration storage temperatures above 65 °C degrade reliability – 125 See Package label °C See package label – 72 Hours TSTG Storage temperature TBAKETEMP Bake Temperature tBAKETIME Bake Time TA Ambient temperature with power applied –40 – +85 °C VDD Supply voltage on VDD relative to VSS –0.5 – +6.0 V VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any GPIO pin –25 – +50 mA ESD Electro static discharge voltage 2000 – – V LU Latch up current – – 200 mA Human body model ESD Operating Temperature Min Typ Max Unit TA Parameter Ambient temperature Description –40 – +85 °C TJ Junction temperature –40 – +100 °C Document Number: 001-53516 Rev. *H Notes Page 30 of 44 CY8C20111, CY8C20121 Electrical Specifications DC Electrical Specifications DC Chip Level Specifications Table 3. DC Chip Level Specifications Parameter Description Min Typ Max Unit VDD Supply voltage 2.40 – 5.25 V IDD Supply current – 1.5 2.5 mA Notes Conditions are VDD = 3.10 V, TA = 25 °C DC GPIO Specifications Table 4 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C < TA < 85 °C, 3.10 V to 3.6 V –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 4. 5-V and 3.3-V DC GPIO Specifications Parameter Description Min Typ Max Unit Notes VOH1 High output voltage VDD – 0.2 – – V IOH < 10 µA/pin, VDD > 3.10 V VOH2 High output voltage VDD – 0.9 – – V IOH = 1 mA/pin, VDD 3.10 V VOL Low output voltage – – 0.75 V IOL = 20 mA/pin, VDD > 3.10 V, maximum of 40 mA sink current IOH High output current 0.01 – 1 mA VDD 3.1 V IOL1 Low output current on Port 0 pins – – 10 mA VDD 3.1 V, maximum of 40 mA sink current COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25 °C. Table 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only. Table 5. 2.7-V DC GPIO Specifications Parameter Description Min Typ Max Unit – – V VOH1 High output voltage VDD – 0.2 Notes IOH 10 µA/pin VOH2 High output voltage VDD – 0.5 – – V IOH = 0.2 mA/pin VOL Low output voltage – – 0.75 V IOL = 10 mA/pin, maximum of 20 mA sink current IOH High output current 0.01 – 0.2 mA VDD 2.9 V IOL1 Low output current on Port 0 pins – – 10 mA VDD 2.9 V, maximum of 20 mA sink current COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25 °C. Min Typ Max Unit Notes V V VDD must be greater than or equal to 2.5 V during startup or reset from watchdog. DC POR and LVD Specifications Table 6. DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 Description VDD Value for PPOR Trip VDD = 2.7 V VDD = 3.3 V, 5 V Document Number: 001-53516 Rev. *H – – 2.36 2.60 2.40 2.65 Page 31 of 44 CY8C20111, CY8C20121 DC Flash Write Specifications Table 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications are valid only within the range: 25 °C±20 °C during the flash write operation. It is at the user’s own risk to operate out of this temperature range. If flash writing is done out of this temperature range, the endurance and data retention reduces. Table 7. DC Flash Write Specifications Symbol VDDIWRITE IDDP FlashENPB FlashDR Description Supply Voltage for Flash Write Operations [10] Supply Current for Flash Write Operations Flash Endurance Flash Data Retention Min 2.7 Typ – Max – Units V – 5 25 mA 50,000 10 – – – – Notes – Erase/write cycles Years DC I2C Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 8. DC I2C Specifications Symbol [11] VILI2C Description Input low level VIHI2C VOLP Input high level Low output voltage CI2C Capacitive load on I2C pins RPU Pull-up resistor Min – – 0.7 × VDD – Typ – – – – 0.5 1.7 4 5.6 Max Units Notes 0.3 × VDD V 2.4 V VDD 3.6 V 0.25 × VDD V 4.75 V VDD 5.25 V – V 2.4 V VDD 5.25 V 0.4 V IOL = 5 mA/pin, maximum of 10 mA device sink current 2.4 VDD 2.9 V and 3.1 VDD 3.6 V. 5 pF Package and pin dependent. Temp = 25 °C. 8 k Note 10. Commands involving flash writes (0x01, 0x02, 0x03) and flash read (0x04) must be executed only within the same VCC voltage range detected at POR (power on, or command 0x06) and above 2.7 V. 11. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-53516 Rev. *H Page 32 of 44 CY8C20111, CY8C20121 CapSense Electrical Characteristics Max (V) Typ (V) Min (V) Conditions for Supply Voltage Result 3.6 3.3 3.1 < 2.9 The device automatically reconfigures itself to work in 2.7 V mode of operation. 2.90 2.7 2.45 > 2.9 or < 3.10 5.25 5.0 4.75 This range is not recommended for CapSense usage. < 2.45 V The scanning for CapSense parameters shuts down until the voltage returns to over 2.45 V. > 3.10 The device automatically reconfigures itself to work in 3.3 V mode of operation. < 2.4 V The device goes into reset. < 4.73 V The scanning for CapSense parameters shuts down until the voltage returns to over 4.73 V. AC Electrical Specifications AC Chip-Level Specifications Table 9. 5-V and 3.3-V AC Chip-Level Specifications Parameter Description Min Typ Max Units F32K1 Internal low-speed oscillator (ILO) frequency 15 32 64 tXRST External reset pulse width 10 – – µs tPOWERUP Time from end of POR to CPU executing code – 150 – ms SRPOWER_UP Power supply slew rate – – 250 V/ms Min Typ Max Units Notes kHz Calculations during sleep operations are done based on ILO frequency. Table 10. 2.7-V AC Chip-Level Specifications Parameter Description Notes F32K1 Internal low-speed oscillator (ILO) frequency 8 32 96 kHz Calculations during sleep operations are done based on ILO frequency. tXRST External reset pulse width 10 – – µs tPOWERUP Time from end of POR to CPU executing code – 600 – ms SRPOWER_UP Power supply slew rate – – 250 V/ms Min Max Unit Notes AC GPIO Specifications Table 11. 5-V and 3.3-V AC GPIO Specifications Parameter Description tRise Rise time, strong mode, Cload = 50 pF 15 80 ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% tFall Fall time, strong mode, Cload = 50 pF 10 50 ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% Document Number: 001-53516 Rev. *H Page 33 of 44 CY8C20111, CY8C20121 Table 12. 2.7-V AC GPIO Specifications Parameter Description Min Max Unit Notes tRise Rise time, strong mode, Cload = 50 pF 15 100 ns VDD = 2.4 V to 2.90 V, 10% to 90% tFall Fall time, strong mode, Cload = 50 pF 10 70 ns VDD = 2.4 V to 2.90 V, 10% to 90% AC I2C Specifications Table 13. AC I2C Specifications Parameter Standard Mode Description Fast Mode Min Max Min Max 0 100 0 400 Units FSCLI2C SCL clock frequency tHDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – µs tLOWI2C LOW period of the SCL clock 4.7 – 1.3 – µs tHIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – µs tSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – µs tHDDATI2C Data hold time 0 – 0 – µs tSUDATI2C Data setup time 250 – 100 – ns tSUSTOI2C Setup time for STOP condition 4.0 – 0.6 – µs tBUFI2C BUS free time between a STOP and START condition 4.7 – 1.3 – µs tSPI2C Pulse width of spikes suppressed by the input filter – – 0 50 ns Notes kbps Fast mode not supported for VDD < 3.0 V Figure 17. Definition of Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C TSPI2C THDDATI2CTSUSTAI2C TBUFI2C I2C_SCL THIGHI2C TLOWI2C S START Condition Document Number: 001-53516 Rev. *H TSUSTOI2C Sr Repeated START Condition P S STOP Condition Page 34 of 44 CY8C20111, CY8C20121 Appendix Examples of Frequently Used I2C Commands SI. No. Requirement I2C Commands [12] Comments 1 Enter into setup mode W 00 A0 08 2 Enter into normal mode W 00 A0 07 3 Load factory defaults to RAM registers W 00 A0 02 4 Do a software reset W 00 A0 08 W 00 A0 06 5 Save current configuration to flash W 00 A0 01 6 Load factory defaults to RAM W 00 A0 08 registers and save as user config- W 00 A0 02 uration W 00 A0 01 W 00 A0 06 7 Disable combinational logic output to DIG0 W 00 1C 00 8 Disable combinational logic output to DIG1 W 00 21 00 9 Clearing (logic 0) the both DIG0 W 00 04 00 and DIG1 outputs 10 Setting (logic 1) the DIG0 and clearing (Logic 0) the DIG1 outputs W 00 04 01 11 Clearing (logic 0) the DIG0 and Setting (Logic 1) the DIG1 outputs W 00 04 02 12 Setting (logic 1) the both DIG0 and DIG1 outputs W 00 04 03 13 Change CapSense clock to IMO/2 W 00 A0 08 W 00 51 20 W 00 A0 07 ; Enter into setup mode ; CapSense clock is set as IMO/2 ; Enter into normal mode 14 Change value of IDAC0 to ‘x’h W 00 70 x ‘x’ represents new value of IDAC register 15 Change value of IDAC1 to ‘y’h W 00 71 y ‘y’ represents new value of IDAC register 16 Change value of IDAC0 and IDAC1 to ‘x’h and ‘y’h W 00 70 x y ‘x’ and ‘y’ represents new value of IDAC register 17 Change the value FT0 to ‘x’h W 00 66 x ‘x’ represents new value of FT register 18 Change the value FT1 to ‘y’h W 00 67 y ‘y’ represents new value of FT register 19 Change the value FT0 and FT1 to W 00 66 x y ‘x’h and ‘y’h 20 Change noise threshold to ‘x’h W 00 4E x 21 Read CapSense button CS0 scan results W 00 81 81 W 00 82 R 00 RD RD RD RD RD RD ; Select CapSense button for reading scan result ; Set the read point to 82h ; Consecutive 6 reads gets baseline, difference count and raw count (all two byte each) 22 Read CapSense button status register W 00 88 R 00 RD ; Set the read pointer to 88 ; Reading a byte gets status CapSense inputs ; Enter into setup mode ; Do software reset ; Enter into setup mode ; Load factory defaults to SRAM ; Save the configuration to flash. Wait for time specified in CapSense Express Commands on page 11. ; Do software reset Combinational logic output on DIG0 and DIG1 should be disabled before dong this operation (SL# 7 and 8) ‘x’ and ‘y’ represents new value of FT registers Note 12. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations. Document Number: 001-53516 Rev. *H Page 35 of 44 CY8C20111, CY8C20121 Ordering Information Ordering Code Package Diagram Operating CapSense CapSense Temperature Blocks Inputs Package Type Digital Outputs XRES Pin CY8C20111-SX1I 51-85066 8-pin SOIC Industrial Yes 1 1 No CY8C20111-SX1IT 51-85066 8-pin SOIC (Tape and Reel) Industrial Yes 1 1 No CY8C20121-SX1I 51-85066 8-pin SOIC Industrial Yes 2 2 No 8-pin SOIC (Tape and Reel) Industrial Yes 2 2 No CY8C20121-SX1IT 51-85066 Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 201 XX - S X 1 I X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: I = Industrial 1 = 8-pin device Pb-free Package Type: S = 8-pin SOIC Part Number: XX = 11 or 21 Family Code Technology Code: C = CMOS Marketing Code: 8 = Controllers Company ID: CY = Cypress Thermal Impedances Table 14. Thermal Impedance by Package Typical JA[13] Package 8-pin SOIC 127.22 °C/W Solder Reflow Specifications Table 15. Solder Reflow Specifications Package 8-pin SOIC Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 260 C 30 seconds Note 13. TJ = TA + Power x JA. Document Number: 001-53516 Rev. *H Page 36 of 44 CY8C20111, CY8C20121 Package Diagram Figure 18. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066 51-85066 *E Document Number: 001-53516 Rev. *H Page 37 of 44 CY8C20111, CY8C20121 Acronyms Table 16 lists the acronyms that are used in this document. Table 16. Acronyms Used in this Datasheet Acronym AC Description Acronym Description alternating current LVD low voltage detect CMOS complementary metal oxide semiconductor PCB printed circuit board CRC cyclic redundancy check PGA programmable gain amplifier CSA capsense successive approximation POR power on reset CSD capsense sigma delta PPOR precision power on reset programmable system-on-chip DC direct current PSoC® EEPROM electrically erasable programmable read-only memory PWM pulse width modulator EMC electromagnetic compatibility QFN quad flat no leads GPIO general-purpose I/O SLIMO slow internal main oscillator I/O input/output SPITM serial peripheral interface IDAC current DAC SRAM static random access memory ILO internal low speed oscillator SROM supervisory read only memory IMO internal main oscillator SSOP shrink small-outline package LCD liquid crystal display USB universal serial bus LDO low dropout regulator WDT watchdog timer LED light-emitting diode WLCSP wafer level chip scale package LSB least-significant bit XRES external reset Document Conventions Units of Measure Table 17 lists the units of measures. Table 17. Units of Measure Symbol C Unit of Measure degree Celsius Symbol mm Unit of Measure millimeter kbps kilo bits per second ms millisecond kHz kilohertz nA nanoampere k kilohm ns nanosecond LSB least significant bit % percent µA microampere pF picofarad µs microsecond V volt mA milliampere W watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Document Number: 001-53516 Rev. *H Page 38 of 44 CY8C20111, CY8C20121 Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. Application programming interface (API) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. Bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. Document Number: 001-53516 Rev. *H Page 39 of 44 CY8C20111, CY8C20121 Glossary (continued) cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. Document Number: 001-53516 Rev. *H Page 40 of 44 CY8C20111, CY8C20121 Glossary (continued) low-voltage detect (LVD) A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). Phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. Power on reset (POR) A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. Document Number: 001-53516 Rev. *H Page 41 of 44 CY8C20111, CY8C20121 Glossary (continued) settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-53516 Rev. *H Page 42 of 44 CY8C20111, CY8C20121 Document History Page Document Title: CY8C20111/CY8C20121, CapSense® Express™ – One Button and Two Button Capacitive Controllers Document Number: 001-53516 Rev. ECN No. Orig. of Change Submission Date ** 2709248 SLAN / PYRS See ECN New data sheet. *A 2821828 SSHH / FSU 12/4/2009 Added Contents. Updated Registers (Updated Register Map, added OUTPUT_STATUS). Updated Absolute Maximum Ratings (Added F32k u, tPOWERUP parameters and their details). Updated Electrical Specifications (Updated DC Electrical Specifications (Updated DC Flash Write Specifications (Updated Note 10))). *B 2868929 SLAN 01/28/2010 Changed status from Preliminary to Final. Updated Package Diagram (spec 51-85066 (Changed revision from *C to *D)). *C 2892629 NJF 03/15/2010 Updated Absolute Maximum Ratings (Added TBAKETEMP and TBAKETIME parameters and their details). Added Thermal Impedances. Added Solder Reflow Specifications. *D 3043236 ARVM 09/30/10 Updated Absolute Maximum Ratings (Removed F32ku, tPOWERUP parameters and their details). Updated Electrical Specifications (Updated AC Electrical Specifications (Added AC Chip-Level Specifications)). *E 3087790 NJF 11/16/10 Updated Electrical Specifications ((Updated DC Electrical Specifications (Updated DC GPIO Specifications (Removed sub-section “2.7-V DC Spec for I2C Line with 1.8 V External Pull-up”), added DC I2C Specifications)), updated AC Electrical Specifications (Updated AC I2C Specifications (Updated Figure 17 (No specific changes were made to I2C Timing Diagram. Updated for clearer understanding.)))). Updated Solder Reflow Specifications. Added Acronyms and Units of Measure. Added Glossary. Updated in new template. *F 3148656 ARVM 01/20/11 Updated Layout Guidelines and Best Practices (Updated Table 2 (Removed “Overlay thickness-buttons” category), added the following statement after Table 2 – “The Recommended maximum overlay thickness is 2 mm. For more details refer to the section “The Integrating Capacitor (Cint)” in AN53490.”). Updated CapSense Constraints (Removed the parameter “Overlay thickness”). Updated Solder Reflow Specifications (Updated Table 15). *G 3287607 ARVM 06/20/11 *H 3631370 VAIR / SLAN 05/31/2012 Document Number: 001-53516 Rev. *H Description of Change Post to external web. Updated Typical Circuits (Updated Figure 6 (Added Note 3 and referred the same Note in Figure 6)). Updated in new template. Page 43 of 44 CY8C20111, CY8C20121 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53516 Rev. *H Revised May 31, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 44 of 44