MC10EP51, MC100EP51 3.3V / 5VECL D Flip-Flop with Reset and Differential Clock The MC10/100EP51 is a differential clock D flip–flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip–flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. The 100 Series contains temperature compensation. • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • http://onsemi.com MARKING DIAGRAMS* 8 8 8 HEP51 ALYW 1 SO–8 D SUFFIX CASE 751 1 1 8 8 1 TSSOP–8 DT SUFFIX CASE 948R with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V Open Input Default State 8 KP51 ALYW HP51 ALYW 1 1 H = MC10 K = MC100 A = Assembly Location • • Safety Clamp on Inputs KEP51 ALYW L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC10EP51D SO–8 98 Units/Rail MC10EP51DR2 SO–8 2500 Tape & Reel MC100EP51D SO–8 98 Units/Rail MC100EP51DR2 SO–8 2500 Tape & Reel MC10EP51DT TSSOP–8 100 Units/Rail MC10EP51DTR2 TSSOP–8 2500 Tape & Reel MC100EP51DT TSSOP–8 100 Units/Rail MC100EP51DTR2 TSSOP–8 Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 3 1 2500 Tape & Reel Publication Order Number: MC10EP51/D MC10EP51, MC100EP51 PIN DESCRIPTION RESET 1 8 PIN VCC R D 2 7 D Q Flip-Flop CLK 3 6 Q FUNCTION CLK*, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset D* ECL Data Input Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. TRUTH TABLE CLK 4 5 Figure 1. 8–Lead Pinout (Top View) and Logic Diagram Q L H L CLK Z Z X R L L H D L H X VEE Z = LOW to HIGH Transition ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.) Level 1 Flammability Rating Oxygen Index UL–94 code V–0 A 1/8” 28 to 34 Transistor Count 165 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2.) Symbol Parameter Condition 1 Condition 2 Rating Units 6 V –6 V 6 –6 V V 50 100 mA mA VCC PECL Mode Power Supply VEE = 0 V VEE NECL Mode Power Supply VCC = 0 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 8 SOIC 8 SOIC 190 130 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 8 SOIC 41 to 44 °C/W θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 8 TSSOP 8 TSSOP 185 140 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 8 TSSOP 41 to 44 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC VI VEE MC10EP51, MC100EP51 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4.) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4.) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single Ended) 1365 1690 1430 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5.) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 4. All loading with 50 ohms to VCC–2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA Output HIGH Voltage (Note 7.) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 7.) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single Ended) 3065 3390 3130 3455 3190 3515 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8.) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 7. All loading with 50 ohms to VCC–2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 9.) –40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 10.) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV VOL Output LOW Voltage (Note 10.) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV VIH Input HIGH Voltage (Single Ended) –1210 –885 –1145 –820 –1085 –760 mV VIL Input LOW Voltage (Single Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11.) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 ohms to VCC–2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC10EP51, MC100EP51 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 13.) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 13.) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single Ended) 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 14.) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 13. All loading with 50 ohms to VCC–2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA Output HIGH Voltage (Note 16.) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 16.) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single Ended) 3055 3375 3055 3375 3055 3375 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 17.) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 16. All loading with 50 ohms to VCC–2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 18.) –40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 19.) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV VOL Output LOW Voltage (Note 19.) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV VIH Input HIGH Voltage (Single Ended) –1225 –880 –1225 –880 –1225 –880 mV VIL Input LOW Voltage (Single Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20.) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 ohms to VCC–2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP51, MC100EP51 AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.) –40°C Symbol Characteristic Min Typ 25°C Max Min >3 Typ 85°C Max Min >3 Typ Max fmax Maximum Frequency (See Figure 2. Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential CLK, CLK to Q, Q 10 100 250 275 300 340 350 425 270 300 320 375 370 450 300 350 350 425 420 500 RESET to Q, Q 300 380 450 325 400 475 350 425 500 Reset Recovery 150 150 tS tH Setup Time Hold Time 100 100 100 100 tPW Minimum Pulse Width 500 tr tf Output Rise/Fall Times (20% – 80%) 150 ps 80 40 100 100 ps 440 500 ps RESET Cycle–to–Cycle Jitter (See Figure 2. Fmax/JITTER) 500 440 .2 <1 120 170 .2 <1 130 180 .2 <1 150 200 80 100 11 Measured Simulated 900 10 9 800 8 700 7 600 6 500 5 ÉÉ ÉÉ 400 4 300 3 200 2 100 0 1000 JITTEROUT ps (RMS) 1000 ÉÉÉÉÉ ÉÉÉÉÉ ps ps 70 1100 VOUTpp (mV) 440 Q, Q 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC–2.0 V. 0 GHz ps tRR tJITTER >3 Unit 1 (JITTER) 2000 3000 4000 FREQUENCY (MHz) Figure 2. Fmax/Jitter http://onsemi.com 5 5000 6000 MC10EP51, MC100EP51 Q D Receiver Device Driver Device Qb Db 50 50 V TT V TT = V CC – 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC10EP51, MC100EP51 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–07 ISSUE W –X– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A 8 5 0.25 (0.010) S B 1 M Y M 4 K –Y– G C N DIM A B C D G H J K M N S X 45 SEATING PLANE –Z– 0.10 (0.004) H M D 0.25 (0.010) M Z Y X S J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 TSSOP–8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R–02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 5 0.25 (0.010) B –U– L 0.15 (0.006) T U M M 4 A –V– F DETAIL E C 0.10 (0.004) –T– SEATING PLANE D –W– G DETAIL E http://onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0 6 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0 6 MC10EP51, MC100EP51 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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