OKI MSC1212-01 48-bit grid/anode driver Datasheet

E2C0021-27-Y3
¡ Semiconductor
MSC1212-01
¡ Semiconductor
This version:MSC1212-01
Nov. 1997
Previous version: Jul. 1996
48-Bit Grid/Anode Driver
GENERAL DESCRIPTION
The MSC1212-01 is a driver IC for VFD implemented in BiCMOS technology.
The circuit consists of a 48-bit shift register and a 48-bit latch; they control display data, which
is output from the display drivers.
Since a 64-pin plastic QFP package is used, the display unit size can be reduced.
FEATURES
• Logic supply voltage (VCC)
• Driver supply voltage (VDISP)
• Operating temperature range
• Driver output current
:
:
:
:
4.5 to 5.5 V
8 to 18 V
–40 to +105°C
IO2-1 = –6 mA (for only one driver on state)
IO2-2 = –50 mA (total current for all drivers on
state)
IO2-3 = 0.2 mA
• Built-in 48-bit output Driver (with latch)
• Built-in 48-bit shift register
• Clock frequency
: 0.5 MHz
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSC1212-01GS-BK)
1/11
¡ Semiconductor
MSC1212-01
BLOCK DIAGRAM
VDISP
VCC
VCC
CL
CHG
LS
DIN
CLK
C
L-GND
D-GND
L
SI
PO1
48-BIT
I1
S/R
LATCH
PO48
SO
O1
HVO 1
48-BIT
I48
O48
HVO48
DOUT
2/11
,
¡ Semiconductor
MSC1212-01
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
HVO 18
HVO 19
HVO 20
HVO 21
HVO 22
HVO 23
HVO 24
HVO 25
HVO 26
HVO 27
HVO 28
HVO 29
HVO 30
HVO 31
NC
PIN CONFIGURATION (TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HVO 32
HVO 33
HVO 34
HVO 35
HVO 36
HVO 37
HVO 38
HVO 39
HVO 40
HVO 41
HVO 42
HVO 43
HVO 44
HVO 45
HVO 46
HVO 47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVO1
NC
VDISP
D-GND
L-GND
DIN
CLK
LS
CL
CHG
VCC
DOUT
D-GND
VDISP
NC
HVO 48
HVO 17
HVO 16
HVO 15
HVO 14
HVO 13
HVO 12
HVO 11
HVO 10
HVO 9
HVO 8
HVO 7
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
NC: No-connection pin
64-Pin Plastic QFP
3/11
¡ Semiconductor
MSC1212-01
INPUT AND OUTPUT CONFIGURATION
• Schematic Diagrams of Logic Portion Input Circuit
VDISP
VCC
INPUT
GND
GND
• Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input
Circuit (Pull-down)
Circuit (Pull-up)
VDISP
VDISP
VCC
VCC
INPUT
INPUT
GND
GND
GND
GND
• Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit
Circuit
VCC
VCC
VDISP
VDISP
OUTPUT
OUTPUT
GND
GND
GND
GND
4/11
¡ Semiconductor
MSC1212-01
PIN DESCRIPTION
Pin
Symbol
1 to 17
HVO1
32 to 48
to
50 to 63
HVO48
Driver Power Supply
19, 30
VDISP
Logic Power Supply
27
VCC
Driver GND
20, 29
D-GND
Logic GND
21
L-GND
Function
Driver Output
Description
Driver output pins, applicable to each bit of shift
register.
Power supply pins for driver circuit. Both Pin 19
and 30 should be connected externally.
Power supply pin for logic.
GND pins for the driver circuit.
Both Pin 20 and 29 should be connected externally.
GND pin for the logic circuit.
Input pin without pull-up or pull-down resistor.
Data Input
22
DIN
Input pin of shift register. Display data input is
synchronized with clock signal. (positive logic)
Input pin without pull-up or pull-down resistor.
Clock Input
23
CLK
Data of shift register is shifted from one stage to
the next on application of each clock rising edge.
Input pin without pull-up or pull-down resistor.
Latch Strobe Input
24
LS
When LS is at "H" level, the latch is shunted and the
shift register output becomes the lacth output.
When LS is at "L" level, the lacth holds the shift
register output just bafore LS goes to "L" level.
Clear input pin with pull-up resistor. Normally "L"
Clear Input
25
CL
level. In this condition, driver output changes to "H"
or "L" according to latch output level. When CL is
"H", all driver output pins are fixed to "L".
Test input pin with pull-down resistor. Normally "L"
level, but here, if CL="H", then driver output changes
Test Input
26
CHG
to "H" or "L" according to latch output level.
If CL = "L" when CHG is at "H" level, all driver output
is fixed to "H" for test.
Data Output
28
DOUT
Serial output pin of shift register.
5/11
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MSC1212-01
ABSOLUTE MAXIMUM RATINGS
Parameter
Logic Supply Voltage
*1
Driver Supply Voltage *1, *2
Symbol
Condition
Rating
Unit
VCC
—
–0.3 to +6.5
V
–0.3 to +20
V
–0.3 to VCC +0.3
V
VDISP
Input Voltage
*1
VIN
Data Output Voltage
—
Applicable to all input pins
*1
VO1
Applicable to data output pin
–0.3 to VCC +0.3
V
Driver Output Voltage *1
VO2
Applicable to driver output pin
–0.3 to VDISP +0.3
V
Power Dissipation
PD
Ta £ 25°C
1.0
W
Rj-a
—
120
°C/W
TSTG
—
–55 to +150
°C
Thermal Resistance
Storage Temperature
*3
*1 Maximum supply voltage with respect to L-GND and D-GND
*2 Catastrophic breakdown may occur if the applied voltage is more than the rating.
*3 Thermal resistance of package (between junction and atmosphere)
The junction temperature (Tj) given by the following formula should not exceed 150°C.
Tj = P ¥ Rj-a + Ta (P is the maximum power dissipation)
6/11
¡ Semiconductor
MSC1212-01
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Logic Supply Voltage
VCC
Applicable to logic supply voltage pin
Driver Supply Voltage
VDISP
Applicable to driver supply voltage pin
Max.
Unit
4.5
5.5
V
8
18
V
Applicable to all input pins
0.8 VCC
—
V
VIL
Applicable to all input pins
—
0.2 VCC
V
IO1
Applicable to DOUT pin
–0.1
0.1
mA
—
–6
mA
—
–50
mA
High Level Input Voltage
VIH
Low Level Input Voltage
Logic Output Current
Min.
Driver High Level Output Current
IO2-1
Driver High Level Output Current
IO2-2
Driver Low Level Output Current
IO2-3
Applicable to all driver output pins
—
0.2
mA
CLK Frequency
fCLK
See Timing Diagram
—
0.5
MHz
Data Setup Time
tDS
See Timing Diagram
400
—
ns
Data Hold Time
tDH
See Timing Diagram
300
—
ns
LS Pulse Width
tWLS
See Timing Diagram
125
—
ns
CHG Pulse Width
tWCHG
See Timing Diagram
10
—
ms
CL Pulse Width
tWCL
See Timing Diagram
10
—
ms
Only one driver is ON state
Total current at all driver outputs
are ON state
tWCLK
See Timing Diagram
500
—
ns
tDCLK-LS
See Timing Diagram
525
—
ns
LS-CLK Delay Time
tWLS-CLK
See Timing Diagram
0
—
ns
LS-CHG Delay Time
tWLS-CHG
See Timing Diagram
0
—
ns
LS-CL Delay Time
tWLS-CL
See Timing Diagram
CLK Pulse Width
CLK-LS Delay Time
Operating Temperature
Top
—
0
—
ns
–40
105
°C
7/11
¡ Semiconductor
MSC1212-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC = 4.5 to 5.5 V, VDISP = 8 to 18 V, Ta = –40 to +105°C)
Parameter
Symbol
Logic Power Supply
ICC1
Current
ICC2
Driver Power Supply
Current
High Level Input
IDISP
Condition
fCLK = 0 Hz
No Load
fCLK = 0.5 MHz
No Load
VP
All input pins
VN
All input pins
Hysteresis Voltage
VH
All input pins
High Level Input
IIH1
Current
IIH2
Low Level Input
IIL1
Current
IIL2
High Level Data
IOH1
IOL1
Threshold Voltage
Low Level Input
Threshold Voltage
Output Current
Low Level Data
Output Current
Driver High Level
Output Current
Driver Low Level
Output Current
Voltage Difference
Between GND Pins
IOH2
IOL2
VGND
VI = VCC
Min.
Typ.
Max.
—
2
4
—
4
6
—
—
5
mA
Unit
mA
VCC = 4.5 V
2.4
2.75
—
V
VCC = 5.5 V
2.9
3.25
—
V
VCC = 4.5 V
—
1.75
2.1
V
VCC = 5.5 V
—
2.25
2.6
V
0.3
1
—
V
CHG pin
100
—
600
mA
Input pins except CHG pin
–1
—
1
mA
–600
—
–100
mA
–1
—
1
mA
VCC–VOH1 = 1.0 V
–0.1
—
—
mA
VOL1 = 1.0 V
0.1
—
—
mA
–6
—
—
mA
0.2
—
—
mA
–0.1
0
0.1
V
CL pin
VI = 0V
Input pins except CL pin
Only one driver is ON state
VDISP–VOH2 = 1.0 V
VOL2 = 1.0 V
Voltage difference between
D-GND and L-GND
*1
*1 Pin D-GND and Pin L-GND are not connected internally.
Therefore, set the voltage between D-GND and L-GND at the same level by connecting both
pins externally.
AC Characteristics
(VCC = 4.5 to 5.5 V, VDISP = 8 to 18 V, Ta = –40 to +105°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
CLK-Dout Delay Time
tPD
See Timing Diagram
0.3
—
1.6
ms
Delay Time Low Æ High
tDLH
See Timing Diagram
—
1.0
2.0
ms
Transit Time Low Æ High
tTLH
See Timing Diagram
—
2.0
5.0
ms
Delay Time High Æ Low
tDHL
See Timing Diagram
—
1.0
2.0
ms
Transit Time High Æ Low
tTHL
See Timing Diagram
—
2.0
5.0
ms
8/11
HVO (Others)
HVO (1, 2, 47, and 48)
CL
CHG
LS
DOUT
DIN
CLK
tDS
tDH
T1/2
tWCLK
T3/4
tDLS-CL
tWLS
tDCLK-LS
tPD
T47/48
tDLH
tPD
T1/2
tTLH
tDLS-CHG
tWCHG
tDLS-CLK
1/fCLK
tDLH
tTLH
tWCHG
tDHL
T3/4
tTHL
tDHL
tTHL
tWCL
tWCL
¡ Semiconductor
MSC1212-01
TIMING DIAGRAM
9/11
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MSC1212-01
FUNCTIONAL DESCRIPTION
Function Table
CLOCK
DIN
PO1 PO2
PO3
PO4
. . . . . . . . . . . . . . . . . . . . . . . . . PO46
PO47
PO48
DOUT
H
H
PO1k PO2k
PO3k . . . . . . . . . . . . . . . . . . . . . . . . . PO45k PO46k PO47k PO47k
L
L
PO1k PO2k
PO3k . . . . . . . . . . . . . . . . . . . . . . . . . PO45k PO47k PO47k PO47k
CL
CHG
LS
POn
HVOn
H
X
X
X
L
L
H
X
X
H
L
L
H
H
H
L
L
H
L
L
L
L
L
X
NC
L: Low Level, H: High Level, X: Don't Care, NC: No Change
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¡ Semiconductor
MSC1212-01
PACKAGE DIMENSIONS
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
11/11
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