Dallas DS1844-100 Quad digital potentiometer Datasheet

DS1844
Quad Digital Potentiometer
www.dalsemi.com
FEATURES
§ Four independent, digitally controlled 64position potentiometers
§ Two interface control options
- 5-wire serial
- 2-wire addressable
§ Standard resistance values
- DS1844-010 10 kΩ
- DS1844-050 50 kΩ
- DS1844-100 100 kΩ
§ Mixed resistor value combinations (contact
factory for availability)
§ Operating Temperature Range
- Industrial: -40°C to +85°C
PIN ASSIGNMENT
PS
1
20
VCC
H2
2
19
H1
H3
3
18
H0
W3
4
17
W0
L3
5
16
L0
L2
6
15
L1
W2
7
14
W1
R/W, A0
8
13
SCL, CLK
A2, RST
9
12
SDA, DIN
10
11
A1, DOUT
GND
20-Pin DIP (300-mil)
Device
20-PinDescription
SOIC (300-mil)
20-Pin TSSOP (173-mil)
PIN DESCRIPTION
VCC
PS
A0, A1, A2
SDA
SCL
R/ W
RST
DIN
CLK
DOUT
H0-H3
L0-L3
W0-W3
GND
-
2.7V to 5.5V
Port Select
Device Select Pins (2-Wire)
Serial Data I/O (2-Wire)
Serial Clock (2-Wire)
Read/Write enable (5-Wire)
Serial Port Reset Input (5-Wire)
Serial Port Data Input (5-Wire)
Serial Port Clock Input (5-Wire)
Cascade Data Output (5-Wire)
High-end Terminal of Pot
Low-end Terminal of Pot
Wiper Terminal of Pot
Ground
DESCRIPTION
The DS1844 Quad Digital Potentiometer is a four-channel, digitally controlled linear potentiometer. Each
potentiometer is comprised of 63 equi-resistive sections and has three terminals accessible to the user.
These include the high side terminals, HX, the wiper terminals, WX, and the low-side terminals, LX. The
wiper position on the resistor ladder is selected via an 8-bit register value. Communication and control of
the device are supported by two types of serial interface. These include a 5-wire I/O shift register
interface and a 2-wire addressable interface.
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The DS1844 is available in standard 10 kΩ , 50 kΩ , and 100 kΩ versions. Mixed resistor combinations
are also available through custom setups. The DS1844 is specified to operate over the industrial
temperature range: -40°C to +85°C. Packages for the DS1844 include 20-pin DIPs, SOICs, and TSSOPs.
OPERATION
The DS1844 contains four 64-position potentiometers. Each potentiometer is independent and has three
accessible terminals, which include H X, LX, and WX. Each potentiometer is comprised of 63 individual
resistor elements. Between each resistor element is a tap-point that is multiplexed to the wiper terminal,
WX. Additionally, the wiper terminal can be multiplexed directly to the end-terminals, HX and LX.
The DS1844 supports two interface control options. Both options allow for the direct placement of the
wiper position on the resistor ladder. Each wiper has an associated 6-bit register used to hold its positional
value.
The DS1844 is a volatile device and will always power-up with the wiper positions set to mid-tap
(position 32-decimal). The end-terminal HX will have wiper position value 63-decimal and the LX terminal
will have wiper position value 0-decimal. Because the DS1844 is a 64-position device only 6 bits of data
are necessary to write a wiper’s value. However, communication with the DS1844 will require using a
full 8 bits, with the remaining 2 bits specifying the potentiometer selected. A discussion of proper
communication protocol is provided under the section entitled Serial Port Operation. A block diagram of
the DS1844 is shown in Figure 1.
SERIAL PORT OPERATION
As stated, the DS1844 can support two types of serial interface control. This includes a 5-wire serial
interface and a 2-wire addressable interface. The type interface supported during operation is selectable
via the port select input pin, PS. Additionally, certain pins provide dual functionality dependent on the
serial port selected. The pin description table lists pin functionality according to the interface selected.
5-Wire Serial Port Control
The 5-wire serial interface provides an 8-bit I/O shift register for loading and reading wiper data. The 5wire serial interface control is selected when the port select input, PS, is in a low state. This interface is
controlled by the signals RST , DIN, DOUT, CLK, and R/ W . Timing diagrams for the 5-wire serial port
can be found in Figure 3. Timing information for the 5-wire serial port is provided in the AC Electrical
Characteristics table for 5-wire serial communications.
Data is loaded MSB first and in multiples of 8 bits. The 8-bit data to specify wiper position has the format
or protocol as that shown in Figure 2. The 8-bit data is divided into potentiometer select data and wiper
position value. The 6 least significant bits of data specify the wiper position value while the 2 most
significant bits specify the potentiometer to be loaded. This allows the interface control logic/protocol to
provide order independent potentiometer loading, as well as variable-length data loads.
As stated earlier, the 5-wire serial port is selected when the PS input is in a low state. If the device will
only be used in the 5-wire mode, the PS input can be tied directly to ground. Communication via the 5wire interface is enabled when RST is in a high state. A low-to-high transition on the RST indicates the
start of a communication transaction with the DS1844. While RST is high, data can be read or written to
the part. Data will be read or written dependent on the state of the read-write enable input, R/ W . The
state of R/ W must be stable before a low-to-high transition on RST . Once the RST input has begun a
communication transaction, the serial port will ignore any transitions on the R/ W input.
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When writing data, the R/ W input should be in a low state. Once RST has activated the port, a data bit is
latched (or valid) on the low-to-high transition of the CLK signal. Once, eight low-to-high transitions
have occurred on the CLK input, the associated 8-bit data block will be loaded as the wiper’s value on the
falling edge of the eighth clock pulse. Potentiometer wiper values can be loaded in any order. Also,
potentiometer wiper data can be loaded 1, 2, 3, or 4 bytes at a time. When RST transitions from high to
low, the 5-wire port will be disabled.
While RST is high and R/ W is low, (the write or load state) the cascade data output, DOUT will be
inhibited; preventing the passing of data from DIN to DOUT . However, when RST is low data is passed
directly from DIN to DOUT .
When reading data, the R/ W input should be in a high state. Once RST has enabled the port, data can be
clocked out of the device and will appear on the DOUT terminal. A data bit will be valid on the falling
edge of a clock pulse after a maximum time period of 20 ns (of that falling edge). Data will appear on
DOUT most significant bit (MSB) first and starting with potentiometer-0, followed by potentiometer-1 and
so forth.
2-Wire Addressable Serial Port Control
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device which generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1844 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The 2-wire serial port is selected when the port select input, PS, is in a high-state. The following I/O
terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2, PS=1. Timing diagrams for the 2-wire
serial port can be found in Figures 4 through 8. Timing information for the 2-wire serial port is provided
in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined (See Figure 4).
-
Data transfer may be initiated only when the bus is not busy.
-
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
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Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 4 details how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th
bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1844 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1.
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master
is the command/control byte. Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2.
Data transfer from a slave transmitter to a master receiver. The 1st byte (the command/control
byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
The DS1844 may operate in the following two modes:
1.
Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2.
Slave transmitter mode: The 1st byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1844 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
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SLAVE ADDRESS
A command/control byte is the 1st byte received following the START condition from the master device.
The command/control byte consists of a 4-bit control code. For the DS1844, this is set as 0101 binary for
read/write operations. The next 3 bits of the command/ control byte are the device select bits or slave
address (A2, A1, A0). They are used by the master device to select which of eight devices is to be
accessed. When reading or writing the DS1844, the device-select bits must match the device-select pins
(A2, A1, A0). The last bit of the command/control byte (R/W) defines the operation to be performed.
When set to a 1 a read operation is selected, and when set to a 0 a write operation is selected. Figure 5
shows the command/control byte structure for the DS1844.
Following the START condition, the DS1844 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the
read/write bit, the slave device outputs an acknowledge signal on the SDA line.
COMMAND AND PROTOCOL
The command and protocol structure of the DS1844 allows the user to read or write the potentiometer(s).
Additionally, the 2-wire command/protocol structure of the DS1844 will support eight different devices
and a maximum of 32 channels that can be uniquely controlled. The command structures for the device
are presented in Figures 6 and 7. Potentiometer data values and control and command values are always
transmitted most significant bit (MSB) first. During communications, the receiving unit always generates
the acknowledgement.
Reading the DS1844
As shown in Figure 6, the DS1844 provides one read command operation. This operation allows the user
to read all potentiometers. Specifically, the R/W bit of the command/control byte is set equal to a 1 for a
read operation. Communication to read the DS1844 begins with a START condition which is issued by
the master device. The command/control byte from the master device will follow the START condition.
Once the command/control byte has been received by the DS1844, the part will respond with an
ACKNOWLEDGE. The read/write bit of the command/control byte, as stated, should be set equal to 1
for reading the DS1844.
When the master has received the ACKNOWLEDGE from the DS1844, the master can then begin to
receive potentiometer wiper data. The value of the potentiometer-0 wiper position will be the first
returned from the DS1844, followed by potentiometer-1 and so forth. Once the 8 bits of the
potentiometer-0 wiper position have been transmitted, the master will need to issue an
ACKNOWLEDGE, unless it is the only byte to be read, in which case the master issues a NOT
ACKNOWLEDGE. If desired the master may stop the communication transfer at this point by issuing the
STOP condition. However, if the value of the remaining potentiometers is needed, transfer can continue
by clocking the 8 bits of the potentiometer-1 value, followed by an ACKNOWLEDGE, and so forth.
Final communication transfer is terminated by issuing the STOP command. Again, the flow of the read
operation is presented in Figure 6.
Writing the DS1844
A data flow diagram for writing the DS1844 is shown in Figure 7. The DS1844 has one write command
that is used to change the position(s) of the wiper. The 2-wire serial interface write structure is similar to
that of the 5-wire serial write. However, there are differences.
All the write operations begin with a START condition. Following the START condition, the master
device will issue the command/control byte. The read/write bit of the command/control byte will be set to
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0 for writing the DS1844. Once the command/control byte has been issued and the master receives the
acknowledgment from the DS1844, potentiometer wiper data is transmitted to the DS1844 by the master
device.
As in the case of the 5-wire serial protocol, a data byte for the DS1844 will contain potentiometer select
data and wiper position value. The six least significant bits of data specify the wiper position value while
the two most significant bits specify the potentiometer to be loaded. When the DS1844 has received the
data byte, it will respond with an ACKNOWLEDGE. At this point, the new wiper value for the
potentiometer selected will be updated in the DS1844. The master device, after the receipt of the
ACKNOWLEDGE, can continue to transmit additional data bytes or if the transaction is complete
respond with the STOP condition. Additionally, the DS1844 does not require a specific order for writing
a particular potentiometer wiper's data. The 2-wire serial timing diagram is presented in Figure 8.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-1.0V to +7.0V
-40°C to +85°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
CONDITION
MIN
(-40°C to +85°C)
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
+2.7
+5.5
V
1
Resistor Inputs
L,H,W
GND
-0.5
VCC
+0.5
V
1,12
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITION
(-40°C to +85°C; VCC =2.7V to 5.5V)
MIN
TYP
MAX
UNITS
NOTES
2
mA
19
+1
µA
500
Ohms
1
mA
Supply Current Active
ICC
Input Leakage
ILI
Wiper Resistance
RW
Wiper Current
IW
Input Logic 1
VIH
0.7VCC
VCC+0.5
V
1,2
VIL
GND-0.5
0.3VCC
V
1,2
Input Logic 1
0.7VCC
VCC+0.5
V
11
Input Logic 0
0.4<VI/O<0.9VDD
GND-0.5
0.3VCC
-10
+10
µA
40
µA
Input Logic 0
Input Logic levels A0, A1,
A2
Input Current each I/O pin
Standby Current
3V
5V
-1
250
Istby
4
15
25
Low Level Output Voltage
(SDA)
VOL1
3 mA sink current
0.0
0.4
V
VOL2
6 mA sink current
0.0
0.6
V
I/O Capacitance
CI/O
10
pF
Pulse width of spikes which
must be suppressed by the
input filter
tSP
50
ns
22
DOUT Output @ 2.4V
IOH
mA
23,24
DOUT Output @ 0.4V
IOL
mA
23,24
Fast Mode
0
-1.0
4
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ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; VCC=2.7V to 5.5V)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
End-to-End Resistor
Tolerance
-20
+20
%
25
Absolute Linearity
-0.5
+0.5
LSB
16
Relative Linearity
-0.25
+0.25
LSB
17
kHz
13
ppm/°C
18
-3dB Cutoff frequency
fcutoff
Temperature Coefficent
750
2-WIRE ADDRESSABLE INTERFACE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Port Select Setup
SYMBOL
CONDITION
(-40°C to +85°C; VCC=2.7V to 5.5V)
MIN
TYP
MAX
UNITS
NOTES
ns
20,22
kHz
*,8
**,22
*,8
tSETUP
30
SCL Clock Frequency
fSCL
0
0
Bus Free Time Between
STOP and START Condition
tBUF
1.3
4.7
µs
0.6
4.0
µs
1.3
4.7
µs
0.6
4.0
µs
Hold Time (repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
Data Setup Time
tHD:STA
tLOW
tHIGH
tHD:DAT
tR
Fall Time of Both SDA and
SCL Signals
tF
Setup Time for STOP
Condition
Capacitive Load for each
Bus Line
**,22
0.9
µs
ns
*,8
**,22
300
300
0.6
ns
*,9
**,22
ns
*,9
**,22
µs
4.0
CB
*,6,7,
**,22
300
tSU:STO
*,8
**,22
1000
20+0.1CB
*,8
**,22
100
250
20+0.1CB
*,5,8
**,22
0
0
tSU:DAT
Rise Time of Both SDA and
SCL Signals
400
100
*,
**,22
400
pF
9
* fast mode
** standard mode
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5-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(-40°C to +85°C; VCC=2.7V to 5.5V)
SYMBOL
MIN
Port Select Setup
tSETUP
R/ W Setup
tSETUP
30
30
Clock Frequency
fCLK
DC
Width of CLK Pulse
tCH
UNITS
NOTES
ns
ns
14, 21
14, 21
MHz
14, 15
50
ns
14, 15
tDC
30
ns
14, 15
Data Hold Time
tCDH
0
ns
14, 15
Progapation Delay Time High to Low
Level Clock to Output
tDV
ns
14, 15
RST High to Clock Input High
tCC
50
ns
14, 15
RST Low from Clock Input High
tHLT
50
ns
14, 15
RST Inactive
tRLT
125
ns
14, 15
CLK Rise Time, CLK Fall Time
tCR
ns
14, 15
Data Setup Time
TYP
MAX
5
40
50
NOTES:
1.
All voltages are referenced to ground.
2.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
3.
ICC specified with SDA pin open.
4.
ISTBY specified with for VCC equal 3.0V and 5.0V and control port logic pins are driven to the
appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of
ground or VCC for the corresponding inactive state.
5.
After this period, the first clock pulse is generated.
6.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW ) of
the SCL.
8.
A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tRMAX + tSU:DAT = 1000+250=1250 ns before the SCL line
is released.
9.
CB - total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)
(VCC).
10.
Typical values are for ta = 25°C and nominal supply voltage.
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11.
Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
12.
Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by more than 0.5
volts.
13.
-3dB cutoff frequency characteristics for the DS1844 depend on potentiometer total resistance:
DS1844-010; 1 MHz; DS1844-050; 200 kHz; DS1844-100; 100 kHz.
14.
See Figure 3, 5-wire timing diagram.
15.
For 5-wire control logic and VCC = 5V ±10%, maximum VIL = +0.8V. For VCC = 3.0V ±10%,VIL
= +0.6V.
16.
Absolute linearity is used to measure expected wiper voltage versus measured wiper voltage as
determined by wiper position. The DS1844 is specified to provide an absolute linearity of ± 0.5
LSB.
17.
Relative linearity is used to determine the change in wiper voltage between two adjacent wiper
positions. The DS1844 is specified to provide a relative linearity of ± 0.25 dB.
18.
When used as a rheostat or variable resistor the temperature coefficient applies: 650 ppm/°C.
When used as a voltage divider or potentiometer, the effective temperature coefficient approaches
30 ppm/°C.
19.
Maximum ICC active current is dependent on clock rates during serial port activity. Maximum
ICC active current is specified for 5 MHz clock rates, and worse case input logic levels.
20.
tSETUP is the minimum time required for the port select input, PS, to be stable before any activity
on SDA or SCL terminals.
21.
tSETUP is the minimum time required for the port select input, PS, and/or the R/ W input to be
stable before RST becomes active (or goes to a high state).
22.
See Figure 8, 5-wire timing diagram.
23.
Measured with load as shown in Figure 9.
24.
Valid for VCC = 5V only.
25.
Valid at 25°C only.
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DS1844 BLOCK DIAGRAM Figure 1
WIPER REGISTER CONFIGURATION Figure 2
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5-WIRE SERIAL TIMING DIAGRAM Figure 3 (A), (B)
(A) WRITING DATA TO THE DS1844
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2-WIRE DATA TRANSFER OVERVIEW Figure 4
START
COMMAND/CONTROL BYTE Figure 5
2-WIRE READ PROTOCOL Figure 6
2-WIRE WRITE PROTOCOLS Figure 7
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2-WIRE TIMING DIAGRAM Figure 8
DIGITAL OUTPUT LOAD Figure 9
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