LINER LTC3407-2 Dual synchronous, 800ma, 2.25mhz step-down dc/dc regulator Datasheet

LTC3407-2
Dual Synchronous, 800mA,
2.25MHz Step-Down
DC/DC Regulator
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
n
High Efficiency: Up to 95%
Very Low Quiescent Current: Only 40μA
2.25MHz Constant-Frequency Operation
High Switch Current: 1.2A on Each Channel
No Schottky Diodes Required
Low RDS(ON) Internal Switches: 0.35Ω
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: IQ < 1μA
Output Voltages from 5V down to 0.6V
Power-On Reset Output
Externally Synchronizable Oscillator
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages
APPLICATIONS
n
n
n
n
n
n
PDAs/Palmtop PCs
Digital Cameras
Cellular Phones
Portable Media Players
PC Cards
Wireless and DSL Modems
The LTC®3407-2 is a dual, constant-frequency, synchronous step down DC/DC converter. Intended for low power
applications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1.2mm. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1.2A power
switches provide high efficiency without the need for
external Schottky diodes.
A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while pulse-skipping mode provides low noise ripple at
light loads.
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
TYPICAL APPLICATION
VIN = 2.5V*
TO 5.5V
C1
10μF
RUN2
VIN
MODE/SYNC
RUN1
LTC3407-2 Efficiency Curve
R5
100k
POR
100
RESET
95
C3
10μF
L2
2.2μH
L1
2.2μH
C5, 22pF
R4
887k
C4, 22pF
R3
280k
VOUT1 = 1.8V
AT 800mA
VFB1
VFB2
GND
R1
301k
2.5V
90
SW1
SW2
R2
604k
C2
10μF
EFFICIENCY (%)
VOUT2 = 2.5V
AT 800mA
LTC3407-2
1.8V
85
80
75
70
VIN = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
65
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
L1, L2: MURATA LQH32CN2R2M33
*VOUT CONNECTED TO VIN FOR VIN b 2.8V
3407 TA01
60
1
10
100
LOAD CURRENT (mA)
1000
3407 TA02
Figure 1. 2.5V/1.8V at 800mA Step-Down Regulators
34072fc
1
LTC3407-2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN Voltages .................................................– 0.3V to 6V
VFB1, VFB2 Voltages .......................... –0.3V to VIN + 0.3V
RUN1, RUN2 Voltages .................................–0.3V to VIN
MODE/SYNC Voltage........................ –0.3V to VIN + 0.3V
SW1, SW2 Voltage ........................... –0.3V to VIN + 0.3V
POR Voltage ................................................. –0.3V to 6V
Ambient Operating Temperature Range (Note 2)
LTC3407E-2 ......................................... –40°C to 85°C
LTC3407I-2 ........................................ –40°C to 125°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range...................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSE Package Only ............................................ 300°C
Reflow Peak Body Temperature ............................ 260°C
PIN CONFIGURATION
TOP VIEW
1
RUN1
VIN
2
SW1
4
7 SW2
GND
5
6 MODE/
SYNC
3
TOP VIEW
10 VFB2
VFB1
VFB1
RUN1
VIN
SW1
GND
9 RUN2
11
8 POR
1
2
3
4
5
11
10
9
8
7
6
VFB2
RUN2
POR
SW2
MODE/
SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3407EDD-2#PBF
LTC3407EDD-2#TRPBF
LBFB
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC3407IDD-2#PBF
LTC3407IDD-2#TRPBF
LBFB
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC3407EMSE-2#PBF
LTC3407EMSE-2#TRPBF
LTBDZ
10-Lead Plastic MSOP
–40°C to 85°C
LTC3407IMSE-2#PBF
LTC3407IMSE-2#TRPBF
LTBDZ
10-Lead Plastic MSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3407EDD-2
LTC3407EDD-2#TR
LBFB
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC3407IDD-2
LTC3407IDD-2#TR
LBFB
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC3407EMSE-2
LTC3407EMSE-2#TR
LTBDZ
10-Lead Plastic MSOP
–40°C to 85°C
LTC3407IMSE-2
LTC3407IMSE-2#TR
LTBDZ
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Operating Voltage Range
●
IFB
Feedback Pin Input Current
●
2.5
TYP
MAX
UNITS
5.5
V
30
nA
34072fc
2
LTC3407-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VFB
Feedback Voltage (Note 3)
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 125°C (Note 2)
0.588
0.585
0.585
0.6
0.6
0.6
0.612
0.612
0.612
V
V
V
ΔVLINE REG
Reference Voltage Line Regulation
VIN = 2.5V to 5.5V (Note 3)
0.3
0.5
ΔVLOAD REG
IS
Output Voltage Load Regulation
(Note 3)
0.5
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
VFB1 = VFB2 = 0.5V
VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
700
40
0.1
950
60
1
μA
μA
μA
fOSC
Oscillator Frequency
VFBX = 0.6V
2.25
2.7
MHz
fSYNC
Synchronization Frequency
ILIM
Peak Switch Current Limit
VIN = 3V, VFBX = 0.5V, Duty Cycle <35%
RDS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
ISW(LKG)
POR
●
●
●
1.8
%
2.25
0.95
%/V
MHz
1.2
1.6
A
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
Switch Leakage Current
VIN = 5V, VRUN = 0V, VFBX = 0V
0.01
1
μA
Power-On Reset Threshold
VFBX Ramping Up, MODE/SYNC = 0V
VFBX Ramping Down, MODE/SYNC = 0V
8.5
–8.5
Power-On Reset On-Resistance
100
Power-On Reset Delay
200
262,144
VRUN
RUN Threshold
●
IRUN
RUN Leakage Current
●
VMODE
Mode Threshold Low
Mode Threshold High
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3407E-2 is guaranteed to meet specified performance
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407I-2 is guaranteed over the
full –40°C to 125°C operating temperature range.
Burst Mode Operation
0.3
1
1.5
V
0.01
1
μA
0
0.5
V
VIN – 0.5
VIN
V
TA = 25°C unless otherwise specified.
Pulse-Skipping Mode
Load Step
SW
5V/DIV
SW
5V/DIV
VOUT
200mV/DIV
VOUT
100mV/DIV
VOUT
10mV/DIV
IL
500mA/DIV
IL
200mA/DIV
IL
200mA/DIV
ILOAD
500mA/DIV
34072 G01
Ω
Cycles
Note 3: The LTC3407-2 is tested in a proprietary test mode that connects
VFB to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6V
2μs/DIV
VOUT = 1.8V
ILOAD = 100mA
CIRCUIT OF FIGURE 1
%
%
VIN = 3.6V
1μs/DIV
VOUT = 1.8V
ILOAD = 20mA
CIRCUIT OF FIGURE 1
34072 G02
VIN = 3.6V
20μs/DIV
VOUT = 1.8V
ILOAD = 80mA TO 800mA
CIRCUIT OF FIGURE 1
3407 G03
34072fc
3
LTC3407-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise specified.
Oscillator Frequency
vs Temperature
Efficiency vs Input Voltage
100
2.5
Oscillator Frequency
vs Supply Voltage
10
VIN = 3.6V
8
95
1mA
85
FREQUENCY (MHz)
10mA
800mA
80
75
70
60
2
4
3
2.3
2.2
2.1
VOUT = 1.8V
Burst Mode OPERATION
CIRCUIT OF FIGURE 1
65
FREQUENCY DEVIATION (%)
100mA
90
EFFICIENCY (%)
2.4
2.0
–50 –25
5
100
VIN = 3.6V
–6
2
0.605
400
0.595
0.585
–50 –25
200
100
125
MAIN
SWITCH
SYNCHRONOUS
SWITCH
2
3
350
300
250
200
4
VIN (V)
5
100
–50 –25
6
Efficiency vs Load Current
25 50 75 100 125 150
TEMPERATURE (°C)
Load Regulation
4
2.7V
3
95
90
EFFICIENCY (%)
4.2V
Burst Mode OPERATION
Burst Mode OPERATION
2
85
80
75
PULSE-SKIPPING MODE
VOUT ERROR (%)
3.6V
1
0
PULSE-SKIPPING MODE
–1
–2
70
65
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
60
3407 G10
0
3407 G09
100
1000
MAIN SWITCH
SYNCHRONOUS SWITCH
3407 G08
Efficiency vs Load Current
75
VIN = 3.6V
400
150
1
100
80
VIN = 4.2V
450
3407 G07
85
VIN = 2.7V
500
300
250
6
RDS(ON) vs Temperature
550
350
0.590
50
25
75
0
TEMPERATURE (°C)
5
3407 G06
RDS(ON) (mΩ)
450
0.600
4
3
SUPPLY VOLTAGE (V)
TA = 25°C
RDS(ON) (mΩ)
REFERENCE VOLTAGE (V)
–4
RDS(ON) vs Input Voltage
0.610
EFFICIENCY (%)
–2
125
500
70 V
OUT = 2.5V
Burst Mode OPERATION
65 NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1
60
1
10
100
LOAD CURRENT (mA)
0
3407 G05
Reference Voltage
vs Temperature
90
2
–10
50
25
75
0
TEMPERATURE (°C)
3407 G04
95
4
–8
INPUT VOLTAGE (V)
0.615
6
1
10
100
LOAD CURRENT (mA)
1000
3407 G11
–3
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
–4
1
10
100
LOAD CURRENT (mA)
1000
3407 G12
34072fc
4
LTC3407-2
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Line Regulation
100
100
0.5
95
95
0.4
2.7V
EFFICIENCY (%)
85
90
80
75
4.2V
85
4.2V
80
75
1000
VOUT = 1.5V
Burst Mode OPERATION
65
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1
60
1
10
100
LOAD CURRENT (mA)
3407 G13
VOUT = 1.8V
IOUT = 200mA
TA = 25°C
0.3
70
70
VOUT = 1.2V
Burst Mode OPERATION
65
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 1
60
1
10
100
LOAD CURRENT (mA)
3.6V
2.7V
VOUT ERROR (%)
3.6V
90
EFFICIENCY (%)
TA = 25°C unless otherwise specified.
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
1000
3407 G14
–0.5
2
3
4
VIN (V)
5
6
3407 G15
PIN FUNCTIONS
VFB1 (Pin 1): Output Feedback. Receives the feedback voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN
enables regulator 1, while forcing it to GND causes regulator
1 to shut down. This pin must be driven; do not float.
VIN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Ground. This pin is not connected internally.
Connect to PCB ground for shielding.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation of the device. When tied to VIN or GND, Burst Mode
operation or pulse-skipping mode is selected, respectively.
Do not float this pin. The oscillation frequency can be
synchronized to an external oscillator applied to this pin
and pulse-skipping mode is automatically selected.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage is not
within ±8.5% of regulation and goes high after 117ms
when both s are within regulation.
RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN
enables regulator 2, while forcing it to GND causes regulator
2 to shut down. This pin must be driven; do not float.
VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of COUT, and (–) terminal of CIN. Must be
connected to electrical ground on PCB.
34072fc
5
LTC3407-2
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
VIN
SLOPE
COMP
0.6V
+
ITH
EA
VFB1
EN
–
SLEEP
–
1
–
+
57
ICOMP
+
0.35V
BURST
S
Q
RS
LATCH
R
0.55V
–
Q
UV
UVDET
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
+
OV
IRCMP
OVDET
–
0.65V
4 SW1
+
+
ANTI
SHOOTTHRU
–
11 GND
SHUTDOWN
PGOOD1
RUN1
2
RUN2
9
0.6V REF
OSC
OSC
VIN
3 VIN
8 POR
POR
COUNTER
5 GND
PGOOD2
VFB2
10
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
7 SW2
34072 BD
OPERATION
The LTC3407-2 uses a constant-frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit a
variety of applications, the selectable Mode pin allows the
user to choose between low noise and high efficiency.
when the VFB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The output voltage is set by an external divider returned
to the VFB pins. An error amplifier compares the divided
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
will go high after 262,144 clock cycles (about 117ms) of
achieving regulation.
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error amplifier.This amplifier compares the VFB pin to the
0.6V reference. When the load current increases, the
VFB voltage decreases slightly below the reference. This
decrease causes the error amplifier to increase the ITH
voltage until the average inductor current matches the
new load current.
Main Control Loop
The main control loop is shut down by pulling the RUN
pin to ground.
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
34072fc
6
LTC3407-2
OPERATION
Low Current Operation
Two modes are available to control the operation of the
LTC3407-2 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407-2
automatically switches into Burst Mode operation, in which
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value.
A hysteretic voltage comparator trips when ITH is below
0.35V, shutting off the switch and reducing the power. The
output capacitor and the inductor supply the power to the
load until ITH exceeds 0.65V, turning on the switch and the
main control loop which starts another cycle.
For lower ripple noise at low currents, the pulse-skipping
mode can be used. In this mode, the LTC3407-2 continues
to switch at a constant frequency down to very low currents, where it will begin skipping pulses. The efficiency in
pulse-skipping mode can be improved slightly by connecting the SW node to the MODE/SYNC input which reduces
the clock frequency by approximately 30%.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
An important design consideration is that the RDS(ON)
of the P-channel switch increases with decreasing input
supply voltage (see Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407-2 is used at 100% duty cycle with low
input voltage (see Thermal Considerations in the Applications Information section).
Low Supply Operation
To prevent unstable operation, the LTC3407-2 incorporates
an undervoltage lockout circuit which shuts down the part
when the input voltage drops below about 1.65V.
APPLICATIONS INFORMATION
A general LTC3407-2 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT
can be selected.
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ΔIL decreases with
higher inductance and increases with higher VIN or VOUT:
V V
IL = OUT • 1 OUT fO • L VIN Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
ΔIL = 0.4 • IOUT(MAX), where IOUT(MAX) is 800mA. The
largest ripple current ΔIL occurs at the maximum input
voltage. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
V
V
L OUT • 1– OUT fO • IL VIN(MAX) The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
34072fc
7
LTC3407-2
APPLICATIONS INFORMATION
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and do not radiate much energy, but generally cost
more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor
to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on
what the LTC3407-2 requires to operate. Table 1 shows
some typical surface mount inductors that work well in
LTC3407-2 applications.
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately VOUT/VIN.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
IRMS ≈IMAX
VOUT (VIN – VOUT )
VIN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2.
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
VIN for high frequency decoupling, when not using an all
ceramic capacitor solution.
Table 1. Representative Surface Mount Inductors
PART
NUMBER
VALUE
(μH)
DCR
(Ω MAX)
MAX DC
CURRENT (A)
SIZE
W × L × H (mm3)
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
4.4 × 5.8 × 1.2
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
2.5 × 3.2 × 2.0
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
2.5 × 3.2 × 2.0
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
4.5 × 5.4 × 1.2
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance
is adequate for filtering. The output ripple (ΔVOUT) is
determined by:
1
VOUT IL ESR+
C
8f
O
OUT
where f = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔIL increases
with input voltage. With ΔIL = 0.4 • IOUT(MAX), the output
ripple will be less than 100mV at maximum VIN and fO =
2.25MHz with:
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantalum capacitors are all available in surface mount
packages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR (size) product
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP,
Panasonic Special Polymer (SP), and Kemet A700, of34072fc
8
LTC3407-2
APPLICATIONS INFORMATION
fer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density, but they have a larger ESR and it
is critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Aluminum electrolytic
capacitors have a significantly larger ESR, and are often
used in extremely cost-sensitive applications provided that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coefficient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407-2 in parallel with the
main capacitors for high frequency decoupling.
VIN = 2.5V
TO 5.5V
CIN
RUN2
BM*
PS*
VIN
MODE/SYNC
R5
RUN1
POWER-ON
RESET
POR
LTC3407-2
L1
L2
VOUT2
SW1
SW2
C5
C4
COUT2
VFB1
VFB2
R4
VOUT1
GND
R3
R2
R1
*MODE/SYNC = 0V: PULSE-SKIPPING
MODE/SYNC = VIN: Burst Mode OPERATION
COUT1
3407 F02
Figure 2. LTC3407-2 General Schematic
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR generates
a loop “zero” at 5kHz to 50kHz that is instrumental in giving
acceptable loop phase margin. Ceramic capacitors remain
capacitive to beyond 300kHz and usually resonate with their
ESL before ESR becomes effective. Also, ceramic caps are
prone to temperature effects which requires the designer
to check loop stability over the operating temperature
range. To minimize their large temperature and voltage
coefficients, only X5R or X7R ceramic capacitors should
be used. A good selection of ceramic capacitors is available
from Taiyo Yuden, AVX, Kemet, TDK and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, three to four cycles are
required to respond to a load step, but only in the first cycle
does the output drop linearly. The output droop, VDROOP,
is usually about two to three times the linear drop of the
first cycle. Thus, a good place to start is with the output
capacitor size of approximately:
COUT ≈ 2.5
ΔIOUT
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3407-2 develops a 0.6V reference voltage between
the feedback pin, VFB, and the ground as shown in Figure 2.
The output voltage is set by a resistive divider according
to the following formula:
R2 VOUT = 0.6V 1+ R1 34072fc
9
LTC3407-2
APPLICATIONS INFORMATION
Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feedforward capacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output voltages are within ±8.5% of regulation, a timer is started which
releases POR after 218 clock cycles (about 117ms). This
delay can be significantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse-skipping
mode during a reset. In addition, if the output voltage
faults during Burst Mode sleep, POR could have a slight
delay for an undervoltage output condition and may not
respond to an overvoltage output. This can be avoided by
using pulse-skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse-skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.
The LTC3407-2 can also be synchronized to an external
LTC3407-2 by the MODE/SYNC pin. During synchronization,
the mode is set to pulse-skipping and the top switch turn-on
is synchronized to the rising edge of the external clock.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD • ESR, where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard secondorder overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feedforward capacitor, CF,
can be added to improve the high frequency response, as
shown in Figure 2. Capacitor CF provides phase lead by
creating a high frequency zero with R2, which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Hot Swap is a trademark of Linear Technology Corporation.
34072fc
10
LTC3407-2
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3407-2 circuits: 1) VIN quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small
(<0.1%) loss that increases with VIN, even at no load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current
out of VIN that is typically much larger than the DC bias
current. In continuous mode, IGATECHG = fO(QT + QB),
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to VIN and thus their effects will
be more pronounced at higher supply voltages.
3. I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC):
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses:
I2R losses = (IOUT)2(RSW + RL)
4. Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these system-level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3407-2 does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3407-2 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.
To prevent the LTC3407-2 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3407-2 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the RDS(ON) resistance of
the main switch is 0.425Ω. Therefore, power dissipated
by each channel is:
PD = (IOUT)2 • RDS(ON) = 272mW
The MS package junction-to-ambient thermal resistance,
θJA, is 45°C/W. Therefore, the junction temperature of
the regulator operating in a 70°C ambient temperature is
approximately:
TJ = 2 • 0.272 • 45 + 70 = 94.5°C
which is below the absolute maximum junction temperature of 125°C.
34072fc
11
LTC3407-2
APPLICATIONS INFORMATION
Design Example
As a design example, consider using the LTC3407-2 in
an portable application with a Li-Ion battery. The battery
provides a VIN = 2.8V to 4.2V. The load requires a maximum
of 800mA in active mode and 2mA in standby mode. The
output voltage is VOUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the inductor value for about 40% IOUT(MAX)
at maximum VIN:
2.5V 2.5V
• 1–
L
=1.4µH
2.25MHz • 320mA 4.2V Choosing a vendor’s closest inductor value of 2.2μH,
results in a maximum ripple current of:
2.5V 2.5V
• 1
IL =
= 204mA
2.25MHz • 2.2µH 4.2V For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
800mA
COUT ≈ 2.5
= 7.1μF
2.25MHz • (5% • 2.5V)
A good standard value is 10μF. Since the output impedance
of a Li-Ion battery is very low, CIN is typically 10μF.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor is 280k, and R2 is then 887k.
The POR pin is a common drain output and requires a pullup resistor. A 100k resistor is used for adequate speed.
Figure 1 shows the complete schematic for this design
example.
in the layout diagram of Figure 3. Check the following in
your layout:
1. Does the capacitor CIN connect to the power VIN (Pin
3) and GND (Exposed Pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals VFB should be routed away from noisy components and traces, such as the SW line (Pins 4 and 7),
and its trace should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point and should not share the high current path of
CIN or COUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to VIN or GND.
VIN
CIN
RUN2
RUN1
POR
LTC3407-2
L1
L2
VOUT2
SW1
SW2
C5
VFB1
VFB2
R4
COUT2
VOUT1
C4
GND
R3
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3407-2. These items are also illustrated graphically
VIN
MODE/SYNC
R2
R1
COUT1
3407 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. LTC3407-2 Layout Diagram (See Board
Layout Checklist)
34072fc
12
LTC3407-2
TYPICAL APPLICATIONS
Low Ripple Buck Regulators Using Ceramic Capacitors
VIN = 2.5V
TO 5.5V
C1
10MF
RUN2
VIN
R5
100k
RUN1
POWER-ON
RESET
POR
C3
10MF
SW2
L1
4.7MH
SW1
C5, 22pF
C4, 22pF
VFB2
R4
887k
R3
442k
MODE/SYNC
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
VOUT1 = 1.2V
AT 800mA
VFB1
GND
R1
604k
R2
604k
L1, L2: SUMIDA CDRH2D18/HP-4R7NC
C2
10MF
3407 TA03
Efficiency vs Load Current
100
95
1.8V
90
EFFICIENCY (%)
VOUT2 = 1.8V
AT 800mA
LTC3407-2
L2
4.7MH
85
1.2V
80
75
70
65
60
55
50
10
VIN = 3.3V
PULSE-SKIPPING MODE
NO LOAD ON OTHER CHANNEL
100
LOAD CURRENT (mA)
1000
3407 TA03b
34072fc
13
LTC3407-2
TYPICAL APPLICATIONS
Efficiency vs Load Current
1.2mm Height Core Supply
100
VIN = 3.6V
TO 5.5V
RUN2
VIN
VOUT2 = 3.3V
AT 800mA
LTC3407-2
L2
2.2μH
SW2
L1
2.2μH
SW1
C5, 22pF
C4, 22pF
3.3V
90
POWER-ON
RESET
POR
MODE/SYNC
95
R5
100k
RUN1
EFFICIENCY (%)
C1*
4.7μF
VOUT1 = 1.8V
AT 800mA
85
1.8V
80
75
70
C3
4.7μF
s2
R4
887k
R3
196k
VIN = 5V
65 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
60
1
10
100
LOAD CURRENT (mA)
VFB1
VFB2
GND
R1
301k
R2
604k
C2
4.7μF
s2
1000
3407 TA07
3407 TA08
C1, C2, C3: TDK C1608X5ROJ475M
L1, L2: CMD4D11-2R2
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
R = 0.125
TYP
6
0.40 ± 0.10
10
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN REV B 0309
5
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.00 – 0.05
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
34072fc
14
LTC3407-2
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 p 0.102
(.110 p .004)
5.23
(.206)
MIN
0.889 p 0.127
(.035 p .005)
1
0.05 REF
10
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
3.00 p 0.102
(.118 p .004)
(NOTE 3)
10 9 8 7 6
DETAIL “A”
0o – 6o TYP
1 2 3 4 5
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.18
(.007)
0.497 p 0.076
(.0196 p .003)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0.254
(.010)
0.29
REF
1.83 p 0.102
(.072 p .004)
2.083 p 0.102 3.20 – 3.45
(.082 p .004) (.126 – .136)
0.50
0.305 p 0.038
(.0197)
(.0120 p .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
2.06 p 0.102
(.081 p .004)
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE) 0908 REV C
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
34072fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3407-2
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN = 2.8V
TO 4.2V
C1
10μF
VOUT2 = 3.3V
AT 200mA
VIN
M1
R5
100k
R4
887k
POWER-ON
RESET
L1
2.2μH
C4, 22pF
VFB1
VFB2
R3
196k
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302
VOUT1 = 1.8V
AT 800mA
SW1
C5, 22pF
C6
47μF
C3
10μF
POR
LTC3407-2
SW2
+
RUN1
MODE/SYNC
L2
10μH
D1
RUN2
GND
R1
301k
C2
10μF
R2
604k
3407 TA04
Efficiency vs Load Current
Efficiency vs Load Current
100
90
95
70
60
50
2.8V
90
4.2V
3.6V
EFFICIENCY (%)
EFFICIENCY (%)
80
2.8V
40 VOUT = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
30
1
10
100
LOAD CURRENT (mA)
4.2V
85
3.6V
80
75
70
VOUT = 1.8V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
65
60
1000
3407 TA05
1
10
100
LOAD CURRENT (mA)
1000
3407 TA06
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1878
600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10μA,
ISD <1μA, MSOP-8, Package
LT1940
Dual Output 1.4A(IOUT), Constant 1.1MHz, High Efficiency
Step-Down DC/DC Converter
VIN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 2.5mA, ISD = <1μA,
TSSOP-16E Package
LTC3252
Dual 250mA (IOUT), 1MHz, Spread Spectrum Inductorless
Step-Down DC/DC Converter
88% Efficiency, VIN: 2.7V to 5.5V, VOUT(MIN) = 0.9V to 1.6V,
IQ = 60μA, ISD < 1μA, DFN-12 Package
LTC3405/
LTC3405A
300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC
Converters
96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA,
ISD <1μA, ThinSOT™ Package
LTC3406/
LTC3406B
600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC
Converters
96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA,
ISD <1μA, ThinSOT Package
LT3407
600mA, 1.5MHz Dual Synchronous Step-Down DC/DC
Converter
96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,
ISD <1μA, MSE, DFN Package
LTC3411
1.25A (IOUT), 4MHz, Synchronous Step Down DC/DC
Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, MSOP-10 Package
LTC3412
2.5A (IOUT), 4MHz, Synchronous Step Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, TSSOP-16E Package
LTC3414
4A (IOUT), 4MHz, Synchronous Step Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD <1μA, TSSOP-28E Package
LTC3440
600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC
Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA,
ISD <1μA, MSOP-10 Package
ThinSOT is a trademark of Linear Technology Corporation.
16 Linear Technology Corporation
34072fc
LT 0809 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004