LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 LMH6624/LMH6626 Single/Dual Ultra Low Noise Wideband Operational Amplifier Check for Samples: LMH6624 FEATURES DESCRIPTION • The LMH6624/LMH6626 offer wide bandwidth (1.5GHz for single, 1.3GHz for dual) with very low input noise (0.92nV/√Hz, 2.3pA/√Hz) and ultra low dc errors (100μV VOS, ±0.1μV/°C drift) providing very precise operational amplifiers with wide dynamic range. This enables the user to achieve closed-loop gains of greater than 10, in both inverting and noninverting configurations. 1 2 • • • • • • • • • • • VS = ±6V, TA = 25°C, AV = 20, (Typical values unless specified) Gain Bandwidth (LMH6624) 1.5GHz Input Voltage Noise 0.92nV/√Hz Input Offset Voltage (limit over temp) 700µV Slew Rate 350V/μs Slew Rate (AV = 10) 400V/μs HD2 @ f = 10MHz, RL = 100Ω −63dBc HD3 @ f = 10MHz, RL = 100Ω −80dBc Supply Voltage Range (dual supply) ±2.5V to ±6V Supply Voltage Range (single supply) +5V to +12V Improved Replacement for the CLC425 (LMH6624) Stable for Closed Loop |AV| ≥ 10 The LMH6624 (single) and LMH6626’s (dual) traditional voltage feedback topology provide the following benefits: balanced inputs, low offset voltage and offset current, very low offset drift, 81dB open loop gain, 95dB common mode rejection ratio, and 88dB power supply rejection ratio. The LMH6624/LMH6626 operate from ± 2.5V to ± 6V in dual supply mode and from +5V to +12V in single supply configuration. LMH6624 is offered in SOT-23-5 and SOIC-8 packages. APPLICATIONS • • • • • • • The LMH6626 is offered in SOIC-8 and VSSOP-8 packages. Instrumentation Sense Amplifiers Ultrasound Pre-amps Magnetic Tape & Disk Pre-amps Wide band active filters Professional Audio Systems Opto-electronics Medical Diagnostic Systems Connection Diagram LMH6624 5-Pin SOT-23 1 5 OUT LMH6624 8-Pin SOIC V + N/C -IN V - 2 8 - 7 + 6 N/C V + 2 +IN + +IN 1 LMH6626 8-Pin SOIC/VSSOP 3 - 3 4 -IN Figure 1. Top View V - 4 5 Figure 2. Top View OUT N/C Figure 3. Top View 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) ESD Tolerance Human Body Model Machine Model 2000V (2) 200V (3) VIN Differential ±1.2V Supply Voltage (V+ - V−) 13.2V V+ +0.5V, V− −0.5V Voltage at Input pins Soldering Information Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C Storage Temperature Range −65°C to +150°C (4) (5) +150°C Junction Temperature (1) (2) (3) (4) (5) , Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Human body model, 1.5kΩ in series with 100pF. Machine Model, 0Ω in series with 200pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) Operating Temperature Range (2) (3) , Package Thermal Resistance (θJA) (1) (2) (3) 2 −40°C to +125°C (3) SOIC-8 166°C/W SOT23–5 265°C/W VSSOP-8 235°C/W Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 ±2.5V Electrical Characteristics Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5V, V− = −2.5V, VCM = 0V, AV = +20, RF = 500Ω, RL = 100Ω. Boldface limits apply at the temperature extremes. See (1). Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Dynamic Performance −3dB BW fCL Slew Rate (4) SR VO = 400mVPP (LMH6624) 90 VO = 400mVPP (LMH6626) 80 VO = 2VPP, AV = +20 (LMH6624) 300 VO = 2VPP, AV = +20 (LMH6626) 290 VO = 2VPP, AV = +10 (LMH6624) 360 VO = 2VPP, AV = +10 (LMH6626) 340 MHz V/μs tr Rise Time VO = 400mV Step, 10% to 90% 4.1 ns tf Fall Time VO = 400mV Step, 10% to 90% 4.1 ns ts Settling Time 0.1% VO = 2VPP (Step) 20 ns Distortion and Noise Response en Input Referred Voltage Noise in Input Referred Current Noise f = 1MHz (LMH6624) 0.92 f = 1MHz (LMH6626) 1.0 f = 1MHz (LMH6624) 2.3 f = 1MHz (LMH6626) 1.8 nV/√Hz pA/√Hz HD2 2nd Harmonic Distortion fC = 10MHz, VO = 1VPP, RL 100Ω −60 dBc HD3 3rd Harmonic Distortion fC = 10MHz, VO = 1VPP, RL 100Ω −76 dBc Input Characteristics VOS Input Offset Voltage Average Drift IOS (5) IB (5) Input Bias Current Average Drift (5) (6) RIN Input Resistance CIN Input Capacitance CMRR −0.75 −0.95 VCM = 0V Input Offset Current Average Drift VCM = 0V (6) Common Mode Rejection Ratio VCM = 0V −0.25 +0.75 +0.95 μV/°C ±0.25 −1.5 −2.0 −0.05 VCM = 0V 2 VCM = 0V 13 mV μA +1.5 +2.0 nA/°C μA +20 +25 VCM = 0V 12 nA/°C Common Mode 6.6 MΩ Differential Mode 4.6 kΩ Common Mode 0.9 pF Differential Mode 2.0 Input Referred, VCM = −0.5 to +1.9V VCM = −0.5 to +1.75V 87 85 90 (LMH6624) RL = 100Ω, VO = −1V to +1V 75 70 79 (LMH6626) RL = 100Ω, VO = −1V to +1V 72 67 79 dB Transfer Characteristics AVOL Xt (1) (2) (3) (4) (5) (6) Large Signal Voltage Gain Crosstalk Rejection f = 1MHz (LMH6626) −75 dB dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change. Simulation results. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 3 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com ±2.5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5V, V− = −2.5V, VCM = 0V, AV = +20, RF = 500Ω, RL = 100Ω. Boldface limits apply at the temperature extremes. See (1). Symbol Parameter Conditions Min Typ RL = 100Ω ±1.1 ±1.0 ±1.5 No Load ±1.4 ±1.25 ±1.7 (2) (3) Max (2) Units Output Characteristics VO Output Swing RO Output Impedance f ≤ 100KHz ISC Output Short Circuit Current (LMH6624) Sourcing to Ground ΔVIN = 200mV (7), (8) 90 75 145 (LMH6624) Sinking to Ground ΔVIN = −200mV (7), 90 75 145 (LMH6626) Sourcing to Ground ΔVIN = 200mV (7), (8) 60 50 120 (LMH6626) Sinking to Ground ΔVIN = −200mV (7), (8) 60 50 120 IOUT Output Current V 10 (8) (LMH6624) Sourcing, VO = +0.8V Sinking, VO = −0.8V 100 (LMH6626) Sourcing, VO = +0.8V Sinking, VO = −0.8V 75 mΩ mA mA Power Supply PSRR Power Supply Rejection Ratio VS = ±2.0V to ±3.0V IS Supply Current (per channel) No Load (7) (8) 4 82 80 90 11.4 dB 16 18 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is 1.5ms. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 ±6V Electrical Characteristics Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6V, V− = −6V, VCM = 0V, AV = +20, RF = 500Ω, RL = 100Ω. Boldface limits apply at the temperature extremes. See (1). Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Dynamic Performance −3dB BW fCL SR Slew Rate (4) VO = 400mVPP (LMH6624) 95 VO = 400mVPP (LMH6626) 85 VO = 2VPP, AV = +20 (LMH6624) 350 VO = 2VPP, AV = +20 (LMH6626) 320 VO = 2VPP, AV = +10 (LMH6624) 400 VO = 2VPP, AV = +10 (LMH6626) 360 MHz V/μs tr Rise Time VO = 400mV Step, 10% to 90% 3.7 ns tf Fall Time VO = 400mV Step, 10% to 90% 3.7 ns ts Settling Time 0.1% VO = 2VPP (Step) 18 ns Distortion and Noise Response en Input Referred Voltage Noise in Input Referred Current Noise f = 1MHz (LMH6624) 0.92 f = 1MHz (LMH6626) 1.0 f = 1MHz (LMH6624) 2.3 f = 1MHz (LMH6626) 1.8 nV/√Hz pA/√Hz HD2 2nd Harmonic Distortion fC = 10MHz, VO = 1VPP, RL 100Ω −63 dBc HD3 3rd Harmonic Distortion fC = 10MHz, VO = 1VPP, RL 100Ω −80 dBc Input Characteristics VOS Input Offset Voltage Average Drift IOS IB (5) +0.5 +0.7 0.05 1.1 2.5 (LMH6626) VCM = 0V −2.0 −2.5 0.1 2.0 2.5 (5) (6) Input Capacitance (6) Common Mode Rejection Ratio VCM = 0V 0.7 VCM = 0V 13 mV μV/°C ±0.2 −1.1 −2.5 Input Resistance CMRR ±0.10 Input Offset Current Average Drift (LMH6624) (5) VCM = 0V Average Drift CIN −0.5 −0.7 VCM = 0V Input Bias Current RIN VCM = 0V μA nA/°C μA +20 +25 VCM = 0V 12 nA/°C Common Mode 6.6 MΩ Differential Mode 4.6 kΩ Common Mode 0.9 Differential Mode 2.0 pF Input Referred, VCM = −4.5 to +5.25V VCM = −4.5 to +5.0V 90 87 95 (LMH6624) RL = 100Ω, VO = −3V to +3V 77 72 81 (LMH6626) RL = 100Ω, VO = −3V to +3V 74 70 80 dB Transfer Characteristics AVOL (1) (2) (3) (4) (5) (6) Large Signal Voltage Gain dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change. Simulation results. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 5 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com ±6V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6V, V− = −6V, VCM = 0V, AV = +20, RF = 500Ω, RL = 100Ω. Boldface limits apply at the temperature extremes. See (1). Symbol Xt Parameter Crosstalk Rejection Conditions Min (2) Typ (3) Max (2) −75 f = 1MHz (LMH6626) Units dB Output Characteristics VO Output Swing (LMH6624) RL = 100Ω ±4.4 ±4.3 ±4.9 (LMH6624) No Load ±4.8 ±4.65 ±5.2 (LMH6626) RL = 100Ω ±4.3 ±4.2 ±4.8 (LMH6626) No Load ±4.8 ±4.65 ±5.2 RO Output Impedance f ≤ 100KHz ISC Output Short Circuit Current (LMH6624) Sourcing to Ground ΔVIN = 200mV (7), (8) 100 85 156 (LMH6624) Sinking to Ground ΔVIN = −200mV (7), 100 85 156 (LMH6626) Sourcing to Ground ΔVIN = 200mV (7), (8) 65 55 120 (LMH6626) Sinking to Ground ΔVIN = −200mV (7), 65 55 120 IOUT Output Current V 10 (8) (8) (LMH6624) Sourcing, VO = +4.3V Sinking, VO = −4.3V 100 (LMH6626) Sourcing, VO = +4.3V Sinking, VO = −4.3V 80 mΩ mA mA Power Supply PSRR Power Supply Rejection Ratio VS = ±5.4V to ±6.6V IS Supply Current (per channel) No Load (7) (8) 6 82 80 88 12 dB 16 18 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is 1.5ms. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 Typical Performance Characteristics Voltage Noise vs. Frequency Current Noise vs. Frequency Figure 4. Figure 5. Inverting Frequency Response Inverting Frequency Response 5 5 VS = ±2.5V 3 AV = -10 RL = 100: 2 AV = -20 1 0 -1 AV = -40 -2 AV = -60 -3 AV = -80 -4 AV = -20 0 -1 AV = -40 -2 AV = -60 -3 AV = -80 -4 AV = -100 -5 1M 100k 10k 10M 100M 1k 1G Figure 6. Figure 7. 2 AV = +10 1 0 AV = +200 AV = +100 AV = +40 AV = +30 -4 1G Non-Inverting Frequency Response VS = ±6V 4 VO = 2VPP -3 100M 5 RF = 500: -2 10M FREQUENCY (Hz) VS = ±2.5V -1 1M 100k 10k FREQUENCY (Hz) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) AV = -10 1 Non-Inverting Frequency Response 3 RL = 100: 2 AV = -100 1k 4 VIN = 5mVPP 3 -5 5 VS = ±6V 4 VIN = 5mVPP NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 RF = 500: 3 VO = 2VPP 2 AV = +10 1 0 AV = +200 -1 AV = +100 -2 AV = +40 -3 AV = +30 -4 AV = +20 -5 AV = +20 -5 1k 10k 100k 1M 10M 100M 1G 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Figure 9. 100M 1G Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 7 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Open Loop Frequency Response Over Temperature 80 -40°C 70 Open Loop Frequency Response Over Temperature 0 -45 25°C PHASE -90 125°C -40°C 50 -135 125°C GAIN 40 -180 25°C 30 -225 20 -270 PHASE (°) GAIN (dB) 60 -315 10 VS = ±2.5V 0 100k 1M 10M 100M -360 1G FREQUENCY (Hz) Figure 10. Figure 11. Frequency Response with Cap. Loading Frequency Response with Cap. Loading 5 5 33pF 3 4 15pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10pF 2 1 5pF 0 0pF -1 VS = ±2.5V -2 AV = +10 -3 -4 RF = 250: RISO = 10: 3 1 5pF 0 -1 VS = ±6V -2 AV = +10 -3 0pF RF = 250: RISO = 10: RL = 1k:||CL -5 -5 1M 10M 1M 1G 100M 10M Figure 12. Figure 13. Frequency Response with Cap. Loading Frequency Response with Cap. Loading 5 5 VS = ±2.5V 4 4 AV = +10 3 RF = 250: 0pF 2 RISO = 100: 1 RL = 1k:||CL NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1G 100M FREQUENCY (Hz) FREQUENCY (Hz) 5pF 0 -1 10pF -2 15pF -3 VS = ±6V AV = +10 3 RF = 250: 2 RISO = 100: 1 RL = 1k:||CL 0pF 5pF 0 -1 10pF -2 15pF -3 33pF -4 33pF -4 -5 -5 1M 10M 100M 1G FREQUENCY (Hz) 1M 10M 100M 1G FREQUENCY (Hz) Figure 14. 8 15pF 10pF 2 -4 RL = 1k:||CL 33pF Figure 15. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Non-Inverting Frequency Response Varying VIN Non-Inverting Frequency Response Varying VIN 5 3 VS = ±6V 4 AV = +10 RF = 500: 2 VIN = 20mV 1 0 -1 -2 VIN = 200mV NOMALIZED GAIN (dB) NOMALIZED GAIN (dB) 4 5 VS = ±2.5V -3 AV = +10 3 RF = 500: 2 VIN = 20mV 1 0 -1 -2 VIN = 200mV -3 -4 -4 -5 -5 100k 1M 10M 100M 100k 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Figure 17. Non-Inverting Frequency Response Varying VIN (LMH6624) Non-Inverting Frequency Response Varying VIN (LMH6626) 5 3 RF = 500: 2 1 0 VIN = 20mV -1 -2 VIN = 200mV -3 VS = ±2.5V 4 AV = +20 NORMALIZED GAIN (dB) NOMALIZED GAIN (dB) 4 5 VS = ±2.5V -4 AV = +20 3 RF = 500: 2 1 VIN = 20mV 0 -1 -2 -3 VIN = 200mV -4 -5 -5 100k 1M 10M 100M 1G 100k 1M FREQUENCY (Hz) 10M 100M 1G FREQUENCY (Hz) Figure 18. Figure 19. Non-Inverting Frequency Response Varying VIN (LMH6624) Non-Inverting Frequency Response Varying VIN (LMH6626) 5 3 5 VS = ±6V RF = 500: 2 1 0 VIN = 20mV -1 -2 -3 VIN = 200mV -4 AV = +20 3 RF = 500: 2 1 VIN = 20mV 0 -1 -2 -3 VIN = 200mV -4 -5 100k VS = ±6V 4 AV = +20 NORMALIZED GAIN (dB) NOMALIZED GAIN (dB) 4 -5 1M 10M 100M 1G FREQUENCY (Hz) 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 9 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Sourcing Current vs. VOUT (LMH6624) Sourcing Current vs. VOUT (LMH6626) 160 140 -40°C -40°C 140 120 120 ISOURCE (mA) ISOURCE (mA) 100 125°C 100 25°C 80 60 80 25°C 125°C 60 40 40 20 20 VS = ±2.5V VS = ±2.5V 0 0 0 0.5 1 1.5 0 0.5 1 1.5 VOUT (V) VOUT (V) Figure 22. Figure 23. Sourcing Current vs. VOUT (LMH6624) Sourcing Current vs. VOUT (LMH6626) 140 180 -40°C -40°C 160 120 25°C 140 100 120 ISOURCE (mA) ISOURCE (mA) 125°C 25°C 100 80 60 80 125°C 60 40 40 20 20 VS = ±6V VS = ±6V 0 0 0 1 2 3 VOUT (V) 4 5 0 1 2 3 Figure 24. Figure 25. VOS vs. VSUPPLY (LMH6624) VOS vs. VSUPPLY (LMH6626) 100 0 125°C 125°C 50 VOS (PV) -50 VOS (PV) 5 150 50 25°C -100 -150 -200 0 25°C -50 -100 -150 -40°C -40°C -250 -200 -250 -300 4 5 6 7 8 9 10 11 12 VSUPPLY (V) 4 5 6 7 8 9 10 11 12 VSUPPLY (V) Figure 26. 10 4 VOUT (V) Figure 27. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Sinking Current vs. VOUT (LMH6624) Sinking Current vs. VOUT (LMH6626) 140 160 -40°C -40°C 140 120 120 125°C 25°C 100 125°C ISINK (mA) ISINK (mA) 100 80 60 25°C 80 60 40 40 20 20 0 VS = ±2.5V VS = ±2.5V 0 -20 0 0.5 1 0 1.5 0.5 VOUT (V) 1 1.5 VOUT (V) Figure 28. Figure 29. Sinking Current vs. VOUT (LMH6624) Sinking Current vs. VOUT (LMH6626) 140 180 -40°C -40°C 160 120 140 100 125°C 125°C ISINK (mA) ISINK (mA) 120 25°C 100 80 80 25°C 60 60 40 40 20 20 VS = ±6V VS = ±6V 0 0 0 1 2 3 4 5 0 1 2 VOUT (V) 3 4 5 VOUT (V) Figure 30. Figure 31. IOS vs. Crosstalk Rejection vs. Frequency (LMH6626) VSUPPLY 0.2 0 0.15 -20 0.1 -40 RL = 100: CROSSTALK (dB) IOS (PA) VIN = 60mVPP AV = +20 25°C 0.05 125°C 0 -0.05 -0.1 CH 1 OUTPUT -60 -80 VS = ±2.5V -100 CH 2 OUTPUT -120 -40°C VS = ±6V -140 -0.15 4 5 6 7 8 9 10 11 12 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) VSUPPLY (V) Figure 32. Figure 33. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 11 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Distortion vs. Frequency Distortion vs. Frequency 0 0 AV = +20 AV = +10 RL = 100: -40 -60 RL = 100: -20 DISTORTION (dBc) DISTORTION (dBc) -20 HD2 VS = ±6V, VO = 2VPP -80 HD3 -100 -40 VS = ±6V, -60 -80 VS = ±2.5V, VO = 1VPP -100 -120 VS = ±2.5V, VO = 1VPP -140 100k 1M 10M HD3 -120 100k 100M 1M FREQUENCY (Hz) Figure 34. Figure 35. Distortion vs. Frequency Distortion vs. Gain -50 VS = ±6V RL = 500: VO = 2VPP -60 DISTORTION (dBc) DISTORTION (dBc) AV = +20 -40 -60 HD2 VS = ±2.5V, VO = 1VPP -80 -100 HD2 -70 -80 HD3 VS = ±2.5V -90 HD3 VO = 1VPP -120 -100 -140 100k 1M 10M 0 100M 20 40 60 80 100 GAIN (V/V) FREQUENCY (Hz) Figure 36. Figure 37. Distortion vs. VOUT Peak to Peak Distortion vs. VOUT Peak to Peak 0 0 AV = +20 AV = +20 VS = ±2.5V RL = 100: fC = 10MHz -40 HD2 -60 -80 fC = 1MHz -100 VS = ±6V -20 RL = 100: DISTORTION (dBc) -20 DISTORTION (dBc) fC = 1MHz RL = 100: VS = ±6V, VO = 2VPP HD2 fC = 10MHz -40 -60 -80 HD3 fC = 1MHz -100 HD3 -120 -120 0 0.5 1 1.5 2 2.5 3 3.5 4 VOUT (V) 0 2 4 6 8 10 12 VOUT (VPP) Figure 38. 12 100M 10M FREQUENCY (Hz) 0 -20 HD2 VO = 2VPP Figure 39. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Non-Inverting Large Signal Pulse Response Non-Inverting Large Signal Pulse Response VS = ±6V 200 mV/DIV 200 mV/DIV VS = ±2.5V VO = 1VPP AV = +10 RL = 100: VO = 1VPP AV = +20 RL = 100: 10 ns/DIV 10 ns/DIV Figure 40. Figure 41. Non-Inverting Small Signal Pulse Response Non-Inverting Small Signal Pulse Response VS = ±6V 100 mV/DIV 50 mV/DIV VS = ±2.5V VO = 200mV AV = +10 RL = 100: RL = 100: 10 ns/DIV 10 ns/DIV Figure 43. PSRR vs. Frequency PSRR vs. Frequency 0 VS = ±2.5V VS = ±6V +PSRR, AV +10 -20 -20 +PSRR, AV +20 -50 -PSRR, AV +20 -70 PSRR (dB) -40 -60 +PSRR, AV = +10 -40 -30 PSRR (dB) AV = +20 Figure 42. 0 -10 VO = 500mV -60 +PSRR, AV = +20 -80 -PSRR, AV = +10 -100 -80 -120 -90 -100 1k -PSRR, AV = +20 -PSRR, AV +10 10k 100k 1M 10M 100M 1G -140 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 44. Figure 45. 100M 1G Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 13 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Input Referred CMRR vs. Frequency Input Referred CMRR vs. Frequency 0 VS = ±6V -10 VIN = 5mVPP -20 -20 -30 -30 CMRR (dB) CMRR (dB) -10 0 VS = ±2.5V -40 AV = +10 -50 -60 VIN = 5mVPP -40 -50 AV = +10 -60 -70 -70 AV = +20 -80 AV = +20 -80 -90 -90 1k 1M 100k 10k 10M 100M 1k Figure 46. Figure 47. Amplifier Peaking with Varying RF 3 RF = 1k: 2 RF = 750: 1 0 RF = 511: -1 RF = 2k: 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 100M Amplifier Peaking with Varying RF RF = 2k: RF = 1.5k: -2 VS = ±2.5V AV = +10 RF = 1.5k: 3 RF = 1k: 2 1 RF = 750: 0 RF = 511: -1 -2 -3 -4 RL = 100: -5 10M VS = ±6V AV = +10V RL = 100: -5 100M 1G 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 48. 14 10M 5 4 -4 1M FREQUENCY (Hz) 5 -3 100k 10k FREQUENCY (Hz) Figure 49. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 APPLICATION SECTION Figure 50. Non-Inverting Amplifier Configuration INTRODUCTION The LMH6624/LMH6626 are very wide gain bandwidth, ultra low noise voltage feedback operational amplifiers. Their excellent performances enable applications such as medical diagnostic ultrasound, magnetic tape & disk storage and fiber-optics to achieve maximum high frequency signal-to-noise ratios. The set of characteristic plots in the "Typical Performance" section illustrates many of the performance trade offs. The following discussion will enable the proper selection of external components to achieve optimum system performance. BIAS CURRENT CANCELLATION To cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain setting (Rg) and feedback (Rf) resistors should equal the equivalent source resistance (Rseq) as defined in Figure 50. Combining this constraint with the non-inverting gain equation also seen in Figure 50, allows both Rf and Rg to be determined explicitly from the following equations: Rf = AVRseq and Rg = Rf/(AV-1) (1) When driven from a 0Ω source, such as the output of an op amp, the non-inverting input of the LMH6624/LMH6626 should be isolated with at least a 25Ω series resistor. As seen in Figure 51, bias current cancellation is accomplished for the inverting configuration by placing a resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf||(Rg+Rs)). Rb should to be no less than 25Ω for optimum LMH6624/LMH6626 performance. A shunt capacitor can minimize the additional noise of Rb. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 15 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Figure 51. Inverting Amplifier Configuration TOTAL INPUT NOISE vs. SOURCE RESISTANCE To determine maximum signal-to-noise ratios from the LMH6624/LMH6626, an understanding of the interaction between the amplifier’s intrinsic noise sources and the noise arising from its external resistors is necessary. Figure 52 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in−) source, there is also thermal voltage noise (et = √(4KTR)) associated with each of the external resistors. Equation 1 provides the general form for total equivalent input voltage noise density (eni). Equation 2 is a simplification of Equation 1 that assumes Figure 52. Non-Inverting Amplifier Noise Model (2) Rf||Rg = Rseq for bias current cancellation. Figure 53 illustrates the equivalent noise model using this assumption. Figure 54 is a plot of eni against equivalent source resistance (Rseq) with all of the contributing voltage noise source of Equation 2. This plot gives the expected eni for a given (Rseq) which assumes Rf||Rg = Rseq for bias current cancellation. The total equivalent output voltage noise (eno) is eni*AV. Figure 53. Noise Model with Rf||Rg = Rseq 16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 (3) As seen in Figure 54, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source resistances below 33.5Ω. Between 33.5Ω and 6.43kΩ, eni is dominated by the thermal noise (et = √(4kT(2Rseq)) of the external resistor. Above 6.43kΩ, eni is dominated by the amplifier’s current noise (in = √(2) inRseq). When Rseq = 464Ω (ie., en/√(2) in) the contribution from voltage noise and current noise of LMH6624/LMH6626 is equal. For example, configured with a gain of +20V/V giving a −3dB of 90MHz and driven from Rseq = 25Ω, the LMH6624 produces a total equivalent input noise voltage (eni × √Hz1.57*90MHz) of 16.5μVrms. VOLTAGE NOISE DENSITY (nV/ Hz) 100 et 10 eni en 1 in 0.1 10 100 1k 10k 100k RSEQ (:) Figure 54. Voltage Noise Density vs. Source Resistance If bias current cancellation is not a requirement, then Rf||Rg need not equal Rseq. In this case, according to Equation 1, Rf||Rg should be as low as possible to minimize noise. Results similar to Equation 1 are obtained for the inverting configuration of Figure 51 if Rseq is replaced by Rb and Rg is replaced by Rg + Rs. With these substitutions, Equation 1 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains. NOISE FIGURE Noise Figure (NF) is a measure of the noise degradation caused by an amplifier. (4) The Noise Figure formula is shown in Equation 4. The addition of a terminating resistor RT, reduces the external thermal noise but increases the resulting NF. The NF is increased because RT reduces the input signal amplitude thus reducing the input SNR. 2 2 2 2 en + in (RSeq + (Rf||Rg) ) + 4KT (RSeq + (Rf||Rg)) NF = 10 LOG 4KT (RSeq + (Rf||Rg)) (5) The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg. To minimize noise figure. • Minimize Rf||Rg • Choose the Optimum RS (ROPT) ROPT is the point at which the NF curve reaches a minimum and is approximated by: ROPT ≈ en/in (6) Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 17 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com SINGLE SUPPLY OPERATION The LMH6624/LMH6626 can be operated with single power supply as shown in Figure 55. Both the input and output are capacitively coupled to set the DC operating point. Figure 55. Single Supply Operation LOW NOISE TRANSIMPEDANCE AMPLIFIER Figure 56 implements a low-noise transimpedance amplifier commonly used with photo-diodes. The transimpedance gain is set by Rf. Equation 4 provides the total input current noise density (ini) equation for the basic transimpedance configuration and is plotted against feedback resistance (Rf) showing all contributing noise sources in Figure 57. This plot indicates the expected total equivalent input current noise density (ini) for a given feedback resistance (Rf). The total equivalent output voltage noise density (eno) is ini*Rf. Figure 56. Transimpedance Amplifier Configuration CURRENT NOISE DENSITY (pA/ Hz) 16 14 ini 12 it 10 8 en/RF 6 4 2 in 0 100 1k 10k FEEDBACK RESISTANCE, RF (:) Figure 57. Current Noise Density vs. Feedback Resistance 18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 (7) LOW NOISE INTEGRATOR The LMH6624/LMH6626 implement a deBoo integrator shown in Figure 58. Positive feedback maintains integration linearity. The LMH6624/LMH6626’s low input offset voltage and matched inputs allow bias current cancellation and provide for very precise integration. Keeping RG and RS low helps maintain dynamic stability. KO VO # VIN KO = 1 + ; sRSC RF RG RB VO RS + VIN C R - 50: 50: RF RG RF = RB RG = RS||R Figure 58. Low Noise Integrator HIGH-GAIN SALLEN-KEY ACTIVE FILTERS The LMH6624/LMH6626 are well suited for high gain Sallen-Key type of active filters. Figure 59 shows the 2nd order Sallen-Key low pass filter topology. Using component predistortion methods discussed in OA-21 (SNOA369) enables the proper selection of components for these high-frequency filters. C1 R1 R2 + C2 RF RG Figure 59. Sallen-Key Active Filter Topology LOW NOISE MAGNETIC MEDIA EQUALIZER The LMH6624/LMH6626 implement a high-performance low noise equalizer for such application as magnetic tape channels as shown in Figure 60. The circuit combines an integrator with a bandpass filter to produce the low noise equalization. The circuit’s simulated frequency response is illustrated in Figure 61. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 19 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com Figure 60. Low Noise Magnetic Media Equalizer Figure 61. Equalizer Frequency Response LAYOUT CONSIDERATION TI suggests the copper patterns on the evaluation boards listed below as a guide for high frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case with all high-speed amplifiers, accepted-practice RF design technique on the PCB layout is mandatory. Generally, a good high frequency layout exhibits a separation of power supply and ground traces from the inverting input and output pins. Parasitic capacitances between these nodes and ground may cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information). Use high quality chip capacitors with values in the range of 1000pF to 0.1F for power supply bypassing. One terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a point that is as close as possible to each supply pin as allowed by the manufacturer’s design rules. In addition, connect a tantalum capacitor with a value between 4.7μF and 10μF in parallel with the chip capacitor. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize inductance and microstrip line effect. Place input and output termination resistors as close as possible to the input/output pins. Traces greater than 1 inch in length should be impedance matched to the corresponding load termination. Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to minimize the imbalance of amplitude and phase of the differential signal. Component value selection is another important parameter in working with high speed/high performance amplifiers. Choosing external resistors that are large in value compared to the value of other critical components will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path. Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion. 20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 LMH6624 www.ti.com SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 Device Package Evaluation Board Part Number LMH6624MF SOT-23–5 LMH730216 LMH6624MA SOIC-8 LMH730227 LMH6626MA SOIC-8 LMH730036 LMH6626MM VSSOP-8 LMH730123 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 21 LMH6624 SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 22 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LMH6624 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMH6624MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LMH66 24MA LMH6624MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 24MA LMH6624MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 24MA LMH6624MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 A94A LMH6624MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94A LMH6624MFX NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 A94A LMH6624MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94A LMH6626MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 26MA LMH6626MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMH66 26MA LMH6626MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98A LMH6626MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6624MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6624MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6624MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6624MFX SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6624MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6626MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6626MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMH6626MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6624MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6624MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6624MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6624MFX SOT-23 DBV 5 3000 210.0 185.0 35.0 LMH6624MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMH6626MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6626MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMH6626MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated