ICST ICS1890Y-14 10base-t/100base-tx integrated phyceiver-tm Datasheet

ICS1890
Integrated
Circuit
Systems, Inc.
10Base-T/100Base-TX Integrated PHYceiver™
General Description
The ICS1890 is a fully integrated physical layer device
supporting 10 and 100Mb/s CSMA/CD Ethernet applications.
DTE (adapter cards or motherboards), switching hub, repeater
and router applications are fully supported. The ICS1890
is compliant with the ISO/IEC 8802-3 Ethernet standard
for 10 and 100Mb/s operation. A Media Independent Interface
allowing direct chip-to-chip connection, motherboard-todaughterboard connection or connection via an AUI-like
cable is provided. A station management interface is
provided to enable command information and status
information exchange. The ICS1890 interfaces directly to
transmit and receive isolation transformers and can support
shielded twisted pair (STP) and unshielded twisted pair
(UTP) category 5 cables up to 105 meters. Operation in half
duplex or full duplex modes at either 10 or 100 Mbps
speeds is possible with control by Auto-Negotiation or
manual selection. By employing Auto-Negotiation the
technology capabilities of the remote link partner may be
determined and operation automatically adjusted to the
highest performance common operating mode.
Features
•
One chip integrated physical layer
•
All CMOS, Low power design (<200mA max)
•
Small footprint 64-pin 14mm
•
ISO/IEC 8802-3 CSMA/CD compliant
•
Media Independent Interface (MII)
•
Alternate 100M stream and 10M 7-wire serial
interfaces provided
•
10Base-TX Half & Full Duplex
•
100Base-TX Half & Full Duplex
•
Fully integrated TP-PMD including Stream
Cipher Scrambler, MLT-3 encoder, Adaptive
Equalization, and Baseline Wander Correction
Circuitry
2
QFP package
Block Diagram
PHYceiver and QuickPoll are trademarks of Integrated
Circuit Systems, Inc. Patents pending.
ICS1890RevG 10/21/97
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS1890
Introduction
data stream to look for this pattern and thereby establishes
the link integrity.
The ICS1890 is essentially a nibble/bit stream processor.
When transmitting, it takes sequential nibbles presented at
the Media Independent Interface (MII) and translates them to
a serial bit stream for transmission on the media. When receiving,
it takes the serial bit stream from the media and translates it to
sequential nibbles for presentation to the MII. It has no
knowledge of the underlying structure of the MAC frame it is
conveying.
The 100M Stream Interface option allows access to raw groups
of 5-bit data with lower latency through the PHY. This is useful
in building repeaters where latency is critical.
10Base-T Operation
In 10Base-T mode, the bit stream on the cable is identical to
the de-composed MAC frame. Link pulses are used to establish
the channel integrity. When receiving, the ICS1890 first
synchronizes to the preamble. Once lock is detected, it begins
to present preamble nibbles to the MII. On detection of the
SFD, it frames the subsequent 4-bits which are the first data
nibble.
100Base-TX Operation
When transmitting, the ICS1890 encapsulates the MAC
frame (including the preamble) with the start-of-stream and
end-of-stream delimiters. When receiving, it strips off the
SSD and substitutes the normal preamble pattern and then
presents this and subsequent preamble nibbles to the MII.
When it encounters the ESD, it ends the presentation of
nibbles to the MII. Thus, the MAC reconciliation layer sees
an exact copy of the transmitted frame.
Configuration
The ICS1890 is designed to be fully configurable using
either hardware pins or the (usually) software-driven MII
Management interface, as selected with the HW/SW pin. A
rich set of configuration options are provided. This allows
diverse system implementations and costs.
During periods when no frames are being transmitted or
received, the device signals and detects the idle condition.
This allows the higher levels to determine the integrity of the
connection. In the 100Base-TX mode, a continuous stream of
scrambled ones is transmitted signifying the idle condition.
The receive channel includes logic that monitors the IDLE
2
ICS1890
Modes of Operation
Reset & Basic Initialization
section of the data sheet.
Auto-Negotiation
Reset can be accomplished using either register bit 0:15 or the
RESET pin.
A link can automatically be established using Auto-Negotiation.
When enabled, Auto-Negotiation will exchange information
about the local node’s capabilities with its remote link partner.
After the information is exchanged, each device compares its
capabilities with those of its partner and then the highest
performance operational mode is automatically selected.
For a hardware reset, RESET must be held at a logic zero level
for at least two clock cycles and may be held low as long as
desired.
While RESET is held low the device is in Low Power mode.
As an example, if one device supports 10Base-T and 100BaseTX, and the other device supports 100Base-TX and 100BaseT4, 100Base-TX will automatically be selected.
After the RESET pin is released to a logic one level, Low
Power mode is exited, the PHY address is latched into register
16, and the reset process continues to completion.
See the Auto-Negotiation section for more details on how the
process is initiated and controlled.
For a software reset, a management agent must write a logic
one to register bit 0:15. This will start the reset process. The
software reset bit will clear itself automatically when reset is
completed.
100Base-TX
The primary operational mode of the ICS1890 is to provide
100Base-TX physical layer services. This consists mainly of
converting data from parallel to serial at a 100 Mb/s data rate.
The device may be configured in a number of different ways
and also provides detailed operational status information.
All reset timing parameters are specified in the Electricals
section of the data sheet.
Low Power and Automatic 100Base-T PowerDown
10Base-T
The ICS1890 supports two power saving modes. The ICS1890
device can be placed into a state where very littler power is
drawn by the device. This Low Power mode can be activated
by holding the RESET pin continuously low or by writing a
logic one to the Power-down bit (0:11).
The ICS1890 also provides 10Base-T physical layer services
to allow easy migration from 10 to 100 Mb/s service. Complete
data service is provided with configuration and status available
to management.
Full Duplex
When the device is in Low Power mode, all functions are
disabled except for register access through the MII Management
Interface.
The ICS1890 supports either half and full duplex operation
for both 10Base-T and 100Base-TX. Full Duplex operation
allows simultaneous transmission and reception of data which
can effectively double data throughput to 20 or 200 Mb/s.
All register values are maintained during Low Power mode,
except for latching status bits, which are reset to their default
values.
To operate in Full Duplex mode, some of the standard 10BaseT and 100Base-TX behaviors are modified.
The ICS1890 can also automatically reduce its total power
requirements when operating in 10Base-T mode by automatically
powering-down the 100Base-TX modules.
In 10Base-T Full Duplex mode, transmitted data is not looped
back to the receiver and SQE test is not performed.
The power required by the ICS1890 in normal, 100Base-TX
power-down, and Low Power modes is given in the Electricals
In both 10Base-T and 100Base-TX Full Duplex modes, CRS is
asserted in response only to receive activity and COL always
remains inactive.
3
ICS1890
MII Data Interface
Interface Overviews
The ICS1890 implements a fully compliant IEEE 802.3u
Media Independent Interface for connection to MACs or
repeaters allowing connection between the ICS1890 and
MAC on the same board, motherboard/daughter board or via
a cable in a similar manner to AUI connections.
Overview of MAC/Repeater to PHY Interfaces
To accommodate different applications, the ICS1890 provides
four types of MAC/Repeater to PHY interfaces. The four
interfaces are - 10/100 MII Data Interface, 100M Stream Interface, 10M Serial Interface and the Link Pulse Interface.
The MII is a specification of signals and protocols which
formalizes the interfacing of a 10/100 Mbps Ethernet Media
Access Controller (MAC) to the underlying physical layer.
The specification is such that different physical media may be
supported (such as 100Base-TX, 100Base-T4 and 100BaseFX) transparently to the MAC.
The standard and most commonly used interface is the 10/100
MII Data Interface which provides framed 4-bit nibbles and
control signals.
The 100M Stream Interface provides 5-bits of unframed data
as well as the normal CRS signal which can be used as a fast
look-ahead. This interface is intended for 100Base-TX repeater
applications that require nothing more than recovered parallel
data where all framing is handled in the repeater core logic.
The MII Data Interface specifies transmit and receive data
paths. Each path is 4-bits wide allowing for transmission of a
data nibble. The transmit data path includes a transmit clock
for synchronous transfer, a transmit enable signal and a transmit
error signal. The receive data path includes a receive data
clock for synchronous transfer, a receive data valid signal and
a receive error signal. Both the transmit clock and receive
clock are sourced by the ICS1890.
The 10M Serial Interface provides a framed single data bit
interface with control signals and is ideally suited to applications
that already incorporate a serial 10Base-T MAC with a standard
“7-wire” interface.
The Link Pulse Interface is provided for applications that wish
to fully control the Auto-Negotiation process themselves but
not the actual generation and reception of Link Pulses.
The ICS1890 provides the MII signals carrier sense and
collision detect. In half duplex mode, carrier sense indicates
that data is being transmitted or received, and in full duplex
mode it indicates that data is being received. Collision detect
indicates that data has been received while a transmission is
in progress.
4
ICS1890
The ICS1890 is designed to allow hot insertion of an MII
cable into a MAC MII port. During the power-up phase, the
ICS1890 will isolate the MII and the Twisted Pair Transmit
signal pair
The pins have the following mapping:
100M Stream Interface
The 100M Stream Interface is an alternative parallel interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Stream Interface provides a lower level
interface and, therefore, lower bit delay than the standard MII
Data Interface.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 100
mode.
The Stream Interface bypasses the Physical Coding Sublayer
(PCS) and provides a direct unscrambled, unframed 5-bit
interface to the Physical Media Access (PMA) layer.
The Stream Interface consists of a 14 signal interface: STCLK,
STD[4:0], SRCLK, SRD[4:0], SCRS, SD.
Data is exchanged between the MAC and PHY using 5-bit
unframed code groups at 25 MHz clock rate.
MII
Stream
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
STCLK
(1)
STD4
STD3
STD2
STD1
STD0
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
SRCLK
(2)
SRD4
SRD3
SRD2
SRD1
SRD0
CRS
COL
LSTA
SCRS
(3)
SD
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols
when it is not transmitting data when using the Stream Interface.
The Stream Interface provides a CRS signal by continuing to
use the logic that is bypassed by this interface. This gives a
carrier indication faster than is possible from the MAC/Repeater
since the bits are examined serially as soon as they enter the
PHY.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
Since only the Stream Interface or the MII Interface is active
at once, it is possible to share the MII Data interface pins for
Stream Interface functionality.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense, so no collisions can be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
5
ICS1890
Link Pulse Interface
10M Serial Interface
The Link Pulse Interface is an alternative control interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Link Pulse provides detailed control over
the Auto-Negotiation process.
The 10M Serial Interface is an alternative serial interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The 10M Serial interface provides the same
functionality, but with a serial data stream at a 10 MHz clock
rate.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode, by setting the 10/100SEL pin to 10
mode, and by setting the 10/LP pin to LP mode.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 10
mode.
The Link Pulse Interface consists of a five signal interface:
LTCLK, LPTX, LRCLK, LPRX, SD.
The 10M Serial Interface operation consists of a nine signal
interface: 10TCLK, 10TXEN, 10TD 10RCLK, 10RXDV, 10RD,
10CRS, 10COL, and LSTA.
Since only the Link Pulse Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for Link Pulse Interface functionality.
Data is exchanged between the MAC and PHY serially at a 10
MHz clock rate.
The pins have the following mapping:
Since only the 10M Serial Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for 10M Serial Interface functionality.
The pins have the following mapping:
MII
10M Serial
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
10TCLK
10TXEN
(1)
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
10RCLK
10RXDV
(1)
CRS
COL
LSTA
10CRS
10COL
LSTA
10TD
MII
Link Pulse
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
LTCLK
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
LRCLK
CRS
COL
LSTA
10RD
LPTX
LPRX
SD
Other mode configuration pins behave identically
regardless of which data interface is used.
(1) Error generation and detection is not supported by
10Base-T.
Other mode configuration pins behave identically regardless
of which data interface is used.
6
ICS1890
MII Management Interface
It is imperative that the crystal be cut for accuracy and
temperature coeffieients with the equivalent capacitive loading
of the specific board layout and the chosen neutralizing
capacitors. The overall accuracy for ethernet applications
must be ±50ppm total for accuracy, temperature, and aging.
Therefore the crystal must be cut using a fixture with the
equivalent capacitive loading as in the end application. This
custom “cutting” of the crystal will be at additional cost, but
in high volume applications this may be cost effective compared
to “pretuned” crystal oscillator modules. For more information,
contact ICS Datacom Applications.
The MII also specifies a two-wire management interface and a
protocol between station management and the physical layer.
The ICS1890 implements this interface, providing a
bidirectional data line and a clock input for synchronizing the
data transfers. This interface allows station management to
read from and write to all of the device’s registers.
Twisted Pair Interface
The ICS1890 is able to operate in either 10Base-T or 100BaseTX modes using a shared interface to a universal magnetics
module and single RJ-45 connector jack.
Configuration and Status Interface
The interface signals consist of a differential pair of transmit
signals and a differential pair of receive signals. The interface
also provides pins for setting the 10 & 100M transmit current.
This interface provides a full set of pins to allow the device
to be completely configured by hardware.
The interface also provides dynamic tristate control over
both the Twisted Pair Transmit interface and the MII Receive
interface.
Clock Reference Interface
The ICS1890 synthesizes all its required clock signals from
a single 25MHz frequency reference supplied to the Clock
Reference Interface (REF_IN & REF_OUT).
Link Status and Stream Cipher Locking status signals are
provided for use by a MAC or custom logic.
Any reference must meet the stringent IEEE standard
requirements for total accuracy under all conditions of ±50
parts per million (ppm), even though the device can easily
function with a less accurate reference.
PHY Address & LED Interface
The ICS1890 device uses a unique scheme to multiplex the
PHY Address and the LED outputs onto the same set of five
pins.
Three reference configurations are supported.
Simply connecting the LED from the device pin to either
power or ground sets the address bit to a 1 or 0. The device
then uses the address info to drive the LED correctly
independent of its connection. The Pin Description section
provides detailed connection instructions.
A simple CMOS level signal may be fed into the REF_IN
input, leaving the REF-output unconnected.
A crystal oscillator module may be used to provide the
frequency reference for the REF_IN input instead of simple
reference.
It is possible to use a high precision crystal between the
REF_IN and REF_OUT pins on the ICS1890 to provide the
25MHz time base for part operation. In addition to the
connection of the crystal between these pins, a capacitor
from REF_IN and REF_OUT to ground is necessary to
neutralize the capacitance of the crystal. Since these capacitors
are nominally in series, the values of each of these components
(plus stray board capacitance) will equal twice the rated
capacitance of the crystal (series combination).
7
ICS1890
Functional Blocks
Media Independent Interface (MII) Overview
The ICS1890 auto-negotiation logic is designed to operate
with legacy 10Base-T networks or newer systems with multiple
connection technology options. When operating with a legacy
10Base-T remote partner, the ICS1890 will select the 10BaseT operating mode transparently to the remote partner thus
allowing the preservation of existing legacy network structures
without management intervention.
The MII consists of a data interface, basic register set, and a
serial management interface to the register set.
The data interface is a nibble wide transmit and receive data
interface between the MAC and PHY devices. The interface
supports data transfers at 25 MHz for 100Base-T and 2.5 MHz
for 10Base-T.
Auto-negotiation is accomplished using a physical signaling
scheme that is transparent at the packet and higher level
protocols. This scheme builds upon the 10Base-T link test
pulse sequence by using a burst of pulses to signal
configuration information between the two devices.
The register set consists of basic and extended standard
registers as well as vendor specific registers. There are two
basic registers, a control register to handle basic device
configuration, and a status register to report basic device
abilities and status. The standard extended registers provide
access to an Organizationally Unique Identifier and AutoNegotiation functionality.
The Fast Link Pulse Bursts are simultaneously exchanged by
both nodes on a link segment the local node encodes the data
from the Auto-negotiation Advertisement Register (register
4) into the FLP Bursts it transmits. The data received from the
link partner’s FLP Bursts is placed into the Auto-Negotiation
Link Partner Ability Register (register 5). When Auto-Negotiation
is complete (1:5=1 or 17:4=1), the highest priority technology
from the following table that is common in the two registers is
automatically selected as the operating mode.
Priority Resolution Table
Highest Priority Listed first.
The ICS1890 also provides vendor specific registers that
enhance the device operation. Among these is the QuickPoll
Detailed Status register which provides a comprehensive set
of real-time device information with only single register access.
Auto-Negotiation
The auto-negotiation logic of the ICS1890 has three main
purposes. Firstly, to determine the capabilities of the remote
partner (device at the other end of the cable). Secondly, to
advertise its own capabilities to the remote partner. And thirdly,
to establish a connection with the remote partner using the
highest performance common connection technology.
1)
2)
3)
4)
5)
8
100Base-TX Full Duplex
100Base-T4
100Base-TX
10Base-T Full Duplex
10Base-T
ICS1890
Status
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed Successfully
A-N Complete
0
0
0
0
0
0
0
0
1
Progress Monitor Status Bits
Bit 2
Bit 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1
Bit 0
0
1
0
1
0
1
0
1
1
The entire process, in either case, usually takes less than half
a second to complete. Typically, management will poll the
Auto-Negotiation Complete bit and then the Link Status bit to
determine when a connection has been successfully made
and then the actual type of connection can be determined by
management. This information is all contained in the QuickPoll
register.
In the event that the link partner does not support autonegotiation, backward compatibility is guaranteed because
legacy systems will not respond to the burst (called Fast Link
Pulses). 10Base-T systems will continue to send 10Base-T
link test pulses which will be interpreted by the ICS1890 as
a 10Base-T technology only device. 100Base-TX systems
would send scrambled idle symbols, which would be interpreted
by the ICS1890 as a 100Base-TX only device. Auto-negotiation
is invoked at power-up, upon request by management, or
manually.
When Auto-Negotiation fails, Auto-Negotiation Complete may
never become true or Link Status may never become good.
Station management can detect this condition and discover
why there is a failure to connect by using the detailed information
provided by the Auto-Negotiation Progress Monitor.
Auto-Negotiation Progress Monitor
Under normal circumstances, Auto-Negotiation is able to
effortlessly establish a connection with the link partner. There
are, however, some situations that may prevent AutoNegotiation from completing properly. The Auto-Negotiation
Progress Monitor is designed to provide detailed information
to a station management entity to assist it in making a connection
in the event that Auto-Negotiation is unable to establish a
connection by itself.
The Auto-Negotiation Progress Monitor provides four bits of
status in the QuickPoll Detailed Status register when combined
with the already present Auto-Negotiation Complete bit.
As progress is made through the Auto-Negotiation Arbitration
state machine, higher status values are locked in to the progress
monitor. The status value only is allowed to increase until
either Auto-Negotiation is completed successfully or the
progress monitor status is read by management.
During normal Auto-Negotiation operation, the device exchanges capability information with its link partner and then
sets the Auto-Negotiation Complete bit in the Status register
(1:5) (also available in the QuickPoll register as bit 17:4) to a
logic one to indicate that the information exchange has completed
successfully and that Auto-Negotiation has handed off the
link startup process to the negotiated technology.
After the status is read by management, the status is reset to
the current status of the Arbitration state machine. After
negotiation has completed successfully, any link failure will
cause the process to being anew.
This behavior allows management to always determine the
greatest forward progress made by the Auto-Negotiation logic.
Auto-Negotiation can also accommodate legacy 10Base-T
and 100Base-TX link partners that do not have Auto-Negotiation
capability. In this case, Auto-Negotiation identifies the link
partner as not being Auto-Negotiation able by setting the
LP_AutoNeg_Able bit (6:0) to a logic zero, identifies the
legacy connection to be made by setting the single bit
corresponding to that technology in the AN Link Partner
Abilities Register (either bit 5:7 or 5:5), and finally indicates
Auto-Negotiation Complete.
9
ICS1890
100Base-TX Physical Coding Sublayer [PCS]
Carrier Detector & Framer
4B/5B Encoder/Decoder
The carrier detector examines the serial bit stream looking for
the SSD, the “JK” symbol pair. In the idle state, IDLE symbols
(all logic ones) will be received. If the carrier detector detects a
logic zero in the bit stream, it examines the following bits
looking for the first two non-contiguous zeros, confirms that
the first 5-bits form the “J” symbol (11000) and asserts carrier
detect. At this point the serial data is framed and the second
symbol is checked to confirm the “K” symbol (10001). If
successful, the following framed data (symbols) are presented
to the 4B5B decoder. If the “JK” pair is not confirmed, the false
carrier detect is asserted and the idle state is re-entered.
When the ICS1890 is operating in the 100Base-TX mode,
4B5B coding is used. This coding scheme maps a 4-bit nibble
to a 5-bit code group. Since this gives 32 possible symbols
and the data only requires 16 symbols, 16 symbols are designated
control or invalid. The control symbols used are “JK” as the
start-of-stream delimiter (SSD), “TR” as the end-of-stream
delimiter (ESD), “I” as the IDLE symbol and “H” to signal an
error. All other symbols are invalid and, if detected, will set the
receive error bit in the status register.
When transmitting, nibbles from the MII are converted to 5bit code groups. The first 16 nibbles obtained from the MII are
the MAC frame preamble. The ICS1890 replaces the first two
nibbles with the start-of-stream delimiter (the “JK” symbol
pair). Following the last nibble, the ICS1890 adds the end-ofstream delimiter (the “TR” symbol pair).
Collision Detector Collision is asserted in half-duplex
mode when transmission and data reception occur
simultaneously. In full duplex mode, collision is never asserted.
Parallel/Serial Converter
When receiving, 5-bit code groups are converted to nibbles
and presented to the MII. If the ICS1890 detects one or more
invalid symbols, it sets the receive error bit in the status
register. When receiving a frame, the first two 5-bit code
groups received are the start-of-stream delimiter (the “JK”
symbol pair), the ICS1890 strips them and substitutes two
nibbles of the normal preamble pattern. The last two 5-bit code
groups are the end-of- stream delimiter (the “TR” symbol
group), these are stripped from the nibbles presented to the
MAC.
This block converts data between 5-bit symbols and 1-bit
serial data.
10
ICS1890
4B5B Encoding (including invalid test mode coding)
0
1
2
3
4
5
6
7
Data
Data
Data
Data
Data
Data
Data
Data
0
1
2
3
4
5
6
7
4B Code
3210
0000
0001
0010
0011
0100
0101
0110
0111
I
J
K
T
R
H
V
V
Idle
SSD
SSD
ESD
ESD
Error
Invalid
Invalid
undefined
0101
0101
undefined
undefined
undefined
undefined
undefined
Symbol
Meaning
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
11111
11000
10001
01101
00111
00100
00000
00001
8
9
A
B
C
D
E
F
4B Code
3210
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
10010
10011
10110
10111
11010
11011
11100
11101
V
V
V
V
V
V
V
V(S)
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00010
00011
00101
00110
01000
01100
10000
11001
Symbol
8
9
A
B
C
D
E
F
Meaning
Data
Data
Data
Data
Data
Data
Data
Data
Invalid Error Code Test (TXER asserted)
I
Idle
1111
11111
V
Invalid
0010
00010
J
SSD
1110
11000
V
Invalid
0011
00011
K
SSD
1011
10001
V
Invalid
0101
00101
T
ESD
1001
01101
V
Invalid
0110
00110
R
ESD
0111
00111
V
Invalid
1000
01000
Invalid
1010
01100
H
Error
0100
00100
V
V
Invalid
0000
00000
V
Invalid
1100
10000
V
Invalid
0001
00001
V(S)
Invalid
1101
11001
11
ICS1890
100Base-T Physical Media Access [PMA]
Clock Recovery
Signal Detector
The Clock Recovery block locks onto the incoming data stream,
extracts the embedded clock, and presents the data synchronized
to the recovered clock. This process produces signals with
very low timing uncertainty and noise (jitter).
The ICS1890 Signal Detector is part of the clock recovery
PLL. It detects a Receive Signal Error if no receive signal is
received and detects a PLL Lock Error if the PLL is unable to
lock on to the receive channel signal. A receive channel error
is defined as the loss of receive signal or the loss of PLL lock.
In the event that the PLL is unable to lock on to the receive
signal, it generates a “not locked signal.” The transmit clock
synthesizer provides a center frequency reference for operation
of the clock recovery circuit in the absence of data. The
“receive signal detected” and “not locked” signals are both
used by the logic which monitors the receive channel for
errors.
Remote Fault Signaling Remote fault signaling allows a
link partner to signal receive channel errors on its transmit
channel. It is then possible to establish the integrity of both
the transmit and receive channels. If auto-negotiation is enabled,
the ICS1890 monitors the receive channel for Fast Link
Pulses or Normal Link Pulses. If an error is detected, the
remote error condition is signaled.
Transmit Clock Synthesizer
The ICS1890 synthesizes the transmit clock using a PLL to
produce 2.5 MHz for 10Base-T and 25 MHz for 100Base-TX.
Internal clock frequencies of 20 MHz and 125 MHz are also
generated. This allows the use of a low cost 25 MHz crystal
oscillator for a low jitter reference frequency.
The ICS1890 is able to report a remote fault detected by its
link partner. When the link partner is an ICS1890, a remote
fault will be signaled when it detects a receive signal error. The
definition of a remote fault for a non-ICS1890 link partner is
undefined, but generally will mean that there is a problem with
the integrity of the link partner’s receive channel.
12
ICS1890
100Base-T Twisted Pair Physical Media
Dependent [TP-PMD]
Stream Cipher Scrambler/Descrambler
When the ICS1890 is operating in the 100Base-TX mode, a
stream cipher scrambler/descrambler that conforms to the ANSI
Standard X3T9.5 FDDI TP-PMD is employed. The purpose of
the stream cipher scrambler is to randomize the 100 Mbps data
on transmission resulting in a reduction of the peak amplitudes
in the frequency spectrum. The stream cipher descrambler
restores the received 5-bit code groups to their unscrambled
values. The stream cipher scrambler/descrambler is bypassed
in the 100M stream interface mode.
Figure 1
The ICS1890 uses DC restoration to restore the lost DC
component of the recovered digital data thus correcting for
baseline wander.
MLT-3 Encoder/Decoder
When the ICS1890 is operating in the 100Base-TX mode, an
MLT-3 encoder and decoder is employed. The encoder converts
the NRZI transmitted bit stream to a three-level code resulting
in a reduction in the energy over the critical frequency range
of 20MHz to 100MHz.The MLT-3 decoder converts the received
three-level code back to an NRZI bit stream.
Adaptive Equalizer
The ICS1890 includes an adaptive equalizer to compensate
for signal amplitude and phase distortion incurred from the
transmission media. Signal equalization will actively occur for
twisted pair cable lengths of up to 105 meters.
At a data rate of 100 Mbps, the cable introduces significant
signal distortion due to high frequency roll off and phase
shift. The high frequency loss is mainly due to skin-effect
which causes the conductor resistance to rise as the square of
the frequency (see Figure 2).
DC Restoration
The 100Base-TX specification uses a stream cipher scrambler
to minimize peak amplitudes in the frequency spectrum.
However, the nature of the stream cipher and MLT-3 encoding
is such that long run lengths of zeroes and ones can cause the
production of a DC component. This DC component cannot
be transmitted through the isolation transformers and results
in baseline wander. Baseline wander decreases noise immunity
since the base-line moves closer to either the positive or
negative signal comparaters. Figure 1 is an exaggerated
simulation of the effect of baseline wander (the time period
would normally be much longer).
Resistance (Ohm/m) v. Freq. (MHz)
4
2
0
0.1
1
10
Figure 2
13
100
ICS1890
Typical and worst case frequency response for 100 meters
(worst case length as derived from draft standard EIA/TIA568- A) of UTP Category 5 cable is shown in Figure 3.
The adaptive equalization process consists of applying increasing
amounts of phase and gain correction while monitoring the
integrity of the recovered data. The adaptive equalizer picks
the best of 32 equalization settings and “Fixes” this value into
the equalization register. This setting provides the best recovery
of the transmitted data with lowest Bit Error Rate (BER).
Cable Attenuation (dB) v. Freq. (MHz)
0
10
Line Transmitter The line transmitter logic of the ICS1890
is a current-driven differential driver which can be programmed
for either two-level (10Base-T, Manchester) or three-level
(100Base-TX, MLT-3) transmission. Waveshaping is applied
to control the output edge rate and eliminate the need for
expensive external filters. The transmitter interfaces directly to
an inexpensive isolation transformer (magnetics).
20
30
0.1
1
10
100
typical
worst case
Figure 3
Line Receiver The line receiver circuit accepts either a
The pulse shape of the received signal is critical for MLT-3
encoded data since there are three distinct levels to resolve in
order to properly recover the data. Figure 4 shows the typical
signal at the input and output ends of 100 meters of UTP
Category 5 cable.
differential two-level (10Base-T, Manchester) or three-level
(100Base-TX, MLT-3) signal which first passes through an
isolation transformer. If the polarity correct bit in the Configuration
Register is asserted, the ICS1890 has sensed the reversed
polarity of the receive pair and can switch polarity automatically.
Magnetics A Universal Magnetics module is used to provide
isolation and signal coupling onto the twisted pair cabling for
both 10Base-T and 100Base-TX.
Figure 4
Since the cable length that must be equalized can be anything
from 0 to 105 meters, the optimum equalization cannot be fixed,
but must depend on cable length. Thus, adaptive equalization
must be applied at the receive end to restore the signal.
14
ICS1890
10Base-T Block Diagram
10Base-T
Manchester Encoder/Decoder
Idle Function
When the ICS1890 is operating in the 10Base-T mode,
Manchester coding is used. When transmitting, nibbles from
the MII are converted to a serial bit stream and then Manchester
en-coded. When receiving, the Manchester encoded bit stream
is decoded and converted to nibbles for presentation to the
MII.
The Idle function is used to keep a 10Base-T link alive in the
absence of data transmission.
If no data traffic is transmitted for 16ms, a link pulse will be
transmitted. Link pulse transmission will continue every 16ms
until real data is transmitted.
Clock Synthesis
Link Monitor
A 2.5 MHz clock is synthesized for nibble wide transactions.
A 10 MHz clock is synthesized for serial transactions.
This function is used to qualify a 10Base-T link. If neither data
or a Link Pulse is received for 50 to 150ms, then the link is
considered down. This state is exited after data is received or
3 to 10 Link Pulses are received.
Clock Recovery
The PLL synchronizes on the MAC frame preamble and then
begins recovering data normally.
15
ICS1890
Carrier Detector
Clock Recovery
In half duplex mode carrier is asserted during transmission or
reception of data. In full duplex or repeater mode, carrier is
asserted only on reception of data.
The PLL synchronizes on the MAC fram preamble and then
begins recovering data normally.
Squelch
Collision Detector
The squelch function qualifies the data coming into the device
so that spurious noise events are rejected.
Collision occurs whenever there is simultaneous transmit
and receive activity when a half duplex link is established.
Collision never occurs in full duplex mode.
Auto Polarity Correction
By examining the polarity of received Link Pulses the ICS1890
can determine if the two wires in the receive data pair were
wired correctly. If the wires were accidentally reversed during
installation, the Auto Polarity Correction function can
automatically correct this in the ICS1890. If the ICS1890
corrects the polarity, this is reflected in the 10Base-T Operations
register. This function can also be disabled through the same
register, if desired.
Jabber
The Jabber function prevents the transmitter from erroneously
transmitting for too long a period. The maximum time the
device should transmit continuously is the time it takes to
send a maximum length packet (1500 bytes). The Jabber
function ensures that transmission lasts no longer than 20150ms. The typical value for the ICS1890 is 21ms.
When the jabber timer is exceeded, Collision (COL) is
asserted and the transmit output goes idle for 0.5 ±0.25s.
Line Transmitter
The line transmitter logic of the ICS1890 is a current-driven
differential driver which can be programmed for either twolevel (10Base-T, Manchester) or three-level (100Base-TX, MLT3) transmission. Wavespaping is applied to control the output
edge late and eliminate the need for expensive external filters.
The transmitter interfaces directly to an inexpensive isolation
transformer (magnetics).
This function can be disabled with the Jabber Inhibit register
bit (18:5).
SQE Test
This test is only used in Half Duplex DTE applications and is
disabled in repeater and Full Duplex mode. This test can also
be disabled with the SQE Test Inhibit register bit (18:2).
When enabled and a link is established, 0.6 to 1.6us after the
last positive transition of a transmitted packet, COL will be
asserted for 10 ±5 bit times.
Line Receiver
The line receiver circuit accepts either a differential two-level
(10Base-T, Manchester) or three-level (100Base-TX, MLT-3)
signal which first passes through an isolation transformer. If
the polarity correct bit in the Configuration Register is asserted,
the ICS1890 will sense the polarity of the receive pair and, if
necessary, switch polarity automatically.
Manchester Encoder/Decoder
When the ICS1890 is operating in the 10Base-T mode,
Manchester coding is used. When transmitting nibbles from
the MII are converted to a serial bit stream and then Manchester
en-coded. When receiving, the Manchester encoded bit stream
is decoded and converted to nibbles for presentation to the
MH.
Magnetics
A Universal Magnetics module is used to provide isolation
and signal coupling onto the twisted pair cabling for both
10Base-T and 100Base-TX.
Clock Synthesis
A 2.5MHz clock is synthesized for nibble wide transactions.
A 10MHz clock is synthesized for serial transactions.
16
ICS1890
Management Interface
The ICS1890 provides a management interface to connect to
a management entity. The two wire serial interface is part of
the MII and is described in the MII section. The interface
allows the transport of status information from the ICS1890
to the management entity and the transport of control information
to the ICS1890. It includes a register set, a frame format, and
a protocol.
Preamble
The ICS1890 looks for a pattern of 32 logic ones followed by
the SOF delimiter before responding to a transaction.
Management Register Set
Operation Code The valid codes are 10 for a read operation
and 01 for a write operation. Other codes are ignored.
Start of Frame
Following the preamble a start of frame delimiter of zero-one
initiates a transaction.
The register set includes the mandatory basic control and
status registers and an extended set. The ICS1890 implements
the following registers.
Control
Status
PHY Identifier
PHY Identifier
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Reserved by IEEE
Extended Control
QuickPoll Status
10Base-T Operations
Extended Control 2
Reserved by ICS
Address
There may be up to 32 PHYs attached to the MII. This 5 bit
address is compared to the internal address of the ICS1890,
as set by the P[0...4]* pins, for a match.
(register 0)
(register 1)
(register 2)
(register 3)
(register 4)
(register 5)
(register 6)
(registers 7-15)
(register 16)
(register 17)
(register 18)
(register 19)
(registers 20-31)
Register Address
The ICS1890 uses this field to select one of the registers
within the set. If a non-existent register is specified, the
ICS1890 ignores the command.
TA
This 2-bit field is used by the ICS1890 to avoid contention
during read transactions. The ICS1890 will remain in the high
impedance state for the first bit time and drive a logic zero for
the second bit time.
Data
This is a 16-bit field with bit 15 being the first bit sent or
received.
Management Frame Structure
The management interface uses a serial bit stream with a
specified frame structure and protocol as defined below.
Preamble
SOF
Op Code
Address
Register
TA
Data
Idle
Idle
The ICS1890 is in the high impedance state during the idle
condition. At least one idle must occur after each write to the
device. No idles are required after a read.
11...11
(32 ones)
01
(2 bits)
10 (read), 01 (write)
(2 bits)
AAAAA
(5 bits)
RRRRR
(5 bits)
NN
(2 bits)
DD...DD
(16 bits)
Zo
high impedance
17
ICS1890
Register Access Rules
RO
CW
RW/0
RW
-
Read Only, writes ignored
Command Override Writable
Read/Write only logic zero
Read/Write
Four types of register access are supported by the device.
Read Only (RO) bits may be read, but writes are ignored.
Command Override Writable (CW) bits may be read, but writes
are ignored unless preceded by writing a logic one to the
Command Register Override bit (16:15). ReadWrite Zero (RW/
0) bits may be read, but must only be written with a logic zero
value. Writing a logic one to this type of bit may prevent the
device from operating normally. Read Write (RW) bits may be
read and may be written to any value.
Default Values
0
1
Pin
name
-
No default value
Default to logic zero
Default to logic one
Default depends on the state of the
named pin
-
Self Clearing
Latching Low
Latching High
Modifier
SC
LL
LH
Self clearing bits will clear without any further writes after a
specified amount of time. Latching bits are used to capture an
event. To obtain the current status of a latching bit, the bit
must be read twice in succession. If the special condition still
persists, the bit will be the same on the second read; otherwise,
the condition indication will not be present.
18
ICS1890
Control Register (register 0
[0x00])
Bit
15
14
13
12
Definition
Reset
Loopback
Data Rate
Auto-Negotiation Enable
When bit=0
no effect
disable loop back mode
10 Mb/s operation
disable Auto-Negotiation
11
Power-Down
normal mode
When bit=1
reset the PHY
enable loop back mode
100 Mb/s operation
enable Auto-Negotiation
reduced power
consumption
Access
RW/SC
RW
RW
RW
RW
10
Isolate
no effect
isolate PHY from MII
RW
9
8
7
6
5
4
3
2
1
0
Restart Auto-Negotiation
Duplex Mode
Collision Test
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
no effect
half duplex
no effect
always 0
always 0
always 0
always 0
always 0
always 0
always 0
restart Auto-Negotiation
full duplex
enable collision signal test
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
Control Register (register 0)
Loop Back (bit 14)
The control register is a 16-bit read/write register used to set
the basic configuration modes of the ICS1890. It is accessed
through the management interface of the MII.
Default
0
0
1
1
Hex
3
0
0 if PHY
Address > 0
1 if PHY
Address=0
0
0
0
0
0
0
0
0
0
0
0*
0
0
Setting this bit to a logic one causes the ICS1890 to tristate
the transmit circuitry from sending data and the receive circuitry
from receiving data. The collision detection circuitry is also
disabled unless the collision test command bit is set. Data
presented to the MII transmit data path is returned to the MII
receive data path. The delay from the assertion of Transmit
Data Enable (TXEN) to the assertion of Receive Data valid
(RXDV) will be less than 512 bit times.
Reset (bit 15)
Setting this bit to a logic 1 will reset the device and result in
the ICS1890 setting all its status and control registers to their
default values. During this process the ICS1890 may change
internal states and the states of physical links attached to it.
While in process, the bit will remain set and no other write
commands to the control register will be accepted. The reset
process will be completed within 500 ms and the bit will be
cleared indicating that the reset process is complete.
19
ICS1890
Restart Auto-Negotiation (bit 9)
Data Rate (bit 13)
Setting this bit to a logic one causes the ICS1890 to restart
auto-negotiation. Upon initiation, this bit will be reset to zero.
Setting this bit has no effect if auto-negotiation is not enabled.
If Auto-Negotiation is disabled, setting this bit to a logic one
causes the ICS1890 to operate in the 100 Mbps mode only
and setting this bit to a logic zero causes it to operate in the 10
Mbps mode only. If Auto-Negotiation is enabled, this bit, if
read, has no meaning and, if written, has no effect on the
ICS1890 operation. This bit also has no meaning when Hardware
Priority mode is selected with the HW/SW pin. The status of
the HW/SW pin is reflected in register bit 19:14. When Hardware
Priority mode is selected, the 10/100SEL pin sets the speed.
The Data Rate status bit in the QuickPoll register (17:14)
always shows the correct setting of an active link.
Duplex Mode (bit 8)
If Auto-Negotiation is disabled, setting this bit to a logic one
causes the ICS1890 to operate in the full duplex mode and
setting this bit to a logic zero causes it to operate in the half
duplex mode. If Auto-Negotiation is enabled, this bit, if read,
has no meaning and, if written, has no effect on the ICS1890
operation. This bit also has no meaning when Hardware Priority
mode is selected with the HW/SW pin. In this case, the DPXSEL
pin sets the duplex mode. If the ICS1890 is operating in loop
back mode, this bit will have no effect on the operation.
Auto-Negotiation Enable (bit 12)
Setting this bit to a logic one causes the ICS1890 to determine
the link configuration using the auto-negotiation process.
This will be accomplished by the ICS Auto-Negotiation logic
and the state of the Data Rate (bit 13) and the Duplex Mode
(bit 8) will be ignored. Setting this bit to a logic zero will cause
the link configuration to be determined by bits 8 & 13 or the
DPXSEL & 10/100SEL pins as selected by the HW/SW pin.
This bit has no meaning when Hardware Priority mode is
selected with the HW/SW pin. In this case, the ANSEL pin
controls Auto-Negotiation use.
Collision Test (bit 7)
This command bit is used to test that the collision circuitry is
working when the ICS1890 is operating in the loop back
mode. Setting this bit to a logic one causes the ICS1890 to
assert the collision signal within 512 bit times of TXEN being
asserted and to de-assert it within 4-bit times of TXEN being
de-asserted. Setting this bit to a logic zero causes the ICS1890
to operate in the normal mode.
Power-Down (bit 11)
Reserved (Bits 6 through 0)
Setting this bit to a logic zero has no effect on the ICS1890.
Setting it to logic one will cause the ICS1890 to isolate its
transmit data output and its MII interface with the exception
of the management interface. The ICS1890 will then enter a
Low Power mode where only the management interface and
logic remain active. Setting this bit to logic zero after it has
been set to a logic one will cause the ICS1890 to power-up its
logic and then reset all error conditions. It then enables transmit
data and the MII interface.
These bits are reserved for future IEEE standards. When read,
logic zeros are returned. Writing has no effect on ICS1890
operation.
Isolate (bit 10)
Setting this bit to a logic one causes the ICS1890 to isolate
its data paths from the MII. In this mode, sourced signals
(TXCLK, RXCLK, RXDV, RXER, RXD0-3, COL and CRS)
are in a high impedance state and input signals (TXD0-3,
TXEN and TXER) are ignored. The management interface is
unaffected by this command.
20
ICS1890
Status Register (register 1
Bit
15
Definition
100Base-T4
14
100Base-TX Full Duplex
13
100Base-TX Half Duplex
12
10Base-T Full Duplex
11
10Base-T Half Duplex
10
9
8
7
Reserved
Reserved
Reserved
Reserved
6
MF Preamble Suppression
by
by
by
by
When bit=0
always 0
TX full duplex not
supported
TX half duplex not
supported
10 full duplex not
supported
10 half duplex not
supported
When bit=1
Access
RO
Default
0
TX full duplex supported
CW
1
TX half duplex supported
CW
1
10 full duplex supported
CW
1
10 half duplex supported
CW
1
CW
CW
CW
CW
0
0
0
0
RO
0
RO
0
IEEE
IEEE
IEEE
IEEE
4
Auto-Negotiation
Complete
Remote Fault
3
Auto-Negotiation Ability
2
1
0
Link Status
Jabber Detect
Extended Capability
5
[0x01])
Frames must have
preamble
Auto-Negotiation in
process
no fault detected
PHY is not able to AutoNegotiate
link is not valid
no jabber detected
always 1
Auto-Negotiation
completed
partner indicated a fault
PHY is able to AutoNegotiate
link is valid
jabber detected
Status (register 1)
Hex
7
8
0
RO /LH
0
RO
1
RO /LL
RO /LH
RO
0
0
1
9
10 Mbps Full Duplex (bit 12)
This bit defaults to a logic one indicating that the ICS1890
is able to support 10Base-T Full Duplex operation.
The ICS1890 status register is a 16-bit read-only register
used to indicate the basic status of the ICS1890. It is accessed
via the management interface of the MII. It is initialized during
a power-up or reset to pre-defined default values.
10 Mbps Half Duplex (bit 11) This bit defaults to a logic
one indicating that the ICS1890 is able to support 10Base-T
Half Duplex operation.
100Base-T4 (bit 15)
This bit is permanently set to a logic zero indicating that the
ICS1890 is not able to support 100Base-T4 operation.
Reserved (Bits 10 through 7)
These bits are reserved for future IEEE standards. When read,
logic zeroes are returned. Writing has no effect on ICS1890
operation. These bits may, however, be set using the Command
Override mechanism. This should only be done in accordance
with the IEEE 802.3 standard.
100Base-X Full Duplex (bit 14)
This bit defaults to a logic one indicating that the ICS1890
is able to support 100Base-X Full Duplex operation.
100Base-X Half Duplex (bit 13)
MF Preamble Suppression (bit 6)
This bit defaults to a logic one indicating that the ICS1890
is able to support 100Base-X Half Duplex operation.
This bit is permanently set to a logic zero indicating that the
ICS1890 is not able to support management frames not
preceded by a normal size preamble.
21
ICS1890
Auto-Negotiation Complete (bit 5)
When set to a logic one, this bit indicates that the ICS1890
has completed the auto-negotiation process and that the
contents of registers 4, 5 and 6 are valid. When set to a logic
zero, this bit indicates that auto-negotiation is not complete
Remote Fault (bit 4)
When set to a logic one, this bit indicates that a remote fault
has been detected by Auto-Negotiation. This bit remains set
to a logic one until the fault condition goes away and the
register bit is cleared by reading the status register or by a
reset command.
Auto-Negotiation Ability (bit 3) This bit defaults to a
logic one indicating that the ICS1890 is able to support AutoNegotiation.
Link Status (bit 2)
When set to a logic one, this bit indicates that the Link
Monitor has established a valid link. If the Link Monitor
detects a link failure, this bit is set to a logic zero and remains
zero through the next read of the status register. A link failure
may be due to an error in the receive channel or an error in the
receive channel of the link partner (that is, a “remote fault”).
If auto-negotiation mode is enabled, a local receive channel
error will occur if link pulses are not present during the autonegotiation process or when operating in the 10Base-T mode.
Jabber detect (bit 1)
When set to logic one, this bit indicates that the ICS1890 has
detected the jabber condition. It remains set until cleared by
reading the status register.
Extended Capability (bit 0)
This bit is permanently set to a logic one indicating that the
ICS1890 has an extended register set.
22
ICS1890
PHY Identifier Register (register 2 [0x02])
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
OUI
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
Definition
3|c
4|d
5|e
6|f
7|g
8|h
9|I
10 | j
11 | k
12 | l
13 | m
14 | n
15 | o
16 | p
17 | q
18 | r
When bit=0
When bit=1
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
PHY Identifier Register (register 2)
Octet Format:
Register 2 and Register 3 contain the 24-bit Organizationally
Unique Identifier (OUI), Manufacturers Model Number and
Revision Number. Integrated Circuit Systems’ OUI is used as
the default for registers 2 and 3.
00
|
|
first octet
These two registers can always be read and may be written by
setting the Command Override bit in the Configuration register
(16:15) and then performing a write operation. At power-up
and reset they are set to Integrated Circuit Systems’ OUI. By
allowing these registers to be written, a systems vendor may
substitute their own OUI.
Binary Format:
0
0000
|
lsb
(I/G)
Organizationally Unique Identifier bits 3-18 (bits
15-0)
Default
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0000
abcd
OUI Formatting Information The ICS OUI is shown
below with information on mapping the OUI value into registers
2 and 3.
23
0
0
1
5
A0
BE
|
third octet
second octet
0
0000
|
msb
0
0000
|
lsb
A
0101
|
msb
IEEE Standard 802 Lettered Format
This field contains the lowest 16 bits of the IEEE OUI excluding
OUI maps to bit 15 of the register.
Hex
0000
efgh
0000
ijkl
0101
mnop
0111
qrst
E
0111
|
lsb
1101
uvwx
B
1101
|
msb
ICS1890
PHY Identifier Register (register 3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Definition
OUI bit 19 | s
OUI bit 20 | t
OUI bit 21 | u
OUI bit 22 | v
OUI bit 23 | w
OUI bit 24 | x
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Manufacturer’s Model Number
Revision Number bit 3
Revision Number bit 2
Revision Number bit 1
Revision Number bit 0
[0x03])
When bit=0
bit
bit
bit
bit
bit
bit
When bit=1
5
4
3
2
1
0
PHY Identifier Register (register 3)
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
Default
1
1
1
1
0
1
0
0
0
0
1
0
0
0
1
1
Hex
Register 2 and Register 3 contain the 24 bit Organizationally
Unique Identifier (OUI), Manufacturers Model Number and
Revision Number. Integrated Circuit Systems’ OUI is used as
the default for registers 2 and 3.
Manufacturer’s Model Number bits 5-0 (bits 9-4)
These two registers can always be read and may be written by
setting the Command Override bit in the Configuration register
(16:15) and then performing a write operation. At power-up
and reset they are set to Integrated Circuit Systems’ OUI. By
allowing these registers to be written, a systems vendor may
substitute their own OUI.
Revision Number bits 3-0 (bits 3-0)
Model
1
2
F
4
2
3
Part
ICS1889
ICS1890
The revision number will be incremented each time the silicon
is significantly revised. Currently the device is at revision 2.
Revision
0
1
2
3
See register 2 for OUI formatting information.
Organizationally Unique Identifier bits 19-24 (bits
15-10)
This field contains the upper 6 bits of the IEEE OUI. Bit 19 of
the OUI maps to bit 15 of the register.
24
Description
ICS Internal Release
1st Alpha Customer Samples
1st General Release
1890 “J” Release and above
ICS1890
Auto-Negotiation Advertisement Register (register 4
Bit
Definition
15
Next Page
14
13
12
11
10
Reserved by IEEE
Fault Indication to link partner
Technology Ability Field bit A7
Technology Ability Field bit A6
Technology Ability Field bit A5
9
TAF bit A4: 100Base-T4 Capability
8
7
6
5
4
3
2
1
0
TAF A3: 100Base-TX Full Duplex
Capability
TAF A2: 100Base-TX Half Duplex
Capability
TAF A1: 10Base-T Full Duplex
Capability
TAF A0: 10Base-T Half Duplex
Capability
Selector Field bit S4
Selector Field bit S3
Selector Field bit S2
Selector Field bit S1
Selector Field bit S0
When bit=0
always 0 - not capable of
sending next pages
always 0
no fault
reserved by IEEE
reserved by IEEE
reserved by IEEE
always 0 - 100Base-T4 not
supported
[0x04])
Access
Default
RO
0
RO
RW
CW
CW
CW
0
0
0
0
0
0
RO
0
1
100Base-TX FD supported
RW
1
100Base-TX HD not desired 100Base-TX HD supported
RW
1
10Base-T FD not desired
10Base-T FD supported
RW
1
10Base-T HD not supported
10Base-T HD supported
RW
1
CW
CW
CW
CW
CW
0
0
0
0
1
100Base-TX FD not desired
IEEE
IEEE
IEEE
IEEE
IEEE
802.3
802.3
802.3
802.3
802.3
When bit=1
a fault has occurred locally
default
default
default
default
default
Auto-Negotiation Advertisement Register
(register 4)
Hex
E
1
Next Page (bit 15)
The Auto-Negotiation advertisement register is a 16-bit read/
write register used to indicate the basic capabilities of the
local device. The values written into this register are exchanged
with the remote link partner to determine the best link technology to enable. Normally it is desirable to advertise all of the
capabilities supported by a node. In some cases a certain
technology is not desired and in this case the corresponding
bit can be set to logic zero. If a connection cannot be made in
this case, management should enable all of the capabilities
possessed and restart Auto-Negotiation.
The ICS1890 does not support the next page function. This bit
is permanently set to a logic zero.
Reserved by IEEE (bit 14)
This reserved bit has no effect on the ICS1890. When read,
a logic zero is always returned.
25
ICS1890
Remote Fault (bit 13) Management may set this bit to a
logic one, which sets the remote fault bit in the transmitted
base link code word to a logic one. This indicates to the link
partner that an error has been detected at this end.
The Auto-Negotiation Power-up Remote Fault option (19:4)
can also cause the remote fault bit in the transmitted base link
code word to be set to a logic one.
Technology Ability Field (bits 12:5) This 8-bit field
specifies the data transmission technologies supported by
the ICS1890. On power-up when the HW/SW pin is set to SW,
these bits are set to the values specified in the MII Status
register. When the HW/SW pin is set to HW and ANSEL is
enabled, the single bit corresponding to the values of the
DPXSEL and 10/100SEL pins is enabled. All bits, except the
100Base-T4 (unsupported technology bit) may be set or cleared
allowing management to select the advertised technologies.
Note that bits 12-10 are currently reserved by the IEEE AutoNegotiation standard and should always be set to logic zero.
Selector Field (bits 4:0) This 5-bit field is used to select
the technology supported by the ICS1890. It defaults to
select IEEE 802.3 (00001). These bits can only be written using
the command override mode and should only be set to a
different value as allowed by the IEEE standard
26
ICS1890
Auto-Negotiation Link Partner Ability Register (register 5
Bit
Definition
15
Next Page
14
Reserved by IEEE
13
12
11
10
9
Remote Fault
Technology Ability Field
bit A7
Technology Ability Field
bit A6
Technology Ability Field
bit A5
TAF bit A4: 100Base-T4
Capability
8
TAF A3: 100Base-TX
Full Duplex Capability
7
TAF A2: 100Base-TX
Half Duplex Capability
6
5
4
3
2
1
0
TAF A1: 10Base-T Full
Duplex Capability
TAF A0: 10Base-T Half
Duplex Capability
Selector Field bit S4
Selector Field bit S3
Selector Field bit S2
Selector Field bit S1
Selector Field bit S0
When bit=0
partner does not support
next page exchange
always 0
When bit=1
partner supports next
page exchange
[0x05])
Access
Default
RO
0
RO
0
RO
0
reserved by IEEE
RO
0
reserved by IEEE
RO
0
reserved by IEEE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
RO
RO
RO
RO
0
0
0
0
0
a fault has occurred at
the remote link partner
no fault
partner does not support
100Base-T4
partner does not support
100Base- TX Full
Duplex
partner does not support
100Base- TX Half
Duplex
partner does not support
10Base-T Full Duplex
partner does not support
10Base-T Half Duplex
see decode table
see decode table
see decode table
see decode table
see decode table
Auto-Negotiation Link Partner Ability
Register (register 5)
partner supports
100Base-T4
partner supports
100Base- TX Full
Duplex
partner supports
100Base- TX Half
Duplex
partner supports
10Base-T Full Duplex
partner supports
10Base-T Half Duplex
802.3 = 00001
802.9 = 00010
Hex
0
0
0
0
Remote Fault (bit 13)
The Auto-Negotiation link partner ability register is a 16-bit
read-only register used to indicate the abilities of the link
partner. When compared to local abilities in register 4 and
sorted by the standard IEEE priority table the highest possible
performance link can be determined. Note that the values in
this register are only valid when Auto-Negotiation is complete
as indicated by (1:5) or the equivalent bit in the QuickPoll
register.
When the remote fault bit of the Link Code Word is set to a
logic one, the ICS1890 sets the remote fault bit in the Link
Partner Ability Register to a logic one. This indicates that the
link partner has detected an error.
Technology Field (bits 12:5)
This 8-bit field specifies the data transmission technologies
supported by the remote partner. The contents are valid on
successful completion of Auto-Negotiation as indicated by a
logic one in bit 5 of the ICS1890 status register.
Next Page (bit 15)
If set to a logic one, this bit indicates that the link partner can
operate in the next page mode. Since the ICS1890 does not
support the next page function, no action or response results
from this indication.
Selector Field (bits 4:0)
This 5-bit field indicates the technology supported by the link
partner. A valid IEEE 802.3 link partner will always signal
( 00001). A code of ( 00010) indicates an IEEE 802.9a partner.
All other codes are currently undefined.
Reserved (bit 14)
This reserved bit will always be returned as a logic zero.
27
ICS1890
Auto-Negotiation Expansion Register (register 6
Bit
15
14
13
12
11
10
9
8
7
6
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
by
by
by
by
by
by
by
by
by
by
by
Definition
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
4
Parallel Detection Fault
3
Link Partner Next Page Able
2
Next Page Able
1
Page Received
0
Link Partner is AutoNegotiation Able
always
always
always
always
always
always
always
always
always
always
always
When bit=0
0
0
0
0
0
0
0
0
0
0
0
When bit=1
no fault
link partner is not Next
Page Able
always 0 - next page not
supported
new link code word not
received
link partner not able
Auto-Negotiation Expansion Register
(register 6)
[0x06])
more than one technology
appeared valid
link partner is Next Page
Able
new link code word
received
link partner support AutoNegotiation
Access
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
RO
/LH
Default
0
0
0
0
0
0
0
0
0
0
0
RO
0
RO
0
RO
/LH
0
RO
0
Hex
0
0
0
0
0
Next Page Able (bit 2)
This bit is permanently set to a logic zero indicating that the
ICS1890 is not able to operate in the next page mode.
The Auto-Negotiation expansion register is a 16-bit read-only
register used to indicate the status of the auto-negotiation
process. It is accessed via the management interface of the
MII.
Page Received (bit 1)
If set to a logic one, this bit indicates that three identical and
consecutive link code words have been received from the link
partner.
Reserved (bits 15:5)
These bits are reserved. The contents are permanently set to
logic zeros.
Link Partner Auto-Negotiation Able (bit 0)
Parallel Detection Fault (bit 4)
If set to a logic one, this bit indicates that the link partner is
able to participate in the auto-negotiation process. If set to a
logic zero, it is not able to participate in the auto-negotiation
process.
If set to a logic one, this bit indicates that a parallel detection
fault has been detected. This means that more than one of the
allowed technologies has detected a valid link.
Link Partner Next Page Able (bit 3)
If set to a logic one, this bit indicates that the link partner is
capable of operating in the next page mode.
28
ICS1890
Extended Control Register (register 16
Bit
Definition
15
Command Register Override
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
PHY address bit 4
PHY address bit 3
PHY address bit 2
PHY address bit 1
PHY address bit 0
Stream Cipher Scrambler Test Mode
Reserved for ICS
NRZ/NRZ1 Encoding
Invalid Error Code Test
Reserved for ICS
Stream Cipher Disable
[0x10])
When bit=0
don’t allow writes to CW
bits
Read unspecified
Read unspecified
Read unspecified
Read unspecified
A
MII Management’s
Register Address code
0 - 31 Read Only
Read unspecified
normal
Read unspecified
NRZ
disabled
Read unspecified
enabled
Extended Control Register (register 16)
When bit=1
allow next write to effect
both RW & CW bits
test mode
NRZ1
enabled
disabled
Access
RW
/SC
RW /0
RW /0
RW /0
RW /0
RO
RO
RO
RO
RO
RW
RW /0
RW
RW
RW /0
RW
Default
Hex
0
P4RD
P3TD
P2LI
P1CL
P0AC
0
1
0
0
Bits Reserved for ICS use (Bit 4)
The Control Register is a 16-bit read/write register used to preprogram the ICS1890. At power-up and reset, this register
will be loaded to the default values specified in the table
above.
These bits are reserved for ICS use. These bits should only
be written as logic zero. Writing a logic one to these bits
may prevent the device from operating correctly. The
value of these bits is unspecified and may be a logic zero
or one.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to any
Command Writeable bit (CW) in any register. A write to any
register after this bit is set will reset the bit, preventing
subsequent writes to Command Write able bits from having
any effect. Therefore, each write to a Command Writeable bit
must be preceded by writing a logic one to this bit.
NRZ/NRZ1 Encoding (bit 3)
When this bit is 1 normal NRZ1 encoding of data is performed
for 100Base-TX. When this bit is 0 NRZ coding is used
instead. NRZ encoding can be useful for system debug.
Invalid Error Code Test (bit 2)
Bits Reserved for ICS use (14-11)
If this bit is set to a logic one, the 4B5B encoder allows nondata symbols to be sent when TXER is asserted. See the
Invalid Error Code Test table for the symbol mapping.
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
Reserved for ICS use (bit 1)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits in unspecified and may be a logic zero or one.
PHY Address (Bits 10 through 6)
These five bits are used to indicate the address of the
ICS1890 on the management port of the MII (any number in
the range 0 - 31). The connection of the LEDs to the LED pins
sets the address. A read returns the address. A write is ignored.
Stream Cipher Disable (bit 0)
If this bit is set to a logic one, the stream cipher encoder and
decoder are disabled. This will result in unscrambled IDLES
and data streams being transmitted and received for ease of
debug
Stream Cipher Scrambler Test Mode (Bit 5)
If set to a logic one, the scrambler will resynchronize after
252 bits of non-idle data instead of its normal time.
29
ICS1890
QuickPoll Detailed Status Register (register 17
Bit
15
14
Definition
Data Rate
Duplex
When bit=0
10 Mb/s negotiated
half duplex negotiated
[0x11])
When bit=1
100 Mb/s negotiated
full duplex negotiated
13
Auto-Negotiation Progress
Monitor bit 2
see decode table
12
Auto-Negotiation Progress
Monitor bit 1
see decode table
11
Auto-Negotiation Progress
Monitor bit 0
see decode table
10
Receive Signal Error
signal
loss of signal
9
PLL Lock Error
PLL locked
PLL failed to lock
8
False Carrier Detect
normal carrier or idle
false carrier detected
7
Invalid Symbol
valid symbols
invalid symbol detected
6
Halt Symbol
normal symbols
HALT symbol detected
5
Premature End
normal stream
4
3
Auto-Negotiation complete
Signal Detect 100Base-TX
Auto-Negotiation progress
SD active
stream with two IDLE
symbols
Auto-Negotiation complete
SD inactive
2
Jabber Detect
no jabber detected
jabber detected
1
Remote Fault
no remote fault detected
remote fault detected
0
Link Status
link is not valid
link is valid
QuickPoll Detailed Status (register 17)
Data Rate (bit 15)
The ICS1890 detailed status register is a 16-bit read-only
register used to indicate detailed status of the ICS1890. It is
accessed via the management interface of the MII. It is initialized
during a power-up or reset to pre-defined default values. A
number of bits are duplicated in this register from others to
make them more easily accessable when polling the device for
status. This should be the only register that needs to be
repeatedly polled in an application.
Access
RO
RO
RO
/LL
/LH
RO
/LL
/LH
RO
/LL
/LH
RO
/LH
RO
/LH
RO
/LH
RO
/LH
RO
/LH
RO
/LH
RO
RO
RO
/LH
RO
/LH
RO
/LL
Default
*
*
Hex
0
0
0
0
0
0
0
0
0
0
0
0
0
If set to a logic one, this bit indicates that has been selected
100 Mbps mode. If set to a logic zero, it indicates that the
initial-10 Mbps mode has been selected. This bit’s setting
depends on the setting of the HW/SW pin, 10/100SEL pin,
ANSEL pin, and the setting of bits 0:12, 0:13, and 1:5.
30
ICS1890
Duplex (bit 14)
Premature End (bit 5)
Auto-Negotiation Progress (bit 13 - 11)
Auto-Negotiation Complete (bit 5)
This bit is normally a logic zero indicating normal data streams.
If two IDLE symbols are detected during the reception of a
receive data stream, this bit is set to a logic one and the
ICS1890 returns to the idle state. This bit is initialized to a
logic zero.
If set to a logic one, this bit indicates that has been selected
full duplex mode. If set to a logic zero, it indicates that the half
duplex mode has been selected. This bit’s setting depends on
the setting of the HW/SW pin, DPXSEL pin, ANSEL pin, and
the setting of bits 0:12, 0:8, and 1:5.
When set to a logic one, this bit indicates that the ICS1890
has completed the auto-negotiation process and that the
contents of registers 4, 5 and 6 are valid. When set to a logic
zero, this bit indicates that auto-negotiation is not complete or
that auto-negotiation has been disabled in the command register
(bit 12).
These three bits are encoded to indicate the progress of the
auto-negotiation cycle. These bits are initialized to zero. The
values indicate the progress of auto-negotiation. See the AutoNegotiation Progress Monitor section for the encodings and
additional details.
Receive Signal Error (bit 10)
100Base_TX Signal Detect (bit 3)
If set to a logic one, the receive channel signal (bit 15) indicates
that the ICS1890 read channel has, at some point, been unable
to detect the receive channel signal (either the IDLE stream in
100Base-TX mode or link pulses in 10Base-T mode). This bit
will remain set until cleared by reading the contents of register
17.
The absence of 100Base_TX signaling on the TP_RX± pins
will cause this bit to be asserted (1)
Jabber Detect (bit 2)
When operating in the 10Base-T mode, if set to a logic one,
this bit indicates that a jabber condition occurred and that the
transmit pair has been isolated.
PLL Lock Error (bit 9)
If set to a logic one, the loss of PLL lock indicates that the
ICS1890 read channel PLL has failed to lock onto the read
channel signal. This bit will remain set until cleared by reading
the contents of register 17.
Remote Fault (bit 1) This is a copy of the Remote Fault bit
of the Status Register (register 1).
Link Status (bit 0) This is a copy of the Link Status bit of
False Carrier (bit 8)
the Status Register (register 1).
If set to a logic one, the false carrier indicates that the
ICS1890 has detected a false carrier sometime since this bit
was last reset. This bit will remain set until cleared by reading
the contents of register 17.
Invalid Symbol (bit 7)
If set to a logic one, the invalid symbol indicates that an
invalid symbol has been detected in a received frame since the
bit was last reset. This bit will remain set until cleared by
reading the contents of register 17.
Halt Symbol (bit 6)
If set to a logic one, the halt symbol (bit 10) indicates that the
ICS1890 has detected the halt symbol in a frame since bit 11
was last reset. This bit will remain set until cleared by reading
the contents of register 17.
31
ICS1890
10Base-T Operations Register (register 18
[0x12])
Bit
15
Definition
Reserved for ICS
When bit=0
Read unspecified
When bit=1
must be wirtten as a 0
14
Polarity Reversed
polarity normal
polarity reserved
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Jabber Inhibit
Reserved for ICS
Auto Polarity Inhibit
SQE Test Inhibit
Link Loss Inhibit
Squelch Inhibit
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
normal jabber behavior
Read unspecified
polarity automatically corrected
normal SQE test behavior
normal Link Loss behavior
normal Squelch
no jabber check
must be written as a 1
polarity not corrected
no SQE test
link always = Link Pass
no Squelch
Access
RW /0
RO
/LH
RW /0
RW /0
RW /0
RW /0
RW /0
RW /0
RW /0
RW /0
RW
RW /1
RW
RW
RW
RW
Default
0
Hex
0
0
1
0
0
0
0
0
10Base-T Operations Register (register 18)
This register contains all of the extra status and control bits
required for 10Base-T operation.
Bits Reserved for ICS use (15, 13, 6)
Jabber Inhibit (bit 5)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
Setting this bit to a logic one turns off the internal check for
transmit jabber. When the jabber check is disabled, no action
occurs when transmissions are longer than the jabber timer
value. When this bit is set to a logic zero normal 10Base-T
jabber checking is enabled.
Polarity Reversed (bit 14)
Bit Reserved for ICS use (bit 4)
This bit is set to a logic one if the polarity of the receive data
pair is reversed. This bit will be a logic zero if the polarity is
correct.
This bit must be written to a 1. The read value of this bit is
undefined.
Auto Polarity Inhibit (bit 3)
When this bit is set to a logic one, correction for reversed
receive data wires is disabled. When this bit is set to a logic
Zero, reversed receive data wires are automatically corrected
for internally.
32
ICS1890
SQE Test Inhibit (bit 2)
When this bit is set to a logic one, SQE testing is disabled.
When this bit is set to a logic zero, a normal 10Base-T SQE test
is performed by pulsing the Collision signal for a short time
shortly after each packet transmission completes.
Note that the SQE Test is automatically inhibited in Full Duplex
and Repeater modes.
Link Loss Inhibit (bit 1)
When this bit is set to a logic one, the 10Base-T Link Integrity
Test state machine is forced into the Link Pass state regardless
of the line conditions. This can be useful in debugging a bad
link segment. When this bit is set to a logic zero, the state
machine behaves normally.
Squelch Inhibit (bit 0)
When this bit is set to a logic one, the receive squelch circuitry
is disabled. This can be useful in debugging a bad link segment
or for link segments longer than 100 meters. When this bit is
set to a logic zero, the normal Squelch circuitry is enabled to
filter out spurious line noise.
33
ICS1890
Extended Control Register 2 (register 19
Bit
Definition
When bit=0
[0X13])
When bit=1
Access
Default
NOD/REP
HW/SW
15
Node/Repeater Mode
Node Mode
Repeater Mode
RO
14
Hardware/Software Priority
Hardware Priority
Software Priority
RO
unknown
partner supports Remote Fault
RO
0
RW /0
RW /0
-
RW /0
-
RW /0
RW /0
RW /0
RW /0
RW /0
RW
RW /0
RW /0
RW /0
0
0
0
RW
1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Link Partner Supports
Remote Fault
Reserved for ICS
Reserved for ICS
Transmitted Remote Fault
Status
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
A-N Power-up Remote Fault
Reserved for ICS
Reserved for ICS
Reserved for ICS
Automatic 100Base-TX
Power-down
Read unspecified
Read unspecified
RF bit in transmitted LCW=0
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Normal
Read unspecified
Read unspecified
Read unspecified
RF bit in transmitted LCW=1
Remote Fault on Power-up
Never Power-down automatically
Extended Control Register 2 (register 19)
Node/Repeater Configuration (bit 15)
Power-down automatically
Hex
Hardware/Software Priority Status (bit 14)
This bit directly reflects the status of the NOD/REP pin.
This bit directly reflects the status of the HW/SW pin.
When this bit is logic zero, hardware pins have priority over
software settings. The 10/100SEL pin becomes an input and
controls speed selection. The DPXSEL pin becomes an input
and controls duplex selection. The ANSEL pin becomes an
input and chooses configuration with or without AutoNegotiation.
When configuration through Auto-Negotiation is selected,
the DPXSEL and 10/100SEL settings control the AutoNegotiation register 4 default settings and Auto-Negotiation
is enabled. When configuration without Auto-Negotiation is
selected, DPXSEL controls the duplex setting and 10/100SEL
controls the data rate setting.
When this bit is logic zero, the device will default to Node
operation. SQE test will default to on. Carrier sense in half
duplex mode will be on transmit or receive activity.
When this bit is logic one, the device will default to Repeater
operation. SQE test will default to off. Carrier sense in half
duplex mode will be on receive activity only.
When this bit is a logic one, software bits have priority over
hardware pin settings. The 10/100SEL pin becomes an output
indicating the link speed when LSTA the link is established
and parallels bit (17:15). The DPXSEL pin becomes an output
indicating the link duplex state when the link is established
and parallels bit (17:14). The ANSEL pin becomes an output
indicating whether auto-negotiation is being used and parallels
bit (0:12).
34
ICS1890
Link Partner Remote Fault Capable (bit 13)
Power-up Remote Fault (bit 4)
Note that a logic zero can not definitively mean that the link
partner does not support remote fault indications.
Bits Reserved for ICS use (bits 3-1)
This bit tries to indicate if the link partner supports indication
of a remote fault. If the ICS1890 observes the link partner
Auto-Negotiating with the Remote Fault bit set, this status bit
will be set to a logic one. Otherwise, this bit will be a logic zero.
When this bit is set to a logic one, the RF bit in the outgoing
Auto-Negotiation Link Code Word will automatically be set to
a logic one until receive activity is detected (Normal Link
Pulses, Fast Link Pulses, 100Base-TX data, ...).
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
Reserved (bits 12-11)
These bits are reserved for ICS use. They must only be written
as logic zero. Writing a logic one to any of these bits may
prevent the device from operating normally. The value of
these bits when read is unspecified and may be a logic zero or
one.
Automatic 100Base-TX Power-down (bit 0)
When this bit is set to a logic one and 10Base-T is selected for
the network connection, the 100Base-TX transceiver will
automatically turn off to save power.
Transmitted Remote Fault Status (bit 10)
This bit reflects the current status of the Remote Fault bit in
the Transmitted Link Code Word. This bit is set when bit 4:15
is set or when bit 19:4 is set and the link partner is not
transmitting.
When this bit is set to a logic zero, the 100Base-TX transceiver
will never power-down by itself. The 100Base-TX transceiver
will still power-down when the entire device is isolated using
bit (0:10).
Reserved (bits 9-5)
These bits are reserved for ICS use. They must only be written
as logic zero. Writing a logic one to any of these bits may
prevent the device from operating normally. The value of
these bits when read is unspecified and may be a logic zero or
one.
35
ICS1890
Pin Descriptions
Signal
Meaning
TXCLK*
TXEN*
TXD3*
TXD2*
TXD1*
TXD0*
TXER*
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
RXCLK*
RXDV*
RXD3
RXD2*
RXD1*
RXD0*
RXER*
CRS*
Receive Clock
Receive Data Valid
Receive Data 3
Receive Data 2
Receive Data 1
Receive Data 0
Receive Error
Carrier Sense
COL*
Collision Detect
MDC
MDIO
Management Data Clock
Management Data Input/Output
REF_IN
REF_OUT
Frequency reference
Frequency reference
Clock
Enable
Data 3
Data 2
Data 1
Data 0
Error
TP_TX+
Twisted Pair Transmit Data+
TP_TXTwisted Pair Transmit DataTP_RX+
Twisted Pair Receive Data+
TP_RXTwisted Pair Receive Data10TCSR
10M transmit Current Set Resistor
100TCSR
100M Transmit Current Set Resistor
*Re-defined for other MAC-PYY interfaces
Signal
Meaning
NOD/REP
MII/SI
10/LP
HW/SW
10/100SEL
DPXSEL
ANSEL
ITCLS~
TPTRI
RXTRI
LSTA*
LOCK
RESET~
Node/Repeater Mode
MII Data/Stream Interface
10M Serial/Link Pulse Interface
Hardware/Software Priority
10/100 Select
Duplex Select
Auto-Negotiation Select
Invert Transmit Clock Latching Setting
Twisted Pair Tristate
Receive MAC-PHY Interface Tristate
Link Status
Cipher Lock
System Reset
P4RD
PSTD
P2LI
P1CL
P0AC
PHY
PHY
PHY
PHY
PHY
NC
5 No Connect Pins
VDD
VSS
8 VDD Pins
7 VSS Pins
36
ID
ID
ID
ID
ID
4/Receive data LED
3/Transmit data LED
2/Link Integrity LED
1/Collision det LED
0/Activity LED
ICS1890
Pin Descriptions
MII Data Interface
The following pin descriptions apply in either 10 or 100 Mbps
mode when the MII Data Interface is selected. These pins are
re-used for the 100M Stream Interface, 10M Serial Interface,
and the Link Pulse Interface. These extra pin meanings are
described in separate interface sections with the “pseudo”
pin name followed by the actual pin name that the function is
mapped onto.
Transmit Data 0
TXD0
Transmit Clock
Transmit Error
When operating in the 100 Mbps mode, the assertion of
Transmit Error (TXER) for one or more clock periods will cause
the ICS1890 to emit one or more invalid symbols. The signal
must be synchronous with TXCLK. In the normal operating
mode, a HALT symbol will be substituted for the next nibble
decoded.
TXER
Transmit Data 0 (TXD0) is the least significant bit of the
transmit data nibble. TXD0 is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD0.
TXCLK
The Transmit Clock (TXCLK) is a continuous clock signal
generated by the ICS1890 to synchronize information transfer
on the Transmit Enable, Transmit Data and Transmit Error
lines. The ICS1890 clock frequency is 25% of the nominal
transmit data rate. At 10 Mbps, its frequency is 2.5 MHz and at
100 Mbps is 25 MHz.
Transmit Enable
If the Invalid Error Code Test bit (16:2) is set, the 5-bit code
group shown in the 4B5B encoding table will be substituted
for the transmit data nibble presented.
TXEN
Transmit Enable (TXEN) indicates to the ICS1890 that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion, the ICS1890
will begin reading the data nibbles on the transmit data lines. It
is the responsibility of the MAC to order the nibbles so that
the preamble is sent first, followed by destination, source,
length, data and CRC fields since the ICS1890 has no knowledge
of the frame structure and is merely a “nibble” processor. The
ICS1890 terminates transmission of nibbles following the
de-assertion of Transmit Enable (TXEN).
Transmit Data 3
The value of TXER during 10 Mbps operation has no effect on
the ICS1890.
Receive Clock
TXD3
Transmit Data 3 (TXD3) is the most significant bit of the
transmit data nibble. TXD3 is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD3.
Transmit Data 2
TXD2
Transmit Data 1
TXD1
RXCLK
The Receive Clock (RXCLK) is sourced by the ICS1890.
There are two possible sources for the Receive Clock (RXCLK).
When a carrier is present on the receive pair, the source is the
recovered clock from the data stream. When no carrier is
present on the receive pair, the source is the Transmit Clock
(TXCLK). In 10Base-T mode, the receive data pair will be
quiescent during periods of inactivity and the Transmit Clock
will be selected. In 100Base-T mode, the IDLE symbol is sent
during periods of inactivity and the Recovered clock will be
selected.
The ICS1890 will only switch between clock sources when
Receive Data Valid (RXDV) is de-asserted. During the period
between Carrier Sense (CRS) being asserted and Receive Data
Valid being asserted, a clock phase change of up to 360
degrees may occur. Following the de-assertion of Receive
Data Valid a clock phase of 360 degrees may occur.
Transmit Data 2 (TXD2) is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD2.
When Receive Data Valid is asserted, the Receive Clock
frequency is 25% of the data rate, 2.5 MHz in 10Base-T mode
and 25 MHz in 100Base-T mode. The ICS1890 synchronizes
Receive Data Valid, Received Data and Receive Error with
Receive Clock (RXCLK).
Transmit Data 1 (TXD1) is sampled by the ICS1890
synchronously with the Transmit Clock when TXEN is asserted.
When TXEN is de-asserted, the ICS1890 is unaffected by the
state of TXD1.
37
ICS1890
Receive Data Valid
RXDV
Receive Data 3
RXD3
The assertion of Receive Error (RXER) for one or more
clock periods during the period when RXDV is asserted
(receiving a frame) indicates that the ICS1890 has detected
a read channel error. There are three sources of read channel
error: loss of receive signal, failure of the PLL to lock and
invalid symbol detection. RXER may also be asserted when
RXDV is de-asserted. The ICS1890 will assert RXER and set
RXD(3:0) to 1110 if a false carrier is detected. For a good
carrier to be detected, the ICS1890 looks continuously at the
incoming IDLE stream (1111...) for two non-contiguous
logic zeroes and then checks for the SSD of “JK.” In the event
that two non-contiguous logic zeroes are detected but the JK
symbol pair is not, then a false carrier condition is signaled
and the IDLE condition is re-entered.
Receive Data Valid (RXDV) is generated by the ICS1890. It
indicates that the ICS1890 is recovering and decoding data
nibbles on the Receive Data (RXD) data lines synchronous
with the Receive Data Clock (RXCLK). It is the responsibility
of the MAC to frame the nibbles since the ICS1890 has no
knowledge of the frame structure and is merely a “nibble”
processor. The ICS1890 asserts RXDV when it detects and
recovers the pre-amble or the start of stream delimiter (SSD)
and de-asserts it following the last data nibble or upon detection
of a signal error. RXDV is synchronous with the Receive Data
Clock (RXCLK).
Receive Data 3 (RXD3) is the most significant bit of the receive
data nibble. RXD is sourced by the ICS1890. When Receive
Data Valid (RXDV) is asserted by the ICS1890, it will
transfer the 4th bit of the symbol synchronously with Receive
Clock (RXCLK).
Receive Data 2
Carrier Sense
RXD2
Receive Data 2 (RXD2) is sourced by the ICS1890. When
Receive Data Valid (RXDV) is asserted by the ICS1890, it
will transfer the 3rd bit of the symbol synchronously with
Receive Clock (RXCLK).
Receive Data 1
In full duplex mode and repeater mode, CRS is asserted only
on receive activity.
Collision Detected
RXD1
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the unsquelched receive signal. In the 100 Mbps
mode, the non-idle condition is detected by two non-contiguous
zeros in any 10-bit code group. COL is not synchronous to
either the transmit or receive clocks.
RXD0
Receive Data 0 (RXD0) is the least significant bit of the receive
data nibble. RXD0 is sourced by the ICS1890. When Receive
Data Valid (RXDV) is asserted by the ICS1890, it will
transfer the 1st bit of the symbol synchronously with Receive
Clock (RXCLK).
Receive Error
COL
The ICS1890 asserts Collision Detected (COL) when it
detects a receive carrier (non-idle condition) while transmitting
(TXEN asserted).
Receive Data 1 (RXD1) is sourced by the ICS1890. When
Receive Data Valid (RXDV) is asserted by the ICS1890, it
will transfer the 2nd bit of the symbol synchronously with
Receive Clock (RXCLK).
Receive Data 0
CRS
The ICS1890 asserts Carrier Sense (CRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are idle in half duplex mode. CRS is not synchronous
to either the transmit or receive clocks.
In full duplex mode, COL is disabled and always remains low.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).
RXER
In 100 Mbps mode, the ICS1890 detects two types of receive
errors, errors occurring during the reception of valid frames
and an error condition known as false carrier detect. False
carrier detect is signaled so that repeater applications can
prevent the propagation of false carrier detection. RXER always
transitions synchronously with RXCLK.
38
ICS1890
100M Stream Interface
100M Stream Interface - Pin Mapping
When the ICS1890 is operating in the stream mode, the MII
Data Interface is remapped to accommodate the 100M Stream
Interface. The following table details the exact pin mapping.
Each individual pin description also contains the “new 100M
Stream Interface pseudo pin name” followed by the real MII
Data Interface pin name that it is mapped onto.
100M Stream Interface provides a lower latency parallel
interface producing an AMD PDR/PDT and twister type 5 bit
unscrambled interface when the data is scrambled by the
upper layer.
39
MII
Stream
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
STCLK
(1)
STD4
STD3
STD2
STD1
STD0
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
SRCLK
(2)
SRD4
SRD3
SRD2
SRD1
SRD0
CRS
COL
LSTA
SCRS
(3)
SD
ICS1890
Receive Clock
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols when
it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense so collisions can not be detected.
The Receive Clock frequency is 25 MHz in the 100M Stream
Interface mode.
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
STCLK/(TXCLK)
STD4/(TXER)
STD2/(TXD2)
Transmit Data 0
STD0/(TXD0)
Receive Data 2
SRD2/(RXD2)
Receive Data 1
SRD1/(RXD1)
Receive Data 0
SRD0/(RXD0)
Receive Data 0 (SRD0) is the least significant bit of the receive
data nibble.
Transmit Data 2 (STD2) is sampled continuously by the
ICS1890 synchronously with the Transmit Data Clock.
STD1/(TXD1)
SRD3/(RXD3)
Receive Data 1 (SRD1) is continuously asserted by the
ICS1890.
STD3/(TXD3)
Transmit Data 1
Receive Data 3
Receive Data 2 (SRD2) is continuously asserted by the
ICS1890.
Transmit Data 3 (STD3) is sampled continuously by the
ICS1890 synchronously with the Transmit Clock.
Transmit Data 2
SRD4/(RXER)
Receive Data 3 (SRD3) is continuously asserted by the
ICS1890.
Transmit Data 4 (STD4) is the most significant bit and is
sampled continuously by the ICS1890 synchronously with
the Transmit Clock.
Transmit Data 3
Receive Data 4
Receive Error (SRD4) is the most significant bit of the receive
data nibble and is continuously asserted by the ICS1890.
The Transmit Clock (STCLK) is a continuous clock signal
generated by the ICS1890 to synchronize the Transmit Data
lines. In the 100M Stream Interface mode, the ICS1890
clock frequency is 25 MHz.
Transmit Data 4
SRCLK/(RXCLK)
The Receive Clock (SRCLK) is sourced by the ICS1890.
There are two possible sources for the Receive Clock (SRCLK).
When a carrier is present on the receive pair, the source is the
recovered clock from the data stream. When no carrier is
present on the receive pair, the source is the Transmit Clock
(STCLK).
Carrier Sense
SCRS/(CRS)
Carrier Sense is provided in the 100M Stream Interface mode
as a fast receive carrier look-ahead for optional application
use. Carrier is detected using the same circuitry used in the
MII Data Interface mode that is “bypassed” in this mode.
Transmit Data 1 (STD1) is sampled continuously by the
ICS1890 synchronously with the Transmit Clock.
The ICS1890 asserts Carrier Sense (SCRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are non-idle in half duplex mode. SCRS is not
synchronous to either the transmit or receive clocks.
Transmit Data 0 (STD0) (the least significant bit) is sampled
continuously by the ICS1890 synchronously with the Transmit
Clock.
In full duplex mode and repeater mode, SCRS is asserted only
on receive activity.
Signal Detect
SD/(LSTA)
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
40
ICS1890
10M Serial Interface
Transmit Data
10M Serial Interface - Pin Mapping
MII
TXCLK
TXEN
TXER
TXD3
TXD2
XD1
TXD0
Receive Clock
10TCLK
10TXEN
(1)
The ICS1890 will only switch between clock sources when
Receive Data Valid is de-asserted. During the period between
Carrier Sense (CRS) being asserted and Receive Data Valid
being asserted, a clock phase change of up to 360 degrees
may occur. Following the de-assertion of Receive Data valid, a
clock phase of 360 degrees may occur.
10TD
10RD
CRS
COL
LSTA
10CRS
10COL
LSTA
10RCLK/(RXCLK)
The Receive Clock (10RCLK) is sourced by the ICS1890 and
is 10 MHz in frequency. There are two possible sources for the
Receive Clock. When a carrier is present on the receive pair,
the source is the recovered clock from the data stream. When
no carrier is present on the receive pair, the source is the
Transmit Clock. In 10Base-T mode, the receive data pair will
be quiescent during periods of inactivity and the Transmit
Clock will be selected.
10M Serial
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
10TD/(TXD0)
Transmit Data 0 (10TD) is the serial transmit data bit and is
sampled continuously by the ICS1890 synchronously with
the Transmit Clock.
When the ICS1890 is operating in the 10M Serial mode, the
MII Data Interface is remapped to accommodate the 10M
Serial Interface. The following table details the exact pin mapping.
Each individual pin description also contains the “new 10M
Serial Interface pseudo pin name” followed by the real MII
Data Interface pin name that it is mapped onto.
10RCLK
10RXDV
(1)
Receive Data Valid
10RXDV/(RXDV)
Receive Data Valid (10RXDV) is generated by the ICS1890.
It indicates that the ICS1890 is recovering serial data on the
Receive Data (10RD) line synchronous with the Receive Data
Clock.
(1) Error generation and detection is not supported by 10BaseT. Other mode configuration pins behave identically regardless
of which data interface is used.
The ICS1890 asserts RXDV when it detects and recovers the
preamble or the start of stream delimiter (SSD) and de-asserts
it following the last data nibble or upon detection of a signal
error. RXDV is synchronous with the Receive Data Clock
(10RCLK).
Transmit Clock
Receive Data
10RD/(RXD0)
Carrier Sense
10CRS/(CRS)
10TCLK/(TXCLK)
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the ICS1890 to synchronize the Transmit Data
lines. In the 10M Serial Interface mode, the ICS1890 clock
frequency is 10 MHz.
Transmit Enable
Receive Data 0 (10RD) is the received serial data stream.
The ICS1890 asserts Carrier Sense (CRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are idle in half duplex mode. CRS is not synchronous
to either the transmit or receive clocks.
10TXEN/(TXEN)
Transmit Enable (10TXEN) indicates to the ICS1890 that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion, the ICS1890
will begin reading the serial data on the transmit data line. The
ICS1890 terminates transmission of data following the deassertion of Transmit Enable.
In full duplex mode and repeater mode, CRS is asserted only
on receive activity.
41
ICS1890
Collision Detected
10COL/(COL)
Transmit Clock
The ICS1890 asserts Collision Detected (COL) when it
detects a receive carrier (non idle condition while transmitting
(TXEN asserted).
Transmit Link Pulse
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the un-squelched receive signal. COL is not
synchronous to either the transmit or receive clocks.
Receive Clock
Receive Link Pulse
Link Pulse Interface - Pin Mapping
Signal Detect
When the ICS1890 is operating in the Link Pulse mode, the
MII Data Interface is remapped to accommodate the Link
Pulse Interface. The following table details the exact pin mapping.
Each individual pin description also contains the “new Link
Pulse Interface pseudo pin name” followed by the real MII
Data Interface pin name that it is mapped onto.
K LRCLK
CRS
COL
LSTA
SD/(LSTA)
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
Link Pulse
RXCL
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
LPRX/(RXER)
Receive activity that is qualified as a Link Pulse will be output
on this pin as a high level of approximately the same duration
as the Link Pulse.
Link Pulse Interface
LTCLK
TXER
LRCLK/(RXCLK)
The Receive Clock (LRCLK) is sourced by the ICS1890 and
is 25 MHz in frequency.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).
TXCLK
TXEN
LPTX
TXD3
TXD2
XD1
TXD0
LPTX/(TXER)
Data presented on this input will be transmitted as a Link Pulse
of approximately the same duration.
In full duplex mode, COL is disabled and always remains low.
MII
LTCLK/(TXCLK)
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the ICS1890 with a frequency of 25 MHz.
LPRX
SD
Other mode configuration pins behave identically regardless
of which data interface is used.
42
ICS1890
MII Management Interface
Management Data Clock
MDC
The Management Data Clock (MDC) is used by the ICS1890
to synchronize the transfer of management information to or
from the ICS1890 using the serial MDIO data line.
The value and tolerance of this resistor is specified in the
Electricals section.
Management Data Input/Output
Frequency Reference
Clock Reference Interface
MDIO
The Management Data Input/Output (MDIO) is a tri-statable
line driven by station management to transfer command
information or driven by the ICS1890 to transfer status
information. All transfers and sampling are synchronous with
MDC. If the ICS1890 is to be used in an application which
uses the mechanical MII specification, MDIO must have a
1.5KΩ±5% pull-up at the ICS1890 end and a 2KΩ±5% pulldown at the station management end. This enables station
management to deter-mine if the connection is intact.
Twisted Pair Interface
Transmit Pair
(REF_IN & REF_OUT)
These pins connect to the 25 MHz crystal or the frequency
reference source.
When a frequency reference source like a crystal oscillator
module is used, its output should be connected to REF_IN
and REF_OUT should be left unconnected.
Configuration and Status Interface
Node/Repeater Mode
NOD/REP
When this input is logic zero, the device will default to Node
operation. SQE test will default to on for 10Base-T.
TP_TX+ & TP_TX-
The Transmit pair TP_TX+ and TP_TX- carries the serial bit
stream for transmission over the UTP cable. The currentdriven differential driver is programmed to produce two-level
(10Base-T, Manchester) or three-level (100Base-TX, MLT-3)
signals depending on the mode of operation selected (manually
or by Auto-Negotiation). These output signals interface directly
with an isolation transformer.
When this input is logic one, the device will default to Repeater
operation. SQE test will default to off and Carrier Sense will be
determined by receive activity only.
Note that these pins may be tristated using the TPTRI control
pin.
MII Data/Stream Interface Select
Receive Pair
This pin setting also affects which clock, TXCLK or REF_IN,
is used to latch the transmit data, TXD. See the description of
the ITCLS pin for the details.
MII/SI
This input pin selects the MAC to PHY interface to be used.
When the input is low the MII Data Interface is selected.
TP_RX+ & TP_RX-
The Receive pair TP_RX+ and TP_RX- carries the serial bit
stream from the mandatory isolation transformer. The serial bit
stream may be two-level (10Base-T, Manchester) or threelevel (100Base-TX, MLT-3) signals depending on the ICS
mode of operation
When this input is high, the “Stream” Interface is selected.
The “Stream” Interface that is used depends on the settings
of the 10/100SEL and 10/LP pins which allow selection of the
100M Stream Interface, 10M/Serial Interface, or Link Pulse
Interface.
10M Transmit Current Set Resistor
This input selects between the 10M Serial and Link Pulse
Interfaces when Stream Interface mode is selected with the
MII/SI pin. When this input is low and Stream Interface mode
is selected, the 10M Serial Interface is selected. When this
input is high and Stream Interface mode is selected, the Link
Pulse Interface is selected.
10M Serial/Link Pulse Interface Select
10TCSR
A resistor is required to be connected between this pin and
the nearest transmit ground to set the value of the transmit
current used in 10M mode.
The value and tolerance of this resistor is specified in the
Electricals section.
100M Transmit Current Set Resistor
100TCSR
A resistor is required to be connected between this pin and
the nearest transmit ground to set the value of the transmit
current used in 100M mode.
43
10/LP
ICS1890
Hardware/Software Priority Select
HW/SW
In SW mode, this pin is an output and correctly reflects the
selected duplex mode when the link is established (LSTA is
asserted). The output is low when Half Duplex is selected and
high when Full Duplex is selected which gives the same indication
as register bit (17:14).
When this pin is logic zero, hardware pins have priority over
software settings. The 10/100SEL pin becomes an input and
controls speed selection. The DPXSEL pin becomes an input
and controls duplex selection. The ANSEL pin becomes an
input and chooses configuration with or without Auto-Negotiation.
In Full Duplex mode, CRS is asserted only on receive activity.
In Full Duplex mode, COL is disabled and always remains low.
When configuration through Auto-Negotiation is selected,
the DPXSEL and 10/100SEL settings control the AutoNegotiation register 4 default settings and Auto-Negotiation
is enabled. When configuration without Auto-Negotiation is
selected DPXSEL controls the duplex setting and 10/100SEL
controls the data rate setting.
Auto-Negotiation Select
In HW mode, it is an input and controls the enabling of AutoNegotiation.When the input is low, Auto-Negotiation is disabled.
When the input is high, Auto-Negotiation is enabled and the
single technology selected by 10/100SEL and DPXSEL is
advertised.
When this pin is a logic one, software bits have priority over
hardware pin settings. The 10/100SEL pin becomes an output
indicating the link speed when the link is established and
parallels bit (17:15). The DPXSEL pin becomes an output
indicating the link duplex state when the link is established
and parallels bit (17:14). The ANSEL pin becomes an output
indicating whether auto-negotiation is being used and parallels
bit (0:12).
10/100 Select
In SW mode, this pin is an output and reflects whether AutoNegotiation has been enabled or disabled. The output is low
when Auto-Negotiation is disabled and high when AutoNegotiation is enabled which gives the same indication as
register bit (0:12).
10/100SEL
This pin is an input or an output depending on the setting of
the HW/SW pin.
Invert Transmit Clock Latching Setting ITCLS~
The ICS1890 allows transmit data to be latched relative to
either TXCLK or REF_IN. Latching the data to TXCLK is the
behavior specified in the 100Base-T MII specification, but in
some applications it is desirable to latch data with the REF_IN
clock. An example of where this might be beneficial is in a
repeater application where all data transmission on multiple
1890s need to be synchronized to a common clock.
In HW mode, it is an input and controls speed selection
directly or through Auto-Negotiation. When the input is low,
10Base-T is selected. When the input is high, 100Base-TX is
selected.
In SW mode, this pin is an output and correctly reflects the
selected speed when the link is established (LSTA is asserted).
The output is low when 10Base-T is selected and high when
100Base-TX is selected which gives the same indication as
register bit (17:15).
To select the proper setting of this pin, first choose the setting
of the NOD/REP pin. Then select the setting of the ITCLS pin
that latches the transmit data with the clock of your choice.
The following table shows the possible combinations. This
pin has an internal pull-up so it may be left not connected for
some applications.
Note this pin also affects the MAC - PHY interface that is used
in conjunction with the MII/SI pin.
Duplex Select
ANSEL
This pin is an input or output depending on the setting of the
HW/SW pin.
DPXSEL
This pin is an input or an output depending on the setting of
the HW/SW pin.
In HW mode, it is an input and controls duplex selection
directly or through Auto-Negotiation. When the input is low,
Half Duplex is selected. When the input is high, Full Duplex is
selected.
44
NOD/REP
ITCLS
Latching Clock
NOD
(0)
0
REF_IN
1
TXCLK
REP
(1)
0
TXCLK
1
REF_IN
ICS1890
TP_TXTristate
LED/PHY Address Usage
TPTRI
When this pin is set to a logic zero, the twisted pair transmitter
output pins will be enabled normally to source 100Base-TX or
10Base-T data.
The ICS1890 device uses a unique pin sharing scheme that
allows the 5 LED pins to also be used to set the PHY address.
At power-up and reset they define the MII PHY address of the
device. Subsequent to power-up and reset, they become LED
status indicators.
When this pin is set to a logic one, the twisted pair transmitter
output pins will be tristated.
MAC - PHY Receive Interface Tristate
The PHY address can be any number between 0 and 31. When
PHY address 0 is used, the device’s MII interface starts out
Isolated and must be enabled through the MII management
port (Reg 0 bit 10), as defined by the IEEE specification. All
other addresses leave the MII interface active.
RXTRI
When this input is a logic zero the selected MAC-PHY interface
behaves normally.
When this input is a logic one, the RXCLK, RXD[3:0], RXER,
and RXDV pins are tristated. This allows repeater designs to
bus the shared receive lines without requiring extra tristatable
buffers on each port.
The actual value used for the individual PHY address bits
depends on the configuration of the LED components. This is
shown in the figure below. When a “1” value is desired the
LED and resistor are connected between the LED pin and Vdd
(LED Pin X). When a “0” value is desired the LED and resistor
are connected between the LED pin and Ground (LED Pin Y).
The special driver will sense the polarity and adjust its drive
logic to appropriately turn the LED light on or off.
Note that the CRS and COL pins are not tristated. This allows
repeater logic to use these signals to determine which receive
port to enable.
Link Status
LSTA
This output reflects the current Link Status. It is similar to bit
(1:2) but changes dynamically instead of latching on a link
failure. The output is low when the link is invalid and is high
when a valid link has been established.
When this bit is high, the 10/100SEL and DPXSEL bits can be
observed to determine what type of link has been established.
Cipher Locked Status
LOCK
This output reflects the status of the Stream Cipher decoder
block. When the Stream Cipher has not locked onto the incoming
data stream, this output will be a logic zero. When the Stream
Cipher has locked onto the incoming data stream, this output
will be a logic one.
Resistor values should be in the range of 510Ω to 10kΩ. A
1kΩ resistor is recommended.
Note that the Stream Cipher will only lock onto 100Base-TX
data (or IDLE symbols) and will not lock when 10Base-T data
is present.
System Reset
If LEDs are not required for the application, only a resistor is
required to set the PHY address.
RESET~
If LEDs are not required for the application and the ICS1890
will not be accessed with the serial MII management interface,
then only a single resistor to VDD on any one of the LED pins
is required. This will ensure that the PHY address is not zero,
which would cause the ICS1890 to power up in the isolated
state with no way for management to enable the MII interface.
When grounded, this pin causes the ICS1890 to enter a reset/ low power state. On the low to high transition of RESET,
the device will begin to complete its reset cycle. Upon
comple-tion, the ICS1890 will be initialized its default state.
While this pin is held low, the device is kept in its low power
mode. Power savings and timings are shown in the Electricals
section.
45
ICS1890
Phy Address 4 - Receive Data LED
ICS1890 Power Supply Isolation and Filtering
P4RD
It is important to properly isolate the ICS1890 10/100BaseTX Physical Layer Device from noise sources in a system
design. There are two key areas to consider, isolation from
digital noise and noise coupling between the transmitter and
receiver.
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 16 is set in the
configuration register.
The ICS1890 sets this bit to the appropriate value to turn on
the LED when receive data is detected. This signal is stretched
ensure that a single packet will be seen. If the packet stream
is continuous, the LED will appear permanently on.
Phy Address 3 - Transmit Data LED
Filtering for the ICS1890 is accomplished by separating the
power supply into three domains: digital, transmit, and receive.
All supply pins on the device fall into one of these three
categories as shown in the table below.
P3TD
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 8 is set in the
configuration register.
In the above table, each supply pin is followed directly by its
ground pin. Each supply pair should be bypassed with a 0.1µF
capacitor located as close to the device as possible.
The ICS1890 sets this bit to the appropriate value to turn on
the LED when transmit data is detected. This signal is stretched
to ensure that a single packet will be seen. If the packet stream
is continuous, the LED will appear permanently on.
Phy Address 2 - Link Integrity LED
Digital Domain
41 VDD 8 VDD
40 VSS 7VSS
54
51
57
63
P2LI
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 4 is set in the
configuration register.
VDD
VSS
VDD
VSS
56 VDD
55 VSS
Receive Domain
16
18
17
25
29
VDD
VDD
VSS
VDD
VSS
The PCB board may have separate power and ground planes
for the ICS1890. The power planes could be split into three
domains following the pin isolation. A single, uniform plane
should be used for ground. Power plane placement is illustrated
in the figure below.
The ICS1890 sets this bit to the appropriate value to turn on
the LED when the Link Integrity status is OK.
Phy Address 1 - Collision LED
Transmit Domain
P1CL
Point-to-point trace routing for power connections may be
used instead of actual power “planes” if required by printed
circuit board constraints.
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 2 is set in the
configuration register.
The ICS1890 sets this bit to the appropriate value to turn on
the LED when a collision is detected. This signal is stretched
to ensure that a single collision will be seen. If the collisions
are continuous, the LED will appear permanently on.
Phy Address 0 - Activity LED
P0AC
At power-up and reset, this pin is sampled for a logic high or
zero. If a logic one is detected, a value of 1 is set in the
configuration register.
Both the Receive and Transmit Domains should be connected
to the Digital Domain or main supply through a ferrite bead or
inductor, with a value of .1µH to 1µH.The best filter configuration
is a pi filter composed of a .1µH capacitor, .1µH ferrite bead,
and a .1µH capacitor at the device pin.
The ICS1890 sets this bit to the appropriate value to turn on
the LED when either transmit or receive activity is detected.
This signal is stretched to ensure that a single activity event
will be seen. If the activity is continuous, the LED will appear
permanently on.
Reserved & N/C Pins
Four pins are labeled “Reserved” or “N/C.” These pins should
be left unconnected. Connecting these pins to ground or
power may prevent the device from operating properly
Power Supply
These 7 VDD and 8 VSS pins supply power to the ICS1890 device.
46
ICS1890
Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
NOD/REP
10/100SEL
10TCSR
100TCSR
TP_TX
TP_TXVSS
VDD
TPTRI
TP_RX+
TP_RXN/C
ITCLS~
N/C
N/C
VDD
VSS
VDD
MII/SI
REG
LSTA*
RESET~
HW/SW
DPXSEL
VDD
N/C
LOCK
10/LP
VSS
MDIO
MDC
RXD3*
I/O
I
I/O
I
I
O
O
TYPE
TTL-compatible
TTL-compatible
I
I
I
TTL-compatible
I
TTL-compatible
Description
Node/Repeater Mode
10/100 Select
10M Transmit Current Set Resistor
100M Transmit Current Set Resistor
Twisted Pair Transmit Data+
Twisted Pair Transmit DataDitigal Domain Power (Transmitter)
Twisted Pair Tristate
Twisted Pair Receive Data+
Twisted Pair Receive DataInvert Transmit Clock Latching Setting
Receive Domain Power (Receiver)
I
I
O
I
I
I/O
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
Receive Domain Power (Receiver)
MII Data/Stream Interface
Ground for high order register access
Link Status
System Reset
Hardware/Software Priority
Duplex Select
Receive Domain Power (RPLL)
O
I
TTL-compatible
TTL-compatible
Cipher Lock
10M Serial/Link Pulse Interface
I/O
I
O
TTL-compatible
TTL-compatible
TTL-compatible
Management Data Input/Output
Management Data Clock
Receive Data 3
* Redefined for other MAC-PHY interfaces.
47
ICS1890
Pin Descriptions
PIN
NUMBER
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN NAME
RXD2*
RXD1*
RXD0*
RXDV*
RXCLK*
RXER
RXTRI
VSS
VDD
TXER*
TXCLK*
TXEN*
TXD0*
TXD1*
TXD2*
TXD3*
COL*
CRS*
VSS
REF_OUT
REF_IN
VDD
VSS
VDD
VDD
P0AC
P1CL
P2LI
P3TD
P4RD
VSS
ANSEL
I/O
TYPE
DESCRIPTION
O
O
O
O
O
O
I
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Data 2
Data 1
Data 0
Data Valid
Clock
Error
MAC-PHY Interface Tristate
I
O
I
I
I
I
I
O
O
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
TTL-compatible
Digital Domain Power
Transmit Error
Transmit Error
Transmit Enable
Transmit Data 0
Transmit Data 1
Transmit Data 2
Transmit Data 3
Collision Detect
Carrier Sense
O
I
CMOS-compatible
Frequency Reference Output
Frequency Reference Input
Digital Domain Power
I/O
I/O
I/O
I/O
I/O
LED
LED
LED
LED
LED
Transmit Domain Power (TPLL)
Digital Domain Power
Special PHY ID 0/Activity LED
Special PHY ID 1/Collision det LED
Special PHY ID 2/Link Integrity LED
Special PHY ID 3/Transmit data LED
Special PHY ID 4/Receive data LED
I/O
TTL-compatible
Auto-Negotiation Select
* Redefined for other MAC-PHY interfaces.
48
ICS1890
Pin Configuration
49
ICS1890
Absolute Maximum Ratings
VDD (measured to VSS) . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Digital Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VDD+0.5V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Recommended Operating Conditions
PARAMETER
Ambient Operating Temp.
Power Supply
SYMBOL
TA
VSS
VDD
TEST CONDITIONS
MIN
0
0.0
+4.75
MAX
+70
0.0
+5.25
UNITS
°C
V
V
Recommended Component Values
PARAMETER
Crystal Oscillator Frequency*
Crystal Oscillator Frequency Tolerance
10TCSR Resistor Value
100TCSR Resistor Value
LED Resistor Value
MIN
TYP
25
-50
1.4
6.49
510
2.0
6.81
1000
MAX
+50
2.61
7.50
10,000
UNITS
MHz
ppm
KΩ
KΩ
Ω
* CMOS output drive recommended
Note: This matches the IEEE requirement in the 100Base-X standard definition for the code-bit-timer (24.2.3.4)
which is more stringent than the basic media independent interface (MII) specification for the TX_CLK of
±100ppm (22.2.2.1).
50
ICS1890
DC Characteristics
VDD = VMIN to VMAX, VSS = OV, TA = TMIN to TMAX
PARAMETER
IC Supply Current
SYMBOL
IDD
CONDITIONS
VDD=5.25V
MIN
-
MAX
195
CONDITIONS
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
VDD=5V, VSS=0V
MIN
2.0
2.4
3.68
8
-
UNITS
mA
TTL Input/Output
PARAMETER
TTL Input High Voltage
TTL Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
TTL Driving CMOS, Output High Voltage
TTL Driving CMOS, Output Low Voltage
TTL/CMOS Output Sink Current
TTL/CMOS Output Source Current
SYMBOL
VIH
VIL
VOH
VOL
VOH
VOL
IOL
IOH
MAX
0.8
0.4
0.4
-0.4
UNITS
V
V
V
V
V
V
mA
mA
REF_IN Input
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
VIL
CONDITIONS
VDD=5V, VSS=0V
VDD=5V, VSS=0V
MIN
3.5
-
MAX
1.5
UNITS
V
V
MAX
-
UNITS
pF
pF
Ohms
Note: REF_IN Input switch point is 50% of VDD.
PARAMETER (condition)
MII Input Pin Capacitance
MII Output Pin Capacitance
MII Output Pin Impedance
MIN
-
TYP
8
14
38
Note: Total system operating current will include load current required by the Tx transformer.
51
ICS1890
Clock - Reference In (REF_IN)
T#
t1
t2
PARAMETER (condition)
REF_IN Duty Cycle
REF_IN Period
MIN
45
-
Note: REF_IN switching point is 50% of VDD.
52
TYP
50
40
MAX
55
-
UNITS
%
ns
ICS1890
MII - Transmit Clock Tolerance
T#
t1
t2a
t2b
t2c
t2d
TXCLK
TXCLK
TXCLK
TXCLK
TXCLK
PARAMETER (condition)
Duty Cycle
Period (100Base-T/MII Interface)
Period (10Base-T/MII Interface)
Period (100Base-T/100M Stream Interface)
Period (10Base-T/10M Serial Interface)
MIN
35
-
TYP
50
40
400
40
100
MAX
65
-
UNITS
%
ns
ns
ns
ns
MIN
45
-
TYP
50
40
400
MAX
55
40
100
UNITS
%
ns
ns
ns
ns
-
-
65
ns
Note: TXCLK Duty Cycle = REF_IN Duty Cycle ±5%.
MII - Receive Clock Behavior
T#
t1
t2a
t2b
t2c
t2d
t4
PARAMETER (condition)
RXCLK Duty Cycle
RXCLK Period (100Base-T/MII Interface)
RXCLK Period (10Base-T/MII Interface)
RXCLK Period (100Base-T/100M Stream Interface)
RXCLK Period (10Base-T/10M Serial Interface)
RXDV Asserted Nominal Clock to Recovered Clock
Cycle Extension
53
ICS1890
MII/100M Stream - Synchronous Transmit Timing
T#
t1
t2
PARAMETER (condition)
TXD, TXEN, TXER Setup to TXCLK rise
TXD, TXEN, TXER Hold after TXCLK rise
MIN
10
0
TYP
-
MAX
-
UNITS
ns
ns
TYP
-
MAX
-
UNITS
ns
ns
Note: With ITCLS low (or in repeater mode) timing is with respect to REF_IN
MII/100M Stream - Synchronous Receive Timing
T#
t1
t2
PARAMETER (condition)
RXD, RXDV, RXER Setup to RXCLK rise
RXD, RXDV, RXER Hold after RXCLK rise
54
MIN
10.0
10.0
ICS1890
MII - Management Interface Timing
T#
t1
t2
t3
t4
t5
t6
t7
PARAMETER (condition)
MDC Minimum High Time
MDC Minimum Low Time
MDC Period
MDC rise to MDIO valid
MDIO Setup to MDC
MDIO Hold after MDC
Maximum allowable frequency (50pF Loading)
55
MIN
160
160
400
0
10
10
-
TYP
-
MAX
300
10
UNITS
ns
ns
ns
ns
ns
ns
MHz
ICS1890
Receive Latency (10M Serial)
T#
t1
PARAMETER (condition)
TP_RX input to 10RD delay
(10M Serial Interface)
MIN
TYP
MAX
UNITS
15
-
16.5
bits
MIN
TYP
MAX
UNITS
18
-
19.5
bits
Receive Latency (10M MII)
T#
t1
PARAMETER (condition)
1st bit of /5/ on TP_RX to /5/ on RXD
(10M MII)
56
ICS1890
Transmit Latency (10M Serial)
T#
t1
PARAMETER (condition)
10TD in to TP_TX out delay
(10M Serial Interface)
MIN
TYP
MAX
UNITS
-
1.5
-
bits
MIN
TYP
MAX
UNITS
-
1.5
-
bits
Transmit Latency (10M MII)
T#
t1
PARAMETER (condition)
TXD sampled to MDI Output of 1st bit
(10M MII)
57
ICS1890
Transmit Latency (MII/100M Stream)
T#
t1
t2
PARAMETER (condition)
TXEN sampled to MDI Output 1st bit of /J/ (MII IF)*
TXD sampled to MDI Output of 1st bit (100M Stream IF)
* Note that the IEEE maximum is 18 bits.
58
MIN
-
TYP
-
MAX
4BT
5
UNITS
bits
bits
ICS1890
MII - CarrierAssertion/De-assertion on Transmission
T#
t1
t2
PARAMETER (condition)
TXEN sampled to CRS assert
TXD sampled to CRS de-assert
MIN
0
0
TYP
-
MAX
4
4
UNITS
bits
bits
MAX
19BT
12.5
UNITS
bits
bits
MII - Receive Latency (MII/100M Stream)
T#
t1
t2
PARAMETER (condition)
1st bit of /J/ into TP_RX to /J/ on RXD (100M MII IF)
1st bit of /J/ into TP_RX to /J/ on RXD (100M Stream IF)
* Note that the IEEE maximum is 23 bits.
59
MIN
-
TYP
-
ICS1890
MDI Input to Carrier Assertion/De-assertion
T#
PARAMETER (condition)
MIN
TYP
MAX
UNITS
t1
1st bit of /J/ into TP_RX to CRS assert*
-
-
124ns/13BT
bits
t2
1st bit of /J/ into TP_RX while transmitting data to
COL assert (Half Duplex Mode)*
First bit of /T/ into TP_RX to CRS de-assert**
First bit of /T/ received into TP_RX to COL deassert (Half Duplex Mode)**
-
-
13
bits
-
-
130ns/13BT
bits
-
-
14
bits
t3
t4
* Note that the IEEE maximum is 20 bit times.
** Note that the IEEE minimum is 13 bit times and the maximum is 24 bit times.
60
ICS1890
Reset - Power on Reset
T#
t1
PARAMETER (condition)
VDD to 4.5V to Reset Complete
MIN
-
TYP
-
MAX
20
UNITS
µs
Reset - Hardware Reset & Power-down
T#
t1
t2
t3
PARAMETER (condition)
RESET active to device isolation and initialization
Minimum RESET pulse width
RESET released to device ready
61
MIN
80
-
TYP
-
MAX
200
640
UNITS
ns
ns
ns
ICS1890
10Base-T Heartbeat Timing
T#
t1
t2
PARAMETER (condition)
COL Heartbeat assertion delay from TXEN de-assertion
(10Base-T Half Duplex)
COL Heartbeat assertion duration (10Base-T Half Duplex)
MIN
TYP
MAX
UNITS
-
-
1210
ns
-
-
1170
ns
10Base-T Jabber Timing
T#
t1
t2
PARAMETER (condition)
Jabber activation time (10Base-T Half Duplex)
Jabber deactivation time (10Base-T Half Duplex)
62
MIN
-
TYP
26
410
MAX
-
UNITS
ms
ms
ICS1890
10Base-T Normal Link Pulse Timing
T#
t1
t2
PARAMETER (condition)
Normal Link Pulse Width (10Base-T)
COL Heartbeat assertion duration (10Base-T Half Duplex)
MIN
8
TYP
100
-
MAX
24
UNITS
ns
ms
MIN
55.5
111
8
17
TYP
100
62.5
125
2
16
-
MAX
69.5
139
24
33
UNITS
ns
µs
µs
ms
ms
pulses
Auto-Negotiation Fast Link Pulse Timing
T#
t1
t2
t3
t4
t5
t6
PARAMETER (condition)
Clock/Data pulse width
Clock pulse to Data pulse timing
Clock pulse to Clock pulse
FLP Burst width
FLP burst to FLP burst timing
Number of Clock/Data pulses in a burst
63
ICS1890
Clock Recovery
T#
t1
t2
t3
t4
PARAMETER (condition)
Ideal data recovery window
Actual data recovery window
Data recovery window truncation
SD assert to data acquired
MIN
6
0
-
64
TYP
-
MAX
8
8
1
100
UNITS
ns
ns
ns
ns
ICS1890
The following magnetics modules have been tested with the ICS1890
PHYceiver and have been found to perform acceptably.
Manufacture
Extra Choke Type
Without Extra Choke Type
Nano Pulse (NPI)
Pulse
Valor
Bell Fuse
Halo
Innet
Unicom
NP16120-30
PE-68517
ST6114
S558-5999-01
TG22-SO10ND
T0027S
2HT16-27
NP16170-30
PE-68515
STG118
S558-5999-00
TG22-SO20ND
T0019S
* Repeaters and Hubs are generally responsible for including a cable crossover. One way of doing this is to exchange
transmit (1 & 2) and receive (3 & 6) connections to the RJ-45.
** A minimum of 2KV capacitor should be used to make the connection to the chasis ground.
*** These are close starting values. These resistors need to be tailored to individual system insertion losses, these values
can go as low as 1KΩ. Average 10TCSR value (pin 3) is 1.91KΩ.
65
ICS1890
TQFP/MQFP Package
DIMENSION NAME
Full Package Height
Package Standoff
Package Thickness
Tip-to-Tip Width
Body Width
Tip-to-Tip Width
Body Width
Footlength
Lead Pitch
Lead Width w/Plate
Lead Height w/Plate
LEAD COUNT (N) 64L
BODY THICKNESS
FOOTPRINT (BODY+) Nominal
TOLERANCE TOLERANCE
DIMENSIONS
TQFP
MQFP
A
MAX.
MAX.
MAX.
MAX.
A1
±0.05
+0.10/-0.05
A2
D
BASIC
±0.25
BASIC
±0.10
D1
E
BASIC
±0.25
E1
BASIC
±0.10
L
±0.15
+0.10/-0.10
e
BASIC
BASIC
B
+0.08/-0.05
+0.10/-0.05
*
+0.04/-0.07
MAX.
TQFP
1.4
2.0
MQFP
2.7
3.20
1.60
0.15
1.4
16.0
14.0
16.0
14.0
0.60
0.80
0.37
0.16
3.00
0.25
2.7
17.20
14.00
17.20
14.00
0.88
0. 80
0.35
0.23
Dimensions in millimeters.
Ordering Information
ICS1890Y
ICS1890Y-14
Example:
ICS XXXX Y
Package Type
Y=MQFP Y-14=TQFP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
66
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.