LM25117/LM25117Q Wide Input Range Synchronous Buck Controller with Analog Current Monitor General Description Features The LM25117 is a synchronous buck controller intended for step-down regulator applications from a high voltage or widely varying input supply. The control method is based upon current mode control utilizing an emulated current ramp. Current mode control provides inherent line feed-forward, cycle-bycycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage applications. The operating frequency is programmable from 50 kHz to 750 kHz. The LM25117 drives external high-side and low-side NMOS power switches with adaptive dead-time control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions. A high voltage bias regulator that allows external bias supply further improves efficiency. The LM25117’s unique analog telemetry feature provides average output current information. Additional features include thermal shutdown, frequency synchronization, hiccup mode current limit and adjustable line under-voltage lockout. ■ LM25117Q is an Automotive Grade product that is AEC■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Q100 grade 1 qualified (-40°C to +125°C operating junction temperature) Emulated peak current mode control Wide operating range from 4.5V to 42V Robust 3.3A peak gate drives Adaptive dead-time output driver control Free-run or synchronizable clock up to 750kHz Optional diode emulation mode Programmable output from 0.8V Precision 1.5% voltage reference Analog current monitor Programmable current limit Hiccup mode over current protection Programmable soft-start and tracking Programmable line under-voltage lockout Programmable switch-over to external bias supply Thermal shutdown Packages ■ TSSOP-20EP (Thermally enhanced) ■ LLP-24 (4mmx4mm) Typical Application 30155001 © 2012 Texas Instruments Incorporated 301550 SNVS714D www.ti.com LM25117/LM25117Q Wide Input Range Synchronous Buck Controller with Analog Current Monitor April 10, 2012 LM25117/LM25117Q Connection Diagram 30155002 30155079 Top View LLP-24 (4mmx4mm) Top View 20-Lead TSSOP EP Ordering Information Order Number Package Type NSC Package Drawing Supplied As Feature AEC-Q100 Grade 1 qualified. Automotive Grade Production Flow* LM25117QPMH TSSOP-20EP MXA20A 73 Units Per Rail LM25117QPMHE TSSOP-20EP MXA20A 250 Units on Tape and Reel LM25117QPMHX TSSOP-20EP MXA20A 2500 Units on Tape and Reel LM25117QPSQ LLP-24 SQA24A 1000 Units on Tape and Reel LM25117QPSQE LLP-24 SQA24A 250 Units on Tape and Reel LM25117QPSQX LLP-24 SQA24A 4500 Units on Tape and Reel LM25117PMH TSSOP-20EP MXA20A 73 Units Per Rail LM25117PMHE TSSOP-20EP MXA20A 250 Units on Tape and Reel LM25117PMHX TSSOP-20EP MXA20A 2500 Units on Tape and Reel LM25117PSQ LLP-24 SQA24A 1000 Units on Tape and Reel LM25117PSQE LLP-24 SQA24A 250 Units on Tape and Reel LM25117PSQX LLP-24 SQA24A 4500 Units on Tape and Reel *Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive Grade products are identified with the letter Q. For more information, go to http://www.national.com/automotive. www.ti.com 2 TSSOP Pin LLP Pin Name Description 1 24 UVLO Under-voltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than 1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pin is allowed to ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20μA current source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors to provide hysteresis. 2 1 DEMB Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow (current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation is disabled allowing current to flow in either direction through the low-side NMOS. A 50kΩ pull-down resistor internal to the LM25117 holds DEMB pin low and enables diode emulation if the pin is left floating. 3 2 RES The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin determines the time the controller remains off before automatically restarting. The hiccup mode commences when the controller experiences 256 consecutive PWM cycles of cycle-by-cycle current limiting. After this occurs, an 10μA current source charges the RES pin capacitor to the 1.25V threshold and restarts LM25117. 4 3 SS An external capacitor and an internal 10μA current source set the ramp rate of the error amplifier reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or during thermal shutdown. 5 4 RT The internal oscillator is programmed with a single resistor between RT and the AGND. The recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor. 6 5 AGND 7 7 8 8 FB Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 0.8V. 9 9 COMP Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin. 10 10 CM Current monitor output. Average of the sensed inductor current is provided. Monitor directly between CM and AGND. CM should be left floating when the pin is not used. 11 11 RAMP PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin and the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP signal that emulates the AC component of the inductor with a slope proportional to input supply voltage. 12 12 CS 13 13 CSG Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current sense resistor. 14 14 PGND Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current sense resistor. 15 15 LO Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor through a short, low inductance path. 16 16 VCC Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible. 17 18 SW Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low inductance path. Analog ground. Return for the internal 0.8V voltage reference and analog circuits. VCCDIS Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator is disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC regulator when the pin is left floating. The internal 500kΩ pull-down resistor can be overridden by pulling VCCDIS above 1.25V with a resistor divider connected to an external bias supply. Current sense amplifier input. Connect to the high-side of the current sense resistor. 3 www.ti.com LM25117/LM25117Q Pin Descriptions LM25117/LM25117Q TSSOP Pin LLP Pin Name 18 19 HO High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor through a short, low inductance path. 19 20 HB High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side NMOS gate and should be placed as close to controller as possible. 20 22 VIN Supply voltage input source for the VCC regulator. EP EP EP Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to reduce thermal resistance. 6 NC No electrical contact. 17 NC No electrical contact. 21 NC No electrical contact. 23 NC No electrical contact. www.ti.com Description 4 VIN to AGND SW to AGND HB to SW VCC to AGND (Note 2) HO to SW LO to AGND FB, DEMB, RES, VCCDIS, UVLO to AGND CM, COMP to AGND(Note 3) -0.3 to 45V -3.0 to 45V -0.3 to 15V -0.3 to 15V -0.3 to HB+0.3V -0.3 to VCC+0.3V -0.3 to 15V -0.3 to 7V -0.3 to 0.3V 2kV -55°C to +150°C +150°C Operating Ratings (Note 1) VIN (Note 5) VCC HB to SW Junction Temperature -0.3 to 7V 4.5V to 42V 4.5V to 14V 4.5V to 14V -40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VVIN = 24V, VVCCDIS = 0V, RT = 25kΩ, no load on LO & HO. Symbol Parameter Conditions VIN Operating Current (Note 6) Min Typ Max Units VSS = 0V 4.8 6.2 mA VSS = 0V, VVCCDIS = 2V 0.4 0.55 mA VSS = 0V, VUVLO = 0V 16 40 µA 7.6 8.2 V VIN Supply IBIAS ISHUTDOWN VIN Shutdown Current VCC Regulator VCC(REG) IVCC VCC Regulation No Load VCC Dropout (VIN to VCC) VVIN = 4.5V, No external load 0.05 0.14 V VVIN = 5.0V, ICC = 20mA 0.4 0.5 V 6.85 VCC Sourcing Current Limit VVCC = 0V VCC Operating Current (Note 6) VSS = 0V, VVCCDIS = 2V 30 VSS = 0V, VVCCDIS = 2V, VVCC = 14V VCC Under-voltage Threshold VCC Rising 42 4.0 3.75 VCC Under-voltage Hysteresis mA 5.0 mA 5.8 7.3 mA 4.0 4.15 V 0.2 V VCC Disable VCCDIS Threshold VCCDIS Rising 1.22 VCCDIS Hysteresis VCCDIS Input Current 1.25 1.29 0.06 VVCCDIS = 0V VCCDIS Pull-down Resistance V V -20 nA 500 kΩ UVLO UVLO Threshold UVLO Rising 1.22 1.25 1.29 V UVLO Hysteresis Current VUVLO = 1.4V 15 20 25 µA UVLO Shutdown Threshold UVLO Falling 0.23 0.3 V 0.1 V UVLO Shutdown Hysteresis Soft Start ISS SS Current Source VSS = 0V 7 SS Pull-down Resistance 10 12 µA 13 24 Ω 800 812 mV Error Amplifier VREF FB Reference Voltage Measured at FB, FB = COMP FB Input Bias Current VFB = 0.8V VOH COMP Output High Voltage ISOURCE = 3mA VOL COMP Output Low Voltage ISINK = 3mA AOL DC Gain 80 dB fBW Unity Gain Bandwidth 3 MHz 788 1 nA V 2.8 0.26 V PWM Comparator tHO(OFF) Forced HO Off-time 260 5 320 440 ns www.ti.com LM25117/LM25117Q SS, RAMP, RT to AGND CS, CSG, PGND, to AGND ESD Rating HBM (Note 4) Storage Temperature Junction Temperature Absolute Maximum Ratings (Note 1) LM25117/LM25117Q Symbol Parameter Conditions tON(MIN) Minimum HO On-time VVIN = 42V Min COMP to PWM comparator offset Typ Max Units 100 ns 1.2 V Oscillator fSW1 Frequency 1 RT = 25kΩ 180 fSW2 Frequency 2 RT = 10kΩ 430 RT Output Voltage 200 220 kHz 480 530 kHz 1.25 RT Sync Positive Threshold 2.6 Sync Pulse Width 100 3.2 V 3.95 V ns Current Limit VCS(TH) Cycle-by-cycle Sense Voltage Threshold VRAMP = 0, CSG to CS 106 120 CS Input Bias Current VCS = 0V -100 -66 µA CSG Input Bias Current VCSG = 0V -100 -66 µA 135 mV Current Sense Amplifier Gain 10 V/V Hiccup Mode Fault Timer 256 Cycles RES IRES RES Current Source VRES RES Threshold 10 RES Rising 1.22 µA 1.25 1.285 V 2.0 1.65 V Diode Emulation VIL DEMB Input Low Threshold VIH DEMB Input High Threshold 2.5 V SW Zero Cross Threshold -5 mV DEMB Input Pull-down Resistance 50 kΩ 2.95 Current Monitor Current Monitor Amplifier Gain CS to CM Current Monitor Amplifier Gain Drift over Temperature 17.5 20.5 23.5 V/V -2 0 +2 % 25 120 mV V Zero Input Offset HO Gate Driver VOHH HO High-state Voltage Drop IHO = –100mA, VOHH = VHB - VHO 0.17 0.3 VOLH HO Low-state Voltage Drop IHO = 100mA, VOLH = VHO - VSW 0.1 0.2 HO Rise Time C-load = 1000pF (Note 7) V 6 ns HO Fall Time C-load = 1000pF (Note 7) 5 ns IOHH Peak HO Source Current VHO = 0V, SW = 0V, HB = 7.6V 2.2 A IOLH Peak HO Sink Current VHO = VHB = 7.6V 3.3 A HB to SW Under-voltage HB DC Bias Current 2.56 HB - SW = 7.6V 2.9 3.32 V 65 100 µA LO Gate Driver VOHL LO High-state Voltage Drop ILO = –100mA, VOHL = VCC-VLO 0.17 0.27 V VOLL LO Low-state Voltage Drop ILO = 100mA, VOLL = VLO 0.1 0.2 V LO Rise Time C-load = 1000pF (Note 7) 6 ns LO Fall Time C-load = 1000pF (Note 7) 5 ns IOHL Peak LO Source Current VLO = 0V 2.5 A IOLL Peak LO Sink Current VLO = 7.6V 3.3 A LO Fall to HO Rise Delay No load 72 ns HO Fall to LO Rise Delay No load 71 ns Thermal Shutdown Temperature Rising 165 °C 25 °C Switching Characteristics TDLH Thermal TSD Thermal Shutdown Hysteresis www.ti.com 6 Parameter Conditions Min Typ Max Units θJA Junction to Ambient TSSOP-20EP 40 °C/W θJC Junction to Case TSSOP-20EP 4 °C/W θJA Junction to Ambient LLP-24 (4mmx4mm) 40 °C/W θJC Junction to Case LLP-24 (4mmx4mm) 6 °C/W Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics Table. Note 2: See Application Information when input supply voltage is less than the VCC voltage. Note 3: These pins are output pins. As such they are not specified to have an external voltage applied. Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 5: Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. Note 6: Operating current does not include the current into the RT resistor. Note 7: High and low reference are 80% and 20% of the pulse amplitude respectively. 7 www.ti.com LM25117/LM25117Q Symbol LM25117/LM25117Q Typical Performance Characteristics HO Peak Driver Current vs Output Voltage LO Peak Driver Current vs Output Voltage 30155003 30155004 Driver Dead Time vs VVCC Driver Dead Time vs Temperature 30155006 30155005 Forced HO Off-time vs Temperature Switching Frequency vs RT 30155007 www.ti.com 30155008 8 LM25117/LM25117Q VVCC vs IVCC VVCC vs VVIN 30155009 30155069 VCS(TH) vs Temperature VREF vs Temperature 30155070 30155071 VVCC vs Temperature Error Amp Gain and Phase vs Frequency 301550162 30155073 9 www.ti.com LM25117/LM25117Q VCM vs IOUT VCM vs VCSG-CS 30155072 www.ti.com 30155078 10 LM25117/LM25117Q Block Diagram and Typical Application Circuit 30155010 FIGURE 1. Block Diagram and Typical Application Circuit 11 www.ti.com LM25117/LM25117Q externally supplied bias should be coupled to the VCC pin through a diode, preferably a Schottky diode. If the VCCDIS pin voltage exceeds the VCCDIS threshold, the internal VCC regulator is disabled. VCCDIS has a 500kΩ internal pull-down resistor to ground for normal operation with no external bias. The VCC regulator series pass transistor includes a diode between VCC (Anode) and VIN (Cathode) that should not be forward biased in normal operation. If the voltage of the external bias supply is greater than the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply through VCC. Functional Description The LM25117 high voltage switching controller features all of the functions necessary to implement an efficient high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode control utilizing an emulated current ramp. Peak current mode control provides inherent line feed-forward, cycle-by-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the PWM circuit, allowing reliable processing of the very small duty cycles necessary in high input voltage applications. The switching frequency is user programmable up to 750 kHz. The RT pin allows the switching frequency to be programmed by a single resistor or synchronized to an external clock. Fault protection features include cycle-by-cycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down UVLO pin. The UVLO input enables the regulator when the input voltage reaches a user selected threshold and provides a very low quiescent shutdown current when pulled low. A unique analog telemetry feature provides averaged output current information, allowing various applications that need either a current monitor or current control. The functional block diagram and typical application circuit of the LM25117 are shown in Figure 1 The device is available in TSSOP-20EP and LLP24 package featuring an exposed pad to aid in thermal dissipation. 30155011 FIGURE 2. VIN Configuration for VVIN<VVCC For VOUT between 5V and 14.5V, the output can be connected directly to VCC through a diode. High Voltage Startup Regulator and VCC Disable The LM25117 contains an internal high voltage bias regulator that provides the VCC bias supply for the PWM controller and NMOS gate drivers. The VIN pin can be connected to an input voltage source as high as 42V. The output of the VCC regulator is set to 7.6V. When the input voltage is below the VCC set-point level, the VCC output tracks the VIN with a small dropout voltage. The output of the VCC regulator is current limited at 30mA minimum. Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. The recommended capacitance range for the pin VCC is 0.47µF to 10µF. When the VCC pin voltage exceeds the VCC UV threshold and the UVLO pin is greater than UVLO threshold, the HO and LO drivers are enabled and a soft-start sequence begins. The HO and LO drivers remain enabled until either the VCC pin voltage falls below VCC UV threshold, the UVLO pin voltage falls below UVLO threshold, hiccup mode is activated or the die temperature exceeds the thermal shutdown threshold. Enabling/ Disabling the IC by controlling UVLO is recommended in most of cases. An output voltage derived bias supply can be applied to the VCC pin to reduce the controller power dissipation at higher input voltage. The VCCDIS input can be used to disable the internal VCC regulator when external biasing is supplied. The www.ti.com 30155012 FIGURE 3. External VCC Supply for 5V< VOUT<14.5V For VOUT < 5V, a bias winding on the output inductor can be added to generate the external VCC supply voltage. 30155057 FIGURE 4. External VCC Supply for VOUT <5V 12 30155059 FIGURE 5. External VCC Supply for 14.5V <VOUT In high input voltage applications, extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 45V. During line or load transients, voltage ringing on the VIN that exceeds the Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass capacitors located close to the VIN and AGND pin are essential. Adding an R-C filter (RVIN, CVIN) on VIN is optional and helps to prevent faulty operation caused by poor PC board layout and high frequency switching noise injection. The recommended capacitance and resistance range are 0.1µF to 10µF and 1Ω to 10Ω. (1) (2) UVLO Where VHYS is the desired UVLO hysteresis and VIN(STARTUP) is the desired startup voltage of the regulator during turn-on. The LM25117 contains a dual level UVLO (under-voltage lockout) circuit. When the UVLO is less than 0.4V, the LM25117 is in shutdown mode. The shutdown comparator provides 100mV of hysteresis to avoid chatter during transitions. When the UVLO pin voltage is greater than 0.4V but less than 1.25V, the controller is in standby mode. In the standby mode, the VCC bias regulator is active but the HO and LO drivers are disabled and the SS pin is held low. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO pin down below 0.4V with an external open collector or open drain device. When the VCC pin exceeds its under-voltage lockout threshold and the UVLO pin voltage is greater than 1.25V, the HO and LO drivers are enabled and normal operation begins. Oscillator and Sync Capability The LM25117 switching frequency is programmed by a single external resistor connected between the RT pin and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and AGND pins. To set a desired switching frequency (fSW), the resistor value can be calculated from the following equation: (3) The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25V and the voltage at the RT pin must exceed the RT Sync Positive Threshold to trip the internal synchronization pulse detector. A 5V amplitude pulse signal coupled through 100pF capacitor is a good starting point. The frequency of the external synchronization pulse is recommended to be within +/-10% of the frequency programmed by the RT resistor but will operate to +100/-40% of the programmed frequency. Care should be taken to guarantee that the RT pin voltage does not go below -0.3V at the falling edge of the external pulse. This may limit the duty cycle of external synchronization pulse. The RT resistor is always required, whether the oscillator is free running or externally synchronized. 30155068 FIGURE 6. UVLO Configuration The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is used to set 13 www.ti.com LM25117/LM25117Q the minimum input operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.25V and never exceeds 15V when the input voltage is in the desired operating range. If necessary, the UVLO pin can be clamped with a Zener diode. UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the impedance of the UVLO set-point divider. When the UVLO pin voltage exceeds the 1.25V threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. The use of a CFT capacitor in parallel with RUV1 helps to minimize switching noise injection into UVLO pin, but it may slow down the falling speed of the UVLO pin when the 20μA current source is disabled. The recommended range for CFT is 10pF to 220pF. The values of RUV1 and RUV2 can be determined from the following equations: For 14.5V <VOUT, the external supply voltage can be regulated by using a series Zener diode from the output to VCC. LM25117/LM25117Q Ramp Generator and Emulated Current Sense The ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly from the high-side switch current. This switch current corresponds to the positive slope portion of the inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the high-side switch current signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Minimum achievable pulse width is limited by the filtering, blanking time and propagation delay with a high-side current sensing scheme. In the applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation. The LM25117 utilizes a unique ramp generator which does not actually measure the high-side switch current but rather reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays, while maintaining the advantages of traditional peak current mode control. The current reconstruction is comprised of two elements: a sample-and-hold DC level and the emulated inductor current ramp as shown in Figure 7. The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the high-side switch. The current sense amplifier with a gain of 10 and sample-and-hold circuit provide the DC level of the reconstructed current signal as shown in Figure 8. 30155013 FIGURE 8. RAMP Generator and Current Limit Circuit The positive slope inductor current ramp is emulated by CRAMP connected between RAMP and AGND and RRAMP connected between SW and RAMP. RRAMP should not be connected to VIN directly because the RAMP pin absolute maximum voltage rating could be exceeded under high input voltage conditions. CRAMP is discharged by an internal switch during the off-time and must be fully discharged during the minimum off-time. This limits the ramp capacitor to be less than 2nF. A good quality, thermally stable ceramic capacitor is recommended for CRAMP. The selection of RRAMP and CRAMP can be simplified by adopting a K factor, which is defined as: (4) Where AS is the current sense amplifier gain which is normally 10. By choosing 1 as the K factor, the regulator removes any error after one switching cycle and the design procedure is simplified. See Application Information for detailed information. Error Amplifier and PWM Comparator The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin voltage and the internal precision 0.8V reference. The output of error amplifier is connected to the COMP pin allowing the user to provide Type 2 loop compensation components, RCOMP, CCOMP and optional CHF. 30155016 FIGURE 7. Composition of Emulated Current Sense Signal 30155017 FIGURE 9. Feedback Configuration and PWM Comparator www.ti.com 14 Soft-Start The soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing startup stresses and surges. The LM25117 regulates the FB pin to the SS pin voltage or the internal 0.8V reference, whichever is lower. The internal 10µA soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage. Soft-start time (tss) can be calculated from the following equation: (5) (6) (8) The LM25117 can track the output of a master power supply during soft-start by connecting a voltage divider from the output of master power supply to the SS pin. At the beginning of the soft-start sequence, VSS should be allowed to go below 25mV by the internal SS pull-down switch. During soft-start period, when SS pin voltage is less than 0.8V, the LM25117 forces diode emulation for startup into a pre-biased load. If the tracking feature is desired, connect the DEMB pin to GND or leave the pin floating. (7) The PWM comparator compares the emulated current sense signal from Ramp Generator to the voltage at the COMP pin through a 1.2V internal voltage drop and terminates the present cycle when the emulated current sense signal is greater than VCOMP - 1.2V. Diode Emulation A fully synchronous buck regulator implemented with a freewheeling NMOS rather than a diode has the capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup. The LM25117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the low-side NMOS device. When configured for diode emulation, the low-side NMOS driver is disabled when SW pin voltage is greater than -5mV during the off-time of the high-side NMOS driver, preventing reverse current flow. A benefit of the diode emulation is lower power loss at no load or light load conditions. The negative effect of diode emulation is degraded light load transient response. The diode emulation feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin to GND or leave the pin floating. If continuous conduction operation is desired, the DEMB pin should be tied to a voltage greater than 3V and may be connected to VCC. The LM25117 forces the regulator to operate in diode emulation mode when SS pin voltage is less than the internal 0.8V reference, allowing for startup into a pre-biased load with the continuous conduction configuration. Cycle-by-Cycle Current Limit The LM25117 contains a current limit monitoring scheme to protect the regulator from possible over-current conditions as shown in Figure 8. If the emulated ramp signal exceeds 1.2V, the present cycle is terminated. For the case where the switch current overshoots when the inductor is saturated or the output is shorted to ground, the sample-and-hold circuit detects the excess recirculating current before the high-side NMOS driver is turned on again. The high-side NMOS driver is disabled and will skip pulses until the current has decayed below the current limit threshold. This approach prevents current runaway conditions since the inductor current is forced to decay to a controlled level following any current overshoot. Maximum peak inductor current can be calculated as: (9) (10) Where IPP represents inductor peak to peak ripple current in Figure 10, and is defined as: (11) 15 www.ti.com LM25117/LM25117Q RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage loop gain. This network creates a pole at DC (FP1), a mid-band zero (FZ) for phase boost, and a high frequency pole (FP2). The recommended range of RCOMP is 2kΩ to 40kΩ. See Application Information for detailed information. LM25117/LM25117Q 30155015 FIGURE 10. Inductor Current During an output short condition, the worst case peak inductor current is limited to: 30155018 FIGURE 11. Hiccup Mode Current Limit Timing Diagram (12) Where tON(MIN) is the minimum HO on-time. In most of cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating inductor such as a powder core device is used. If a sharp-saturating inductor is used, the inductor saturation level must be above ILIM_PK. The temperatures of the NMOS devices, RS and inductor should be checked under this output short condition. Hiccup Mode Current Limiting To further protect the regulator during prolonged current limit conditions, LM25117 provides a hiccup mode current limit. An internal hiccup mode fault timer counts the PWM clock cycles during which cycle-by-cycle current limiting occurs. When the hiccup mode fault timer detects 256 consecutive cycles of current limiting, an internal restart timer forces the controller to enter a low power dissipation standby mode and starts sourcing 10μA current into the RES pin capacitor CRES. In this standby mode, HO and LO outputs are disabled and the softstart capacitor CSS is discharged. CRES is connected from RES pin to AGND and determines the time (tRES) in which the LM25117 remains in the standby before automatically restarting. When the RES pin voltage exceeds the 1.25V RES threshold, RES capacitor is discharged and a soft-start sequence begins. tRES can be calculated from the following equation: 30155019 FIGURE 12. Hiccup Mode Current Limit Circuit The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current limiting. If the RES pin is tied to VCC or a voltage greater than the RES threshold at initial power-on, the restart timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. If the RES pin is tied to GND, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then never restarts until UVLO shutdown is cycled. The restart timer is configured during initial power-on when UVLO is above the UVLO threshold and VCC is above the VCC UV threshold. (13) 30155020 FIGURE 13. RES Configurations www.ti.com 16 The LM25117 contains high current NMOS drivers and an associated high-side level shifter to drive the external highside NMOS device. This high-side gate driver works in conjunction with an external diode DHB, and bootstrap capacitor CHB. A 0.1μF or larger ceramic capacitor, connected with short traces between the HB and SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately 0V and the CHB is charged from VCC through the DHB. When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged. The LO and HO outputs are controlled with an adaptive deadtime methodology which insures that both outputs are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device, especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate resister, RGH or RGL, may decrease the effective dead-time. Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input voltages, the lowside NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the high-side NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor is above the VCC regulation level. (14) The current monitor output is only valid in continuous conduction operation. The current monitor has a limited bandwidth of approximately one tenth of fSW. Adding an R-C filter, RCM and CCM, on the output of current monitor with the cut off frequency below one tenth of fSW is recommended to attenuate sampling noise. Maximum Duty Cycle When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged and to allow time to sample and hold the current in the low-side NMOS FET. This forced off-time limits the maximum duty cycle of the controller. When designing a regulator with high switching frequency and high duty cycle requirements, a check should be made of the required maximum duty cycle against the graph shown in Figure 15. The actual maximum duty cycle varies with the switching frequency as follows: 30155014 FIGURE 15. Maximum Duty Cycle vs Switching Frequency Current Monitor Thermal Protection The LM25117 provides average output current information, enabling various applications requiring monitoring or control of the output current. Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power shutdown mode, disabling the output drivers and the VCC regulator. This feature is designed to prevent overheating and destroying the device. 30155080 FIGURE 14. Current Monitor 17 www.ti.com LM25117/LM25117Q The average of CM output can be calculated by: HO and LO Drivers LM25117/LM25117Q The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since the addition of CHF adds a pole in the feedback transfer function. The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the fSW. In a simplified formula, the crossover frequency can be defined as: Application Information FEEDBACK COMPENSATION Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain. The modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in equation (15). (17) (15) For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. The sampled gain inductor pole is inversely proportional to the K factor, which is defined as: (18) The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM25117’s unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. This frees the user from additional concerns in wide varying input range applications and is an advantage of the LM25117. If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. If a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response. If the ESR of COUT (RESR) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in equation (16). (16) www.ti.com 18 (20) The relationship between Q and K factor is illustrated graphically in Figure 18. 30155081 30155077 FIGURE 16. Effect of Initial Perturbation when dl1/dl0 < -1 FIGURE 18. Sampling gain Q vs K Factor dI1/dI0 can be calculated by: The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at FSW/2. When K=1, one-cycle damping is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency equation in Table 1. (19) The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 17. PC BOARD LAYOUT RECOMMENDATION In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic operation. High quality input capacitors should be placed as close as possible to the NMOS power switches, with the VIN side of the capacitor connected directly to the high-side NMOS drain and the ground side of the capacitor connected as close as possible to the current sense resistor ground connection. Connect all of the low power ground connections (RUV1, RT, RFB1, CSS, CRES, CCM, CVIN, CRAMP) directly to the regulator AGND pin. Connect CVCC directly to the regulator PGND pin. Note that CVIN and CVCC must be as physically close as possible to the IC. AGND and PGND must be directly connected together through a top-side copper pattern connected to the exposed pad. Ensure no high current flows beneath the underside exposed pad. 30155076 FIGURE 17. dl1/dl0 vs K Factor The minimum value of K is 0.5. When K<0.5, the amplitude of dI1 is greater than the amplitude of dI0 and any initial per19 www.ti.com LM25117/LM25117Q turbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be under-damped. Any perturbation will be over-damped when 0<dl1/dl0<1. In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as: SUB-HARMONIC OSCILLATION Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 7. By choosing K≥1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage. In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI1, caused by an initial perturbation, dI0, is less than the magnitude of dI0 or dI1/dI0 > -1, the perturbation naturally disappears after a few cycles. When dI1/dI0 < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steadystate operation. LM25117/LM25117Q The LM25117 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the IC. The junction to ambient thermal resistance varies with application. The most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and the amount of forced air www.ti.com cooling. The integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating components are the two power switches. Selecting NMOS switches with exposed pads aids the power dissipation of these devices. 20 LM25117/LM25117Q TABLE 1. LM25117 Frequency Analysis Formulas SIMPLE FORMULA COMPREHENSIVE FORMULA* MODULATOR TRANSFER FUNCTION Modulator DC Gain ESR Zero ESR Pole Not considered Dominant Load Pole Sampled Gain Inductor Pole Not considered Quality Factor Not considered Sub-harmonic Double Pole Not considered K Factor FEEDBACK TRANSFER FUNCTION Feedback DC Gain Mid-band Gain Low Frequency Zero High Frequency Pole OPEN-LOOP RESPONSE 21 www.ti.com LM25117/LM25117Q SIMPLE FORMULA COMPREHENSIVE FORMULA* Cross Over Frequency (Open Loop Bandwidth) Maximum Cross Over Frequency The frequency at which 45° phase shift occurs in modulator phase characteristics. * Comprehensive Equation includes an inductor pole and a gain peaking at fSW/2, which caused by sampling effect of the current mode control. Also it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1 . www.ti.com 22 OPERATING CONDITIONS • Output Voltage • Full Load Current • Minimum Input Voltage • Maximum Input Voltage • Switching Frequency • Diode Emulation • External VCC Supply VOUT = 3.3V IOUT = 9A VIN(MIN) = 6V VIN(MAX) = 36V fSW = 230kHz Yes No TIMING RESISTOR RT Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of RT for 230 kHz switching frequency can be calculated from the equation (3) as follows: A value of 8mΩ was chosen for RS. A larger value resistor can be placed in parallel with RS to adjust the maximum output current capability. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the low-side NMOS for the majority of the PWM cycle. The maximum power dissipation of RS can be calculated as: A standard value of 22.1kΩ was chosen for RT. OUTPUT INDUCTOR LO The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple current of 20% of 9A was chosen. Knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows: The worst case peak inductor current under the output short condition can be calculated from the equation (12) as follows: Where tON(MIN) is normally 100ns. The closest standard value of 6.8μH was chosen for LO. Using the value of 6.8μH for LO, calculate IPP again. This step is necessary if the chosen value of LO differs significantly from the calculated value. From the equation (11), CURRENT SENSE FILTER RCS and CCS The LM25117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not used Adding RCS resistor changes the current sense amplifier gain which is defined as AS=10k / (1k+RCS). A small value of RCS resistor below 100Ω is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors. At the minimum input voltage, this value is 0.95A. DIODE EMULATION FUNCTION The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions. RAMP RESISTOR RRAMP and RAMP CAPACITOR CRAMP The positive slope of the inductor current ramp signal is emulated by RRAMP and CRAMP. For this example, the value of CRAMP was set at the standard capacitor value of 820pF. With the inductor, sense resistor and the K factor selected, the val- 23 www.ti.com LM25117/LM25117Q CURRENT SENSE RESISTOR RS The performance of the converter will vary depending on the K value. For this example, K=1 was chosen to control subharmonic oscillation and achieve one-cycle damping. The maximum output current capability (IOUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 150% of 9A was chosen. The current sense resistor value can be calculated from the equation (9), (10) as follows: Design Example LM25117/LM25117Q ue of RRAMP can be calculated from the equation (4) as follows: (PSW) occurs during the brief transition period as the high-side NMOS device turns on and off. During the transition period both current and voltage are present in the channel of the NMOS device. The switching loss can be approximated as: tR and tF are the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this example, the maximum drain-tosource voltage applied to either NMOS device is 36V. The selected NMOS devices must be able to withstand 36V plus any ringing from drain to source and must be able to handle at least the VCC voltage plus any ringing from gate to source. The standard value of 105 kΩ was selected for RRAMP. UVLO DIVIDER RUV2, RUV1 AND CFT The desired startup voltage and the hysteresis are set by the voltage divider RUV1 and RUV2. Capacitor CFT provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below VIN(MIN). VHYS was set to 1V. The value of RUV1, RUV2 can be calculated from equations (1) and (2) as follows: SNUBBER COMPONENTS RSNB AND CSNB A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50Ω. Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout. The standard value of 50kΩ was selected for RUV2. RUV1 was selected to be 14kΩ. A value of 100pF was chosen for CFT. VCC DISABLE AND EXTERNAL VCC SUPPLY In this example, VCCDIS is left floating to enable the internal VCC regulator. BOOTSTRAP CAPACITOR CHB AND BOOTSTRAP DIODE DHB The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1μF. CHB should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated as: POWER SWITCHES QH and QL Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging loss, and switching loss. Conduction loss PDC is approximately: Where D is the duty cycle and the factor of 1.3 accounts for the increase in the NMOS device on-resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS device can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss (PGC) results from the current driving the gate capacitance of the power NMOS devices and is approximated as: Where Qg is the high-side NMOS gate charge and ΔVHB is the tolerable voltage droop on CHB, which is typically less than 5% of VCC or 0.15V conservatively. A value of 0.47μF was selected for this design. VCC CAPACITOR CVCC The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The recommended value of CVCC should be no smaller than 0.47μF, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed at the pins of the IC to minimize potentially dam- Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC. Switching loss www.ti.com 24 jection into the VIN pin. 0.47μF ceramic capacitor is used for CVIN in the example. OUTPUT CAPACITOR CO The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 680μF electrolytic capacitor with maximum 10mΩ ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage with maximum ESR is approximated as: SOFT-START CAPACITOR CSS The capacitor at the SS pin (CSS) determines the soft-start time (tSS), which is the time for the output voltage to reach the final regulated value. The tSS for a given CSS can be calculated from equation (8) as follows: For this example, a value of 0.047μF was chosen for a softstart time of 3.8ms. RESTART CAPACITOR CRES The capacitor at the RES pin (CRES) determines tRES, which is the time the LM25117 remains off before a restart attempt is made in hiccup mode current limiting. tRES for a given CRES can be calculated from equation (13) as follows: Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added. For this example, a value of 0.47μF was chosen for a restart time of 59ms. INPUT CAPACITOR CIN The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the ontime. When the high-side NMOS device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2. In this example, seven 2.2μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will be triangular. The input ripple voltage can be approximated as: OUTPUT VOLTAGE DIVIDER RFB2 and RFB1 RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as: The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation small. 3.24kΩ was chosen for RFB2 in this example, which results in a RFB1 value of 1.05kΩ for 3.3V output. LOOP COMPENSATION COMPONENTS CCOMP, RCOMP and CHF RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below. For detailed information, see Application Information. STEP1: Select fCROSS By selecting one tenth of the switching frequency, fCROSS is calculated as follows: Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency. VIN FILTER RVIN, CVIN An R-C filter (RVIN, CVIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching noise in- 25 www.ti.com LM25117/LM25117Q aging voltage transients caused by trace inductance. A value of 1μF was selected for this design. LM25117/LM25117Q The standard value of 10nF was selected for CCOMP STEP4: Determine CHF to cancel ESR zero Knowing RCOMP and CCOMP, CHF is calculated as follows: STEP2: Determine required RCOMP Knowing fCROSS, RCOMP is calculated as follows: The standard value of 27.4kΩ was selected for RCOMP STEP3: Determine CCOMP to cancel load pole Knowing RCOMP, CCOMP is calculated as follows: Half of the maximum ESR is assumed as a typical ESR. The standard value of 150pF was selected for CHF. www.ti.com 26 LM25117/LM25117Q Application Circuit 30155021 FIGURE 19. 3.3V, 9A Typical Application Schematic 27 www.ti.com LM25117/LM25117Q When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold, both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV threshold, the over-voltage protection operates in hiccup mode. See Figure 20. Example of Constant Current Regulator The LM25117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output over-voltage. 30155082 FIGURE 20. Constant Current Regulator with Hiccup Mode Output OVP www.ti.com 28 the output current is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor sources a current into CRAMP and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit set-point. See Figure 21 and Figure 22. 30155083 FIGURE 21. Constant Voltage Regulator with Accurate Current Limit 301550145 FIGURE 22. Current Limit Comparison 29 www.ti.com LM25117/LM25117Q The LM25117 also can be configured as a constant voltage and constant current regulator, known as CV+CC regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-by-cycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current amplifier in the current loop. This amplifier circuitry does not affect the normal operation when LM25117/LM25117Q Physical Dimensions inches (millimeters) unless otherwise noted 20 Pin TSSOP with Exposed Pad NS Package Number MXA20A 24 Pin LLP NS Package Number SQA24A www.ti.com 30 LM25117/LM25117Q Notes 31 www.ti.com LM25117/LM25117Q Wide Input Range Synchronous Buck Controller with Analog Current Monitor Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated