LINER LTC2323-14 Dual, 14-bit sign, 5msps differential input adc with wide input common mode range Datasheet

LTC2323-14
Dual, 14-Bit + Sign, 5Msps
Differential Input ADC with Wide
Input Common Mode Range
FEATURES
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DESCRIPTION
5Msps Throughput Rate
±1LSB INL (Typ)
Guaranteed 14-Bit, No Missing Codes
8VP-P Differential Inputs with Wide Input Common
Mode Range
80dB SNR (Typ) at fIN = 2MHz
–85dB THD (Typ) at fIN = 2MHz
Guaranteed Operation to 125°C
Single 3.3V or 5V Supply
Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal
Reference
1.8V to 2.5V I/O Voltages
CMOS or LVDS SPI-Compatible Serial I/O
Power Dissipation 38mW/Ch (Typ)
Small 28-Lead (4mm × 5mm) QFN Package
The LTC®2323-14 is a low noise, high speed dual 14‑bit +
sign successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2323-14
has an 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range with high
common mode rejection. The LTC2323-14 achieves ±1LSB
INL typical, no missing codes at 14 bits and 80dB SNR.
The LTC2323-14 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference.
The LTC2323-14 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
5Msps per channel throughput with one-cycle latency
makes the LTC2323-14 ideally suited for a wide variety of
high speed applications. The LTC2323-14 dissipates only
38mW per channel and offers nap and sleep modes to
reduce the power consumption to 5μW for further power
savings during inactive periods.
APPLICATIONS
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High Speed Data Acquisition Systems
Communications
Remote Data Acquisition
Imaging
Optical Networking
Automotive
Multiphase Motor Control
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
VDD
REFOUT1
AIN1+
VBYP1
LTC2323-14
0V
REFOUT2
220pF
VBYP2
BIPOLAR
UNIPOLAR
25Ω
0V
0V
AIN1–
AIN2+
AIN2–
VDD CMOS/LVDS
REFINT
GND
SDO1
SDO2
CLKOUT
SCK
CNV
OGND OVDD
10µF
1µF
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
1.8V TO 2.5V
1µF
AMPLITUDE (dBFS)
DIFFERENTIAL
25Ω
0V
0
10µF
IN+, IN –
INSTRUMENTATION
32k Point FFT, fS = 5Msps, fIN = 2.2MHz
3.3V OR 5V
SNR = 80.0dB
THD = –85.5dB
–20 SINAD = 79.1dB
SFDR = 88.4dB
–40
–60
–80
–100
–120
–140
0
232314 TA01a
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
232314 TA01b
232314f
For more information http://www.linear.com/LTC2323-14
1
LTC2323-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
OGND
VBYP2
CMOS/LVDS
REFOUT2
REFRTN2
REFINT
TOP VIEW
28 27 26 25 24 23
VDD 1
22 SCK –
AIN2+ 2
21 SCK+
20 SDO2 –
AIN2 – 3
29
GND
GND 4
GND 5
19 SDO2+
18 CLKOUT –
AIN1 – 6
17 CLKOUT+
AIN1+ 7
16 SDO1 –
VDD 8
15 SDO1+
OVDD
VBYP1
REFOUT1
REFRTN1
CNV
9 10 11 12 13 14
GND
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................3V
Supply Bypass Voltage (VBYP1, VBYP2)........................3V
Analog Input Voltage
AIN+, AIN – (Note 3).................... –0.3V to (VDD + 0.3V)
REFOUT1,2.............................. .–0.3V to (VDD + 0.3V)
CNV (Note 15)........................... –0.3V to (VDD + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation................................................200mW
Operating Temperature Range
LTC2323C................................................. 0°C to 70°C
LTC2323I..............................................–40°C to 85°C
LTC2323H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2323CUFD-14#PBF
LTC2323CUFD-14#TRPBF
23234
28-Lead (4mm × 5mm) Plastic QFN
0°C to 70°C
LTC2323IUFD-14#PBF
LTC2323IUFD-14#TRPBF
23234
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2323HUFD-14#PBF
LTC2323HUFD-14#TRPBF
23234
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIN+
Absolute Input Range (AIN1+, AIN2+)
(Note 5)
l
VIN–
Absolute Input Range (AIN1–, AIN2–)
(Note 5)
l
0
VDD
V
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
l
–REFOUT1,2
REFOUT1,2
V
VCM
Common Mode Input Range
VIN = (VIN+ + VIN–)/2
l
0
VDD
V
IIN
Analog Input DC Leakage Current
l
–1
1
µA
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
IREFOUT
External Reference Current
0
MAX
UNITS
VDD
V
10
pF
fIN = 2.2MHz
85
dB
REFINT = 0V, REFOUT = 4.096V
675
µA
232314f
2
For more information www.linear.com/LTC2323-14
LTC2323-14
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Notes 4, 16).
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
UNITS
Resolution
14
Bits
No Missing Codes
l
14
Bits
l
–4
±1
4
LSB
l
–0.99
±0.4
0.99
LSB
l
–5
0
5
Transition Noise
INL
Integral Linearity Error
DNL
Differential Linearity Error
BZE
Bipolar Zero-Scale Error
0.4
(Note 6)
(Note 7)
Bipolar Zero-Scale Error Drift
FSE
TYP
l
LSBRMS
0.006
Bipolar Full-Scale Error
VREFOUT1,2 = 4.096V (REFINT Grounded) (Note 7)
Bipolar Full-Scale Error Drift
VREFOUT1,2 = 4.096V (REFINT Grounded)
l
50
±3
LSB
LSB/°C
50
15
LSB
ppm/°C
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
SYMBOL PARAMETER
CONDITIONS
SINAD
Signal-to-(Noise + Distortion) Ratio fIN = 2.2MHz, VREFOUT1,2 = 4.096V, Internal Reference
fIN = 2.2MHz, VREFOUT1,2 = 5V, External Reference
l
SNR
Signal-to-Noise Ratio
fIN = 2.2MHz, VREFOUT1,2 = 4.096V, Internal Reference
l
MIN
TYP
72.8
79
dB
79
dB
73
fIN = 2.2MHz, VREFOUT1,2 = 5V, External Reference
THD
Total Harmonic Distortion
fIN = 2.2MHz, VREFOUT1,2 = 4.096V, Internal Reference
SFDR
Spurious Free Dynamic Range
fIN = 2.2MHz, VREFOUT1,2 = 4.096V, Internal Reference
l
80
fIN = 2.2MHz, VREFOUT1,2 = 5V, External Reference
UNITS
80
dB
80.5
dB
–85
l
fIN = 2.2MHz, VREFOUT1,2 = 5V, External Reference
MAX
–80
dB
–86
dB
88
dB
88
dB
–3dB Input Linear Bandwidth
10
MHz
Aperture Delay
500
ps
Aperture Delay Matching
500
ps
Aperture Jitter
Transient Response
Full-Scale Step
1
psRMS
3
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VREFOUT1,2
Internal Reference Output Voltage
4.75V < VDD < 5.25V
3.13V < VDD < 3.47V
l
l
VREFOUT1,2 Temperature Coefficient
(Note 14)
l
REFOUT1,2 Output Impedance
VREFOUT1,2 Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
UNITS
4.088
2.044
4.096
2.048
4.106
2.053
V
V
3
20
ppm/°C
0.25
Ω
0.3
mV/V
232314f
For more information http://www.linear.com/LTC2323-14
3
LTC2323-14
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VIN = 0V to OVDD
VOH
High Level Output Voltage
IO = -500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
l
TYP
MAX
UNITS
0.8 • OVDD
V
–10
0.2 • OVDD
V
10
μA
5
ISOURCE
Output Source Current
VOUT = 0V
ISINK
Output Sink Current
VOUT = OVDD
VID
LVDS Differential Input Voltage
100Ω Differential Termination, OVDD = 2.5V
l
pF
OVDD – 0.2
V
–10
0.2
V
10
µA
–10
mA
10
mA
240
600
mV
VIS
LVDS Common Mode Input Voltage
100Ω Differential Termination, OVDD = 2.5V
l
1
1.45
V
VOD
LVDS Differential Output Voltage
100Ω Differential Load, LVDS Mode,
OVDD = 2.5V
l
100
150
300
mV
VOS
LVDS Common Mode Output Voltage
100Ω Differential Load, LVDS Mode,
OVDD = 2.5V
l
0.85
1.2
1.4
V
VOD_LP
Low Power LVDS Differential Output
Voltage
100Ω Differential Load, Low Power,
LVDS Mode ,OVDD = 2.5V
l
75
100
250
mV
VOS_LP
Low Power LVDS Common Mode
Output Voltage
100Ω Differential Load, Low Power,
LVDS Mode ,OVDD = 2.5V
l
0.9
1.2
1.4
V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
VDD
Supply Voltage
OVDD
Supply Voltage
CONDITIONS
MIN
5V Operation
3.3V Operation
IVDD
Supply Current
5Msps Sample Rate (IN+ = IN– = 0V)
IOVDD
Supply Current
5Msps Sample Rate (CL = 5pF)
5Msps Sample Rate (RL = 100Ω)
INAP
Nap Mode Current
Conversion Done (IVDD)
ISLEEP
Sleep Mode Current
Sleep Mode (IVDD + IOVDD)
Sleep Mode (IVDD + IOVDD)
CMOS Mode
LVDS Mode
PD_3.3V
Power Dissipation
PD_5V
MAX
UNITS
l
l
4.75
3.13
TYP
5.25
3.47
V
V
l
1.71
2.63
V
l
14.5
18
mA
l
l
2.8
9.5
5
12
mA
mA
l
2.85
5
mA
l
l
1
1
5
5
μA
μA
VDD = 3.3V 5Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode
VDD = 3.3V 5Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode
l
l
55
72
58
86
mW
mW
Nap Mode
VDD = 3.3V Conversion Done (IVDD + IOVDD)
VDD = 3.3V Conversion Done (IVDD + IOVDD)
CMOS Mode
LVDS Mode
l
l
9
32
13
41
mW
mW
Sleep Mode
VDD = 3.3V Sleep Mode (IVDD + IOVDD)
VDD = 3.3V Sleep Mode (IVDD + IOVDD)
CMOS Mode
LVDS Mode
l
l
5
5
16.5
16.5
μW
μW
Power Dissipation
VDD = 5V 5Msps Sample Rate (IN+ = IN– = 0V) CMOS Mode
VDD = 5V 5Msps Sample Rate (IN+ = IN– = 0V) LVDS Mode
l
l
76
105
100
110
mW
mW
Nap Mode
VDD = 5V Conversion Done (IVDD + IOVDD)
VDD = 5V Conversion Done (IVDD + IOVDD)
CMOS Mode
LVDS Mode
l
l
15
38
25
40
mW
mW
Sleep Mode
VDD = 5V Sleep Mode (IVDD + IOVDD)
VDD = 5V Sleep Mode (IVDD + IOVDD)
CMOS Mode
LVDS Mode
l
l
5
5
25
25
μW
μW
CMOS Mode
LVDS Mode
232314f
4
For more information www.linear.com/LTC2323-14
LTC2323-14
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
l
MIN
tCYC
Time Between Conversions
l
200
TYP
MAX
UNITS
5
Msps
1000000
ns
tCONV
Conversion Time
l
171.5
ns
tCNVH
CNV High Time
l
25
ns
tDCNVSCKL
SCK Quiet Time from CNV↓
(Note 11)
l
9.5
ns
tDSCKLCNVH
SCK Delay Time to CNV↑
(Note 11)
l
19.1
ns
tSCK
SCK Period
(Notes 12, 13)
l
9.4
ns
tSCKH
SCK High Time
l
4
ns
tSCKL
SCK Low Time
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
tDCLKOUTSDOV
SDO Data Valid Delay from CLKOUT↓
CL = 5pF (Note 12)
l
2
ns
tHSDO
SDO Data Remains Valid Delay from
CLKOUT↓
CL = 5pF (Note 11)
l
2
ns
tDCNVSDOV
SDO Data Valid Delay from CNV↓
CL = 5pF (Note 11)
l
tDCNVSDOZ
Bus Relinquish Time After CNV↑
(Note 11)
l
tWAKE
REFOUT1,2 Wakeup Time
CREFOUT1,2 = 10μF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground, or above VDD
or OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground, or above VDD or OVDD, without
latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 5MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 000 0000 0000 0000 and 111 1111
1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
l
4
ns
l
2.8
ns
2.5
10
3
ns
3
ns
ms
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REFIN = 4.096V.
Note 9: When REFOUT1,2 is overdriven, the internal reference buffer must
be turned off by setting REFINT = 0V.
Note 10: fSMPL = 5MHz, IREFBUF varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and
OVDD = 2.5V.
Note 13: tSCK of 9.4ns maximum allows a shift clock frequency up to
105MHz for rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels. This input pin has a TTL style input that will draw a small
amount of current.
Note 16: 1LSB = 2 • REFOUT1,2/214
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
232314 F01
Figure 1. Voltage Levels for Timing Specifications
232314f
For more information http://www.linear.com/LTC2323-14
5
LTC2323-14
TYPICAL PERFORMANCE CHARACTERISTICS
REFOUT1,2 = 4.096V, fSMPL = 5Msps, unless otherwise noted. (Note 16)
Integral Nonlinearity
vs Output Code
TA = 25°C, VDD = 5V, OVDD = 2.5V,
Differential Nonlinearity
vs Output Code
3
DC Histogram
35000
1.0
30000
2
0.5
0
–1
25000
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
1
0
–2
50000
–3
8192
–8192
0
16384
–16384
4096
–12288
–4096
12288
TEMPERATURE (C)
LT1372 • G03
2
1.5
FREQUENCY (MHz)
2.5
SINAD
79.5
79.0
0
1
1.5
FREQUENCY (MHz)
2
2.5
THD
–95
–100
–110
SNR, SINAD (dBFS)
–90
THD
–95
HD2
–100
HD3
–105
2.1
2.3
2.5
2.7
2.9
INPUT COMMON MODE (V)
3.1
3.3
232314 G07
0
1
1.5
FREQUENCY (MHz)
2
2.5
232314 G06
8k Point FFT, IMD, fS = 5Msps,
VIN+ = 100kHz, VIN– = 2.2MHz
–20
SNR
78
SINAD
76
74
72
68
0.5
0.5
0
70
1.9
HD3
232314 G05
80
–85
HD2
–105
82
–80
3
2
–90
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
–75
–110
1.7
0.5
232314 G04
THD, Harmonics vs Input Common
Mode (100kHz to 2.2MHz)
THD, HARMONICS (dBFS)
THD, HARMONICS (dBFS)
SNR
80.0
78.0
1
–85
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
SNR, SINAD (dBFS)
1
0
THD, Harmonics vs Input
Frequency (100kHz to 2.2MHz)
78.5
–120
–1
232314 G03
81.5
–100
–2
CODE
81.0
–80
0.5
–3
SNR, SINAD vs Input Frequency
(100kHz to 2.2MHz)
–60
0
0
–1.0
8192
16384
–16384
–8192
0
4096
12288
–12288
–4096
INPUT VOLTAGE (V)
232314 G02
32k Point FFT, fS = 5Msps,
fIN = 2.2MHz
SNR = 80.0dB
THD = –85.5dB
–20 SINAD = 79.1dB
SFDR = 88.4dB
–40
–140
15000
10000
–0.5
0
20000
–40
–60
–80
–100
–120
1
1.5
2
2.5
3
VREF (V)
3.5
4
4.5
5
232314 G08
–140
0
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
232314 G09
232314f
6
For more information www.linear.com/LTC2323-14
LTC2323-14
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V,
REFOUT1,2 = 4.096V, fSMPL = 5Msps, unless otherwise noted. (Note 16)
Crosstalk vs Input Frequency
Output Match with Simultaneous
Input Steps at CH1, CH2
CMRR vs Input Frequency
–80
–126
20000
–83
–132
OUTPUT CODE (CH1, CH2)
–130
–89
CH1
10000
–92
–95
–98
–134
–136
15000
–86
CMRR (dB)
CROSSTALK (dBc)
–128
CH2
5000
O
–101
0
0.5
1
1.5
FREQUENCY (MHz)
2
–104
2.5
0
0.5
232314 G10
1
1.5
FREQUENCY (MHz)
2
2.5
–5000
100
0
200
TIME (ns)
232314 G11
232314 G12
Offset Error vs Temperature
Gain Error vs Temperature
REFOUT1,2 Output vs Temperature
0.5
0.6
200
0.4
GAIN ERROR (14-BIT LSB)
CH2
LSB
0.2
0
CH1
–0.2
–0.4
100
0.3
0
0.2
REFOUT (ppm)
0.4
0.1
0
–0.1
–0.2
0
–0.3
–25
50
25
0
75
TEMPERATURE (°C)
232314 G13
0.680
2.048V
–400
–0.4
–50
25 50 75 100 125 150
TEMPERATURE (°C)
–200
–300
–0.4
–0.6
–50 –25
4.096V
–100
100
125
–500
–50
0
50
100
TEMPERATURE (°C)
150
232314 G15
232314 G14
IREF vs Temperature,
VREF = 4.096V
Supply Current
vs Sample Frequency
8
OVDD Current vs SCK Frequency,
CLOAD = 10pF
0.675
0.670
0.665
–40 –20
0
20
40
60
TEMPERATURE (°C)
80
100 120
232314 G16
OVDD CURRENT (mA)
SUPPLY CURRENT (mA)
REFERENCE CURRENT (mA)
16
14
12
10
8
0.2
1.0
1.9
2.9
3.8
4.8
SAMPLE FREQUENCY (Msps)
5.2
232314 G17
6
4
2
0
0 10 20 30 40 50 60 70 80 90 100 110
SCK FREQUENCY (MHz)
232314 G18
232314f
For more information http://www.linear.com/LTC2323-14
7
LTC2323-14
PIN FUNCTIONS
VDD (Pins 1, 8): Power Supply. Bypass VDD to GND with
a 10µF ceramic and a 0.1µF ceramic close to the part. The
VDD pins should be shorted together and driven from the
same supply.
not connect SDO1–. In LVDS mode, the result is output
differentially on SDO1+ and SDO1-. These pins must be
differentially terminated by an external 100 ohm resistor
at the receiver (FPGA).
AIN2+, AIN2– (Pins 2, 3): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
CLKOUT+, CLKOUT– (Pins 17, 18): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to latch
the SDO output at the receiver. In CMOS mode, the skewmatched clock is output on CLKOUT+. The logic level
is determined by OVDD. Do not connect CLKOUT–. For
low throughput applications using SCK to latch the SDO
output, CLKOUT+ can be disabled by tying CLKOUT– to
OVDD. In LVDS mode, the skew-matched clock is output
differentially on CLKOUT+ and CLKOUT–. These pins must
be differentially terminated by an external 100Ω resistor
at the receiver (FPGA).
GND (Pins 4, 5, 10, 29): Ground. These pins and exposed
pad (Pin 29) must be tied directly to a solid ground plane.
AIN1–, AIN1+ (Pins 6, 7): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
CNV (Pin 9): Convert Input. This pin, when high, defines
the sampling phase. When this pin is driven low, the conversion phase is initiated and output data is clocked out.
This input pin is a TTL-style input typically driven at OVDD
levels with a low jitter pulse, but it is bound to VDD levels.
This pin is unaffected by the CMOS/LVDS pin.
REFRTN1 (Pin 11): Reference Buffer 1 Output Return.
Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1
pin to the ground plane.
REFOUT1 (Pin 12): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is referred to REFRTN1 and should be decoupled closely to the
pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor and
a 10μF (X5R, 0805 size) ceramic capacitor in parallel. The
internal buffer driving this pin may be disabled by grounding the REFINT pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
VBYP1 (Pin 13): Bypass this internally supplied pin to
ground with a 1µF ceramic capacitor. The nominal output
voltage on this pin is 1.6V.
OVDD (Pin 14): I/O Interface Digital Power. The range of
OVDD is 1.71V to 2.5V. This supply is nominally set to the
same supply as the host interface (CMOS: 1.8V or 2.5V,
LVDS: 2.5V). Bypass OVDD to OGND with a 0.1μF capacitor.
SDO1+, SDO1– (Pins 15, 16): Channel 1 Serial Data Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO1+. The logic level is determined by OVDD. Do
SDO2+, SDO2– (Pins 19, 20): Channel 2 Serial Data Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO2+. The logic level is determined by OVDD. Do
not connect SDO2–. In LVDS mode, the result is output
differentially on SDO2+ and SDO2–. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
SCK+, SCK– (Pins 21, 22): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins. In CMOS mode, drive SCK+ with
a single-ended clock. The logic level is determined by
OVDD. Do not connect SCK–. In LVDS mode, drive SCK+
and SCK– with a differential clock. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (ADC).
OGND (Pin 23): I/O Ground. This ground must be tied to
the ground plane at a single point. OVDD is bypassed to
this pin.
VBYP2 (Pin 24): Bypass this internally supplied pin to
ground with a 1µF ceramic capacitor. The nominal output
voltage on this pin is 1.6V
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
to enable CMOS mode, tie to OVDD to enable LVDS mode.
Float this pin to enable low power LVDS mode.
232314f
8
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LTC2323-14
PIN FUNCTIONS
REFOUT2 (Pin 26): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to REFRTN2 and should be decoupled closely to
the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor
and a 10μF (X5R, 0805 size) ceramic capacitor in parallel. The internal buffer driving this pin may be disabled
by grounding the REFINT pin. If the buffer is disabled,
an external reference may drive this pin in the range of
1.25V to VDD.
REFRTN2 (Pin 27): Reference Buffer 2 Output Return.
Bypass REFRTN2 to REFOUT2. Do not tie the REFRTN2
pin to the ground plane.
REFINT (Pin 28): Reference Buffer Output Enable. Tie to
VDD when using the internal reference. Tie to ground to
disable the internal REFOUT1 and REFOUT2 buffers for
use with external voltage references. This pin has a 500k
internal pull-up to VDD.
Exposed Pad (Pin 29): Ground. Solder this pad to ground.
FUNCTIONAL BLOCK DIAGRAM
VDD
1,8
7
6
AIN1+
AIN1–
VBYP1 13
LDO
+
14-BIT + SIGN
SAR ADC
S/H
–
28 REFINT
REFOUT1
12
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
1.2V REF
26
9
TIMING CONTROL
LOGIC
OUTPUT
CLOCK DRIVER
LVDS/CMOS
RECEIVERS
2
3
AIN2–
VDD
1,8
15
16
OVDD 14
G
CNV
AIN2+
SDO1–
GND
4, 5, 10, 29
G
REFOUT2
SDO1+
+
14-BIT + SIGN
SAR ADC
S/H
–
LVDS/CMOS
TRI-STATE
SERIAL OUTPUT
LDO
CLKOUT+
CLKOUT–
SCK+
SCK –
SDO2+
SDO2 –
17
18
21
22
19
20
VBYP2 24
232314 BD
232314f
For more information http://www.linear.com/LTC2323-14
9
LTC2323-14
TIMING DIAGRAM
ACQUISITION
CONVERSION AND READOUT
ACQUISITION
CNV
SCK
HI-Z
SDO
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
CLKOUT
B1
B0
0
HI-Z
232314 TD
SERIAL DATA BITS B[14:0] CORRESPOND TO PREVIOUS CONVERSION
APPLICATIONS INFORMATION
OVERVIEW
CONVERTER OPERATION
The LTC2323-14 is a low noise, high speed 14-bit + sign
dual successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
The flexible analog inputs support fully differential, pseudodifferential bipolar and pseudo-differential unipolar drive
without requiring any hardware configuration. The MSB
of the 14-bit + sign two’s complement output indicates
the sign of the differential analog input voltage.
The LTC2323-14 operates in two phases. During the
acquisition phase, the sample capacitor is connected to
the analog input pins AIN+ and AIN – to sample the differential analog input voltage, as shown in Figure 3. A
falling edge on the CNV pin initiates a conversion. During the conversion phase, the 15-bit CDAC is sequenced
through a successive approximation algorithm for each
input SCK pulse, effectively comparing the sampled input
with binary-weighted fractions of the reference voltage
(e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/8192) using a
differential comparator. At the end of conversion, a CDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 15-bit digital output code
for serial transfer.
OUTPUT CODE (TWO’S COMPLEMENT)
The ADC’s transfer function provides 15 bits of resolution
across the full-scale span of 2 • REFOUT, as shown in
Figure 2. If the analog input spans less than this full-scale,
such as in the case of pseudo-differential drive, the ADC
provides 14 bits of resolution across this reduced span,
with the additional benefit of digitizing over and underrange conditions, as shown in Table 1. This unique feature
is particularly useful in control-loop applications.
011 1111 1111 1111
TRANSFER FUNCTION
The LTC2323-14 digitizes the full-scale voltage of 2 •
REFOUT into 215 levels, resulting in a 15-bit resolution
size of 250µV with REFBUF = 4.096V. The ideal transfer
function is shown in Figure 2. The output data is in 2’s
complement format. When driven by fully differential inputs, the transfer function spans 215 codes. When driven
by pseudo differential inputs, the transfer function spans
214 codes.
1LSB = 2 • REFOUT/32768
011 1111 1111 1110
000 0000 0000 0001
000 0000 0000 0000
111 1111 1111 1111
100 0000 0000 0001
100 0000 0000 0000
–REFOUT
–1 0 1
REFOUT – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
232314 F02
Figure 2. LTC2323-14 Transfer Function
232314f
10
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LTC2323-14
APPLICATIONS INFORMATION
Single-Ended Signals
Table 1: Code Ranges for the Analog Input Operational Modes
MODE
Span (VIN+ – VIN–)
Min Code
Fully Differential
–REFOUT to
+REFOUT
100 0000 0000 011 1111 1111
0000
1111
Max Code
Pseudo-Differential –REFOUT/2 to
Bipolar
+REFOUT/2
110 0000 0000 001 1111 1111
0000
1111
Pseudo-Differential 0 to REFOUT
Unipolar
000 0000 0000 011 1111 1111
0000
1111
Single-ended signals can be directly digitized by the
LTC2323-14. These signals should be sensed pseudodifferentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
the main analog signal to the other AIN pin, any noise or
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2323-14 flexibility
handles both pseudo-differential unipolar and bipolar signals, with no configuration required. The wide common
mode input range relaxes the accuracy requirements of
any signal conditioning circuits prior to the analog inputs.
Analog Input
The differential inputs of the LTC2323-14 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2323-14 digitizes the
difference voltage between the AIN+ and AIN – pins while
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between VDD and GND.
The LTC2323-14 can also digitize more limited classes of
analog input signals such as pseudo-differential unipolar/
bipolar and fully differential with no configuration required.
Pseudo-Differential Bipolar Input Range
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically
VREF /2, and applying a signal to the other AIN pin. In this
case the analog input swings symmetrically around the
fixed input yielding bipolar two’s complement output codes
with an ADC span of half of full-scale. This configuration
is illustrated in Figure 4, and the corresponding transfer
function in Figure 5. The fixed analog input pin need not
be set at VREF /2, but at some point within the VDD rails
allowing the alternate input to swing symmetrically around
this voltage. If the input signal (AIN+ – AIN –) swings beyond
±REFOUT/2, valid codes will be generated by the ADC and
must be clamped by the user, if necessary.
The analog inputs of the LTC2323-14 can be modeled
by the equivalent circuit shown in Figure 3. The back-toback diodes at the inputs form clamps that provide ESD
protection. In the acquisition phase, 10pF (CIN) from the
sampling capacitor in series with approximately 15Ω
(RON) from the on-resistance of the sampling switch is
connected to the input. Any unwanted signal that is common to both inputs will be reduced by the common mode
rejection of the ADC sampler. The inputs of the ADC core
draw a small current spike while charging the CIN capacitors during acquisition.
VDD
RON
15Ω
AIN1+
CIN
10pF
BIAS
VOLTAGE
VDD
AIN1–
RON
15Ω
CIN
10pF
232314 F03
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2323-14
232314f
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11
LTC2323-14
APPLICATIONS INFORMATION
VREF
0V
LT1819
VREF
+
–
0V
LTC2323-14
25Ω
AIN1+
REFOUT1
VREF
VBYP1
220pF
10k
VREF /2
10k
1µF
+
–
25Ω
VREF /2
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232314 F04
Figure 4. Pseudo-Differential Bipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
–VREF
–VREF /2
0
–8192
–16384
VREF /2
VREF
AIN
(AIN+ – AIN–)
DOTTED REGIONS AVAILABLE
BUT UNUSED
232314 F05
Figure 5. Pseudo-Differential Bipolar Transfer Function
Pseudo-Differential Unipolar Input Range
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other AIN pin. In this case, the analog input
swings between ground and VREF yielding unipolar two’s
complement output codes with an ADC span of half of
full-scale. This configuration is illustrated in Figure 6, and
the corresponding transfer function in Figure 7. If the input
signal (AIN+ – AIN –) swings negative, valid codes will be
generated by the ADC and must be clamped by the user,
if necessary.
Single-Ended-to-Differential Conversion
While single-ended signals can be directly digitized as previously discussed, single-ended to differential conversion
circuits may also be used when higher dynamic range is
desired. By producing a differential signal at the inputs of
the LTC2323-14, the signal swing presented to the ADC is
maximized, thus increasing the achievable SNR.
The LT®1819 high speed dual operational amplifier is
recommended for performing single-ended-to-differential
conversions, as shown in Figure 8. In this case, the first
amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high impedance input of this amplifier.
Fully-Differential Inputs
To achieve the full distortion performance of the LTC2323-14,
a low distortion fully-differential signal source driven
through the LT1819 configured as two unity-gain buffers,
as shown in Figure 9, can be used. This circuit achieves
the full data sheet THD specification of –85dB at input
232314f
12
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LTC2323-14
APPLICATIONS INFORMATION
VREF
0V
LT1818
VREF
+
–
0V
LTC2323-14
25Ω
AIN1+
VBYP1
220pF
25Ω
REFOUT1
AIN1–
SDO1
CLKOUT
SCK
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232314 F06
Figure 6. Pseudo-Differential Unipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
–VREF
–VREF /2
–8192
–16384
0
VREF /2
VREF
AIN
(AIN+ – AIN–)
DOTTED REGIONS AVAILABLE
BUT UNUSED
232314 F07
Figure 7. Pseudo-Differential Unipolar Transfer Function
VREF
0V
200Ω
VREF /2
LT1819
+
–
VREF
+
–
VREF
200Ω
0V
0V
VREF
0V
VREF
0V
232314 F08
Figure 8. Single-Ended to Differential Driver
LT1819
+
–
VREF
+
–
VREF
0V
0V
232314 F09
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
232314f
For more information http://www.linear.com/LTC2323-14
13
LTC2323-14
APPLICATIONS INFORMATION
frequencies of 500kHz and less. Data sheet typical performance curves taken at higher frequencies used a harmonic
rejection filter between the ADC and the signal source to
eliminate the op amp as the dominant source of distortion.
on each AIN pin, yielding a signal span for each AIN pin of
4.096VP-P. This leaves ~0.9V of common mode variation
tolerance. When using external references, it is possible
to increase common mode tolerance by compressing the
ADC full-range codes into a tighter range. For example,
using an external 2.048V reference with VDD = 5V the total
span would be ±2.048V and each AIN span would be limited to 2.048VP-P allowing a common mode range of ~3V.
Compressing the input span would incur a SNR penalty
of approximately 2dB. Input span compression may be
useful if single-supply analog input drivers are used which
cannot swing rail-to-rail. The fully-differential configuration
is illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
The fully-differential configuration yields an analog input
span (AIN+ – AIN –) of ±REFOUT. In this configuration, the
input signal is driven on each AIN pin, typically at equal
spans but opposite polarity. This yields a high common
mode rejection on the input signals. The common mode
voltage of the analog input can be anywhere within the VDD
input range, but will be limited by the peak swing of the
full-range input signal. For example, if the internal reference is used with VDD = 5VDC, the full-range input span
will be ±4.096V. Half of the input span is typically driven
VREF
0V
LT1819
VREF
+
–
0V
LTC2323-14
25Ω
AIN1+
VBYP1
220pF
VREF
0V
REFOUT1
VREF
+
–
0V
25Ω
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232314 F10
Figure 10. Fully-Differential Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
–VREF
–VREF /2
0
VREF /2
VREF
AIN
(AINn + – AINn –)
–8192
–16384
232314 F11
Figure 11. Fully-Differential Transfer Function
232314f
14
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LTC2323-14
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2323-14 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2323-14. The amplifier
provides low output impedance to minimize gain error
and allow for fast settling of the analog signal during the
acquisition phase. It also provides isolation between the
signal source and the ADC inputs, which draw a small
current spike during acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter
to minimize noise. The simple 1-pole RC lowpass filter
shown in Figure 12 is sufficient for many applications.
The input resistor divider network, sampling switch onresistance (RON) and the sample capacitor (CIN) form a
second lowpass filter that limits the input bandwidth to the
ADC core to 110MHz. A buffer amplifier with a low noise
density must be selected to minimize the degradation of
the SNR over this bandwidth.
SINGLE-ENDED
INPUT SIGNAL
50Ω
3.3nF
BW = 1MHz
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
ADC REFERENCE
Internal Reference
The LTC2323-14 has an on-chip, low noise, low drift
(20ppm/°C max), temperature compensated bandgap
reference. It is internally buffered and is available at
REFOUT1,2 (Pins 12, 26). The reference buffer gains
the internal reference voltage to 4.096V for supply voltages VDD = 5V and to 2.048V for VDD = 3.3V. Bypass
REFOUT1,2 to REFRTN1,2 with the parallel combination
of a 0.1µF (X7R, 0402 size) capacitor and a 10μF (X5R,
0805 size) ceramic capacitor to compensate the reference
buffer and minimize noise. The 0.1µF capacitor should
be as close as possible to the LTC2323-14 package to
minimize wiring inductance. Tie the REFINT pin to VDD to
enable the internal reference buffer.
Table 2. REFOUT1,2 Sources and Ranges vs VDD
VDD
REFINT
PIN
REFOUT1,2 PIN
DIFFERENTIAL
SPAN
5V
5V
Internal 4.096V
±4.096V
5V
0V
External (1.25V to 5V)
±1.25V to ±5V
3.3V
3.3V
Internal 2.048V
±2.048V
3.3V
0V
External (1.25V to 3.3V)
±1.25V to ±3.3V
IN+
LTC2323
IN–
SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
232314 F12
Figure 12. Input Signal Chain
232314f
For more information http://www.linear.com/LTC2323-14
15
LTC2323-14
APPLICATIONS INFORMATION
External Reference
The internal reference buffer can also be overdriven from
1.25V to 5V with an external reference at REFOUT1,2
as shown in Figure 13 (b and c). To do so, REFINT must
be grounded to disable the reference buffer. A 55k internal
resistance loads the REFOUT1,2 pins when the reference
buffer is disabled. To maximize the input signal swing
and corresponding SNR, the LTC6655-5 is recommended
when overdriving REFOUT1,2. The LTC6655-5 offers the
same small size, accuracy, drift and extended temperature
range as the LTC6655-4.096. By using a 5V reference, a
higher SNR can be achieved. We recommend bypassing
the LTC6655-5 with a parallel combination of a 0.1µF
(X7R, 0402 size) ceramic capacitor and a 10μF ceramic
capacitor (X5R, 0805 size) close to each of the REFOUT1,2
and REFRTN1,2 pins.
Internal Reference Buffer Transient Response
The REFOUT1,2 pins of the LTC2323-14 draw charge
(QCONV) from the external bypass capacitors during each
conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge
with a DC current equivalent to IREF = QCONV/tCYC.
Thus, the DC current draw of REFOUT1,2 depends
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
REFINT
VDD
REFINT
REFOUT1
3.3V TO 5V
0.1µF
10µF
REFOUT1
LTC2323-14
0.1µF
5V TO 13.2V
REFRTN1
0.1µF
REFRTN2
0.1µF
10µF
LTC6655-4.096
VIN
VOUT_F
SHDN VOUT_S
10µF
LTC2323-14
REFRTN1
0.1µF
REFRTN2
10µF
REFOUT2
GND
REFOUT2
GND
232314 F14b
232314 F14a
(13a) LTC2323-14 Internal Reference Circuit
(13b) LTC2323-14 with a Shared External Reference Circuit
5V TO 13.2V
0.1µF
REFINT
LTC6655-4.096
VIN
VOUT_F
SHDN VOUT_S
REFOUT1
0.1µF
10µF
REFRTN1
0.1µF
0.1µF
LTC6655-2.048
VIN
VOUT_F
SHDN VOUT_S
LTC2323-14
REFRTN2
10µF
REFOUT2
GND
232314 F13c
(13c) LTC2323-14 with Different External Reference Voltages
Figure 13. Reference Connection
232314f
16
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LTC2323-14
APPLICATIONS INFORMATION
periods, as shown in Figure 14 , IREFBUF quickly goes
from approximately ~75µA to a maximum of 500µA for
REFOUT1,2 = 5V at 5Msps. This step in DC current draw
triggers a transient response in the external reference
that must be considered since any deviation in the voltage at REFOUT1,2 will affect the accuracy of the output
code. Due to the one-cycle conversion latency, the first
conversion result at the beginning of a burst sampling
period will be invalid. If an external reference is used to
overdrive REFOUT1,2 the fast settling LTC6655 reference
is recommended.
CNV
IDLE
PERIOD
232314 F14
Figure 14. CNV Waveform Showing Burst Sampling
20000
OUTPUT CODE (CH1, CH2)
15000
CH1
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
to frequencies from above DC and below half the sampling
frequency. Figure 16 shows that the LTC2323-14 achieves
a typical SINAD of 79dB at a 5MHz sampling rate with a
2.2MHz input.
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2323-14 achieves a typical SNR of 80dB at a
5MHz sampling rate with a 2.2MHz input.
CH2
5000
O
0
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2323-14 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise Ratio (SNR)
10000
–5000
DYNAMIC PERFORMANCE
100
200
TIME (ns)
232314 F15
Figure 15. Transient Response of the LTC2323-14
AMPLITUDE (dBFS)
0
SNR = 80.0dB
THD = –85.5dB
–20 SINAD = 79.1dB
SFDR = 88.4dB
–40
–60
–80
–100
–120
–140
0
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
232314 F16
Figure 16. 32k Point FFT of the LTC2323-14
For more information http://www.linear.com/LTC2323-14
232314f
17
LTC2323-14
APPLICATIONS INFORMATION
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL /2).
THD is expressed as:
V22 + V32 + V42 +…+ VN 2
THD= 20log
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2323-14 requires two power supplies: the 5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows
the LTC2323-14 to communicate with any digital logic
operating between 1.8V and 2.5V. When using LVDS I/O,
the OVDD supply must be set to 2.5V.
Power Supply Sequencing
The LTC2323-14 does not have any specific power supply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described
in the Absolute Maximum Ratings section. The LTC232314 has a power-on-reset (POR) circuit that will reset the
LTC2323-14 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
SUPPLY CURRENT (mA)
16
14
12
10
8
0.2
1.0
1.9
2.9
3.8
4.8
SAMPLE FREQUENCY (Msps)
5.2
232314 F17
Figure 17. Power Supply Current of the LTC2323-14 Versus Sampling Rate
232314f
18
For more information www.linear.com/LTC2323-14
LTC2323-14
APPLICATIONS INFORMATION
TIMING AND CONTROL
Nap/Sleep Modes
CNV Timing
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2323-14,
the SCK signal must be held high or low and a series of
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
a single rising edge of SCK is applied, or further CNV pulses
are applied. The SCK rising edge will put the LTC2323-14
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2323-14 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2323-14 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2323-14 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2323-14 between
operational, nap and sleep modes indefinitely.
The LTC2323-14 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
falling edge starts the conversion and readout process. The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling edge
of the CNV signal. The rising edge jitter of CNV is much
less critical to performance. The typical pulse width of the
CNV signal is 30ns at a 5Msps conversion rate.
SCK Conversion/Readout Input Clock
The falling edge of this clock shifts the conversion result
MSB first onto the SDO pins. A 105MHz external clock must
be applied at the SCK pin to achieve 5Msps throughput.
CLKOUT Readout Output Clock
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK
to capture the SDO output eases timing requirements at
the receiver. For low throughput applications, CLKOUT+
can be disabled by tying CLKOUT– to OVDD.
CNV
1
Refer to the timing diagrams in Figure 18, Figure 19, Figure 20
and Figure 21 for more detailed timing information about
sleep and nap modes.
2
NAP MODE
SCK
SDO1
SDO2
FULL POWER MODE
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
Z
Z
232314 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
232314f
For more information http://www.linear.com/LTC2323-14
19
LTC2323-14
APPLICATIONS INFORMATION
REFOUT1
REFOUT2
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1
SDO2
Z
Z
Z
Z
232314 F19
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
REFOUT1
REFOUT2
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
WAKE ON 5TH
CSB EDGE
5
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
SDO1
SDO2
Z
Z
Z
Z
Z
232314 F20
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
tCNVH
tDSCKLCNVH
CNV
tDCNVSCKL
SCK
HI-Z
SDO1,2
CLKOUT
1
2
tSCKL
3
4
5
tSCKH
6
7
8
tDCNVSDOZ
tSCK
9
10
11
12
13
14
15
16
tDCNVSDOV
B14
B13
B12
tDCLKOUTSCOV
1
B11
B10
B9
B8
B7
B6
B5
B4
3
4
B2
B1
B0
0
HI-Z
tDSCLKCLKOUT
tHSDO
2
B3
5
6
7
8
9
10
11
12
13
14
15
16
tCONV
tTHROUGHPUT
232314 F21
SERIAL DATA BITS B[14:0] CORRESPOND TO PREVIOUS CONVERSION
Figure 21. LTC2323-14 Timing Diagram
232314f
20
For more information www.linear.com/LTC2323-14
LTC2323-14
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2323-14 features a serial digital interface that
is simple and straight forward to use. The flexible OVDD
supply allows the LTC2323-14 to communicate with any
digital logic operating between 1.8V and 2.5V. A 105MHz
external clock must be applied at the SCK pin to achieve
5Msps throughput.
In addition to a standard CMOS SPI interface, the
LTC2323‑14 provides an optional LVDS SPI interface to
support low noise digital design. The CMOS/LVDS pin is
used to select the digital interface mode.
The falling edge of SCK outputs the conversion result MSB
first on the SDO pins. CLKOUT provides a skew-matched
clock to latch the SDO output at the receiver. The timing
LTC2323-14
OVDD
skew of the CLKOUT and SDO outputs are matched. For
high throughput applications, using CLKOUT instead of
SCK to capture the SDO output eases timing requirements
at the receiver.
In CMOS mode, use the SDO1+, SDO2+ and CLKOUT+ pins
as outputs. Use the SCK+ pin as an input. Do not connect
the SDO1–, SDO2–, SCK– and CLKOUT– pins, as they each
have internal pull-down circuitry to OGND.
In LVDS mode, use the SDO1+/SDO1–, SDO2+/SDO2– and
CLKOUT+/CLKOUT– pins as differential outputs. These
pins must be differentially terminated by an external 100Ω
resistor at the receiver (FPGA). The SCK+/SCK– pins are
differential inputs and must be terminated differentially by
an external 100Ω resistor at the receiver (ADC).
FPGA OR DSP
2.5V
SDO1+
SDO1–
100Ω
+
–
100Ω
+
–
CLKOUT+
CLKOUT –
SCK+
+
–
100Ω
2.5V
CMOS/LVDS
SCK–
SDO2+
100Ω
SDO2–
+
–
CNV
232314 F22
Figure 22. LTC2323 Using the LVDS Interface
232314f
For more information http://www.linear.com/LTC2323-14
21
LTC2323-14
APPLICATIONS INFORMATION
BOARD LAYOUT
Recommended Layout
To obtain the best performance from the LTC2323-14,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information, refer to the DC1996,
the evaluation kit for the LTC2323-14.
Figure 23. Layer 1, Top Layer
Figure 25. Layer 3, Power Plane
Figure 24. Layer 2, Ground Plane
Figure 26. Layer 4, Bottom Layer
232314f
22
For more information www.linear.com/LTC2323-14
LTC2323-14
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
232314f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
its circuits ashttp://www.linear.com/LTC2323-14
described herein will not infringe on existing patent rights.
For more of
information
23
LTC2323-14
TYPICAL APPLICATION
Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop
VCC
0.1µF
50Ω
1k
NC7SVUO4P5X
MASTER_CLOCK
VCC
1k
D
PRE
NC7SV74KBX Q
CLR
CONV
CONV ENABLE
LTC2323-14
CNV
SCK
CLKOUT
GND
CMOS/LVDS
SDO1
SDO2
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
10Ω
10Ω
10Ω
NC7SVU04P5X (× 3)
232314 TA02
RELATED PARTS
PART NUMBER
ADCs
LTC2323-16/LTC2323-12
DESCRIPTION
COMMENTS
16-/12-Bit, 5Msps Simultaneous Sampling ADC
3.3V/5V Supply, Differential Input with Wide Input Common-Mode
Range, 4mm × 5mm QFN-28 Package
LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, Dual 2Msps Simultaneous Sampling 3.3V/5V Supply, Differential Input with Wide Input Common-Mode
LTC2321-12
ADC
Range, 4mm × 5mm QFN-28 Package
LTC2314-14
14-Bit, 4.5Msps Serial ADC
3V/5V Supply, 18mW/31mW, 20ppm/°C Max Internal Reference,
Unipolar Inputs, 8-Lead TSOT-23 Package
LTC2389-16
16-Bit, 2.5Msps, All-In-One ADC
5V Supply, Pin-Configurable Input, 96dB SNR, ±4.096V, 0V to 4.096V,
and ±2.048V Input Ranges, Internal 4.096V Reference, 7mm × 7mm
LQFP-48 and QFN-48 Packages
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range,
LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
LTC2367-16/LTC2364-16 Low Power ADC
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, PinLTC2377-16/LTC2376-16 Low Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACs
Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal
Reference
Dual 16-/14-/12-Bit SPI VOUT DACs with External
Reference
2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, 8-Pin ThinSOT™ Package
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead
MSOP Package
LTC6655
Precision Low Drift, Low Noise Buffered Reference
LTC6652
Precision Low Drift, Low Noise Buffered Reference
5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 0.25ppm
Peak-to-Peak Noise, MSOP-8 Package
5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm
Peak-to-Peak Noise, MSOP-8 Package
LTC2632
LTC2602/LTC2612/
LTC2622
References
Amplifiers
LT1818/LT1819
LT1806
LT6200
400MHz, 2500V/µs, 9mA Single/Dual Operational
Amplifiers
325MHz, Single, Rail-to-Rail Input and Output, Low
Distortion, Low Noise Precision Op Amps
165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz
Low Noise, Op Amp Family
–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply
Current, Unity-Gain Stable
–80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,
9mA Supply Current, Unity-Gain Stable
Low Noise, Low Distortion, Unity-Gain Stable
232314f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2323-14
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2323-14
LT 0614 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2014