FAIRCHILD 74LVTH373SJ

74LVT373, 74LVTH373
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
General Description
■ Input and output interface capability to systems at
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in a high
impedance state.
■
■
■
■
■
■
5V VCC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH373),
also available without bushold feature (74LVT373)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32 mA/+64 mA
Functionally compatible with the 74 series 373
ESD performance:
– Human-body model > 2000V
– Machine model > 200V
– Charged-device model > 1000V
The LVTH373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and
LVTH373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Ordering Information
Order Number
Package
Number
Package Description
74LVT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
February 2008
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O0–O7
3-STATE Latch Outputs
Truth Table
Functional Description
Inputs
The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
Outputs
LE
OE
Dn
On
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition
of Latch Enable
www.fairchildsemi.com
2
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Connection Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
3
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Logic Diagram
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Rating
Supply Voltage
–0.5V to +4.6V
VI
DC Input Voltage
–0.5V to +7.0V
VO
DC Output Voltage
Output in 3-STATE
–0.5V to +7.0V
State(1)
Output in HIGH or LOW
–0.5V to +7.0V
DC Input Diode Current, VI < GND
–50mA
IOK
DC Output Diode Current, VO < GND
–50mA
IO
DC Output Current, VO > VCC
IIK
Output at HIGH State
64mA
Output at LOW State
128mA
ICC
DC Supply Current per Supply Pin
±64mA
IGND
DC Ground Current per Ground Pin
±128mA
TSTG
Storage Temperature
–65°C to +150°C
Note:
1. IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VI
Parameter
Min
Max
Units
Supply Voltage
2.7
3.6
V
Input Voltage
0
5.5
V
IOH
HIGH-Level Output Current
–32
mA
IOL
LOW-Level Output Current
64
mA
TA
Free-Air Operating Temperature
–40
85
°C
0
10
ns/V
∆t / ∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
4
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Absolute Maximum Ratings
T A =–40°C to +85°C
Symbol
Parameter
VCC (V)
2.7
Conditions
II = –18mA
VIK
Input Clamp Diode Voltage
VIH
Input HIGH Voltage
2.7–3.6
VIL
Input LOW Voltage
2.7–3.6
VO ≤ 0.1V or
VO ≥ VCC – 0.1V
VOH
Output HIGH Voltage
2.7–3.6
IOH = –100µA
Output LOW Voltage
II(HOLD)
II(OD)(3)
II
Max. Units
–1.2
2.0
0.8
VCC–0.2
3.0
IOH = –32mA
2.0
IOL = 100µA
0.2
IOL = 24mA
0.5
IOL = 16mA
0.4
IOL = 32mA
0.5
IOL = 64mA
0.55
75
VI = 2.0V
–75
Bushold Input Minimum
Drive
3.0
Bushold Input Over-Drive
Current to Change State
3.0
Input Current
3.6
VI = 5.5V
10
Control Pins
3.6
VI = 0V or VCC
±1
Data Pins
3.6
VI = 0V
–5
VI = VCC
1
(4)
500
(5)
–500
V
V
2.7
VI = 0.8V
V
V
2.4
3.0
(3)
Typ.(2)
IOH = –8mA
2.7
VOL
Min.
V
µA
µA
µA
0V ≤ VI or VO ≤ 5.5V
±100
µA
VO = 0.5V to 3.0V,
VI = GND or VCC
±100
µA
VO = 0.5V
–5
µA
3.6
VO = 3.0V
5
µA
3-STATE Output Leakage
Current
3.6
VCC < VO ≤ 5.5V
10
µA
ICCH
Power Supply Current
3.6
Outputs HIGH
0.19
mA
ICCL
Power Supply Current
3.6
Outputs LOW
5
mA
IOFF
Power Off Leakage Current
0
IPU/PD
Power up/down 3-STATE
Output Current
0–1.5V
IOZL
3-STATE Output Leakage
Current
3.6
IOZH
3-STATE Output Leakage
Current
IOZH+
ICCZ
Power Supply Current
3.6
Outputs Disabled
0.19
mA
ICCZ+
Power Supply Current
3.6
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
0.19
mA
∆ICC
Increase in Power Supply
Current(6)
3.6
One Input at VCC – 0.6V,
Other Inputs at VCC or
GND
0.2
mA
Notes:
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. Applies to bushold versions only (74LVTH373).
4. An external driver must source at least the specified current to switch from LOW-to-HIGH.
5. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
6. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
5
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
DC Electrical Characteristics
TA = 25°C
Conditions
Symbol
Parameter
VCC (V)
CL = 50pF, RL = 500Ω
VOLP
Quiet Output Maximum
Dynamic VOL
3.3
(8)
VOLV
Quiet Output Minimum
Dynamic VOL
3.3
(8)
Min.
Typ.
Max.
Units
0.8
V
–0.8
V
Notes:
7. Characterized in SOIC package. Guaranteed parameter, but not tested.
8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = –40°C to +85°C,
CL = 50pF, RL = 500Ω
VCC = 3.3V ±0.3V
Symbol
tPHL
Parameter
Typ.(9)
Min.
VCC = 2.7V
Max.
Min.
Max.
Units
ns
Propagation Delay,
Dn to On
1.5
4.5
1.5
5.0
1.5
4.5
1.5
4.9
1.7
4.6
1.7
4.9
tPLH
Propagation Delay,
LE to On
1.7
4.5
1.7
5.0
tPZL
Output Enable Time
tPLH
tPHL
tPZH
tPLZ
Output Disable Time
tPHZ
1.3
4.8
1.3
5.9
1.3
4.8
1.3
5.5
1.9
4.6
1.9
4.9
1.9
4.6
1.9
4.9
ns
ns
ns
tW
LE Pulse Width
3.0
3.0
ns
tS
Setup Time, Dn to LE
1.1
1.0
ns
tH
Hold Time, Dn to LE
1.4
1.4
ns
Note:
9. All typical values are at VCC = 3.3V, TA = 25°C.
Capacitance(10)
Symbol
CIN
COUT
Parameter
Conditions
Typical
Units
Input Capacitance
VCC = OPEN, VI = 0V or VCC
3
pF
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
5
pF
Note:
10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
6
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Dynamic Switching Characteristics(7)
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.51
0.35
PIN ONE
INDICATOR
0.25
M
0.65
1.27
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
GAGE PLANE
(R0.10)
0.10 C
0.30
0.10
0.25
8°
0°
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
(1.40)
DETAIL A
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
7
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
8
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
9
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PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
10
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
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