LT3510 Monolithic Dual Tracking 2A Step-Down Switching Regulator DESCRIPTION FEATURES n n n n n n n n n n n n The LT®3510 is a dual current mode PWM step-down DC/DC converter with two internal 2.5A switches. Independent input voltage, feedback, soft-start and power good pins for each channel simplify complex power supply tracking/sequencing requirements. Wide Input Range: 3.1V to 25V Two Switching Regulators with 2A Output Capability Independent Supply to Each Regulator Adjustable/Synchronizable Fixed Frequency Operation from 250kHz to 1.5MHz Antiphase Switching Outputs Can be Paralleled Independent, Sequential, Ratiometric or Absolute Tracking Between Outputs Independent Soft-Start and Power Good Pins Enhanced Short-Circuit Protection Low Dropout: 95% Maximum Duty Cycle Low Shutdown Current: <10μA 20-Lead TSSOP Package with Exposed Leadframe Both converters are synchronized to either a common external clock input or a resistor programmable fixed 250kHz to 1.5MHz internal oscillator. At all frequencies, a 180° phase relationship between channels is maintained, reducing voltage ripple and component size. Programmable frequency allows for optimization between efficiency and external component size. Minimum input-to-output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles, only switching off when the boost capacitor needs recharging, resulting in ~95% maximum duty cycle. APPLICATIONS n n n n n n DSP Power Supplies Disc Drives DSL/Cable Modems Wall Transformer Regulation Distributed Power Regulation PCI Cards Each output can be independently disabled using its own soft-start pin, or by using the SHDN pin the entire part can be placed in a low quiescent current shutdown mode. The LT3510 is available in a 20-lead TSSOP package with exposed leadframe for low thermal resistance. , LT, LTC, and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V and 1.8V Dual 2A Step-Down Converter with Output Tracking Efficiency 4.7μF VIN1 SHDN 4.7μH PMEG4005 VOUT1 3.3V 2A PMEG4005 0.47μF BST1 BST2 SW1 SW2 B360A 24.9k 470pF 8.06k 10pF 100 61.9k VOUT2 1.8V 2A 100μF 10k 70 VOUT = 1.8V 60 50 30 VIN = 12V IOUT2 = 0A FREQUENCY = 500kHz 10 470pF VOUT = 2.5V 40 20 40.2k 40.2k VOUT = 3.3V 80 3.3μH 0.47μF IND2 VOUT2 PG1 PG2 FB1 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND VOUT = 5V 90 B360A LT3510 IND1 VOUT1 47μF VIN2 RT/SYNC EFFICIENCY (%) VIN 12V 0 47pF 8.06k 0.1μF 0 0.5 1.5 1 LOAD CURRENT (A) 2 3510 TA01b 3510 TA01a 3510fc 1 LT3510 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW VIN1/2, SHDN, PG1/2 ...................................... 25V/–0.3V SW1/2 ....................................................................VIN1/2 BST1/2 ........................................................... 35V/–0.3V BST1/2 Pins Above SW1/2........................................25V IND1/2 .....................................................................±4A VOUT1/2 ........................................................ VIN1/2/–0.3V FB1/2, SS1/2, RT/SYNC ............................................5.5V VC1/2 ......................................................................±1mA Operating Junction Temperature Range LT3510EFE (Notes 2, 8) ..................... –40°C to 125°C LT3510IFE (Notes 2, 8) ...................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C VIN1 1 20 BST1 SW1 2 19 SS/TRACK1 IND1 3 18 VC1 VOUT1 4 17 FB1 PG1 5 PG2 6 15 SHDN VOUT2 7 14 FB2 IND2 8 13 VC2 SW2 9 12 SS/TRACK2 16 RT/SYNC 21 VIN2 10 11 BST2 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 45°C/W, θJC(PAD) = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3510EFE#PBF LT3510EFE#TRPBF LT3510FE 20-Lead TSSOP –40°C to 125°C LT3510IFE#PBF LT3510IFE#TRPBF LT3510FE 20-Lead TSSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3510EFE LT3510EFE#TR LT3510FE 20-Lead TSSOP –40°C to 125°C LT3510IFE LT3510IFE#TR LT3510FE 20-Lead TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open, unless otherwise specified. PARAMETER CONDITIONS SHDN Threshold VOUT1/2 = 0V, RT/SYNC = 133k SHDN Input Current VSHDN = 1.375V VSHDN = 1.225V Minimum Input Voltage Ch 1 (Note 3) VFB1/2 = 0V, VVOUT1/2 = 0V, VIND1/2 = 0V, RT/SYNC = 133k Minimum Input Voltage Ch 2 VFB1/2 = 0V, VVOUT1/2 = 0V, VIND1/2 = 0V Supply Shutdown Current Ch 1 VSHDN = 0V Supply Shutdown Current Ch 2 VSHDN = 0V l MIN TYP MAX 1.23 1.28 1.37 V 7 2 10 3 13 5 μA μA 2.8 3 V l UNITS 2.8 3 V 9 30 μA 0 5 μA Supply Quiescent Current Ch 1 VFB1/2 = 0.9V 3.5 5 mA Supply Quiescent Current Ch 2 VFB1/2 = 0.9V 200 500 μA Feedback Voltage Ch 1/2 VVC1/2 = 1V 0.8 0.816 V l 0.784 3510fc 2 LT3510 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX Feedback Voltage Line Regulation VVIN1/2 = 3V to 25V l Feedback Voltage Offset Ch 1 to Ch 2 VVC1/2 = 1V l –16 Feedback Bias Current Ch 1/2 VFB1/2 = 0.8V, VVC1/2 = 1V l –200 –1 0 1 % 0 16 mV 75 200 nA Error Amplifier gm Ch 1/2 VVC1/2 = 1V, IVC1/2 = ±5μA l 150 275 450 μmho Error Amplifier Gain Ch 1/2 Error Amplifier to Switch Gain Ch 1/2 UNITS 1000 V/V 2.2 A/V Error Amplifier Source Current Ch 1/2 VFB1/2 = 0.6V, VVC1/2 = 1V 10 15 25 μA Error Amplifier Sink Current Ch 1/2 VFB1/2 = 1V, VVC1/2 = 1V 15 20 30 μA Error Amplifier High Clamp Ch 1/2 VFB1/2 = 0.7V 1.75 2.0 2.25 V 0.5 0.7 1.0 V 2.5 3.25 4 μA Error Amplifier Switching Threshold Ch 1/2 VOUT1/2 = 5V, RT/SYNC = 133k Soft-Start Source Current Ch 1/2 VFB1/2 = 0.6V, VSS1/2 = 0.4V l Soft-Start VOH Ch 1/2 VFB1/2 = 0.9V 1.9 2 2.4 V Soft-Start Sink Current Ch 1/2 VFB1/2 = 0.6V, VSS1/2 = 1V 200 600 1000 μA Soft-Start VOL Ch 1/2 VFB1/2 = 0V 50 80 125 mV –16 0 16 mV 0.5 1.5 2 mA l Soft-Start to Feedback Offset Ch 1/2 VVC1/2 = 1V, VSS1/2 = 0.4V Soft-Start Sink Current Ch 1/2 POR VSS1/2 = 0.4V (Note 4), VVC = 1V Soft-Start POR Threshold Ch 1/2 VFB1/2 = 0V (Note 4) 55 80 105 mV Soft-Start Switching Threshold Ch 1/2 VFB1/2 = 0V 30 50 70 mV Power Good Leakage Ch 1/2 VFB1/2 = 0.9V, VPG1/2 = 25V, VVIN1/2 = 25V, VOUT = 5V 0 1 μA l Power Good Threshold Ch 1/2 VFB1/2 Rising, PG1/2 = 20k to 5V 87 90 93 % Power Good Hysteresis Ch 1/2 VFB1/2 Falling, PG1/2 = 20k to 5V 20 30 50 mV Power Good Sink Current Ch 1/2 VFB1/2 = 0.65V, VPG1/2 = 0.4V 400 800 1200 μA Power Good Shutdown Sink Current Ch 1/2 VVIN1/2 = 2V, VFB1/2 = 0V, VPG1/2 = 0.4V 10 50 100 μA RT/SYNC Reference Voltage VFB1/2 = 0.9V, IRT/SYNC = –40μA 0.93 0.975 1 V Switching Frequency RT/SYNC = 133k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V RT/SYNC = 15.4k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V 200 1.2 250 1.5 300 1.8 kHz MHz Switching Phase Angle Ch A to Ch B RT/SYNC = 133k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V 120 180 210 Deg Minimum Boost for 100% Duty Cycle Ch 1/2 VFB1/2 = 0.7V, IRT/SYNC = –35μA (Note 5), VOUT = 0V SYNC Frequency Range VBST1/2 = VSW + 3V 250 SYNC Switching Phase Angle Ch A to Ch B SYNC = 250kHz, VBST1/2 = VSW + 3V 120 IND + VOUT Current Ch 1/2 VVOUT1/2 = 0V, VFB1/2 = 0.9V VVOUT1/2 = 5V 40 IND to VOUT Maximum Current Ch 1/2 VVOUT1/2 = 0.5V (Note 6), VFB1/2 = 0.7V, VBST1/2 = 20V VVOUT1/2 = 5V (Note 6), RT/SYNC = 133k, VBST1/2 = 20V 2.25 2.5 Switch Leakage Current Ch 1/2 VSW1/2 = 0V, VVIN1/2 = 25V l 0 50 μA Switch Saturation Voltage Ch 1/2 ISW1/2 = 2A, VBST1/2 = 20V, VFB1/2 = 0.7V l 250 400 mV Boost Current Ch 1/2 ISW1/2 = 2A, VBST1/2 = 20V, VFB1/2 = 0.7V 50 100 mA Minimum Boost Voltage Ch 1/2 ISW1/2 = 2A, VBST1/2 = 20V, VFB1/2 = 0.7V (Note 7) 1.4 2.5 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 1.7 25 2 V 1500 kHz 180 210 Deg 70 0 100 1 μA μA 2.8 2.8 4 4 A A Note 2: The LT3510EFE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The 3510fc 3 LT3510 ELECTRICAL CHARACTERISTICS LT3510IFE is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. Note 3: Minimum input voltage is defined as the voltage where internal bias lines are regulated so that the reference voltage and oscillator remain constant. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: An internal power-on reset (POR) latch is set on the positive transition of the SHDN pin through its threshold. The output of the latch activates current sources on each SS pin which typically sink 1.5mA, discharging the SS capacitor. The latch is reset when both SS pins are driven below the soft-start POR threshold or the SHDN pin is taken below its threshold. Note 5: To enhance dropout operation, the output switch will be turned off for the minimum off time only when the voltage across the boost capacitor drops below the minimum boost for 100% duty cycle threshold. Note 6: The IND to VOUT maximum current is defined as the value of current flowing from the IND pin to the VOUT pin which resets the switch latch when the VC pin is at its high clamp. Note 7: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS Feedback Voltage vs Temperature 3.0 1.05 0.816 0.811 0.801 VOLTAGE (V) 0.806 1.01 0.99 0.97 0.791 0.786 –50 –25 SHUTDOWN THRESHOLD VOLTAGE 1.5 50 25 75 0 TEMPERATURE (°C) 100 0.5 0.95 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 3510 G02 CURRENT (μA) VVIN1 10 8 6 4 2 VVIN2 75 50 25 TEMPERATURE (°C) 100 125 3510 G05 50 25 75 0 TEMPERATURE (°C) 4.0 3.8 3.8 3.6 3.6 3.4 3.4 3.2 3.0 2.8 3.2 3.0 2.6 2.4 2.4 2.2 2.2 50 25 0 75 TEMPERATURE (°C) 100 125 3510 G07 VOUT = 5V 2.8 2.6 –25 125 IND to VOUT Maximum Current vs Temperature 4.0 2.0 –50 100 3510 G04 CURRENT (A) 14 0 0 –50 –25 125 Soft-Start Source Current vs Temperature 16 0 –50 –25 100 3510 G03 Shutdown Quiescent Current vs Temperature CURRENT (μA) 2.0 1.0 0.796 12 MINIMUM INPUT VOLTAGE 2.5 1.03 VOLTAGE (V) VOLTAGE (V) Shutdown Threshold and Minimum Input Voltage vs Temperature RT/SYNC Voltage vs Temperature VOUT = 0V 2.0 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 3510 G30 3510fc 4 LT3510 TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start to Feedback Offset Voltage vs Temperature VC Switching Threshold Voltage vs Temperature Power Good Threshold Voltage vs Temperature 1000 4 800 780 3 900 760 0 –1 VOLTAGE (V) 1 740 800 VOLTAGE (V) VOLTAGE (mV) 2 VOUT = 5V 700 VOUT = 0V 600 620 –25 75 50 25 TEMPERATURE (°C) 0 100 400 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 600 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 3510 G09 3510 G08 Power Good Sink Current vs Temperature 950 230 290 900 210 280 850 190 800 170 MINIMUM ON TIME FREQUENCY (kHz) TIME (ns) 300 150 130 MINIMUM OFF TIME 200 RT/SYNC = 133k 190 180 PHASE 270 170 160 260 250 150 FREQUENCY 240 140 650 110 230 130 600 90 220 120 550 70 210 110 500 –50 50 –50 200 –50 50 25 0 75 TEMPERATURE (°C) 100 125 –25 50 25 0 75 TEMPERATURE (°C) 100 3510 G11 186 FREQUENCY 175 1500 170 1450 165 160 1400 PHASE (DEG) 180 164 2000 185 1550 50 25 75 0 TEMPERATURE (°C) 100 150 125 3510 G14 182 MAXIMUM SYNCHRONIZATION FREQUENCY 1500 1000 SYNCHRONIZATION FREQUENCY = 250kHz 180 178 176 174 MINIMUM SYNCHRONIZATION FREQUENCY 500 155 1350 –50 –25 100 125 188 2500 190 PHASE 100 Channel Phase vs Temperature with External Synchronization 195 FREQUENCY (kHz) 1600 50 25 0 75 TEMPERATURE (°C) 3510 G13 Synchronization Clock Frequency Range vs Temperature 200 RRT/SYNC = 15.4k –25 3510 G12 Switching Frequency and Channel Phase vs Temperature 1650 125 PHASE (DEG) –25 PHASE (DEG) 250 700 125 Switching Frequency and Channel Phase vs Temperature Minimum Switching Times vs Temperature 750 100 3510 G10 1000 CURRENT (μA) FALLING 680 640 500 –4 –50 FREQUENCY (kHz) 700 660 –2 –3 RISING 720 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 172 SYNCHRONIZATION FREQUENCY = 1500kHz 170 100 125 3510 G15 168 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3510 G16 3510fc 5 LT3510 TYPICAL PERFORMANCE CHARACTERISTICS Frequency and Phase vs RT/SYNC Pin Resistance External Sync Duty Cycle Range vs External Sync Frequency 100 1600 190 90 1400 185 50 40 1200 180 1000 175 800 MINIMUM CLOCK DUTY CYCLE 600 165 400 160 200 155 100 500 1000 1250 750 FREQUENCY (kHz) 1500 0 20 40 60 80 100 RESISTANCE (kΩ) 120 0 0.5 1.5 1.0 0.5 100 90 90 80 85 70 80 75 70 30 20 55 10 –25 50 25 0 75 TEMPERATURE (°C) 100 0 125 3510 G23 6.0 Minimum Input Voltage vs Load Current 7.5 VOUT = 3.3V 7.0 4.0 5.0 6.5 VOLTAGE (V) 5.5 VOLTAGE (V) 4.5 4.5 4.0 100 1000 CURRENT (mA) 6.0 5.5 RUNNING 3.5 5.0 3.0 10 VOUT = 5V RUNNING 2.0 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOLTAGE (V) 0 3510 G22 VOUT = 2.5V 10000 3510 G24 1.9 40 Minimum Input Voltage vs Load Current RUNNING 1.7 50 60 Minimum Input Voltage vs Load Current 2.5 1.1 1.3 1.5 CURRENT (A) 60 65 3510 G21 3.0 0.9 VOUT + IND Current vs VOUT Voltage 100 50 –50 125 3.5 0.7 3510 G19 95 CURRENT (μA) VOLTAGE (V) 150 100 2.0 50 25 0 75 TEMPERATURE (°C) 140 CURRENT (μA) 2.5 5.0 100 VOUT + IND Current vs Temperature Minimum Boost Voltage vs Temperature –25 –50°C 3510 G18 3510 G17 0 –50 150 50 10 0 250 170 PHASE 25°C VOLTAGE (mV) FREQUENCY (kHz) 60 20 125°C 200 PHASE (DEG) DUTY CYCLE (%) 70 30 250 FREQUENCY MAXIMUM CLOCK DUTY CYCLE 80 VOLTAGE (V) Switch Saturation Voltage vs Switch Current 1 10 100 1000 CURRENT (mA) 10000 3510 G25 4.5 1 10 100 1000 CURRENT (mA) 10000 3510 G26 3510fc 6 LT3510 TYPICAL PERFORMANCE CHARACTERISTICS 6 1500 LOAD = 1A 5 1500 VOUT = 3.3V IRIPPLE = 1A L = 2.2μH 1250 VOUT = 3.3V 2 0 2 2.5 3 4.5 5 3.5 4 INPUT VOLTAGE (V) 5.5 L = 3.3μH 750 L = 4.7μH 500 FREQUENCY 1.5MHz 250kHz 1 1000 6 FREQUENCY (kHz) L = 2.2μH 4 3 VOUT = 5V IRIPPLE = 1A 1250 VOUT = 5V FREQUENCY (kHz) OUTPUT VOLTAGE (V) Inductor Value vs Frequency for 2A Maximum Load Current Inductor Value vs Frequency for 2A Maximum Load Current Dropout Operation L = 3.3μH 1000 L = 4.7μH 750 L = 6.8μH 500 L = 6.8μH L = 10μH 250 250 7 9 11 13 15 17 19 21 INPUT VOLTAGE (V) 3510 G27 23 25 3510 G28 10 12.5 15 17.5 20 INPUT VOLTAGE (V) 22.5 25 3510 G29 PIN FUNCTIONS VIN1 (Pin 1): The VIN1 pin powers the internal control circuitry for both channels and is monitored by the undervoltage lockout comparator. The VIN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The VIN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the onchip power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective VIN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. IND1/IND2 (Pins 3, 8): The IND pin is the input to the on-chip sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset, disabling the output switch. Bias current flows out of the IND pin when IND is less than 1.6V. VOUT1/VOUT2 (Pins 4, 7): The VOUT pin is the output to the on-chip sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset, disabling the output switch. Bias current flows out of the VOUT pin when VOUT is less than 1.6V. PG1/PG2 (Pins 5, 6): The power good pin is an open-collector output that sinks current when the feedback falls below 90% of its nominal regulating voltage. For VIN1 above 1V, its output state remains true, although during shutdown, VIN1 undervoltage lockout or thermal shutdown, its current sink capability is reduced. The PG pins can be left open circuit or tied together to form a single power good signal. VIN2 (Pin 10): The VIN2 pin is the collector of channel 2’s on-chip power NPN switch. This pin is independent of VIN1 and may be connected to the same or a separate supply. In either case, high dI/dt edges are present and decoupling to ground must be used close to this pin. SS1/SS2 (Pins 19, 12): The SS1/2 pins control the softstart and sequence of their respective outputs. A single capacitor from the SS pin to ground determines the outpt ramp rate. For soft-start and output tracking/sequencing details, see the Applications Information section. VC1/VC2 (Pins 18, 13): The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally used for frequency compensation, but can also be used as a current clamp or control loop override. If the error amplifier drives VC above the maximum switch current level, a voltage clamp activates. 3510fc 7 LT3510 PIN FUNCTIONS This indicates that the output is overloaded and current is pulled from the SS pin, reducing the regulation point. FB1/FB2 (Pins 17, 14): The FB pin is the negative input to the error amplifier. The output switches regulate this pin to 0.8V, with respect to the exposed ground pad. Bias current flows out of the FB pin. SHDN (Pin 15): The shutdown pin is used to turn off both channels and control circuitry to reduce quiescent current to a typical value of 9μA. The accurate 1.28V threshold and input current hysteresis can be used as an undervoltage lockout, preventing the regulator from operating until the input voltage has reached a predetermined level. Force the SHDN pin above its threshold or let it float for normal operation. RT/SYNC (Pin 16): This RT/SYNC pin provides two modes of setting the constant switch frequency. Connecting a resistor from the RT/SYNC pin to ground will set the RT/SYNC pin to a typical value of 0.975V. The resultant switching frequency will be set by the resistor value. The minimum value of 15.4k and maximum value of 133k sets the switching frequency to 1.5MHz and 250kHz respectively. Driving the RT/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchronization occurs on the rising edge of the clock signal after the clock signal is detected, with switch 1 in phase with the synchronization signal. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the oscillator charging current to maintain a constant oscillator amplitude. Hence, the slope compensation and channel phase relationship remain unchanged. If the clock signal is removed, the oscillator reverts to resistor mode and reapplies the 0.975V bias to the RT/SYNC pin after the synchronization detection circuitry times out. The clock source impedance should be set such that the current out of the RT/SYNC pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. BST1/BST2 (Pins 20, 11): The BST pin provides a higher than VIN base drive to the power NPN to ensure a low switch drop. A comparator to VIN imposes a minimum off time on the SW pin if the BST pin voltage drops too low. Forcing a SW off time allows the boost capacitor to recharge. Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is the only ground connection for the device. The Exposed Pad should be soldered to a large copper area to reduce thermal resistance. The GND pin is common to both channels and also serves as small-signal ground. For ideal operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns. 3510fc 8 LT3510 BLOCK DIAGRAM RT/SYNC R3 VIN1 3μA OSCILLATOR AND CLK2 AGC INTERNAL REGULATOR AND REFERENCE C DROPOUT ENHANCEMENT SLOPE COMPENSATION 7μA 3 SHDN + 1.28V VIN ONE CHANNEL CLK1 S – + C3 PRE DRIVER CIRCUITRY Q R + – SHUTDOWN COMPARATOR BST SW L1 IND POR UNDERVOLTAGE TSD + – + D VOUT 0.8V C + – LOWEST VOLTAGE R1 FB R2 VC CLAMP S R Q POWER GOOD COMPARATOR 3.25A + – GND D SOFT-START RESET COMPARATOR PGOOD – + SS CLAMP + + 80mV 0.72V 3510 BD SS VC C Figure 1. Block Diagram (One of Two Switching Regulators Shown) APPLICATIONS INFORMATION The LT3510 is dual channel, constant frequency, current mode buck converter with internal 2A switches. Each channel is identical with a common shutdown pin, internal regulator, oscillator, undervoltage detect, thermal shutdown and power-on reset. If the SHDN pin is taken below its 1.28V threshold the LT3510 will be placed in a low quiescent current mode. In this mode the LT3510 typically draws 9μA from VIN1 and <1μA from VIN2. In shutdown mode the PG is active with a typical sink capability of 50μA for VIN1 voltage greater than 2V. When the SHDN pin is opened or driven above 1.28V, the internal bias circuits turn on generating an internal regulated voltage, 0.8VFB, 0.975V RT/SYNC references, and a POR signal which sets the soft-start latch. As the RT/SYNC pin reaches its 0.975V regulation point, the internal oscillator will start generating two clock signals 180° out of phase for each regulator at a frequency determined by the resistor from the RT/SYNC pin to ground. Alternatively, if a synchronization signal is detected by the LT3510 at the RT/SYNC pin, clock signals 180° out of phase 3510fc 9 LT3510 APPLICATIONS INFORMATION will be generated at the incoming frequency on the rising edge of the synchronization pulse with switch 1 in phase with the synchronization signal. In addition, the internal slope compensation will be automatically adjusted to prevent subharmonic oscillation during synchronization. The two regulators are constant frequency, current mode step-down converters. Current mode regulators are controlled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180°, shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. The Block Diagram in Figure 1 shows only one of the switching regulators whose operation will be discussed below. The additional regulator will operate in a similar manner with the exception that its clock will be 180° out of phase with the other regulator. When, during power up, the POR signal sets the soft-start latch, both SS pins will be discharged to ground to ensure proper start-up operation. When the SS pin voltage drops below 80mV, the VC pin is driven low disabling switching and the soft-start latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 3.25μA. As the voltage rises above 80mV on the SS pin, the VC pin will be driven high by the error amplifier. When the voltage on the VC pin exceeds 0.7V, the clock set pulse sets the driver flip-flop which turns on the internal power NPN switch. This causes current from VIN, through the NPN switch, inductor and internal sense resistor, to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the VC pin, the flip-flop is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor. The cycle is repeated with the start of each clock cycle. However, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the flip-flop will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the VC voltage, output regulation is achieved by the error amplifier continually adjusting the VC pin voltage. The error amplifier is a transconductance amplifier that compares the FB voltage to the lowest voltage present at either the SS pin or an internal 0.8V reference. Compensation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the VC pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maximum current dictated by the VC pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. When overload is removed, the output will soft-start from the overload regulation point. VIN1 undervoltage detection or thermal shutdown will set the soft-start latch, resulting in a complete soft-start sequence. The switch driver operates from either the VIN or BST voltage. An external diode and capacitor are used to generate a drive voltage higher than VIN to saturate the output NPN and maintain high efficiency. If the BST capacitor voltage is sufficient, the switch is allowed to operate to 100% duty cycle. If the boost capacitor discharges towards a level insufficient to drive the output NPN, a BST pin comparator forces a minimum cycle off time, allowing the boost capacitor to recharge. A power good comparator with 30mV of hysteresis trips at 90% of regulated output voltage. The PG output is an open-collector NPN that is off when the output is in regulation allowing a resistor to pull the PG pin to a desired voltage. 3510fc 10 LT3510 APPLICATIONS INFORMATION Choosing the Output Voltage 1600 The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: 1400 185 FREQUENCY (kHz) FREQUENCY 1200 180 1000 175 R2 should be 10k or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure 1. 800 PHASE 600 165 400 160 200 155 100 0 20 40 Choosing the Switching Frequency The LT3510 switching frequency is set by resistor R3 in Figure 1. The RT/SYNC pin is internally regulated at 0.975V. Setting resistor R3 sets the current in the RT/SYNC pin which determines the oscillator frequency as illustrated in Figure 2. The switching frequency is typically set as high as possible to reduce overall solution size. The LT3510 employs techniques to enhance dropout at high frequencies but efficiency and maximum input voltage decrease due to switching losses and minimum switch on times. The maximum recommended frequency can be approximated by the equation: Frequency (Hz) = VOUT + VD 1 • VIN – VSW + VD tON(MIN) where VD is the forward voltage drop of the catch diode (D1 Figure 2), VSW is the voltage drop of the internal switch, and tON(MIN) in the minimum on time of the switch, all at maximum load current. 170 60 80 100 RESISTANCE (kΩ) 120 140 PHASE (DEG) ⎛V ⎞ R1 = R2 • ⎜ OUT – 1⎟ ⎝ 0.8 V ⎠ 190 150 3510 F02 Figure 2. Frequency and Phase vs RT/SYNC Resistance The following example along with the data in Table 1 illustrates the tradeoffs of switch frequency selection. Example. VIN = 25V, VOUT = 3.3V, IOUT = 2.5A, Temperature = 0°C to 85°C tON(MIN) = 200ns (85°C from the Typical Performance Characteristics graph), VD = 0.6V, VSW = 0.4V (85°C) 3.3 + 0.6 1 Max Frequency = • ~ 750 kHz 25 – 0.4 + 0.6 200e-9 RT /SYNC ~ 42k (Figure 2) Input Voltage Range Once the switching frequency has been determined, the input voltage range of the regulator can be determined. The minimum input voltage is determined by either the LT3510’s minimum operating voltage of ~2.8V, or by its Table 1. Efficiency and Size Comparisons for Different RRT/SYNC Values. 3.3V Output EFFICIENCY FREQUENCY RT/SYNC VVIN1/2 = 12V VIN(MAX)† L* C* L + C AREA 1.2MHz 20.5k 79.0% 16 1.5μH 22μF 63mm2 1.0MHz 26.7k 80.9% 18 2.2μH 47μF 66mm2 750kHz 38.3k 81.2% 22 3.3μH 47μF 66mm2 500kHz 61.9k 82.0% 24 4.7μH 47μF 66mm2 250kHz 133k 83.9% 24 10μH 100μF 172mm2 †V IN(MAX) is defined as the highest input voltage that maintains constant output voltage ripple. *Inductor and capacitor values chosen for stability and constant ripple current. 3510fc 11 LT3510 APPLICATIONS INFORMATION 6.0 maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on during a clock cycle. Unlike 5.5 DCMAX = 1 1+ B where B is 2A divided by the typical boost current from the Electrical Characteristics. This leads to a minimum input voltage of: V +V VIN(MIN) = OUT D – VD + VSW DCMAX where VSW is the voltage drop of the internal switch. Figure 3 shows a typical graph of minimum input voltage vs load current for the 3.3V and 1.8V application on the first page of this data sheet. The maximum input voltage is determined by the absolute maximum ratings of the VIN and BST pins and by the frequency and minimum duty cycle. The minimum duty cycle is defined as : DCMIN = tON(MIN) • Frequency Maximum input voltage as: VIN(MAX ) = VOUT + VD – VD + VSW DCMIN Note that the LT3510 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the VIN and BST pins are not violated. However operation in this region of input voltage will exhibit pulse skipping behavior. VOLTAGE (V) most fixed frequency regulators, the LT3510 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. Forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. This operation has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. The resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: 1 VOUT = 3.3V 5.0 START-UP 4.5 4.0 3.5 RUNNING 3.0 1 10 100 1000 CURRENT (mA) 10000 3510 F03 Figure 3. Minimum Input Voltage vs Load Current Example: VOUT = 3.3V, IOUT = 1A, Frequency = 1MHz, Temperature = 25°C VSW = 0.1V, B = 40 (from boost characteristics specification), VD = 0.4V, tON(MIN) = 200ns DCMAX = 1 1 1+ 40 VIN(MIN) = = 98% 3.3 + 0.4 – 0.4 + 0.1 = 3.48 V 0.98 DCMIN = tMIN(ON) • f = 0.200 VIN(MAX ) = 3.3 + 0.4 – 0.4 + 0.1 = 18.2V 0.200 Inductor Selection and Maximum Output Current A good first choice for the inductor value is: L= ( VIN – VOUT ) • VOUT VIN • f where f is frequency in MHz and L is in μH. With this value the maximum load current will be ~2A, independent of input voltage. The inductor’s RMS current rating must be greater than your maximum load current 3510fc 12 LT3510 APPLICATIONS INFORMATION and its saturation current should be about 30% higher. To keep efficiency high, the series resistance (DCR) should be less than 0.05Ω. For applications with a duty cycle of about 50%, the inductor value should be chosen to obtain an inductor ripple current less than 40% of peak switch current. Of course, such a simple design guide will not always result in the optimum inductor for your application. A larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. If your load is lower than 2A, then you can decrease the value of the inductor and operate with higher ripple current. This allows you to use a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-topeak inductor ripple current. The LT3510 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT3510 will deliver depends on the current limit, the inductor value, switch frequency, and the input and output voltages. The inductor is chosen based on output current requirements, output voltage ripple requirements, size restrictions and efficiency goals. 2.5A over the entire duty cycle range. The maximum output current is a function of the chosen inductor value: IOUT(MAX ) = ILIM – If the inductor value is chosen so that the ripple current is small, then the available output current will be near the switch current limit. One approach to choosing the inductor is to start with the simple rule given above, look at the available inductors and choose one to meet cost or space goals. Then use these equations to check that the LT3510 will be able to deliver the required output current. Note again that these equations assume that the inductor current is continuous. Discontinuous operation occurs when IOUT is less than IL/2 as calculated above. Figure 4 illustrates the inductance value needed for a 3.3V output with a maximum load capability of 2A. Referring to Figure 4, an inductor value between 3.3μH and 4.7μH will be sufficient for a 15V input voltage and a switch frequency of 750kHz. There are several graphs in the Typical Performance Characteristics section of this data sheet that show inductor selection as a function of input voltage and switch frequency for several popular output voltages and output ripple currents. Also, low inductance When the switch is off, the inductor sees the output voltage plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor: (1– DC)( VOUT + VD ) L•f where f is the switching frequency of the LT3510 and L is the value of the inductor. The peak inductor and switch current is: ISW(PK ) = ILPK = IOUT + ΔIL 2 1500 L = 2.2μH VOUT = 5V IRIPPLE = 1A 1250 FREQUENCY (kHz) ΔIL = ΔIL ΔI = 2.5 – L 2 2 L = 3.3μH 1000 L = 4.7μH 750 L = 6.8μH 500 L = 10μH 250 10 12.5 15 17.5 20 INPUT VOLTAGE (V) 22.5 25 3510 F04 To maintain output regulation, this peak current must be less than the LT3510’s switch current limit ILIM. ILIM is Figure 4. Inductor Values for 2A Maximum Load Current vs Frequency and Input Voltage 3510fc 13 LT3510 APPLICATIONS INFORMATION may result in discontinuous mode operation, which is okay, but further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology Application Note 44. Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. See Application Note 19 for more information. Input Capacitor Selection Bypass the inputs of the LT3510 circuit with a 4.7μF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3510 and to force this very high frequency switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency to do this effectively, and it must have an adequate ripple current rating. With two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor RMS current is not simple. However, a conservative value is the RMS input current for the channel that is delivering most power (VOUT • IOUT). This is given by: I CIN(RMS) = IOUT VOUT • ( VIN – VOUT ) VIN < IOUT 2 and is largest when VIN = 2VOUT (50% duty cycle). As the second, lower power channel draws input current, the input capacitor’s RMS current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. Considering that the maximum load current from a single channel is ~2A, RMS ripple current will always be less than 1A. The frequency, VIN to VOUT ratio, and maximum load current requirement of the LT3510 along with the input supply source impedance, determine the energy storage require- ments of the input capacitor. Determine the worst-case condition for input ripple current and then size the input capacitor such that it reduces input voltage ripple to an acceptable level. Typical values for input capacitors run from 10μF at low frequencies to 2.2μF at higher frequencies. The combination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors make them the preferred choice. The low ESR results in very low voltage ripple and the capacitors can handle plenty of ripple current. They are also comparatively robust and can be used in this application at their rated voltage. X5R and X7R types are stable over temperature and applied voltage, and give dependable service. Other types (Y5V and Z5U) have very large temperature and voltage coefficients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. While they will still handle the RMS ripple current, the input voltage ripple may become fairly large, and the ripple current may end up flowing from your input supply or from other bypass capacitors in your system, as opposed to being fully sourced from the local input capacitor. An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1μF ceramic capacitor in parallel with a low ESR tantalum capacitor. For the electrolytic capacitor, a value larger than 10μF will be required to meet the ESR and ripple current requirements. Because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor. Be sure to place the 1μF ceramic as close as possible to the VIN and GND pins on the IC for optimal noise immunity. When the LT3510’s input supplies are operated at different input voltages, an input capacitor sized for that channel should be placed as close as possible to the respective VIN pins. A final caution regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the LT3510. The solution is to 3510fc 14 LT3510 APPLICATIONS INFORMATION either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. For details, see Application Note 88. The RMS content of this ripple is very low, and the RMS current rating of the output capacitor is usually not of concern. Output Capacitor Selection Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. For a 5% overshoot, this requirement becomes: Typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switching frequency. This means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. With an allowable 5% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: CVOUT = Max Load Step Frequency • 0.05 • VOUT Example: VOUT = 3.3V, Frequency = 1MHz, Max Load Step = 2A CVOUT = 2 = 12μF 1e6 • 0.05 • 3.3V The calculated value is only a suggested starting value. Increase the value if transient response needs improvement or reduce the capacitance if size is a priority. The output capacitor filters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and to stabilize the LT3510’s control loop. The switching frequency of the LT3510 determines the value of output capacitance required. Also, the current mode control loop doesn’t require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. Estimate output ripple with the following equations: VRIPPLE = ΔIL/(8f COUT) for ceramic capacitors, and VRIPPLE = ΔIL ESR for electrolytic capacitors (tantalum and aluminum) where ΔIL is the peak-to-peak ripple current in the inductor. COUT ⎛ I ⎞ > 10 L ⎜ LIM ⎟ ⎝ VOUT ⎠ 2 Finally, there must be enough capacitance for good transient performance. The last equation gives a good starting point. Alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. This topic is covered more thoroughly in the section on loop compensation. The high performance (low ESR), small size and robustness of ceramic capacitors make them the preferred type for LT3510 applications. However, all ceramic capacitors are not the same. As mentioned above, many of the high value capacitors use poor dielectrics with high temperature and voltage coefficients. In particular, Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and temperature extremes. Because the loop stability and transient response depend on the value of COUT, you may not be able to tolerate this loss. Use X7R and X5R types. You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer, lower ESR organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may give better transient response for large changes in load current. Table 2 lists several capacitor vendors. 3510fc 15 LT3510 APPLICATIONS INFORMATION Table 2 VENDOR TYPE SERIES Taiyo Yuden Ceramic X5R, X7R AVX Ceramic X5R, X7R Tantalum Kemet Tantalum TA Organic AL Organic T491, T494, T495 T520 A700 Sanyo TA/AL Organic POSCAP Panasonic AL Organic SP CAP TDK Ceramic X5R, X7R Catch Diode The diode D1 conducts current only during switch off time. Use a Schottky diode to limit forward voltage drop to increase efficiency. The Schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. Average forward current can be calculated from: ID( AVG) = IOUT • ( VIN – VOUT ) VIN The only reason to consider a larger diode is the worstcase condition of a high input voltage and shorted output. With a shorted condition, diode current will increase to a typical value of 3A, determined by the peak switch current limit of the LT3510. This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions can be tolerated. BST Pin Considerations The capacitor and diode tied to the BST pin generate a voltage that is higher than the input voltage. In most cases a 0.47μF capacitor and fast switching diode (such as the CMDSH-3 or FMMD914) will work well. Almost any type of film or ceramic capacitor is suitable, but the ESR should be <1Ω to ensure it can be fully recharged during the off time of the switch. The capacitor value can be approximated by: CBST = ( IOUT(MAX ) • DC ) B • VOUT – VBST(MIN) • f where IOUT(MAX) is the maximum load current, and VBST(MIN) is the minimum boost voltage to fully saturate the switch. Figure 5 shows four ways to arrange the boost circuit. The BST pin must be more than 1.4V above the SW pin for full efficiency. Generally, for outputs of 3.3V and higher the standard circuit (Figure 5a) is the best. For outputs between 2.8V and 3.3V, replace the D2 with a small Schottky diode such as the PMEG4005. For lower output voltages the boost diode can be tied to the input (Figure 5b). The circuit in Figure 5a is more efficient because the BST pin current comes from a lower voltage source. Figure 5c shows the boost voltage source from available DC sources that are greater than 3V. The highest efficiency is attained by choosing the lowest boost voltage above 3V. For example, if you are generating 3.3V and 1.8V and the 3.3V is on whenever the 1.8V is on, the 1.8V boost diode can be connected to the 3.3V output. In any case, you must also be sure that the maximum voltage at the BST pin is less than the maximum specified in the Absolute Maximum Ratings section. The boost circuit can also run directly from a DC voltage that is higher than the input voltage by more than 3V, as in Figure 5d. The diode is used to prevent damage to the LT3510 in case VX is held low while VIN is present. The circuit saves several components (both BST pins can be tied to D2). However, efficiency may be lower and dissipation in the LT3510 may be higher. Also, if VX is absent, the LT3510 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because the switch will not be able to saturate, dropping 1.5V to 2V in conduction. The minimum input voltage of an LT3510 application is limited by the minimum operating voltage (<3V) and by the maximum duty cycle as outlined above. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3510 is turned on with its SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on 3510fc 16 LT3510 APPLICATIONS INFORMATION D2 C3 BST VIN BST VIN SW VIN C3 D2 LT3510 IND VOUT IND VOUT VOUT GND VBST – VSW = VOUT VBST(MAX) = VIN + VOUT (5b) D2 D2 VX = LOWEST VIN OR VOUT > 3V VX > VIN + 3V C3 BST VIN BST VIN SW LT3510 VIN SW LT3510 IND VOUT VBST – VSW = VX VBST(MAX) = VIN + VX VX(MIN) = 3V VOUT < 3V GND VBST – VSW = VIN VBST(MAX) = 2 • VIN (5a) VIN SW VIN LT3510 IND VOUT VOUT < 3V GND VBST – VSW = VX VBST(MAX) = VX VX(MIN) = VIN + 3V (5c) VOUT < 3V GND 3510 F05 (5d) Figure 5. BST Pin Considerations input and output voltages, and on the arrangement of the boost circuit. The Typical Performance Characteristics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3V and 5V outputs. In many cases the discharged output capacitor will present a load to the switcher which will allow it to start. The plots show the worst-case situation where VIN is ramping very slowly. Use a Schottky diode for the lowest start-up voltage. Frequency Compensation The LT3510 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3510 does not require the ESR of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. Frequency compensation is provided by the components tied to the VC pin. Generally a capacitor and a resistor in series to ground determine loop gain. In addition, there is a lower value capacitor in parallel. This capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. Loop compensation determines the stability and transient performance. Designing the compensation network is a bit complicated and the best values depend on the application and in particular the type of output capacitor. A practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. Figure 6 shows an equivalent circuit for the LT3510 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that 3510fc 17 LT3510 APPLICATIONS INFORMATION LT3510 CURRENT MODE POWER STAGE gm = 2.2mho SW R1 gm = 275μmho + – VC 3.6M RC CF ERROR AMP OUTPUT CPL ESR FB C1 + CC 0.8V R2 C1 CERAMIC TANTALUM OR POLYMER 3510 F06 Figure 6. Model for Loop Response the output capacitor integrates this current, and that the capacitor on the VC pin (CC) integrates the error amplifier output current, resulting in two poles in the loop. In most cases a zero is required and comes from either the output capacitor ESR or from a resistor in series with CC. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. A phase lead capacitor (CPL) across the feedback divider may improve the transient response. Synchronization The RT/SYNC pin can be used to synchronize the regulators to an external clock source. Driving the RT/SYNC resistor with a clock source triggers the synchronization detection circuitry. Once synchronization is detected, the rising edge of SW1 will be synchronized to the rising edge of the RT/SYNC pin signal. An AGC loop will adjust the internal oscillators to maintain a 180 degree phase between SW1 and SW2, and also adjust slope compensation to avoid subharmonic oscillation. The synchronizing clock signal input to the LT3510 must have a frequency between 250kHz and 1.5MHz, a duty cycle between 20% and 80%, a low state below 0.5V and a high state above 1.6V. Synchronization signals outside of these parameters will cause erratic switching behavior. The RT/SYNC resistor should be set such that the free running frequency ((VRT/SYNC – VSYNCLO)/RRT/SYNC) is approximately equal to the synchronization frequency. If the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10μs at which VOUT1 LT3510 PG1 RT/SYNC VCC SYNCHRONIZATION CIRCUITRY CLK 3510 F07 Figure 7. Synchronous Signal Powered from Regulator’s Output time the LT3510 reverts to the free-running frequency based on the current through RT/SYNC. If the RT/SYNC resistor is held above 2V at any time, switching will be disabled. If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry is powered from the regulator output) the RT/SYNC pin must see an equivalent resistance to ground between 15.4k and 133k until the synchronization circuitry is active for proper start-up operation. If the synchronization signal powers up in an undetermined state (VOL, VOH, Hi-Z), connect the synchronization clock to the LT3510 as shown in Figure 7. The circuit as shown will isolate the synchronization signal when the output voltage is below 90% of the regulated output. The LT3510 will start-up with a switching frequency determined by the resistor from the RT/SYNC pin to ground. If the synchronization signal powers up in a low impedance state (VOL), connect a resistor between the RT/SYNC pin and the synchronizing clock. The equivalent resistance seen from the RT/SYNC pin to ground will set the start-up frequency. 3510fc 18 LT3510 APPLICATIONS INFORMATION If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC pin to ground. The equivalent resistance seen from the RT/SYNC pin to ground will set the start-up frequency. defaults the open-pin condition to be operating (see Typical Performance Characteristics). Current hysteresis is added above the SHDN threshold. This can be used to set voltage hysteresis of the UVLO using the following: If the synchronization signal changes between high and low impedance states during power up (VOL, Hi-Z), connect the synchronization circuitry to the LT3510 as shown in the Typical Applications section. This will allow the LT3510 to start-up with a switching frequency determined by the equivalent resistance from the RT/SYNC pin to ground. R1 = VH – VL 7μA R2 = 1.28 VH – 1.28 + 3μA R1 Shutdown and Undervoltage Lockout VH = Turn-on threshold Figure 8 shows how to add undervoltage lockout (UVLO) to the LT3510. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. VL = Turn-off threshold An internal comparator will force the part into shutdown below the minimum VIN1 of 2.8V. This feature can be used to prevent excessive discharge of battery-operated systems. Since VIN2 supplies the output stage of channel 2 and is not monitored, care must be taken to insure that VIN2 is present before channel 2 is allowed to switch. If an adjustable UVLO threshold is required, the SHDN pin can be used. The threshold voltage of the SHDN pin comparator is 1.28V. A 3μA internal current source LT3510 VIN1 VIN1 > 2.8V VIN1 OR VIN2 3μA R1 C1 7μA + 1.28V SHDN R2 – + INTERNAL REGULATOR 3510 F08 Example: switching should not start until the input is above 4.75V and is to stop if the input falls below 3.75V. VH = 4.75V VL = 3.75V R1 = 4.75 – 3.75 ≅ 143k 7μA R2 = 1.28 ≅ 47k 4.75 – 1.28 + 3μA A 143k Keep the connections from the resistors to the SHDN pin short and make sure that the interplane or surface capacitance to switching nodes is minimized. If high resistor values are used, the SHDN pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node. Soft-Start The output of the LT3510 regulates to the lowest voltage present at either the SS pin or an internal 0.8V reference. A capacitor from the SS pin to ground is charged by an internal 3.25μA current source resulting in a linear output ramp from 0V to the regulated output whose duration is given by: tRAMP = CSS • 0.8 V 3.25μA Figure 8. Undervoltage Lockout 3510fc 19 LT3510 APPLICATIONS INFORMATION At power-up, a reset signal sets the soft-start latch and discharges both SS pins to approximately 0V to ensure proper start-up. When both SS pins are fully discharged the latch is reset and the internal 3.25μA current source starts to charge the SS pin. threshold is exceeded. The PG pin is active (sink capability is reduced in shutdown and undervoltage lockout mode) as long as the VIN1 pin voltage exceeds 1V. When the SS pin voltage is below 50mV, the VC pin is pulled low which disables switching. This allows the SS pin to be used as an individual shutdown for each channel. Complex output tracking and sequencing between channels can be implemented using the LT3510’s SS and PG pins. Figure 9 shows several configurations for output tracking/sequencing for a 3.3V and 1.8V application. As the SS pin voltage rises above 50mV, the VC pin is released and the output is regulated to the SS voltage. When the SS pin voltage exceeds the internal 0.8V reference, the output is regulated to the reference. The SS pin voltage will continue to rise until it is clamped at 2V. Output Tracking/Sequencing Independent soft-start for each channel is shown in Figure 9a. The output ramp time for each channel is set by the soft-start capacitor as described in the soft-start section. In the event of a VIN1 undervoltage lockout, the SHDN pin driven below 1.28V, or the internal die temperature exceeding its maximum rating during normal operation, the soft-start latch is set, triggering a start-up sequence. Ratiometric tracking is achieved in Figure 9b by connecting both SS pins together. In this configuration, the SS pin source current is doubled (6.5μA) which must be taken into account when calculating the output rise time. In addition, if the load exceeds the maximum output switch current, the output will start to drop causing the VC pin clamp to be activated. As long as the VC pin is clamped, the SS pin will be discharged. As a result, the output will be regulated to the highest voltage that the maximum output current can support. For example, if a 6V output is loaded by 1Ω the SS pin will drop to 0.4V, regulating the output at 3V ( 3A • 1Ω ). Once the overload condition is removed, the output will soft-start from the temporary voltage level to the normal regulation point. By connecting a feedback network from VOUT1 to the SS2 pin with the same ratio that sets VOUT2 voltage, absolute tracking shown in Figure 9c is implemented. The minimum value of the top feedback resistor (R1) should be set such that the SS pin can be driven all the way to ground with 700μA of sink current when VOUT1 is at its regulated voltage. In addition, a small VOUT2 voltage offset will be present due to the SS2 3.25μA source current. This offset can be corrected for by slightly reducing the value of R2. Since the SS pin is clamped at 2V and has to discharge to 0.8V before taking control of regulation, momentary overload conditions will be tolerated without a soft-start recovery. The typical time before the SS pin takes control is: tSS(CONTROL ) = CSS • 1.2V 700μA Power Good Indicators The PG pin is the open-collector output of an internal comparator. The comparator compares the FB pin voltage to 90% of the reference voltage with 30mV of hysteresis. The PG pin has a sink capability of 800μA when the FB pin is below the threshold and can withstand 25V when the Figure 9d illustrates output sequencing. When VOUT1 is within 10% of its regulated voltage, PG1 releases the SS2 soft-start pin allowing VOUT2 to soft-start. In this case PG1 will be pulled up to 2V by the SS pin. If a greater voltage is needed for PG1 logic, a pull-up resistor to VOUT1 can be used. This will decrease the soft-start ramp time and increase tolerance to momentary shorts. If precise output ramp up and down is required, drive the SS pins as shown in Figure 9e. The minimum value of resistor (R3) should be set such that the SS pin can be driven all the way to ground with 700μA of sink current during power-up and fault conditions. Multiple Input Voltages For applications requiring large inductors due to high VIN to VOUT ratios, a 2-stage step-down approach may reduce 3510fc 20 LT3510 APPLICATIONS INFORMATION Independent Start-Up Ratiometric Start-Up Absolute Start-Up VOUT1 0.5V/DIV VOUT1 0.5V/DIV PG1 PG1 PG1 VOUT2 0.5V/DIV VOUT2 0.5V/DIV PG2 3.3V 10ms/DIV 3.3V VOUT1 SS1 0.1μF LT3510 SS1 0.22μF LT3510 PG1 VOUT1 1.8V SS2 3.3V LT3510 PG1 VOUT2 SS2 PG2 10ms/DIV VOUT1 SS1 VOUT2 0.5V/DIV PG2 5ms/DIV 0.1μF VOUT1 0.5V/DIV PG1 1.8V VOUT2 SS2 VOUT2 1.8V 0.22μF PG2 PG2 PG2 R1 13.7k R2 8.08k (9a) (9b) Output Sequencing (9c) Controlled Power Up and Down VOUT1 0.5V/DIV VOUT1 0.5V/DIV PG1 VOUT2 0.5V/DIV VOUT2 0.5V/DIV PG1 SS1/2 PG2 10ms/DIV 10ms/DIV R3 25k SS1 0.1μF VOUT1 3.3V PG1 SS2 VOUT2 SS1 EXTERNAL SOURCE LT3510 1.8V + – LT3510 SS2 3.3V VOUT1 PG1 1.8V VOUT2 0.1μF PG2 PG2 3510 F09 (9d) (9e) Figure 9 3510fc 21 LT3510 APPLICATIONS INFORMATION VIN 6V TO 24V 4.7μF PMEG4005 VIN1 3.3μH 0.47μF PMEG4005 VOUT1 5V FSET BST1 BST2 SW1 SW2 B360A 1μH 0.47μF IND2 VOUT2 42.3k 100k PG1 FB1 8.06k 470pF 10pF 26.7k B360A LT3510 IND1 VOUT1 47μF VIN2 SHDN 40.2k 47μF s2 4k VOUT2 1.2V PG2 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 0.1μF 8.06k 470pF 0.1μF 32.4k 10pF 3510 F10 Figure 10. 5V and 1.2V 2-Stage Step-Down Converter with Output Sequencing inductor size by allowing an increase in frequency. A dual step down application (Figure 10) steps down the input voltage (VIN1) to the highest output voltage then uses that voltage to power the second output (VIN2). VOUT1 must be able to provide enough current for its output plus VOUT2 maximum load. Note that the VOUT1 must be above VIN2 minimum input voltage (2V) when the second channel starts to switch. Delaying channel 2 can be accomplished by either independent soft-start capacitors or sequencing with the PG1 output. Single Step Down: For example, assume a maximum input of 24V: 2-Stage Step-Down: VIN = 24V, VOUT1 = 5V at 1.5A and VOUT2 = 1.2V at 1.5A VOUT + VD V –V +V Frequency (Hz) ≤ IN SW D tMIN(ON) L≥ ( VIN – VOUT ) • VOUT 1.2 + 0.6 Frequency (Hz) ≤ 24 – 0.4 + 0.6 = 392kHz 190ns L1 = L2 = (24 – 5) • 5 24 • 392kHz ≥ 10μH (24 – 1.2) • 1.2 ≥ 2.7μH 24 • 392kHz 5 + 0.6 Frequency ≤ 24 – 0.4 + 0.6 = 1.2MHz 190ns Max Frequency = 1.2MHz L1 = VIN • f L2 = (24 – 5) • 5 24 • 1.2MHz ≥ 3.3μH (5 – 1.2) • 1.2 ≥ 0.76μH 5 • 1.2MHz 3510fc 22 LT3510 APPLICATIONS INFORMATION VIN LT3510 SW VIN LT3510 SW VIN LT3510 SW GND GND GND 3510 F11 (11a) (11b) (11c) Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also Be Switched; Keep These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane PCB Layout For proper operation and minimum EMI, care must be taken during printed circuit board (PCB) layout. Figure 11 shows the high di/dt paths in the buck regulator circuit. Note that large switched currents flow in the power switch, the catch diode and the input capacitor. The loop formed by these components should be as small as possible. These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board and their connections should be made on that layer. Place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor C2. Additionally, the SW and BST traces should be kept as short as possible. The topside metal from the DC964A demonstration board in Figure 12 illustrates proper component placement and trace routing. Thermal Considerations The PCB must also provide heat sinking to keep the LT3510 cool. The exposed metal on the bottom of the package must be soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3510. Place additional vias near the catch diodes. Adding more copper to the top and bottom layers and tying this copper Figure 12. Topside PCB Layout 3510fc 23 LT3510 APPLICATIONS INFORMATION to the internal planes with vias can further reduce thermal resistance. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to θJA = 45°C/W. The power dissipation in the other power components such as catch diodes, boost diodes and inductors, cause additional copper heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal Considerations section. Single, Low Ripple 4A Output The LT3510 can generate a single, low ripple 4A output if the outputs of the two switching regulators are tied together and share a single output capacitor. By tying the two FB pins together and the two VC pins together, the two channels will share the load current. There are several advantages to this 2-phase buck regulator. Ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. Although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. This may be important when there are tight height restrictions on the circuit. There is one special consideration regarding the 2-phase circuit. When the difference between the input voltage and output voltage is less than 2.5V, then the boost circuits may prevent the two channels from properly sharing current. If, for example, channel 1 gets started first, it can supply the load current, while channel 2 never switches enough current to get its boost capacitor charged. In this case, channel 1 will supply the load until it reaches current limit, the output voltage drops, and channel 2 gets started. Two solutions to this problem are shown in the Typical Applications section. The single 3.3V/4A output converter generates a boost supply from either SW that will service both switch pins. The synchronized 3.3V/8A output converter utilizes undervoltage lockout to prevent the start-up condition. Other Linear Technology Publications Application notes AN19, AN35 and AN44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note DN100 shows how to generate a dual (+ and –) output supply using a buck regulator. 3510fc 24 LT3510 TYPICAL APPLICATIONS 5V and 2.5V with Absolute Tracking VIN 12V 4.7μF VIN1 SHDN 3.3μH 0.47μF BST1 BST2 SW1 SW2 B360A PMEG4005 VIN2 RT/SYNC 47μF 470pF 8.06k 10pF PMEG4005 B360A IND2 VOUT2 100k 42.3k 2.2μH 0.47μF LT3510 IND1 VOUT1 VOUT1 5V 26.7k 100k PG1 PG2 FB1 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 47μF 16.9k VOUT2 2.5V 470pF 40.2k 40.2k 10pF 8.06k 0.1μF 16.9k 3510 TA02 7.68k 1.25MHz Single 3.3V/4A Low Ripple Output VIN 6V TO 25V 4.7μF VIN1 1.5μH BST1 BST2 SW1 SW2 B360A 24.9k 0.47μF B360A LT3510 IND1 VOUT1 47μF s2 20.5k RT/SYNC 0.47μF PMEG4005 VOUT1 3.3V 4A VIN2 SHDN 1.5μH PMEG4005 IND2 VOUT2 100k PG1 FB1 8.06k 1000pF PG2 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 22pF 17.8k 0.1μF 3510 TA03 3510fc 25 LT3510 TYPICAL APPLICATIONS 1.25MHz Single 3.3V/4A Low Ripple Output VIN 4.5V TO 6V 4.7μF 1μF* VIN1 VIN2 SHDN 20.5k RT/SYNC PMEG4005* 1.5μH PMEG4005* BST1 BST2 SW1 SW2 B360A PMEG4005 B360A LT3510 47μF s2 24.9k PMEG4005 IND2 VOUT2 IND1 VOUT1 VOUT1 3.3V 4A 0.47μF 1.5μH 0.47μF 100k PG1 FB1 8.06k 1000pF PG2 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 22pF 17.8k 0.1μF 3510 TA04 *ADDITIONAL COMPONENTS ADDED TO SHARE THE BOOST VOLTAGE WHEN VIN <6V. THIS IS REQUIRED TO ENSURE LOAD SHARING BETWEEN THE TWO CHANNELS. Dual LT3510 Synchronized 3.3V/8A Output, 3MHz Effective Switch Frequency VIN 5.5V TO 24V 10μF 143k VIN1 SHDN 36.5k 3.3μH 0.47μF VOUT1 3.3V 47μF s4 BST1 BST2 SW1 SW2 B360A PMEG4005 VIN2 RT/SYNC 24.9k 8.06k 3300pF 47pF 5.3k B360A LT3510 IND2 VOUT2 IND1 VOUT1 3.3μH 0.47μF PMEG4005 49.9k PG1 PG2 FB1 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 49.9k V+ OUT1 133k LTC6908-1 SET MOD GND OUT2 0.1MF 49.9k PMEG4005 PMEG4005 3.3μH VIN1 SHDN 0.47μF VIN2 RT/SYNC BST1 BST2 SW1 SW2 B360A 3.3μH B360A LT3510 IND1 VOUT1 0.47μF IND2 VOUT2 49.9k PG1 PG2 FB1 FB2 VC1 VC2 SS/TRACK1 SS/TRACK2 GND 3510 TA05 3510fc 26 LT3510 PACKAGE DESCRIPTION FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3510fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LT3510 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1766 60V, 1.2A (IOUT), 200kHz High Efficiency Step-Down DC/DC Converter VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, ISD = 25μA, 16-Lead TSSOPE Package LT1933 500mA (IOUT), 500kHz Step-Down Switching Regulator in SOT-23 VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.6mA, ISD <1μA, ThinSOT Package LT1936 36V, 1.4A (IOUT), 500kHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.9mA, ISD <1μA, 8-Lead MS8E Package LT1940 Dual 25V, 1.4A (IOUT), 1.1MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 25V, VOUT(MIN) = 1.20V, IQ = 3.8mA, ISD <30μA, 16-Lead TSSOPE Package LT1976/LT1977 60V, 1.2A (IOUT), 200kHz/500kHz High Efficiency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100μA, ISD <1μA, 16-Lead TSSOPE Package LTC 3407/LTC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converters VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, 3mm × 3mm DFN and 10-Lead MSE Packages LT3434/LT3435 60V, 2.4A (IOUT), 200kHz/500kHz High Efficiency Step-Down DC/DC Converters with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100μA, ISD <1μA, 16-Lead TSSOPE Package LT3437 60V, 400mA (IOUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.3V to 60V, VOUT(MIN) = 1.25V, IQ = 100μA, ISD <1μA, DFN Package LT3493 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.9mA, ISD <1μA, DFN Package LT3501 Dual 25V, 2A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC Converter VIN: 3.3V to 25V, VOUT(MIN) = 0.8V, IQ = 3.5mA, ISD <1μA, 20-Lead TSSOPE Package LT3505 36V, 1.2A (IOUT), 3MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.78V, IQ = 2mA, ISD <2μA, 3mm × 3mm DFN and 8-Lead MSE Packages LT3506/LT3506A Dual 25V, 1.6A (IOUT), 575kHz/1.1MHz High Efficiency Step-Down DC/DC Converters VIN: 3.6V to 25V, VOUT(MIN) = 0.8V, IQ = 3.8mA, ISD <30μA, 4mm × 5mm DFN Package LTC3548 Dual 400mA/800mA, 2.25MHz Synchronous Step-Down DC/DC Converters VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, 3mm × 3mm DFN and 10-Lead MSE Packages ® ® TM Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. 3510fc 28 Linear Technology Corporation LT 1008 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006