Intersil ISL78171ARZ-EVALZ 6-channel, 50ma automotive led driver with ultra-high dimming ratio and phase shift control Datasheet

DATASHEET
6-Channel, 50mA Automotive LED Driver with Ultra-high
Dimming Ratio and Phase Shift Control
ISL78171
Features
ISL78171 is a 6-channel, 50mA, LED driver capable of very
high dynamic range dimming. It offers an integrated boost
converter, six high precision, adjustable current sinks and a
SMBus/I2C interface for digital programmability and extensive
diagnostics. These features provide the ISL78171 with the
necessary capabilities to design compact, highly versatile LED
backlight for a wide variety of ambient lighting conditions.
• 6 channels at 50mA maximum per channel
• Input voltage: 4.5V to 26.5V, output voltage: 40V max
• Bootstrap operation Input:3V to 21V output: 26.5V max
• PWM dimming with phase shift control
• SMBus/I2C controlled PWM or DC dimming
• Direct PWM dimming
The integrated peak current mode PWM boost converter
operates with a constant frequency and can boost an input
voltage range of 4.5V - 26.5V to an output up to 40V and supply
six strings of LEDs with up to 50mA each. A dynamic headroom
control circuit detects and regulates the highest voltage string to
improve efficiency in multistring configurations.
• Internal PWM dimming mode linearity: 0.4% to 100%,
dimming frequency <30kHz
• Direct PWM dimming duty cycle linearity: 0.007% to 100%
at a dimming frequency of 200Hz
• Current matching ±0.7% typ
The six high precision adjustable current sinks offer typical
current matching better than ±1% and a dimming ratio that is
capable of exceeding 60,000:1. The dimming ratio can be
adjusted with either or both the I2C/SMBus and an external
PWM signal. They also feature an optional channel phase shift
control which helps to reduce the input and output
capacitance and ripple, to improve efficiency and to prevent
audible noise.
• 600kHz/800kHz/1.2MHz selectable switching frequency
• Dynamic headroom control
• Fault protection
- String open/short circuit, OVP, OTP and optional output
short circuit fault protection
• AEC-Q100 qualified
Applications
The SMBus/I2C interface offers a wide range of
programmability that includes the boost FET slew rate control,
individual string enabling and converter switching frequency
selections. It offers a wide range of protection features and
diagnostics that cover all perceivable faults, enabling the
system to self-diagnose the functioning of the backlight and
react to such conditions as failed LEDs. The ISL78171 is offered
in a compact and thermally efficient 20 Ld QFN package with an
ambient temperature range of -40°C to +105°C.
40V, 6 x 50mA*
VIN = 4.5~26.5V
Q1 (OPTIONAL)
4 VDC
• LCD monitor LED backlighting
• Field sequential RGB LED backlighting
Related Literature
• UG035, “ISL78171EVAL1Z Evaluation Board User Guide”
40V, 6 x 50mA*
VIN = 4.5~26.5V
40V, 6 x 50mA*
VIN = 4.5~26.5V
Q1 (OPTIONAL)
Q1 (OPTIONAL)
ISL78171
ISL78171
1 FAULT
2 VIN
• Infotainment display LED backlighting
1 FAULT
LX 20
2 VIN
OVP 16
4 VDC
ISL78171
1 FAULT
LX 20
OVP 16
2 VIN
4 VDC
LX 20
OVP 16
PGND 19
7 SMBCLK/SCL
PGND 19
7 SMBCLK/SCL
8 FPWM
PGND 19
7 SMBCLK/SCL
6 SMBDAT/SDA CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
6 SMBDAT/SDA CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
6 SMBDAT/SDA CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
17 RSET
CH4 14
17 RSET
CH4 14
17 RSET
CH4 14
8 FPWM
CH5 15
8 FPWM
CH5 15
9 AGND
COMP 18
9 AGND
*VIN > 12V
COMP 18
FIGURE 1A. SMBus/I2C CONTROLLED
DIMMING AND ADJUSTABLE
DIMMING FREQUENCY
9 AGND
COMP 18
CH5 15
*VIN > 12V
FIGURE 1B. PWM DIMMING WITH PWM INPUT
AND ADJUSTABLE DIMMING
FREQUENCY
*VIN > 12V
FIGURE 1C. DIRECT PWM DIMMING
FIGURE 1. ISL78171 TYPICAL APPLICATION DIAGRAMS
June 15, 2015
FN8602.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78171
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dynamic Headroom Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Dimming Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5V Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IC Protection Features and Fault Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SMBus/I2C Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Slave Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SMBus/I2C Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PWM Brightness Control Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Control Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fault/Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Identification Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Brightness Control Register (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Configuration Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Channel Mask/Fault Readout Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Phase Shift Control Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Secondary Boost Oscillator Register (0x7F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
26
26
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Current Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Voltage Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Field Sequential RGB LED Backlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
27
27
27
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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2
FN8602.0
June 15, 2015
ISL78171
Block Diagram
SCHOTTKY
DIODE, 60V, 3A
L=15uH
VIN = 4.5V TO 26.5V
VIN
40V, 6 x 50mA*
LX
FAULT
ISL78171
EN
REG
VDC
OSC AND
RAMP
COMP
FPWM
=0
FET
DRIVER
LOGIC
IMAX ILIMIT
LED PWM
CONTROL
PGND
CH0
COMP
RSET
OVP
OVP
FAULT/STATUS
REGISTER
GM
AMP
REFERENCE
GENERATOR
HIGHEST VF
STRING
DETECT
OC, SC
DETECT
+
-
+
-
CH5
OC, SC
DETECT
*VIN > 12V
FAULT/STATUS
REGISTER
AGND
TEMP
SENSOR
SMBCLK/SCL
SMBDAT/SDA
PWM
SMBUS/I2C
INTERFACE
AND PWM
CONTROL
LOGIC
REGISTERS
PWM BRIGHTNESS CONTROL
DEVICE CONTROL
FAULT/STATUS
IDENTIFICATION
DC BRIGHTNESS CONTROL
CONFIGURATION
+
PWM/OC/SC
FAULT/STATUS
REGISTER
DC
FIGURE 2. ISL78171 BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL78171ARZ
8171
ISL78171ARZ-EVALZ
Evaluation Board
TEMP RANGE
(°C)
-40 to +105
PACKAGE
(RoHS Compliant)
20 Ld 3x4 QFN
PKG.
DWG. #
L20.3x4
NOTES:
1. Add “-T* suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL78171. For more information on MSL please see techbrief TB363.
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3
FN8602.0
June 15, 2015
ISL78171
Pin Configuration
Pin Descriptions
LX
PGND
COMP
RSET
ISL78171
(20 LD QFN)
TOP VIEW
20
19
18
17
FAULT
1
16
OVP
VIN
2
15
CH5
EN
3
14
CH4
VDC
4
13
CH3
PWM
5
12
CH2
SMBDAT/SDA
6
11
CH1
7
8
9
10
SMBCLK/SCL
FPWM
AGND
CH0
EPAD
(I = Input, O = Output, S = Supply, X = Don’t Care)
PIN NAME
PIN #
TYPE
DESCRIPTION
FAULT
1
O
This signal is the Fault disconnect switch gate control.
VIN
2
S
This is the input voltage for the device and LED power.
EN
3
I
This is the Enable input. The device needs 4ms for initial power-up enable. It will be disabled if it is not biased for
longer than 30.5ms.
VDC
4
S
This is the internal LDO output for the purpose of filtering. Connect a 1uF X7R decoupling capacitor to ground.
PWM
5
I
This is the PWM brightness control pin or DPST control input. The pin has an internal pull down of 2M so can be
left floating when not used.
SMBDAT/SDA
6
I/O
This is the SMBus/I2C serial data input and output. When pins 6 and 7 are grounded or in logic 0’s for longer than
60ms, the drivers will be controlled by external PWM signal.
SMBCLK/SCL
7
I
This is the SMBus/I2C serial clock input. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the
drivers will be controlled by external PWM signal.
FPWM
8
I
This pin sets the PWM dimming frequency, by connecting a resistor between this pin and ground. When FPWM is
tied to VDC and SMBCLK/SMBDAT is tied to ground, the device will be in Direct PWM Dimming where the output
follows the input frequency and duty cycle without any digitization.
AGND
9
S
This pin is the Analog Ground for precision circuits.
CH0, CH1
CH2, CH3
CH4, CH5
10, 11,
12, 13,
14, 15
I
These pins are the constant current sink and channel monitoring input for the LED string channels 0 through 5.
OVP
16
I
This is the Over voltage protection input.
RSET
17
I
A resistor connected between this pin and GND sets the max usable LED current, (see Equation 1 for calculating
the ILED(peak)). The value in the DC register 0x07 should be set to FF while setting the max LED current.
COMP
18
O
This is the Boost converter feedback compensation pin.
PGND
19
S
This pin is the Power ground pin.
LX
20
O
This pin is the Boost converter switch node.
EPAD
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This pad is not an electrical connection but should be used to connect PGND and AGND. For example use top plane
as PGND and bottom plane as AGND with vias on EPAD to allow heat dissipation and minimum noise coupling from
PGND to AGND operation.
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June 15, 2015
ISL78171
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN - 0.3V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
SMBCLK/SCL, SMBDAT/SDA, FPWM, PWM . . . . . . . . . . . . . . -0.3V to 5.5V
OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V
CH0-CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 42.5V
PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . .3.5kV
Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . .1.5kV
Thermal Resistance (Typical)
JA (°C/W)
20 Ld QFN Package (Notes 4, 5, 7) . . . . . .
40
Thermal Characterization (Typical)
JC (°C/W)
2.5
JT (°C/W)
1
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 26.5V
LX max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. JT is the  junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction
temperature can be estimated more accurately than the JC and JA thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
temperature range, -40°C to +105°C.
PARAMETER
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply across the operating
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
26.5
V
5
µA
GENERAL
VIN (Note 9)
IVIN_STBY
Backlight Supply Voltage
≤10 LEDs per channel
(type 3.2V (typ)/20mA)
4.5
VIN Shutdown Current
IVIN
VIN Active Current
VIN = 24V, EN =5V, VDD = 5V.
SDA, SCL are high
VOUT
Output Voltage
4.5V < VIN ≤ 26.5V,
fSW = 600kHz
40
V
8.55V < VIN ≤ 26.5V,
fSW = 1.2MHz
40
V
2.6
V
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
5
2.1
mA
200
mV
REGULATOR
VDC
IVDC_STBY
VLDO
LDO Output Voltage
VIN ≥ 6V
Standby Current
EN = 0V
VDC LDO Load Regulation
VIN > 5.5V, ILDO=0 to 20mA
ENLOW
EN Input Low Voltage
ENHI
EN Input High Voltage
tENLow
4.55
4.8
20
5
V
5
µA
200
mV
0.5
V
1.8
EN Low Time To Shutdown
V
30.5
ms
BOOST
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-resistance
TA = +25°C
Soft-start
100% LED Duty Cycle
SS
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5
1.5
2.0
2.7
A
235
300
mΩ
7
ms
FN8602.0
June 15, 2015
ISL78171
Electrical Specifications
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
Eff_peak
IOUT/VIN
DMAX
DMIN
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
VIN = 12V, 72 LEDs, 20mA each,
L = 10µH with DCR 101mΩ,
TA = +25°C
92.9
%
VIN = 12V, 60 LEDs, 20mA each,
L = 10µH with DCR 101mΩ,
TA = +25°C
90.8
%
Line Regulation
4.5V < VIN ≤ 26V, fSW = 600kHz
0.1
%
Boost Maximum Duty Cycle
fSW = 600kHz
90
fSW = 1.2MHz
81
Peak Efficiency
Boost Minimum Duty Cycle
%
fSW = 600kHz
9.5
fSW = 1.2MHz
17
%
fOSC_lo
Lx Frequency Low
Configuration Reg FSW bit=1
475
600
640
kHz
fOSC_hi
Lx Frequency High
Configuration Reg FSW bit=0
0.97
1.2
1.31
MHz
LX Pin Leakage Current
LX = 40V, EN = 0V
10
µA
1.2
V
5
mA
ILX_leakage
LXstart_thres
ILXStart-up
LX Start-up Threshold
0.9
LX Start-up Current
1
3.5
7.5
8.2
FAULT DETECTION
VSC
Short circuit Threshold Accuracy
Measured on the CHx pin
V
Temp_shtdwn
Temperature Shutdown Threshold
150
°C
Temp_Hyst
Temperature Shutdown Hysteresis
23
°C
VOVPlo
Overvoltage threshold on OVP Pin
1.15
1.21
1.27
V
±0.7
±1.5
%
+2.2
%
CURRENT SINKS
IMATCH
IACC
VHEADROOM
VRSET
ILED(max)
DC Channel-to-channel Current Matching
RSET = 20.1kΩ, Reg0x00 = 0xFF,
(ILED = 20mA)
Current Accuracy
RSET = 20.1kΩ, Reg0x00 = 0xFF,
(ILED = 20mA)
-2.2
Dominant Channel Current Sink Headroom at ILED = 20mA
CHx Pin
TA = +25°C
Voltage at RSET Pin
RSET = 20.1kΩ
Maximum LED Current per Channel
VIN = 12V, VOUT = 40V, fSW = 1.2MHz,
TA = +25°C
500
1.17
1.22
mV
1.25
50
V
mA
PWM GENERATOR
VIL
PWM Input Low Voltage
VIH
PWM Input High Voltage
PWM Input Frequency Range
FPWMI
PWMACC
tDIRECTPWM
FPWM
0.8
V
1.5
5.0
V
200
30,000
Hz
PWM Dimming Accuracy (Except Direct PWM
Dimming)
Direct PWM Minimum On Time
8
Direct PWM Mode
PWM Dimming Frequency Range
bits
250
350
ns
100
30,000
Hz
FAULT PIN
IFAULT
Fault Pull-down Current
VIN = 12V
VFAULT
Fault Clamp Voltage with Respect to VIN
VIN = 12, VIN - VFAULT
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12
21
30
µA
6
7
8.3
V
FN8602.0
June 15, 2015
ISL78171
Electrical Specifications
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
0.8
V
5.0
V
0.17
V
10
µA
SMBus/I2C INTERFACE
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
SMBus/I2C Data Line Logic Low Voltage
IPULLUP = 4mA
Input Leakage On SMBData/SMBClk
Measured at 4.8V
ILEAK
1.5
-10
SMBus/I2C TIMING SPECIFICATIONS
tEN-SMB/I2C
Minimum Time Between EN High and
SMBus/I2C Enabled
1µF capacitor on VDC
2
0.15
ms
PWS
Pulse Width Suppression on
SMBCLK/SMBDAT
0.45
µs
fSMB
SMBus/I2C Clock Frequency
400
kHz
tBUF
Bus Free Time Between Stop and Start
Condition
1.3
µs
tHD:STA
Hold Time After (Repeated) START Condition.
After this Period, the First Clock is Generated
0.6
µs
tSU:STA
Repeated Start Condition Setup Time
0.6
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tHD:DAT
Data Hold Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tF
Clock/Data Fall Time
300
ns
tR
Clock/Data Rise Time
300
ns
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. At maximum VIN of 26.5V, minimum VOUT is limited 28V.
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ISL78171
Typical Performance Curves
LED configuration: 6P10S
95
95
90
90
85
85
80
EFFICIENCY (%)
EFFICIENCY (%)
12V
5V
75
24V
26.5V
70
65
80
70
65
60
55
55
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
50
0.20
0
0.02
0.04
0.06
LED CURRENT (A)
90
12V
0.14
0.16
0.18
0.20
-40°C
85
80
EFFICIENCY (%)
EFFICIENCY (%)
0.12
95
85
5V
75
0.10
FIGURE 4. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 600kHz AT +25°C vs VIN
24V
90
0.08
LED CURRENT (A)
FIGURE 3. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 600kHz AT -40°C vs VIN
95
5V
26.5V
75
60
50
24V
12V
26.5V
70
65
+25°C
80
+105°C
75
70
60
65
55
50
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
60
0.20
0
5
10
15
95
95
90
90
12V
85
85
80
80
26.5V
70
5V
24V
65
55
0.04
0.06
0.08
0.10
0.12
0.14
0.16
LED CURRENT (A)
FIGURE 7. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 1.2MHz AT -40°C vs VIN
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0.18
0.20
5V
26.5V
65
55
0.02
12V
70
60
0
30
24V
75
60
50
25
FIGURE 6. EFFICIENCY vs INPUT VOLTAGE AT LX
FREQUENCY = 600kHz vs VIN
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 5. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 600kHz AT +105°C vsVIN
75
20
VIN (V)
LED CURRENT (A)
50
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
LED CURRENT (A)
FIGURE 8. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 1.2MHz AT +25°C vs VIN
FN8602.0
June 15, 2015
ISL78171
Typical Performance Curves
LED configuration: 6P10S (Continued)
95
95
90
26.5V
90
-40°C
85
80
EFFICIENCY (%)
EFFICIENCY (%)
85
12V
75
5V
24V
70
65
+25°C
+105°C
80
75
70
60
65
55
50
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
60
0.20
0
5
10
15
LED CURRENT (A)
FIGURE 9. EFFICIENCY vs LED CURRENT AT LX
FREQUENCY = 1.2MHz AT +105°C vs VIN
0.8
CHANNEL MATCHING (%)
0.6
0.4
20
25
30
0.1
1
VIN (V)
FIGURE 10. EFFICIENCY VS INPUT VOLTAGE AT LX
FREQUENCY = 1.2MHz vs VIN
+25°C,
5V
12V
24V
26.5V
+105°C,
5V
12V
24V
26.5V
-40°C,
5V
12V
24V
26.5V
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1
2
3
4
5
CHANNEL NUMBER
FIGURE 11. CHANNEL-TO-CHANNEL CURRENT MATCHING, 600kHz vs VIN
1
1.2
NORMALIZED LED CURRENT
CURRENT (mA)
1.0
0.8
4.5 VIN
0.6
12 VIN
0.4
0.2
0
0
2
1
3
4
5
PWM DIMMING DUTY CYCLE (%)
FIGURE 12. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE vs VIN
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6
0.1
0.01
0.001
0.0001
0.00001
0.00001
0.0001
0.001
0.01
DIMMING FACTOR
(PWM Reg Value x DC Reg Value) / (255 x 255)
FIGURE 13. NORMALIZED LED CURRENT vs. DIMMING FACTOR,
(MEASURED AT ILED = 20mA)
FN8602.0
June 15, 2015
ISL78171
Typical Performance Curves
LED configuration: 6P10S (Continued)
0.60
-40°C
+25°C
VHEADROOM (V)
0.55
VOUT = 50mV/DIV
2.00µs/DIV
0.50
0°C
VLX = 20V/DIV
2.00µs/DIV
0.45
0.40
0
5
10
15
20
25
30
VIN (V)
FIGURE 14. VHEADROOM vs VIN vs TEMPERATURE AT 20mA
FIGURE 15. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT
20mA/CHANNEL
V_OUT
V_OUT
V_OUT
V_OUT
V_EN
V_EN
V_EN
V_EN
V_LX
V_LX
V_LX
V_LX
I_INDUCTOR
I_INDUCTOR
I_INDUCTOR
I_INDUCTOR
FIGURE 16. SOFT-START INDUCTOR CURRENT AT VIN = 6V FOR
6P12S AT 20mA/CHANNEL
FIGURE 17. SOFT-START INDUCTOR CURRENT AT VIN = 12V FOR
6P12S AT 20mA/CHANNEL
6P12S, 20mA/CH
6P12S, 20mA/CH
VIN = 10V/DIV
10ms/DIV
VIN = 10V/DIV
10.0ms/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
EN
FIGURE 18. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V,
6P12S AT 20mA/CHANNEL
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FIGURE 19. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 6P12S AT 20mA/CHANNEL
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June 15, 2015
ISL78171
Typical Performance Curves
LED configuration: 6P10S (Continued)
6P12S, 20mA/CH
6P12S, 20mA/CH
VO = 1V/DIV
VO = 1V/DIV
10.0ms/DIV
10.0ms/DIV
ILED = 20mA/DIV
ILED = 20mA/DIV
FIGURE 20. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE
FROM 0% TO 100%, VIN = 12V, 6P12S AT
20mA/CHANNEL
FIGURE 21. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE
FROM 100% TO 0%, VIN = 12V, 6P12S AT
20mA/CHANNEL
0.0030
6P12S, 20mA/CH
VO = 10V/DIV
20.0ms/DIV
ILED = 20mA/DIV
I_VIN = 1A/DIV
ILED (mA)
0.0025
0.0020
0.0015
FPWM = 200Hz
NO CH CAPS
ILED = 20mA AT 100% DUTY CYCLE
EN
0.0010
0.006
0.007
0.008
0.009
0.010
0.011
0.012
0.013 0.014
PWM DIMMING DUTY CYCLE (%)
FIGURE 22. ISL78171 SHUTS DOWN AND STOPS SWITCHING
~30ms AFTER EN GOES LOW
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FIGURE 23. DIRECT PWM DIMMING LINEARITY AT VERY LOW DUTY
CYCLE
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June 15, 2015
ISL78171
Theory of Operation
Dynamic Headroom Control
PWM Boost Converter
The PWM boost converter operating in current mode produces
the minimum voltage needed to enable up to six parallel LED
strings having a combination of high and low forward voltage
drop to run at the programmed current. The ISL78171 employs
current mode control boost architecture that has a fast current
sense loop and a slow voltage feedback loop. Such architecture
achieves a fast transient response that is essential for notebook
backlight applications in which drained batteries can be instantly
changed to an AC/DC adapter without noticeable visual
brightness change. The number of LEDs that can be driven by
ISL78171 depends on the type of LED chosen in the application.
The ISL78171 is capable of boosting up to 40V max and typically
driving 12 LEDs in series for each of the 6 channels, enabling a
total of 72 pieces of the 3.2V/20mA type of LEDs. At start-up, the
LX pin injects a fixed current into the output capacitor. The device
does not start unless the voltage at LX exceeds 1.2V. Also note
that the VIN has to be 12V or greater to support an LED string
current of 50mA per channel.
The ISL78171 features a proprietary Dynamic Headroom Control
circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the CH0-CH5 pins to
GND. When this lowest channel voltage is lower than the short
circuit threshold, VSC, such voltage will be used as the feedback
signal for the boost regulator. The boost makes the output to the
correct level such that the lowest channel pin is at the target
headroom voltage. Since all LED stacks are connected to the
same output voltage, the other channel pins will have a higher
voltage, but the regulated current source circuit on each channel
will ensure that each channel has the same programmed
current. The output voltage will regulate cycle-by-cycle and is
always referenced to the highest forward voltage string in the
architecture.If VSC function is enabled then the forward voltages
across the LED string matching must be less than 7.5V.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an appropriate
value for RSET. This should be chosen to fix the maximum
possible LED current:
410.5
I LEDmax = --------------R SET
Enable
The EN pin is used to enable or disable the ISL78171 operation. It
is a high voltage pin that can be tied directly to VIN up to 26.5V. If
EN is pulled low for longer than 30ms, the device will shut down.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 24.
The LED peak current is set by translating the RSET current to the
output with a scaling factor of 410.5/RSET. The sink terminals of
the current source MOSFETs are designed to run at 500mV to
optimize the power loss versus accuracy requirements. The
sources of errors of the channel-to-channel current matching
come from the op amps offset, internal layout, reference and
current source resistors. These parameters are optimized for
current matching and absolute current accuracy. On the other
hand, the absolute accuracy is additionally determined by the
external RSET, and therefore, additional tolerance will be
contributed by the current setting resistor. A 1% tolerance
resistor is therefore recommended.
+
-
REF
+
-
RSET
+
PWM DIMMING
DC DIMMING
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
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(EQ. 1)
Where ILEDmax is in mA and RSET in k. Once RSET is fixed, the
LED DC current can be adjusted by writing a value to the DC
Brightness register 0x07 (BRTDC) as follows:
I LED = 1.61x  BRTDC  R SET 
(EQ. 2)
BRTDC can be programmed from 0 to 255 in decimal and
defaults to 255 (0xFF). If left at the default value, LED current will
be fixed at ILEDmax. BRTDC can be adjusted dynamically on the fly
during operation. BRTDC = 0 disconnects all channels.
For example, if the maximum required LED current (ILED(max)) is
20mA, rearranging Equation 1 yields Equation 3:
R SET = 410.5  0.02 = 20.52k
(EQ. 3)
If BRTDC is set to 200 then:
I LED = 1.61  200  20.52 = 15.69mA
(EQ. 4)
PWM DIMMING CONTROL
The ISL78171 provides multiple PWM dimming methods, as
described in the following. Table 1 summarizes the dimming
mode selection. Each of these methods results in PWM chopping
of the current in the LEDs for all 6 channels to provide a lower
average LED current. During the On periods, the LED current will
be defined by the value of RSET and BRTDC, as described in
Equations 1 and 2. The source of the PWM signal can be
described as follows:
1. Internally Dimming Duty Cycle control: The dimming duty
cycle is controlled by a 256 step PWM brightness control
register (BRT) which is programmed through the SMBus/I2C.
The dimming frequency is set by the resistor connected to the
FPWM pin.
2. External Dimming Duty Cycle control: The signal applied to
the PWM input provides the dimming duty cycle information
for the LED display. The dimming frequency is set by the
resistor connected to the FPWM pin.
FN8602.0
June 15, 2015
ISL78171
3. Display Power Saving Technology (DPST) mode: The PWM
dimming frequency is set by the resistor on FPWM pin & duty
cycle is the product of the duty set by the 256 bit PWM
brightness register (BRT) through PMBus/I2C and the duty
cycle information from the external PWM input signal.
4. Direct PWM mode: In this case the output duty cycle and
dimming frequency follows the input PWM signal. This is
purely an analog dimming method for use when the
PMBus/I2C controls are not needed.
The default PWM dimming mode is in Display Power Saving
Technology (DPST). In all of the methods, the average LED
channel current is controlled by ILED and the PWM duty cycle in
percent, as shown in Equation 5:
I LED  ave  = I LED  PWM
(EQ. 5)
Method 1 (SMBus/I2C Controlled Dimming)
The average LED channel current is controlled by the internally
generated PWM signal, as shown in Equation 6:
I LED  ave  = I LED   BRT  255 
(EQ. 6)
Where BRT is the value programmed in the PWM brightness
Register 0x00. BRT ranges from 0 to 255 in decimal and defaults
to 255 (0xFF). BRT = 0 disconnects all channels.
Setting the Control Register 0x01 to 0x05 programs the device to
use only the SMBus/I2C controlled PWM brightness control.
Alternatively, the same operation can be obtained by setting
Register 0x01 at its default value of 0x01 Display Power Saving
Technology (DPST) and connecting the PWM input to VDC, so that
the dimming level depends only on the BRT register.
The PWM dimming frequency is adjusted by a resistor at the
FPWM pin.
Method 2 (PWM Controlled Dimming with Settable Dimming
Frequency)
The average LED channel current is controlled by the duty cycle of
external PWM signal, as shown in Equation 7:
I LILED  ave  = I LED  PWMI
(EQ. 7)
The PWM dimming frequency is adjusted by a resistor at the
FPWM pin. The PWM input cannot be low for more than 30.5ms
or else the driver will enter shutdown.
Setting the Control Register 0x01 to 0x03 programs the device to
use the duty of the externally applied PWM signal for brightness
control. Alternatively, the same operation can be obtained by
leaving Register 0x01 at its default value of 0x01 Display Power
Saving Technology (DPST), and not program Register BRT, so that
it contains its default value of 0xFF.
Method 3 Display Power Saving Technology (DPST).
The average LED channel current can also be controlled by the
product of the SMBus/I2C controlled PWM and the external PWM
signals as:
(EQ. 8)
I LED  ave  = I LED xPWM DPST
Where:
PPWM DPST = BRT  255  PWMI
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(EQ. 9)
Therefore:
I LED  ave  = I LED  BRT  255  PWMI
(EQ. 10)
Where BRT is the value held in PWM Register 0x00 (default
setting 0xFF) controlled by SMBus/I2C and PWMI is the duty
cycle of the incoming external PWM signal. In this way, the users
can change the PWM current in ratio metric manner to achieve
Display Power Saving Technology (DPST) compliant backlight
dimming. To use the Display Power Saving Technology (DPST)
mode, users need to set the control Register 0x01 to 0x01. The
PWM dimming frequency is adjusted by a resistor at the FPWM
pin.
For example, if the SMBus/I2C controlled PWM duty is 80%
dimming at 200Hz (see Equation 11) and the external PWM duty
cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is
48% dimming at 200Hz.
In Display Power Saving Technology (DPST) mode, the ISL78171
features 8-bit dimming resolution. The product of the PWMI duty
cycle, (digitized with 8-bit resolution) and of the BRT I2C register,
results in a 16 bit value.The device calculates the dimming level
by taking the 8 most significant bits of the 16 bit result.
Method 4 (Direct PWM Mode)
Direct PWM Dimming mode is selected when FPWM is tied to VDC
and SMBCLK/SMBDAT are grounded. The current of the six LED
channels will follow the External PWM signal’s frequency and
duty cycle. The minimum duty cycle can be as low as 0.007% at
200Hz (or equivalent pulse width of 350ns). This ultra low duty
cycle dimming performance can be achieved if no channel
capacitor is present. Also, in Direct PWM Dimming mode the
Phase Shift function will be disabled.
TABLE 1. DIMMING MODE SELECTION
DIMMING
METHOD
SELECTION
SMBCLK/ SMBDAT/
SCL PIN SDA PIN FPWM
PIN
SIGNAL SIGNAL
Method 1
SMBUS/ SMBUS/ Resistor
(SMBUS/I2C
I2C clock I2C data to ground
controlled dimming,
PWM Reg for Duty and
FPWM for Frequency)
0x01 REGISTER
Set to 0x05, or set
to 0x01 and
connect PWM to
VDC
SMBUS/ SMBUS/ Resistor Set to 0x03, or set
Method 2
I2C clock I2C data to ground to 0x01 and not
(PWMI for Duty &
FPWM for Frequency)
program register
0x00
Grounded Grounded Resistor N/A
Method 2
to ground
(PWMI for Duty &
FPWM for Frequency)
SMBUS/ SMBUS/ Resistor Set to 0x01
Method 3
Display Power Saving I2C clock I2C data to ground
Technology (DPST),
Product of PWMI &
PWM Reg for Duty and
FPWM for Frequency
Grounded Grounded Tie to
Method 4
VDC
(Direct PWM dimming,
PWMI for Duty and
Frequency)
N/A
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ISL78171
PWM Dimming Frequency Adjustment
For dimming methods 1-3, the PWM dimming frequency is set by
an external resistor at the FPWM pin and can be calculated by
equation 11:
7
6.66 10
F PWM = -----------------------RFPWM
(EQ. 11)
60%
PWMI
40%
ILED0
60%
40%
tD1
ILED1
tD1
Where FPWM is the PWM dimming frequency in Hz and RFPWM is
the setting resistor in .
The PWM dimming frequency range is between 200Hz to 30kHz
and the duty cycle range is from 0.4% to 100%.
ILED2
tD1
ILED3
tD1
ILED4
tD1
Phase Shift Control
ILED5
For dimming methods 1-3, the ISL78171 is capable of delaying
the phase of each current source to minimize load transients. By
default, phase shifting is disabled as shown in Figure 25 where
the channels PWM currents are switching at the same time.
tD2
tFPWM
ILED0
tON
tOFF
FIGURE 26. SIX EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
tFPWM
tPWMin
ILED0
tON
tOFF
60%
PWMI
40%
tFPWM
(tPWMout)
ILED1
tON
ILED1
tOFF
60%
40%
tD1
ILED2
ILED2
tD1
ILED3
ILED3
tD1
ILED4
ILED4
ILED5
FIGURE 25. NO DELAY (DEFAULT PHASE SHIFT DISABLED)
tD2
ILED1
When EqualPhase = 1 (register 0x0A, bit 7), the phase shift evenly
spreads the channels switching across the PWM cycle, depending on
how many channels are enabled, as shown in Figures 26 and 27.
Equal phase means there are fixed delays between channels and
such delay can be calculated as Equation 12 in Figures 26 and 27.
FIGURE 27. FOUR EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
tFPWM
t FPWM 255
t D1 = ------------------- x  ----------
255  N 
(EQ. 12)
Equation 13 shows the phase delay between the last channel of
the current duty cycle and the first channel of the next duty cycle
in Figures 26 and 27.
t FPWM
255
t D2 = ------------------- x  255 –  N – 1   ---------- 
 N 
255 
ILED0
tON
tOFF
tPD
ILED1
tPD
ILED2
tPD
(EQ. 13)
Where (255/N) is rounded down to the nearest integer. For
example, if N = 6, (255/N) = 42, that leads to:
tD1 = tFPWM x 42/255
ILED3
tPD
ILED4
tPD
ILED5
FIGURE 28. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY
tD2 = tFPWM x 45/255
Where tFPWM is the sum of tON and tOFF. N is the number of LED
channels. The ISL78171 will detect the number of operating
channels automatically.
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Delay with
Integer
only while
the while
decimal value
will be discarded
(eg. will
63.75=63)
tD1 = tFixed
delay
with
integer
only
the decimal
value
be discarded (e.g., 3.75 = 63)
D1 = Fixed
14
The ISL78171 allows the user to program the amount of phase
shift degree with 7-bit resolution, as shown in Figure 28. To
enable programmable phase shifting, the user must write to the
Phase Shift Control register with EqualPhase = 0 and the
desirable phase shift value of PhaseShift[6:0]. The delay
between CH5 and the repeated CH0 is the rest of the PWM cycle.
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ISL78171
Switching Frequency
The default switching frequency is 600kHz but it can be selected
to 600kHz or 1.2MHz if the SMBus/I2C communications is used.
The switching frequency select bit is accessible in the SMBus/I2C
Configuration Register 0x08 bit 2. Alternatively 800kHz can be
selected by writing value 0x80 only to register 0x7F. The default
value for register 0x7F should otherwise be set to 0x00 in order
to use the 600kHz or 1.2MHz.
5V Low Dropout Regulator
An internal 5V low dropout (LDO) regulator supplies the
necessary low-voltage needed for the chip’s internal control
circuitry. VDC is the output of this LDO regulator which requires a
bypass capacitor of 1µF or more for the purpose of filtering &
regulation. The VDC pin can be used as a coarse reference as
long as it is sourcing 20mA or less.
IC Protection Features and Fault
Management
ISL78171 has several protection and fault management features
that improve system reliability. The following sections describe
them in more detail.
INRUSH CONTROL AND SOFT-START
The ISL78171 has separate, built-in, independent inrush control
and soft-start functions. The inrush control function is built
around an external short-circuit protection P-channel FET in
series with VIN. At start-up, the fault protection FET is turned on
slowly due to a 21µA pull-down current output from the FAULT
pin. This discharges the fault FET's gate-source capacitance,
turning on the FET in a controlled fashion. As this happens, the
output capacitor is charged slowly through the low-current FET
before it becomes fully enhanced. This results in a low inrush
current. This current can be further reduced by adding a
capacitor (in the 1nF to 5nF range) across the gate source
terminals of the FET.
Once the chip detects that the fault protection FET is turned on
fully, it assumes that inrush is complete. At this point, the boost
regulator begins to switch, and the current in the inductor ramps
up. The current in the boost power switch is monitored, and
switching is terminated in any cycle in which the current exceeds
the current limit. The ISL78171 includes a soft-start feature in
which this current limit starts at a low value (275mA). This value
is stepped up to the final 2.2A current limit in seven additional
steps of 275mA each. These steps happen over at least 8ms and
are extended at low LED PWM frequencies if the LED duty cycle is
low. This extension allows the output capacitor to charge to the
required value at a low current limit and prevents high input
current for systems that have only a low to medium output
current requirement.
For systems with no master fault protection FET, the inrush
current flows towards COUT when VIN is applied. The inrush
current is determined by the ramp rate of VIN and the values of
COUT and L.
FAULT PROTECTION AND MONITORING
The ISL78171 features extensive protection functions to cover all
perceivable failure conditions.
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The failure mode of an LED can be either an open circuit or a
short. The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some LEDs, a
Zener diode, which is integrated into the device in parallel with
the now-opened LED.
For basic LEDs (which do not have built-in Zener diodes), an
open-circuit failure of an LED results only in the loss of one
channel of LEDs, without affecting other channels. Similarly, a
short-circuit condition on a channel that results in that channel
being turned off does not affect other channels unless a similar
fault is occurring.
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
fault modes. The ISL78171 uses feedback from the LEDs to
determine when it is in a stable operating region and prevents
apparent faults during these transient events from allowing any
of the LED stacks to fault out. See Table 2 for details.
A fault condition that results in an input current that exceeds the
boost FET current limit of 2A (typ.) will result in a shutdown of all
output channels.
All LED faults are reported via the SMBus/I2C interface to
Register 0x02 (Fault/Status register). The controller is able to
determine which channels has failed via Register 0x09 (Output
Masking register). The controller can also choose to use Register
0x09 to disable faulty channels at start-up, resulting in only
further faulty channels being reported by Register 0x02.
SHORT-CIRCUIT PROTECTION (SCP)
The short-circuit detection circuit monitors the voltage on each
channel and disables faulty channels that are above
approximately 7.5V (this action is described in “Protections Table”
on page 17).
OPEN CIRCUIT PROTECTION (OCP)
When one of the LEDs becomes an open circuit, it can behave as
either an infinite resistance or as a gradually increasing finite
resistance. The ISL78171 monitors the current in each channel
such that any string that reaches the intended output current is
considered “good.” Should the current subsequently fall below the
target, the channel is considered an “open circuit.” Furthermore,
should the boost output of the ISL78171 reach the OVP limit, or
should the lower over-temperature threshold be reached, all
channels that are not good are immediately considered to be open
circuit. Detection of an open circuit channel results in a time-out
before the affected channel is disabled. This time-out is sped up
when the device is above the lower over-temperature threshold, in
an attempt to prevent the upper over-temperature trip point from
being reached.
Some users employ special types of LEDs that have a Zener
diode structure in parallel with the LED. This configuration
provides ESD enhancement and enables open circuit operation.
When this type of LED is open circuited, the effect is as if the LED
forward voltage has increased but the lighting level has not
increased. Any affected string will not be disabled, unless the
failure results in the boost OVP limit being reached, which allows
all other LEDs in the string to remain functional. In this case, care
should be taken that the boost OVP limit and SCP limit are set
FN8602.0
June 15, 2015
ISL78171
properly, to ensure that multiple failures on one string do not
cause all other good channels to fault out. This condition could
arise if the increased forward voltage of the faulty channel
makes all other channels look as if they have LED shorts. See
Table 2 for details of responses to fault conditions.
UNDERVOLTAGE LOCK-OUT
If the input voltage falls below the UVLO level, the device stops
switching and is reset. Operation restarts only when VIN returns
to the normal operating range.
INPUT OVERCURRENT PROTECTION
OVP AND VOUT
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
During a normal switching operation, the current through the
internal boost power FET is monitored. If the current exceeds the
current limit, the internal switch is turned off. Monitoring occurs
on a cycle-by-cycle basis in a self-protecting way.
The ISL78171 OVP threshold is set by RUPPER and RLOWER such
that:
OVER-TEMPERATURE PROTECTION (OTP)
 R UPPER + R LOWER 
V OUT_OVP = 1.22Vx -----------------------------------------------------------R LOWER
(EQ. 14)
The output voltage VOUT can regulate between 64% and 100% of
the VOUT_OVP such that:
Allowable VOUT = 64% to 100% of VOUT_OVP
If R1 and R2 are chosen such that the OVP level is set at 40V,
then VOUT is allowed to operate between 25.6V and 40V. If the
VOUT requirement is changed to an application of six LEDs of 21V,
then the OVP level must be reduced. Users should follow the
VOUT = (64% ~100%) OVP level requirement; otherwise, the
headroom control will be disturbed such that the channel voltage
can be much higher than expected. This can sometimes prevent
the driver from operating properly.
The resistances should be large, to minimize power loss. For
example, a 316kΩ RUPPER and a 10kΩ RLOWER sets OVP to 39.8V.
Large OVP resistors also allow COUT to discharge slowly during the
PWM Off time. Parallel capacitors should also be placed across
the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of 30pF is recommended. These capacitors
reduce the AC impedance of the OVP node, which is important
when using high-value resistors. For example, if
RUPPER/RLOWER = 33/1, then CUPPER/CLOWER = 1/33 with
CUPPER = 100pF and CLOWER = 3.3nF
The ISL78171 includes two over-temperature thresholds. The lower
threshold is set to +130°C. When this threshold is reached, any
channel that is outputting current at a level significantly below the
regulation target is treated as “open circuit” and is disabled after a
time-out period. This time-out period is 800µs when it is above the
lower threshold. The lower threshold isolates and disables bad
channels before they cause enough power dissipation (as a result of
other channels having large voltages across them) to hit the upper
temperature threshold.
The upper threshold is set to +150°C. Each time this threshold is
reached, the boost stops switching, and the output current
sources switch off. Once the device has cooled to approximately
+100°C, the device restarts, with the DC LED current level
reduced to 75% of the initial setting. If dissipation persists,
subsequent hitting of the limit causes identical behavior, with the
current reduced in steps to 50% and finally 25%. Unless disabled
via the EN pin, the device stays in an active state throughout.
For complete details of fault protection conditions, see Figure 29
and Table 2.
The OVP pin is also monitored such that if it rises above and
subsequently falls below 20% of the target OVP level, the input
protection FET is also switched off.
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ISL78171
LX
VIN
FAULT
VOUT
O/P
SHORT
DRIVER
OVP
IMAX
ILIMIT
LOGIC
FET
DRIVER
VSC
CH0
CH5
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
Q0 VSET
+
PWM/OC0/SC0
FAULT/
STATUS
REGISTER
SMBUS/I2C
CONTROL
LOGIC
+
Q5
-
-
PWM/OC5/SC5
DC CURRENT
FIGURE 29. SIMPLIFIED FAULT PROTECTIONS
TABLE 2. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
1
CHx Short Circuit
Upper Over-Temperature
Protection limit (OTP) not
triggered and CHx < 7.5V
CHx ON and burns power.
2
CHx Short Circuit
Upper OTP triggered but
CHx < 7.5V
All channels go off until chip cooled Same as CHx
and then comes back on with
current reduced to 76%. Subsequent
OTP triggers will reduce IOUT further.
Highest VF of
remaining
channels
3
CHx Short Circuit
Upper OTP not triggered
but CHx > 7.5V
CHx disabled after 6 PWM cycle
time-outs.
Remaining channels normal
Highest VF of
remaining
channels
4
CHx Open Circuit with Upper OTP not triggered
infinite resistance
and CHx < 7.5V
VOUT will ramp to OVP. CHx will
time-out after 6 PWM cycles and
switch off. VOUT will drop to normal
level.
Remaining channels normal
Highest VF of
remaining
channels
5
CHx LED Open Circuit Upper OTP not triggered
and CHx < 7.5V
but has paralleled
Zener
CHx remains ON and has highest VF, Remaining channels ON,
thus VOUT increases.
remaining channel FETs burn
power
VF of CHX
6
CHx LED Open Circuit Upper OTP triggered but
CHx < 7.5V
but has paralleled
Zener
All channels go off until chip cooled Same as CHx
and then comes back on with
current reduced to 76%. Subsequent
OTP triggers will reduce IOUT further
VF of CHx
7
CHx LED Open Circuit Upper OTP not triggered
but CHx > 7.5V
but has paralleled
Zener
VF of CHx
CHx remains ON and has highest VF, VOUT increases, then CH-X
thus VOUT increases.
switches OFF after 6 PWM cycles.
This is an unwanted shut off and
can be prevented by setting OVP
at an appropriate level.
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Remaining channels normal
VOUT REGULATED
BY
Highest VF of all
channels
FN8602.0
June 15, 2015
ISL78171
TABLE 2. PROTECTIONS TABLE (Continued)
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
VOUT REGULATED
BY
GOOD CHANNELS ACTION
8
Channel-to-Channel
VF too high
Lower OTP triggered but
CHx < 7.5V
Any channel below the target current will fault out after 6 PWM cycles.
Remaining channels driven with normal current.
Highest VF of
remaining
channels
9
Channel-to-Channel
VF too high
Upper OTP triggered but
CHx < 7.5V
All channels go off until chip cools and then come back on with current
reduced to 76%. Subsequent OTP triggers will reduce IOUT further.
Boost switch OFF
10
Output LED stack
voltage too high
VOUT > VOVP
Highest VF of
Any channel that is below the target current will time-out after 6 PWM
cycles, and VOUT will return to the normal regulation voltage required for remaining
channels
other channels.
11
VOUT/LX shorted to
GND at start-up or
VOUT shorted in
operation
LX current and timing are The chip is permanently shutdown 31ms after power-up if VOUT/Lx is
monitored.
shorted to GND.
OVP pins monitored for
excursions below 20% of
OVP threshold.
SMBCLK
tLOW
tF
tR
VIH
VIL
tHIGH
tHD:DAT
tHD:STA
tSU:STA
tSU:DAT
tSU:STO
SMBDAT
VIH
VIL
tBUF
P
S
P
S
NOTES:
SMBus/I2C Description
S = start condition
P = stop condition
A = acknowledge
A = not acknowledge
R/W = read enable at high; write enable at low
FIGURE 30. SMBUS/I2C INTERFACE
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
W
A
COMMAND CODE
A
DATA BYTE
A
P
Master to Slave
Slave to Master
FIGURE 31. WRITE BYTE PROTOCOL
1
7
1
1
8
1
1
8
1
1
8
1
1
S
SLAVE ADDRESS
W
A
COMMAND CODE
A
S
SLAVE ADDRESS
R
A
DATA BYTE
A
P
Master to Slave
Slave to Master
FIGURE 32. READ BYTE PROTOCOL
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ISL78171
SMBus/I2C Communications
Slave Device Address
The ISL78171 can be controlled by SMBus/I2C for PWM or DC
dimming. Except when both the SDA and SCL input pins are tied
to ground, the LEDs are off by default and the user must use the
SMBus/I2C interface to turn them on. When both SDA and SCL are
instead shorted to ground, the LEDs turn on by default when the IC is
turned on, and the customer can use the ISL78171 without having
to control the SMBus/I2C interface. The switching frequency is fixed
at 600kHz if SMBus/I2C is not used.
The slave address contains 7 MSB plus one LSB as R/W bit, but
these 8 bits are usually called Slave Address bytes. Figure 33
shows that the high nibble of the Slave Address byte is 0x5 or
0101b to denote the “backlight controller class.” Bit 3 in the
lower nibble of the Slave Address byte is 1. Bit 0 is always the
R/W bit, as specified by the SMBus/I2C protocol. Note: In this
document, the device address will always be expressed as a full
8-bit address instead of the shorter 7-bit address typically used in
other backlight controller specifications to avoid confusion.
Therefore, if the device is in the write mode where bit 0 is 0, the
slave address byte is 0x58 or 01011000b. If the device is in the
read mode where bit 0 is 1, the slave address byte is 0x59 or
01011001b.
Figure 32 shows that the four byte long Read Byte protocol starts
out with the slave address followed by the “command code”,
which translates to the “register index.” Subsequently, the bus
direction turns around with the re-broadcast of the slave address
with bit 0 indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That byte
value in the data byte reflects the value of the register being
queried at the “command code” index. Note the bus directions,
which are highlighted by the shaded label that is used on cycles
during which the slaved backlight controller “owns” or “drives”
the Data line. All other cycles are driven by the “host master.”
The backlight controller registers are Byte wide and accessible
via the SMBus/I2C Read/Write Byte protocols. Their bit
assignments are provided in the following sections with reserved
bits containing a default value of “0”.
MSB
0
LSB
1
DEVICE
IDENTIFIER
0
1
1
0
DEVICE
ADDRESS
0
R/W
BIT
Read Byte
SMBus/I2C Register Definitions
RIT
E
The Write Byte protocol is only three bytes long. The first byte
starts with the slave address followed by the “command code,”
which translates to the “register index” being written. The third
byte contains the data byte that must be written into the register
selected by the “command code”. A shaded label is used on
cycles during which the slaved backlight controller “owns” or
“drives” the Data line. All other cycles are driven by the “host
master.”
RE
AD
/W
Write Byte
FIGURE 33. SLAVE ADDRESS BYTE DEFINITION
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ISL78171
TABLE 3A. ISL78171 REGISTER LISTING
DEFAULT SMBUS/I2C
VALUE PROTOCOL
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x00
PWM Brightness
Control Register
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
0xFF
Read and
Write
0x01
Device Control
Register
PWM_SEL
BL_CTL
0x00
Read and
Write
FAULT
0x00
Read Only
Note 11)
0x02
0x03
0x07
Reserved Reserved Reserved Reserved Reserved PWM_MD
Fault/Status Register Reserved Reserved 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN
Identification
Register
LED
Panel
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
0xC8
Read Only
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
0xFF
Read and
Write
Reserved Reserved Reserved
BstSlew
Rate1
BstSlew
Rate0
FSW
Reserved
VSC
0x1F
Read and
Write
CH5
CH4
CH3
CH2
CH1
CH0
0x3F
Read and
Write
Phase
Shift5
Phase
Shift4
Phase
Shift3
Phase
Shift2
Phase
Shift1
Phase
Shift0
0x00
Read and
Write
Must be 0
Must be 0
0x00
Read and
Write
DC Brightness Control BRTDC7
Register
0x08
Configuration
Register
0x09
Output Channel
Register
0x0A
Phase Shift Deg
Equal
Phase
0x7F
Note 10)
Secondary Boost
Oscillator
Enable
Reserved Reserved
Phase
Shift6
Must be 0 Must be 0 Must be 0 Must be 0 Must be 0
TABLE 3B. DATA BIT DESCRIPTIONS
ADDRESS
REGISTER
DATA BIT DESCRIPTIONS
0x00
PWM Brightness Control
Register
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
0x01
Device Control Register
PWM_MD, PWM_SEL: select the dimming method - see Table 4 for more details. Default = 00
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
0x02
Fault/Status Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
0x03
Identification Register
LED PANEL = 1
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
0x07
DC Brightness Control Register
BRTDC[7..0] = 256 steps of DC brightness control
0x08
Configuration Register
BstSlewRate[1..0] = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50% drive strength,
10 - 75% drive strength, 11 - 100% drive strength.
fSW = Switching frequencies selection, fSW = 0 = 1.2MHz. fSW = 1 = 600kHz
VSC[0] = Short circuit thresholds selection, 0 = disabled, 1 = 7.5V minimum
0x09
Output Channel Mask/Fault
Readout Register
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In
Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled
0x0A
Phase Shift Degree
EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of
channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is
PhaseShift<6:0>/12.8MHz.
Secondary Boost Oscillator
Enable = 1: Use the secondary boost oscillator 800kHz OR Enable = 0, use the primary
600kHz/1.2MHz oscillator.
0x7F
Note 10)
10. Bit 7 of an additional register 0x7F that allows selecting an override boost frequency of 800kHz. This is done by writing 0x80 to register 0x7F. The
default value for register 0x7F is 0x00 when either 600kHz or 1.2MHz boost frequency is being used. Please ensure that the rest of the bits 0-6 in
register 0xF should remain at 0 at all times, failing to do so will adversely affect the PWM performance of the LED.
11. FAULT is a Read & Write bit.
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PWM Brightness Control Register (0x00)
Device Control Register (0x01)
The brightness control resolution has 256 steps of PWM duty cycle
adjustment. Figure 34 shows the bit assignment. All of the bits in
this Brightness Control Register can be read or written. Step 0
corresponds to the minimum step where the current is less than
10µA. Steps 1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle adjustment
per step.
This register has two bits that control either SMBus/I2C
controlled or external PWM controlled PWM dimming and a
single bit that controls the backlight ON/OFF state. The
remaining bits are reserved. The bit assignment is shown in
Figure 35. All other bits in the Device Control Register will read as
low unless otherwise written.
• An SMBus/I2C Write Byte cycle to Register 0x00 sets the PWM
brightness level only if the backlight controller is in SMBus/I2C
mode (see Table 4) Operating Modes selected by Device
Control Register Bits 1 and 2).
• An SMBus/I2C Read Byte cycle to Register 0x00 returns the
programmed PWM brightness level.
• All reserved bits have no functional effect when written.
• All defined control bits return their current, latched value when
read.
A value of 1 written to BL_CTL turns on the backlight in 4ms or less
after the write cycle completes. The backlight is deemed to be on
when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0.
A value of 0 written to BL_CTL immediately turns off the BL. The
BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0
and Register 0x09 is 0.
• An SMBus/I2C setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
• An SMBus/I2C setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness output.
The default value for Register 0x01 is 0x00.
• Default value for Register 0x00 is 0xFF.
REGISTER 0x00
PWM BRIGHTNESS CONTROL REGISTER
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
BRT[7..0]
= 256 steps of PWM brightness levels
FIGURE 34. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWM_MD
PWM_SEL
BL_CTL
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
PWM_MD
PWM_SEL
BL_CTL
MODE
X
X
0
Backlight Off
0
0
1
SMBus/I2C and PWM input controlled Display Power Saving Technology (DPST)
dimming (Method 3, PWMI x PWM Reg & FPWM)
1
0
1
SMBus/I2C controlled PWM dimming (Method 1, PWM Reg & FPWM)
X
1
1
PWM input controlled PWM dimming (Method 2, PWMI & FPWM)
FIGURE 35. DESCRIPTIONS OF DEVICE CONTROL REGISTER
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TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL
REGISTER BITS 1 AND 2
PWM_MD
PWM_SEL
0
0
SMBus/I2C and PWM input controlled
Display Power Saving Technology (DPST)
dimming (Method 3,PWMI x PWM Reg &
FPWM)
MODE
1
0
SMBus/I2C controlled PWM dimming
(Method 1, PWM Reg & FPWM)
X
1
PWM input controlled PWM dimming
(Method 2, PWMI & FPWM)
The PWM_SEL bit determines whether the SMBus/I2C or PWM
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, only the PWM input drives the
output brightness regardless of whether a 0 or 1 is stored in
PWM_MD.
When the PWM_SEL bit is set to 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted; when
this bit is 1, the PWM dimming is based on the SMBus/I2C
brightness register setting only. When this bit is set to 0, the
PWM dimming reflects a percentage change in the current
brightness programmed in the SMBus/I2C Register 0x00, i.e.,
DPST (Display Power Saving Technology) mode as:
DPST Brightness = Cbt  PWM I
(EQ. 15)
Where BRT is the value programmed in the PWM brightness
Register 0x00. BRT ranges from 0 to 255 in decimal and defaults
to 255 (0xFF). BRT = 0 disconnects all channels.
For example, the Cbt = 50% is the duty cycle programmed in the
SMBus/I2C Register 0x00 and the PWM frequency is tuned to be
200Hz with an appropriate resistor at the FPWM pin. And If the
PWMI is fed with a 1kHz 30% high PWM signal, while setting
PWM_SEL = 0 and PWM_MD = 0, the device is in the DPST mode of
operation, the resultant DPST brightness will be a 15% PWM
dimming at 200Hz.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight
controller’s operating state. Not all of the bits in this register are
fault related (Bit 3 is a simple BL status indicator). The remaining
bits are reserved and return a “0” when an read is executed and
ignored the bit value when written. All of the bits in this register are
read-only, with the exception of bit 0, which can be cleared by writing
to it.
• BL_STAT indicates the current back light on/off status in
BL_STAT (1 if the BL is on, 0 if the BL is off).
• FAULT is the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD,
and 1_CH_SD should these events occur.
• 1_CH_SD returns a 1 if one or more channels have faulted out.
• 2_CH_SD returns a 1 if two or more channels have faulted out.
Where:
PWM = is the percent duty cycle of the PWM input
Cbt = Current brightness setting from SMBus/I2C Register 0x00
(BRT) without influence from the PWM input:
 BRT 
Cbt = ----------------255
(EQ. 16)
• When FAULT is set to 1, it will remain at 1 even if the signal
which sets it goes away. FAULT will be cleared when the
BL_CTL bit of the Device Control Register is toggled or when a
0 is written into the FAULT bit. At that time, if the fault
condition is still present or reoccurs, FAULT will be set to 1
again. BL_STAT will not cause FAULT to be set.
• The default value for Register 0x02 is 0x00.
REGISTER 0x02
FAULT/STATUS REGISTER
RESERVED
RESERVED
2_CH_SD
1_CH_SD
BL_STAT
OV_CURR
THRM_SHDN
FAULT
Bit 7 (R)
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0
(R/W)
BIT
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
Bit 5
2_CH_SD
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
Bit 4
1_CH_SD
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
Bit 3
BL_STAT
= BL Status (1 = BL On, 0 = BL Off)
Bit 2
OV_CURR
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
Bit 1
THRM_SHDN
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
Bit 0
FAULT
= Fault occurred (Logic “OR” of all of the fault conditions)
FIGURE 36. DESCRIPTIONS OF FAULT/STATUS REGISTER
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Identification Register (0x03)
DC Brightness Control Register (0x07)
The ID register contains 3-bit fields to denote the LED driver
(always set to 1), manufacturer and the silicon revision of the
controller IC. The bit field widths allow up to 16 vendors with up
to 8 silicon revisions each. All of the bits in this register are
read-only.
The DC Brightness Control Register 0x07 sets the LED current
level between 0% and 100% of the level set using the RSET pin.
When PWM dimming, the level set is the current during the on
time. This register allows users to have additional dimming
flexibility by:
• Vendor ID 9 represents Intersil Corporation
1. Effectively achieving 16-bits of dimming control when DC
dimming is combined with PWM dimming
• The default value for Register 0x03 is 0xC8
The initial value of REV shall be 0. Subsequent values of REV will
increment by 1.
2. Achieving visual or audio noise free 8-bit DC dimming over
potentially noisy PWM dimming.
The bit assignment is shown in Figure 38. All of the bits in this
Register can be read or written. Steps 0 to 255 represent the
linear steps of DC current adjustment on-the-fly.
• An SMBus/I2C Write Byte cycle to Register 0x07 sets the DC
LED current level.
• An SMBus/I2C Read Byte cycle to Register 0x07 returns the DC
LED current.
• Default value for Register 0x07 is 0xFF.
REGISTER 0x03
ID REGISTER
LED PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Bit 7 = 1
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
MFG[3..0]
= Manufacturer ID. See “Identification Register
(0x03)” on page 23.
data 0 to 8 in decimal correspond to other vendors
data 9 in decimal represents Intersil ID
data 10 to 14 in decimal are reserved
data 15 in decimal Manufacturer ID is not
implemented
REV[2..0]
= Silicon rev (Rev 0 through Rev 7 allowed for silicon
spins)
FIGURE 37. DESCRIPTIONS OF ID REGISTER
REGISTER 0x07
DC BRIGHTNESS CONTROL REGISTER
BRTDC7
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BRTDC[7..0]
BIT FIELD DEFINITIONS
= 256 steps of DC brightness levels
FIGURE 38. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER
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ISL78171
Configuration Register (0x08)
The Configuration Register provides many extra functions that
users can explore in order to optimize the driver performance at
a given application.
A BstSlewRate bit allows users to control the boost FET slew rate
(the rates of turn-on and turn-off). The slew rate can be selected
up to four relative strengths when driving the internal boost FET.
The purpose of this function is to allow users to experiment with
the slew rate in order to meet to EMI compliance in the system.
In general, the slower the slew rate is, the lower the EMI
interference to the surrounding circuits, this however causes an
increase in the switching loss of the boost FET.
The FSW bit allows users to set the boost converter switching
frequency between 1.2MHz and 600kHz. The VSC bit allows
users to set the LED string short circuit threshold VSC to 7.5V or
disable it. If VSC function is enabled then the forward voltages
across the LED string matching must be less than 7.5V.
Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or written. It allows enabling and
disabling each channel individually. The bit position corresponds
to the channel. For example, Bit 0 corresponds to Ch0 and bit 5
corresponds to Ch5 and so on. A 1 bit value enables the channel
of interest. When reading data from this register, any disabled
channel and any faulted out channel will read as 0. This allows
the user to determine which channel is faulty and optionally not
enabling it in order to allow the rest of the system to continue to
function. Additionally, a faulted out channel can be disabled and
re-enabled in order to allow a retry for any faulty channel without
having to power-down the other channels.
The bit assignment is shown in Figure 40. The default for
Register 0x09 is 0x3F.
The bit assignment is shown in Figure 39. The default value for
Register 0x08 is 0x1F.
REGISTER 0x08
CONFIGURATION REGISTER
RESERVED
RESERVED
BIT5
BIT4
BIT3
FSW
RESERVED
VSC
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
BstSlewRate[1..0]
Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,
10 -75% drive strength, 11 to 100% drive strength.
FSW
2 levels of Switching Frequencies (0= 1,200kHz, 1 = 600kHz)
VSC
Enable/Disable Short Circuit Protection (0 = disabled, 1 = 7.5V minimum)
FIGURE 39. DESCRIPTIONS OF CONFIGURATION REGISTER
REGISTER 0x09
OUTPUT CHANNEL REGISTER
RESERVED
RESERVED
CH5
CH4
CH3
CH2
CH1
CH0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
CH[5..0]
CH5 = Channel 5, CH4 = Channel 4 and so on
FIGURE 40. OUTPUT CHANNEL REGISTER
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REGISTER 0x0A
PHASE SHIFT CONTROL REGISTER
EQUALPHASE
PHASESHIFT6
PHASESHIFT5
PHASESHIFT4
PHASESHIFT3
PHASESHIFT2
PHASESHIFT1
PHASESHIFT0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
EqualPhase
Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift
is 360/N (where N is the number of channels enabled).
PhaseShift[6..0]
7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)
FIGURE 41. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
and IL at On = IL at Off, therefore:
The Phase Shift Control register is used to set phase delay
between channels. When Bit 7 is set high, the phase delay is set
by the number of channels enabled and the PWM frequency.
Referring to Figure 3, the delay time is defined by Equation 17:
Where D is the switching duty cycle defined by the turn-on time
over the switching period. VD is a Schottky diode forward voltage
that can be neglected for approximation.
t D1 =  t FPWM  N 
(EQ. 17)
Where N is the number of channels enabled, and tFPWM is the
period of the PWM cycle. When Bit 7 is set low, the phase delay is
set by bits 6 to 0 and the PWM frequency. Referencing Figure 28,
the programmable delay time is defined by Equation 18:
t PD =  PS  6 0  xt FPWM   255  
(EQ. 18)
Where PS is an integer from 0 to 127, and tFPWM is the period of
the PWM cycle. By default, all the register bits are set low, which
sets zero delay between each channel. Note that the user should
not program the register to have more than one period of the
PWM cycle delay between the first and last enabled channels.
Secondary Boost Oscillator Register (0x7F)
The Secondary Boost Oscillator Register allows selecting a
secondary 800kHz oscillator to drive the LX pin switching
frequency, overriding the primary switching frequency selected in
Configuration Register. For those applications where the
switching frequency of the LX node may cause interference with
such functions as an AM radio tuner, etc, a secondary oscillator
with typical frequency of 800kHz is provided to help minimize
interference. Selection of the 800kHz oscillator is done by writing
0x80 to register 0x7F. The default value for register 0x7F is 0x00
when either 600kHz or 1.2MHz boost frequency is being used. It
is to be ensured that the rest of the bits 0-6 in register 0x7F
should remain at 0 at all times, failing to do so will adversely
affect the PWM performance.
Component Selection
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On
time is equal to the change of inductor current during the
switching regulator Off time. As shown in Equations 19 and 20,
since the voltage across an inductor is:
VL
I L = ------- xt
L
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(EQ. 19)
25
 V I – 0   L  D  tS =  VO – VD – VI   L   1 – D   tS
(EQ. 20)
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle, respectively, as shown in Equations 21 and 22:
VO  VI = 1   1 – D 
(EQ. 21)
D =  VO – VI   VO
(EQ. 22)
Input Capacitor
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. The capacitors reduce interaction between the regulator
and input supply, thus improving system stability. The high
switching frequency of the loop causes almost all ripple current
to flow into the input capacitor, which must be rated accordingly.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and to improve system efficiency.
The X5R and X7R ceramic capacitors offer small size and a lower
value for temperature and voltage coefficient compared to other
ceramic capacitors.
An input capacitor of 10µF is recommended. Ensure that the
voltage rating of the input capacitor is able to handle the full
supply range.
Inductor
Inductor selection should be based on its maximum current (ISAT)
characteristics, power dissipation (DCR), EMI susceptibility
(shielded vs unshielded), and size. Inductor type and value
influence many key parameters, including ripple current, current
limit, efficiency, transient performance, and stability.
Inductor maximum current capability must be adequate to
handle the peak current in the worst-case condition. If an
inductor core with too low a current rating is chosen, saturation
in the core will cause the effective inductor value to fall, leading
to an increase in peak-to-average current level, poor efficiency,
and overheating in the core. The inductor series resistance, DCR,
causes conduction loss and heat dissipation. A shielded inductor
is usually more suitable for EMI-susceptible applications such as
LED back light.
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The peak current can be derived from the voltage across the
inductor during the Off period, as shown in Equation 23:
Applications
IL peak =  V O  I O    85%  V I  + 1  2  V I   V O – V I    L  V O  f S  
(EQ. 23)
High Current Applications
The value of 85% is an average term for the efficiency
approximation. The first term is average current that is inversely
proportional to the input voltage. The second term is inductor
current change that is inversely proportional to L and fS. As a
result, for a given switching frequency and minimum input
voltage at which the system operates, the inductor ISAT must be
chosen carefully.
Each channel of the ISL78171 can support up to 30mA (50mA at
VIN = 12V). For applications that need higher current, multiple
channels can be grouped to achieve the desired current
(Figure 42). For example, the cathode of the last LED can be
connected to CH0 through CH2; this configuration can be treated
as a single string with 90mA current driving capability.
VOUT
Output Capacitors
The output capacitor smooths the output voltage and supplies
load current directly during the conduction phase of the power
switch. Output ripple voltage consists of discharge and charge of
the output capacitor during FET ON and OFF time and the voltage
drop due to flow through the ESR of the output capacitor. The
ripple voltage can be shown as Equation 24:
V CO =  I O  C O  D  f S  +   I O  ESR 
(EQ. 24)
The conservation of charge principle shown in Equation 22 also
indicates that, during the boost switch Off period, the output
capacitor is charged with the inductor ripple current, minus a
relatively small output current in boost topology. As a result, the
user must select an output capacitor with low ESR and adequate
input ripple current capability.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
COUT in Equation 24 assumes the effective value of the capacitor
at a particular voltage and not the manufacturer’s stated value,
measured at 0V.
Output Ripple
VCo, can be reduced by increasing Co or fSW, or using small ESR
capacitors. In general, ceramic capacitors are the best choice for
output capacitors in small to medium sized LCD backlight
applications due to their cost, form factor and low ESR.
A larger output capacitor will also ease the driver response
during PWM dimming Off period due to the longer sample and
hold effect of the output drooping. The driver does not need to
boost harder in the next On period that minimizes transient
current. The output capacitor is also needed for compensation,
and, in general 2x4.7µF/50V ceramic capacitors are suitable for
notebook display backlight applications.
CH0
CH1
CH2
FIGURE 42. GANGING MULTIPLE CHANNELS FOR HIGH CURRENT
APPLICATIONS
Low Voltage Operations
The ISL78171 VIN pin can be separately biased from the LED
power input to allow low-voltage operation. For systems that have
only a single supply, VOUT can be tied to the driver VIN pin to allow
initial start-up (Figure 43). The circuit works as follows: when the
input voltage is available and the device is not enabled, VOUT
follows VIN with a Schottky diode voltage drop. The VOUT
boot-strapped to the VIN pin allows initial start-up, once the part
is enabled. Once the driver starts up with VOUT regulating to the
target, the VIN pin voltage also increases. As long as VOUT does
not exceed 26.5V and the extra power loss on VIN is acceptable,
this configuration can be used for input voltage as low as 3.0V.
The Fault Protection FET feature cannot be used in this
configuration.
For systems that have dual supplies, the VIN pin can be biased
from 5V to 12V, while input voltage can be as low as 2.7V
(Figure 44). In this configuration, VBIAS must be greater than or
equal to VIN to use the fault FET.
Schottky Diode
A high-speed rectifier diode is necessary to prevent excessive
voltage overshoot. Schottky diodes are recommended because
of their fast recovery time, low forward voltage and reverse
leakage current, which minimize losses. The reverse voltage
rating of the selected Schottky diode must be higher than the
maximum output voltage. Also the average/peak current rating
of the Schottky diode must meet the output current and peak
inductor current requirements.
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VIN = 3V~21V
26.5V, 6 x 50mA*
ISL78171
1 FAULT
2 VIN
4 VDC
LX 20
The ISL78171 allows to turn each channel ON and OFF
independently. In field sequential RGB LED application, it is
possible to have different DC current and PWM duty cycle for
different channels as long as only one channel is active at a time.
This is achieved by continuously setting a new DC current and/or
PWM duty cycle each time a channel is turned ON. ISL78171
does not allow to have different DC currents or PWM duty cycles
for channels that are ON at the same time.
7 SMBCLK/SCL
CH0 10
CH1 11
5 PWM
3 EN
CH2 12
CH3 13
17 RSET
CH4 14
8 FPWM
CH5 15
9 AGND
COMP 18
Compensation
*VIN > 12V
FIGURE 43. SINGLE SUPPLY 3V OPERATION
40V, 6 x 50mA*
VIN = 2.7~26.5V
Q1 (OPTIONAL)
ISL78171
1 FAULT
VBIAS = 5V~12V
LX 20
2 VIN
OVP 16
4 VDC
The SMBus/I2C controlled PWM and DC dimming can be
combined to effectively provide 16 bits of dimming capability,
which can be valuable for automotive and avionics display
applications.
Field Sequential RGB LED Backlighting
OVP 16
PGND 19
6 SMBDAT/SDA
16-Bit Dimming
PGND 19
7 SMBCLK/SCL
The ISL78171 incorporates a transconductance amplifier in its
feedback path to allow the user to optimize boost stability and
transient response. The ISL78171 uses current mode control
architecture, which has a fast current sense loop and a slow
voltage feedback loop. The fast current feedback loop does not
require any compensation, but for stable operation, the slow
voltage loop must be compensated. The compensation is a
series of Rc, Cc1 network from COMP pin to ground, with an
optional Cc2 capacitor connected between the COMP pin and
ground. The Rc sets the high-frequency integrator gain for fast
transient response, and the Cc1 sets the integrator zero to
ensure loop stability. For most applications, the component
values in Figure 45 can be used: Rc is 10kΩ and Cc1 is 3.3nF.
Depending upon the PCB layout, for stability, a Cc2 of 390pF may
be needed to create a pole to cancel the output capacitor ESR’s
zero effect.
CH0 10
6 SMBDAT/SDA
CH1 11
5 PWM
CH2 12
3 EN
Rc 10k
CH3 13
17 RSET
CH4 14
8 FPWM
CH5 15
9 AGND
COMP 18
COMP
Cc1
3.3nF
*VIN > 12V
FIGURE 44. DUAL SUPPLIES 2.7V OPERATION
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Cc2
390pF
FIGURE 45. COMPENSATION CIRCUIT
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June 15, 2015
ISL78171
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
June 15, 2015
FN8602.0
CHANGE
Initial Release.
About Intersil
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28
FN8602.0
June 15, 2015
ISL78171
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.9± 0.10
C
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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29
FN8602.0
June 15, 2015