The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. CONTINUITY OF SPECIFICATIONS There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. CONTINUITY OF ORDERING PART NUMBERS Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. FOR MORE INFORMATION Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products and services. OUR CUSTOMERS Cypress is for true innovators – in companies both large and small. Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize their industries or create new industries with products and solutions that nobody ever thought of before. ABOUT CYPRESS Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to www.cypress.com. Cypress Semiconductor Corporation Document Number: 002-14829 Rev. *D 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised July 1, 2016 Preliminary Data Sheet BCM43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor GE NE R AL DE S C RI PT ION ® The Broadcom Ltd. BCM43907 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things applications. It supports all rates specified in the IEEE 802.11 a/b/g/n specifications.The device includes an ARM Cortexbased applications processor, a single stream IEEE 802.11n MAC/baseband/radio, a dual-band 5 GHz and 2.4 GHz transmit power amplifier (PA), and a receive low-noise amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments. The BCM43907 is an optimized SoC targeting embedded Internet-of-Things applications in the industrial and medical sensor, home appliance, and embedded audio markets. Using advanced design techniques and process technology to reduce active and idle power, the device is designed for embedded applications that require minimal power consumption and a compact size. The device includes a PMU for simplifying system power topology and allows for direct operation from a battery while maximizing battery life. F E A T U RE S Application Processor Features • ARM Cortex-R4 32-bit RISC processor. • 1 MB of on-chip SRAM for code and data. • An on-chip cryptography core • 640 KB of ROM containing WICED SDK components such as RTOS and TCP/IP stack. • 17 GPIOs supported. • Q-SPI serial flash interface to support up to 40 Mbps of peak transfer. • Support for UART (3), SPI or BSC master (2), BSC-only (2), and I2S (2) interfaces. (Broadcom Serial Control (BSC) is an I2C-compatible interface.) • Dedicated fractional PLL for audio clock (MCLK) generation. • USB 2.0 host and device modes. • SDIO 3.0 host and device modes. F E A T U RE S Key IEEE 801.11x Features • IEEE 802.11n compliant. • Single-stream spatial multiplexing up to 150 Mbps. • Supports 20/40 MHz channels with optional SGI. • Full IEEE 802.11 a/b/g legacy compatibility with enhanced performance. • TX and RX low-density parity check (LDPC) support for improved range and power efficiency. • On-chip power and low-noise amplifiers. • An internal fractional nPLL allows support for a wide range of reference clock frequencies. • Integrated ARM Cortex-R4 processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to future features in the field). • Software architecture supported by standard WICED SDK allows easy migration from existing discrete MCU designs and to future devices. • Security support: – WPA and WPA2 (Personal) support for powerful encryption and authentication. – AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility. – Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX 5.0). – Wi-Fi Protected Setup and Wi-Fi Easy-Setup • Worldwide regulatory support: Global products supported with worldwide design approval. General Features • Supports battery voltage range from 3.0V to 4.8V with an internal switching regulator. • Programmable dynamic power management. • 6 Kb OTP memory for storing board parameters. • 316-bump WLCSP (4.583 mm × 5.533mm, 0.2mm pitch). 43907-DS104-R Corporate Headquarters: San Jose, CA March 12, 2016 BCM43907 Preliminary Data Sheet Revision History Figure 1: Functional Block Diagram BCM43907 2 MB RAM, 640 KB ROM USB 2.0 UART SDIO 3.0 APPS ARM Cortex-R4 32 KB (I), 32 KB (D) ICACHE BSC PWM PWM (6) SDIO UART (3) SPI BSC (2) USB SPI or BSC (2) GPIO Crytography Engine Audio PLL RMII/MII AXI Audio 32 kHz External LPO AXI DMA I2S I2S (2) WLAN ARM Cortex-R4 AXI-to-AXI Bridge AXI to AXI Bridge JTAG GPIO (17) TCM 512 KB RAM 320 KB ROM WLAN IEEE 802.11 MAC APPS Domain RF Switch Controls 1 x 1, IEEE 802.11n PHY Always-On Domain REG_ON VBAT LNA RTC PS PS RAM SR_Eng PMU TX Switch VIO AXI PMU Control HIB_REG_ON_IN 37.4 MHz Crystal 2.4 GHz and 5 GHz Radio AXI-to-AXI Bridge 2.4 GHz PA LNA 5 GHz PA TX Switch BSC = Broadcom Serial Control. An I2C-compatible interface. WRF_PAOUT_5G WRF_RFIN_5G WRF_PAOUT_2G WRF_RFIN_2G Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 2 Revision History Revision Date Change Description 43907-DS104-R 03/12/16 43907-DS103-R 11/03/15 Updated: • General edits Updated: • Table 21: “Absolute Maximum Ratings,” on page 109. • Table 24: “Recommended Operating Conditions and DC Characteristics,” on page 111 • Table 30: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 116 • Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 119. • Table 32: “WLAN 5 GHz Receiver Performance Specifications,” on page 120. • Table 33: “WLAN 5 GHz Transmitter Performance Specifications,” on page 122. © 2016 by Broadcom. All rights reserved. Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, and Avago Technologies are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. BCM43907 Preliminary Data Sheet Revision History Revision Date Change Description 43907-DS102-R 10/15/2015 43907-DS101-R 43907-DS100-R 03/10/2015 11/03/2014 Updated: • Figure 3: “Typical Power Topology (Page 1 of 2),” on page 22. • Table 3: “Crystal Oscillator and External Clock — Requirements and Performance,” on page 32. • “Transmit Path” on page 61. • Figure 14: “Radio Functional Block Diagram,” on page 62. • “Calibration” on page 61. • Table 17: “Strapping Options,” on page 101. • Table 23: “ESD Specifications,” on page 110. • Table 24: “Recommended Operating Conditions and DC Characteristics,” on page 111. • “Introduction” on page 115. • Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 119. • Table 32: “WLAN 5 GHz Receiver Performance Specifications,” on page 120. • Table 33: “WLAN 5 GHz Transmitter Performance Specifications,” on page 122. • Section 18: “System Power Consumption,” on page 132. • Table 56: “SDIO Bus Input Timing Parameters (SDR Modes),” on page 145. • Table 64: “Package Thermal Characteristics,” on page 162. See the revision history of the applicable release. Initial release Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 4 BCM43907 Preliminary Data Sheet Table of Contents Table of Contents About This Document ................................................................................................................................ 13 Purpose and Audience .......................................................................................................................... 13 Acronyms and Abbreviations................................................................................................................. 13 Document Conventions ......................................................................................................................... 13 References ............................................................................................................................................ 14 Technical Support ...................................................................................................................................... 14 Section 1: Overview .......................................................................................................... 15 Introduction................................................................................................................................................. 15 Features .............................................................................................................................................. 16 Standards Compliance............................................................................................................................... 16 Section 2: Power Supplies and Power Management ..................................................... 18 Power Supply Topology............................................................................................................................. 18 BCM43907 Power Management Unit Features......................................................................................... 18 Power Management................................................................................................................................... 20 PMU Sequencing ........................................................................................................................................ 22 Power-Off Shutdown .................................................................................................................................. 23 Power-Up/Power-Down/Reset Circuits..................................................................................................... 23 Section 3: Frequency References.................................................................................... 24 Crystal Interface and Clock Generation ................................................................................................... 24 External Frequency Reference.................................................................................................................. 25 Frequency Selection .................................................................................................................................. 26 External 32.768 kHz Low-Power Oscillator .............................................................................................. 27 Section 4: Applications Subsystem................................................................................. 28 Overview...................................................................................................................................................... 28 Applications CPU and Memory Subsystem ............................................................................................. 28 Memory-to-Memory DMA Core.................................................................................................................. 28 Cryptography Core..................................................................................................................................... 29 Section 5: Applications Subsystem External Interfaces ............................................... 30 Ethernet MAC Controller (MII/RMII)........................................................................................................... 30 GPIO............................................................................................................................................................. 30 Broadcom Serial Control ........................................................................................................................... 30 I2S................................................................................................................................................................. 30 JTAG and ARM Serial Wire Debug............................................................................................................ 32 PWM............................................................................................................................................................. 33 Real-Time Clock.......................................................................................................................................... 33 SDIO 3.0....................................................................................................................................................... 34 Broadcom® March 12, 2016 • 43907-DS104-R Page 5 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Table of Contents SDIO 3.0—Device Mode ...................................................................................................................... 34 Description ..................................................................................................................................... 34 SDIO Pins ...................................................................................................................................... 35 SDIO 3.0—Host Mode .......................................................................................................................... 36 S/PDIF .......................................................................................................................................................... 36 SPI Flash ..................................................................................................................................................... 37 UART............................................................................................................................................................ 37 USB 2.0 ........................................................................................................................................................ 38 Overview ............................................................................................................................................... 38 USB 2.0 Features.................................................................................................................................. 41 Section 6: Global Functions ............................................................................................. 42 External Coexistence Interface ................................................................................................................. 42 One-Time Programmable Memory ............................................................................................................ 42 Hibernation Block....................................................................................................................................... 43 System Boot Sequence.............................................................................................................................. 43 Section 7: Wireless LAN Subsystem ............................................................................... 44 WLAN CPU and Memory Subsystem........................................................................................................ 44 IEEE 802.11n MAC ...................................................................................................................................... 44 PSM....................................................................................................................................................... 46 WEP ...................................................................................................................................................... 46 TXE ....................................................................................................................................................... 47 RXE ....................................................................................................................................................... 47 IFS......................................................................................................................................................... 47 TSF........................................................................................................................................................ 48 NAV ....................................................................................................................................................... 48 MAC-PHY Interface............................................................................................................................... 48 IEEE 802.11™ a/b/g/n PHY ......................................................................................................................... 49 Section 8: WLAN Radio Subsystem ............................................................................... 51 Receiver Path.............................................................................................................................................. 51 Transmit Path.............................................................................................................................................. 51 Calibration................................................................................................................................................... 51 Section 9: Pinout and Signal Descriptions .................................................................... 53 Bump List .................................................................................................................................................... 54 Signal Descriptions .................................................................................................................................... 59 Section 10: GPIO Signals and Strapping Options.......................................................... 65 Overview...................................................................................................................................................... 65 Weak Pull-Down and Pull-Up Resistances............................................................................................... 65 Strapping Options ...................................................................................................................................... 66 Broadcom® March 12, 2016 • 43907-DS104-R Page 6 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Table of Contents Alternate GPIO Signal Functions .............................................................................................................. 67 Section 11: Pin Multiplexing............................................................................................. 68 Section 12: I/O States........................................................................................................ 71 Section 13: Electrical Characteristics ............................................................................. 74 Absolute Maximum Ratings ...................................................................................................................... 74 Environmental Ratings .............................................................................................................................. 75 Electrostatic Discharge Specifications .................................................................................................... 75 Recommended Operating Conditions and DC Characteristics ............................................................. 76 Power Supply Segments............................................................................................................................ 78 Ethernet MAC Controller (MII/RMII) DC Characteristics ......................................................................... 78 GPIO, UART, and JTAG Interfaces DC Characteristics .......................................................................... 78 Section 14: WLAN RF Specifications .............................................................................. 79 Introduction................................................................................................................................................. 79 2.4 GHz Band General RF Specifications................................................................................................. 80 WLAN 2.4 GHz Receiver Performance Specifications ............................................................................ 80 WLAN 2.4 GHz Transmitter Performance Specifications ....................................................................... 83 WLAN 5 GHz Receiver Performance Specifications ............................................................................... 83 WLAN 5 GHz Transmitter Performance Specifications .......................................................................... 86 General Spurious Emissions Specifications ........................................................................................... 86 Transmitter Spurious Emissions Specifications .................................................................................... 87 2.4 GHz Band Spurious Emissions ................................................................................................ 87 20-MHz Channel Spacing ...................................................................................................... 87 5 GHz Band Spurious Emissions ................................................................................................... 89 20-MHz Channel Spacing ...................................................................................................... 89 40-MHz Channel Spacing ...................................................................................................... 90 Receiver Spurious Emissions Specifications ........................................................................................ 90 Section 15: Internal Regulator Electrical Specifications ............................................... 91 Core Buck Switching Regulator................................................................................................................ 91 3.3V LDO (LDO3P3) .................................................................................................................................... 92 CLDO ........................................................................................................................................................... 93 LNLDO ......................................................................................................................................................... 94 BBPLL LDO ................................................................................................................................................. 95 Section 16: System Power Consumption........................................................................ 96 WLAN Current Consumption..................................................................................................................... 96 2.4 GHz Mode ....................................................................................................................................... 96 5 GHz Mode .......................................................................................................................................... 97 Broadcom® March 12, 2016 • 43907-DS104-R Page 7 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Table of Contents Section 17: Interface Timing and AC Characteristics .................................................... 99 Ethernet MAC (MII/RMII) Interface Timing ................................................................................................ 99 MII Receive Packet Timing.................................................................................................................... 99 MII Transmit Packet Timing................................................................................................................. 100 RMII Receive Packet Timing ............................................................................................................... 101 RMII Transmit Packet Timing .............................................................................................................. 102 2 I S Master and Slave Mode TX Timing ................................................................................................... 103 SDIO Interface Timing .............................................................................................................................. 105 SDIO Default-Speed Mode Timing...................................................................................................... 105 SDIO High-Speed Mode Timing.......................................................................................................... 106 SDIO Bus Timing Specifications in SDR Modes ................................................................................. 107 Clock Timing ................................................................................................................................ 107 Device Input Timing ..................................................................................................................... 108 Device Output Timing................................................................................................................... 109 S/PDIF Interface Timing ........................................................................................................................... 110 SPI Flash Timing....................................................................................................................................... 112 Read-Register Timing ......................................................................................................................... 112 Write-Register Timing.......................................................................................................................... 113 Memory Fast-Read Timing.................................................................................................................. 114 Memory-Write Timing .......................................................................................................................... 115 SPI Flash Parameters ......................................................................................................................... 116 USB PHY Electrical Characteristics and Timing ................................................................................... 117 USB 2.0 and USB 1.1 Electrical and Timing Parameters.................................................................... 117 USB 2.0 Timing Diagrams................................................................................................................... 119 Section 18: Power-Up Sequence and Timing ............................................................... 122 Sequencing of Reset and Regulator Control Signals ........................................................................... 122 Description of Control Signals ............................................................................................................. 122 Control Signal Timing Diagrams.......................................................................................................... 123 Section 19: Thermal Information.................................................................................... 124 Package Thermal Characteristics ........................................................................................................... 124 Junction Temperature Estimation and PSIJT Versus THETAJC ........................................................... 124 Environmental Characteristics................................................................................................................ 124 Section 20: Mechanical Information .............................................................................. 125 Section 21: Ordering Information .................................................................................. 126 Broadcom® March 12, 2016 • 43907-DS104-R Page 8 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet List of Figures List of Figures Figure 1: Functional Block Diagram................................................................................................................... 2 Figure 2: Block Diagram and I/O...................................................................................................................... 15 Figure 3: Typical Power Topology (Page 1 of 2).............................................................................................. 19 Figure 4: Typical Power Topology (Page 2 of 2).............................................................................................. 20 Figure 5: Recommended Oscillator Configuration ........................................................................................... 24 Figure 6: Recommended Circuit to Use With an External Reference Clock .................................................... 25 Figure 7: Signal Connections to an SDIO Host (SD 4-Bit Mode) ..................................................................... 35 Figure 8: Signal Connections to an SDIO Host (SD 1-Bit Mode) ..................................................................... 35 Figure 9: Topology of the USB 2.0 Core ......................................................................................................... 38 Figure 10: BCM43907 Configured as a DRD + USB 2.0 PHY......................................................................... 40 Figure 11: Broadcom 2-Wire External Coexistence Interface.......................................................................... 42 Figure 12: WLAN MAC Architecture ................................................................................................................ 45 Figure 13: WLAN PHY Block Diagram............................................................................................................. 50 Figure 14: Radio Functional Block Diagram .................................................................................................... 52 Figure 15: 316-Bump WLCSP Map ................................................................................................................. 53 Figure 16: Port Locations for WLAN Testing ................................................................................................... 79 Figure 17: MII Receive Packet Timing ............................................................................................................. 99 Figure 18: MII Transmit Packet Timing .......................................................................................................... 100 Figure 19: RMII Receive Packet Timing ........................................................................................................ 101 Figure 20: RMII Transmit Packet Timing ....................................................................................................... 102 Figure 21: I2S Master Mode Transmitter Timing ............................................................................................ 103 Figure 22: I2S Slave Mode Receiver Timing.................................................................................................. 103 Figure 23: I2S Frame-Level Timing ................................................................................................................ 104 Figure 24: SDIO Bus Timing (Default-Speed Mode)...................................................................................... 105 Figure 25: SDIO Bus Timing (High-Speed Mode).......................................................................................... 106 Figure 26: SDIO Clock Timing (SDR Modes) ................................................................................................ 107 Figure 27: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 108 Figure 28: SDIO Bus Output Timing (SDR Modes up to 50 MHz) ................................................................. 109 Figure 29: S/PDIF Interface Timing ............................................................................................................... 110 Figure 30: S/PDIF Data Output Timing .......................................................................................................... 110 Figure 31: SPI Flash Read-Register Timing .................................................................................................. 112 Figure 32: SPI Flash Write-Register Timing .................................................................................................. 113 Figure 33: Memory Fast-Read Timing ........................................................................................................... 114 Figure 34: Memory-Write Timing ................................................................................................................... 115 Figure 35: SPI Flash Timing Parameters Diagram ........................................................................................ 116 Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 9 BCM43907 Preliminary Data Sheet List of Figures Figure 36: USB 2.0 Bus Reset to High-Speed Mode Operation .................................................................... 119 Figure 37: USB 2.0 High-Speed Mode Transmit Timing................................................................................ 120 Figure 38: USB 2.0 High-Speed Mode Receive Timing................................................................................. 121 Figure 39: REG_ON = High, No HIB_REG_ON_OUT Connection to REG_ON ........................................... 123 Figure 40: HIB_REG_ON_IN = High, HIB_REG_ON_OUT Connected to REG_ON .................................... 123 Figure 41: WLCSP Package .......................................................................................................................... 125 Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 10 BCM43907 Preliminary Data Sheet List of Tables List of Tables Table 1: BCM43907 Power Modes .................................................................................................................. 21 Table 2: Power-Up/Power-Down/Reset Control Signals.................................................................................. 23 Table 3: Crystal Oscillator and External Clock—Requirements and Performance ......................................... 25 Table 4: External 32.768 kHz Sleep Clock Specifications ............................................................................... 27 Table 5: Variable Sample Rate and MCLK Rate Support................................................................................ 32 Table 6: JTAG_SEL and TAP_SEL States for Test and Debug Function Selection........................................ 33 Table 7: SDIO Pin Descriptions ....................................................................................................................... 35 Table 8: USB Application Cases ...................................................................................................................... 39 Table 9: WLCSP Bump Names ....................................................................................................................... 54 Table 10: Signal Descriptions .......................................................................................................................... 59 Table 11: Strapping Options ............................................................................................................................ 66 Table 12: Alternate GPIO Signal Functions ..................................................................................................... 67 Table 13: Pin Multiplexing................................................................................................................................ 68 Table 14: I/O States ......................................................................................................................................... 71 Table 15: Absolute Maximum Ratings ............................................................................................................. 74 Table 16: Environmental Ratings ..................................................................................................................... 75 Table 17: ESD Specifications .......................................................................................................................... 75 Table 18: Recommended Operating Conditions and DC Characteristics ........................................................ 76 Table 19: Power Supply Segments.................................................................................................................. 78 Table 20: MII Recommended Operating Condition.......................................................................................... 78 Table 21: GPIO, UART, and JTAG Interfaces ................................................................................................. 78 Table 22: 2.4 GHz Band General RF Specifications........................................................................................ 80 Table 23: WLAN 2.4 GHz Receiver Performance Specifications .................................................................... 80 Table 24: WLAN 2.4 GHz Transmitter Performance Specifications ................................................................ 83 Table 25: WLAN 5 GHz Receiver Performance Specifications ....................................................................... 84 Table 26: WLAN 5 GHz Transmitter Performance Specifications ................................................................... 86 Table 27: Recommended Spectrum Analyzer Settings ................................................................................... 86 Table 28: 2.4 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications ......................... 88 Table 29: 5 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications ............................. 89 Table 30: 5 GHz Band, 40-MHz Channel Spacing TX Spurious Emissions Specifications ............................. 90 Table 31: 2G and 5G General Receiver Spurious Emissions .......................................................................... 90 Table 32: Core Buck Switching Regulator (CBUCK) Specifications ................................................................ 91 Table 33: LDO3P3 Specifications .................................................................................................................... 92 Table 34: CLDO Specifications ........................................................................................................................ 93 Table 35: LNLDO Specifications ...................................................................................................................... 94 Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 11 BCM43907 Preliminary Data Sheet List of Tables Table 36: BBPLL LDO Specifications .............................................................................................................. 95 Table 37: 2.4 GHz Mode WLAN Current Consumption ................................................................................... 96 Table 38: 5 GHz Mode WLAN Current Consumption ...................................................................................... 97 Table 39: MII Receive Packet Timing Parameters........................................................................................... 99 Table 40: MII Transmit Packet Timing Parameters........................................................................................ 100 Table 41: RMII Receive Packet Timing.......................................................................................................... 101 Table 42: RMII Transmit Packet Timing Parameters ..................................................................................... 102 Table 43: Timing for I2S Transmitters and Receivers.................................................................................... 103 Table 44: I2S_MCLK Specification ................................................................................................................ 104 Table 45: SDIO Bus Timing Parameters (Default-Speed Mode) ................................................................... 105 Table 46: SDIO Bus Timing Parameters (High-Speed Mode)....................................................................... 106 Table 47: SDIO Bus Clock Timing Parameters (SDR Modes) ....................................................................... 107 Table 48: SDIO Bus Input Timing Parameters (SDR Modes) ........................................................................ 108 Table 49: SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)............................................... 109 Table 50: SPDIF Biphase Mark Code Timing Parameters ............................................................................ 111 Table 51: SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency .................................... 111 Table 52: SPI Flash Timing Parameters ........................................................................................................ 116 Table 53: USB 2.0 Electrical and Timing Parameters.................................................................................... 117 Table 54: USB 1.1 FS/LS Electrical and Timing Parameters ........................................................................ 118 Table 55: Package Thermal Characteristics .................................................................................................. 124 Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 12 About This Document BCM43907 Preliminary Data Sheet About This Document Purpose and Audience This document provides details of the functional, operational, and electrical characteristics of the Broadcom® Ltd. BCM43907. It is intended for hardware design, application, and OEM engineers. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. Document Conventions The following conventions may be used in this document: Convention Description Bold User input and actions: for example, type exit, click OK, press Alt+C Monospace Code: #include <iostream> HTML: <td rowspan = 3> Command line commands and parameters: wl [-l] <command> <> Placeholders for required elements: enter your <username> or wl <command> [] Indicates optional command-line parameters: wl [-l] Indicates bit and byte ranges (inclusive): [0:3] or [7:0] Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 13 Technical Support BCM43907 Preliminary Data Sheet References The references in this section may be used in conjunction with this document. Note: Broadcom provides customer access to technical documentation and software through its Customer Support Portal (CSP) and Downloads and Support site (see Technical Support). For Broadcom documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name Number Source [1] USB 2.0 specification – www.usb.org [2] USB 1.1 Specification – www.usb.org Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads and Support site (http://www.broadcom.com/support/). Broadcom® March 12, 2016 • 43907-DS104-R BROADCOM CONFIDENTIAL Page 14 BCM43907 Preliminary Data Sheet Overview Section 1: Overview Introduction The Broadcom Ltd. BCM43907 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE 802.11 a/b/g/n MAC/baseband/radio and a separate ARM Cortex-R4 applications processor. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the BCM43907 and their associated external interfaces, which are described in greater detail in Section 5: “Applications Subsystem External Interfaces,” on page 30. Figure 2: Block Diagram and I/O BCM43907 SPI Flash GPIO[16:0] RF TX APPS Subsystem WLAN Subsystem ARM Cortex-R4 320 MHz 32 KB I-cache 32 KB D-cache ARM Cortex-R4 160 MHz 448 KB ROM TCM 576 KB SRAM TCM 2 MB SRAM 640 KB ROM 802.11n 1x1 2.4 GHz and 5 GHz RF RX 2x 2-Wire UART 4-Wire UART 2x I2S 2x SPI/BSC 2x BSC JTAG/SWD 10/100 Ethernet Switch Control Antenna Diversity SDIO 3.0/gSPI VDDIOs USB 2.0 GND WAKE Broadcom® March 12, 2016 • 43907-DS104-R Page 15 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Standards Compliance Features The BCM43907 supports the following features: • ARM Cortex-R4 clocked at 160 MHz (in 1× mode) or up to 320 MHz (in 2× mode). • 1 MB of SRAM and 640 KB ROM available for the applications processor. • One high-speed 4-wire UART interface with operation up to 4 Mbps. • Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins. • Two dedicated BSC1 interfaces. • Two SPI master/slave interfaces with operation up to 24 MHz. Note: Either or both of the SPI interfaces can be used as BSC master interfaces. This is in addition to the two dedicated BSC interfaces. • One SPI master interface for serial flash. • Six dedicated PWM outputs. • Two I2S interfaces. • 17 GPIOs. • IEEE 802.11 a/b/g/n 1×1 2.4 GHz and 5 GHz radio. • Single- and dual-antenna support. Standards Compliance The BCM43907 supports the following standards: • IEEE 802.11n • IEEE 802.11b • IEEE 802.11g • IEEE 802.11d • IEEE 802.11h • IEEE 802.11i • Security: – WEP – WPA Personal – WPA2 Personal – WMM – WMM-PS (U-APSD) – WMM-SA – AES (hardware accelerator) 1. Broadcom Serial Control (BSC) is an I2C-compatible interface. Broadcom® March 12, 2016 • 43907-DS104-R Page 16 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Standards Compliance – TKIP (hardware accelerator) – CKIP (software support) • Proprietary Protocols: – CCXv2 – CCXv3 – CCXv4 – CCXv5 – WFAEC The BCM43907 supports the following additional standards: • IEEE 802.11r—Fast Roaming (between APs) • IEEE 802.11w—Secure Management Frames • IEEE 802.11 Extensions: – IEEE 802.11e QoS enhancements (already supported as per the WMM specification) – IEEE 802.11i MAC enhancements – IEEE 802.11k radio resource measurement Broadcom® March 12, 2016 • 43907-DS104-R Page 17 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power Supplies and Power Management Section 2: Power Supplies and Power Management Power Supply Topology One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the BCM43907. All regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in embedded designs. A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the BCM43907. The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO, LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband. The BCM43907 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shut down. When in this state, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the BCM43907 with all required voltages. BCM43907 Power Management Unit Features The BCM43907 supports the following Power Management Unit (PMU) features: • VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator • VBAT to 3.3Vout (450 mA maximum) LDO3P3 • 1.35V to 1.2Vout (150 mA maximum) LNLDO • 1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for deep-sleep • 1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL • Additional internal LDOs (not externally accessible) • PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from the low powerconsumption mode. Figure 3 and Figure 4 on page 20 show the regulators and a typical power topology. Broadcom® March 12, 2016 • 43907-DS104-R Page 18 BROADCOM CONFIDENTIAL BCM43907 Power Management Unit Features BCM43907 Preliminary Data Sheet Figure 3: Typical Power Topology (Page 1 of 2) WLRF TX Mixer and PA (not always) Cap-less LNLDO 1.2V 1.2V VBAT Operational: 2.3V to 4.8V Performance: 3.0V to 4.8V Absolute Maximum: 5.5V Cap-less LNLDO Cap-less VCOLDO 1.2V VDDIO Operational: Cap-less LNLDO 1.2V Cap-less LNLDO 1.2V BCM43907 1.2V 3.3V 15 mA XTAL LDO 1.2V Mini-PMU (Inside WL Radio) VBAT 1.35V LPLDO1 WLRF LNA WLRF AFE and TIA WLRF TX WLRF ADC REF WLRF XTAL WLRF RFPLL, PFD, and MMD 1.2V LNLDO Core Buck Regulator (CBUCK) VDDIO WLRF LOGEN 1.35V BBPLL LNLDO Audio PLL 1.2V WL BBPLL/DFLL REG_ON CLDO 1.3V, 1.2V, .095V (AVS) WLAN/CLB/Top, Always On WL PHY WL Subcore WL VDDM (SRAMS in AOS) Supply ball Supply bump/pad Power switch Ground ball Ground bump/pad No power switch WLAN reset ball External to chip No dedicated power switch, but internal powerdown modes and block-specific power switches APPS VDDM Broadcom® March 12, 2016 • 43907-DS104-R APPS SOCSRAM APPS Subcore Page 19 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power Management Figure 4: Typical Power Topology (Page 2 of 2) BCM43907 2.5V and 3.3V 450 to 800 mA WLRF PA(2.4 GHz and 5 GHz) 3.3V VBAT LDO3P3 WLRF Pad (2.4 GHz and 5 GHz) VDDIO_RF WL OTP 3.3V 2.5V Cap-less LNLDO WL RF RX, TX, NMOS, Mini-PMU LDOs 2.5V Cap-less LNLDO 2.5V 2.5V Cap-less LNLDO 2.5V WL RF VCO WL RF CP VCOLDO2P5 Inside WL Radio Supply ball Supply bump/pad Power switch Ground ball Ground bump/pad No power switch External to chip No dedicated power switch, but internal powerdown modes and block-specific power switches Power Management The BCM43907 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43907 includes an advanced Power Management Unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the BCM43907 into various power management states appropriate to the environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever possible. Table 1 provides descriptions for the BCM43907 power modes. Broadcom® March 12, 2016 • 43907-DS104-R Page 20 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power Management Table 1: BCM43907 Power Modes Mode Description Active All WLAN blocks in the BCM43907 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. Doze The radio, analog domains, and most of the linear regulators are powered down. The rest of the BCM43907 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or TCXO) are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. Deep-sleep Most of the chip, including both analog and digital domains and most of the regulators, is powered off. Logic states in the digital core are saved and preserved in a retention memory in the AlwaysOn domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt, or a host resume through the USB bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. Power-down The BCM43907 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. Broadcom® March 12, 2016 • 43907-DS104-R Page 21 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet PMU Sequencing PMU Sequencing The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of the following four states: • enabled • disabled • transition_on • transition_off The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loaded with the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled and decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: • Computes the required resource set based on requests and the resource dependency table. • Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource and inverts the ResourceState bit. • Compares the request with the current resource status and determines which resources must be enabled or disabled. • Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents. • Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Broadcom® March 12, 2016 • 43907-DS104-R Page 22 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power-Off Shutdown Power-Off Shutdown The BCM43907 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system devices remain operational. When the BCM43907 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM43907 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the BCM43907, all outputs are tristated and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM43907 to be fully integrated in an embedded device while taking full advantage of the lowest power-saving modes. When the BCM43907 is powered on from this state, it is the same as a normal power-up and does not retain any information about its state from before it was powered down. Power-Up/Power-Down/Reset Circuits The BCM43907 has two signals (see Table 2) that enable or disable circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required powerup sequences, see Section 18: “Power-Up Sequence and Timing,” on page 122. Table 2: Power-Up/Power-Down/Reset Control Signals Signal Description REG_ON This signal is used by the PMU to power up the BCM43907. It controls the internal BCM43907 regulators. When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device is in reset and the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. HIB_REG_ON_IN This signal is used by the hibernation block to decide whether or not to power down the internal BCM43907 regulators. If HIB_REG_ON_IN is low, the regulators will be disabled. For a signal at HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON. Broadcom® March 12, 2016 • 43907-DS104-R Page 23 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Frequency References S e c t i o n 3 : F re q u e n c y R e f e r e n c e s An external crystal is used for generating all radio frequencies and normal-operation clocking. As an alternative, an external frequency reference can be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. Crystal Interface and Clock Generation The BCM43907 can use an external crystal to provide a frequency reference. The recommended crystal oscillator configuration, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5: Recommended Oscillator Configuration Device boundary C WRF_XTAL_XON 1.3 pF 27 pF 37.4 MHz C x ohms 27 pF Programmable internal shunt caps are from 0 pF to 7.5 pF in steps of 0.5 pF. WRF_XTAL_XOP 0.4 pF External resistor and programmable internal resistor value is determined by crystal drive level. Programmable internal series resistor is from 50 ohms to 500 ohms in steps of 50 ohms. Boot-up ROM value is 50 ohms. Note: A reference schematic is available for further details. Contact your Broadcom FAE. A fractional-N synthesizer in the BCM43907 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in Table 3 on page 25. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details. Broadcom® March 12, 2016 • 43907-DS104-R Page 24 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet External Frequency Reference External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise requirements listed in Table 3. If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown in Figure 6. The internal clock buffer connected to this pin will be turned off when the BCM43907 goes into sleep mode. When the clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin. Figure 6: Recommended Circuit to Use With an External Reference Clock 1000 pF Reference Clock WRF_XTAL_XON NC WRF_XTAL_XOP Table 3: Crystal Oscillator and External Clock—Requirements and Performance Crystala Parameter Conditions/Notes Frequency 2.4 GHz band: Between 19 MHz and 52 MHz d IEEE 802.11n operation and legacy IEEE 802.11b/g operation 5 GHz band, IEEE 802.11n operation only Min. Typ. Max. External Frequency Referenceb c Min. Typ. Max. Units 19 – 52 35 – 52 MHz Frequency tolerance Without trimming over the lifetime of the equipment, including temperaturee –20 – 20 –20 – 20 ppm Crystal load capacitance – – 16 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – µW – – – 30k 100k – Ω – – 7.5 – – 7.5 pF Input impedance Resistive (WRF_XTAL_XON) Capacitive WRF_XTAL_XON Input low level DC-coupled digital signal – – – 0 – 0.2 V WRF_XTAL_XON Input high level DC-coupled digital signal – – – 1.0 – 1.26 V Broadcom® March 12, 2016 • 43907-DS104-R Page 25 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Frequency Selection Table 3: Crystal Oscillator and External Clock—Requirements and Performance (Cont.) Crystala Parameter Conditions/Notes WRF_XTAL_XON input voltage (see Figure 6) Min. External Frequency Referenceb c Typ. Max. Min. Typ. Max. Units IEEE 802.11a/b/g operation only – – – 400 – 1200 mVp-p WRF_XTAL_XON input voltage (see Figure 6) IEEE 802.11n AC-coupled analog – input – – 1 – – Vp-p Duty cycle 37.4 MHz clock – – 40 50 60 % – Phase (IEEE 802.11b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Phase noisef (IEEE 802.11a) 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz Phase noisef (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Phase noisef (IEEE 802.11n, 5 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz noisef a. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP. b. See “External Frequency Reference” on page 25 for alternative connection methods. c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. The frequency step size is approximately 80 Hz. e. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. f. Assumes that external clock has a flat phase noise response above 100 kHz. Frequency Selection Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard handset reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The BCM43907 must have the reference frequency set correctly in order for any of the external interfaces to function correctly, since all bit timing is derived from the reference frequency. Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Broadcom for more information. Broadcom® March 12, 2016 • 43907-DS104-R Page 26 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet External 32.768 kHz Low-Power Oscillator The reference frequency for the BCM43907 may be set in the following ways: • Set the xtalfreq=xxxxx parameter (in Hertz) in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. • Auto-detect any of the standard handset reference frequencies using an external LPO clock. For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM43907 automatically detects the reference frequency and programs itself to the correct reference frequency. In order for automatic frequency detection to work correctly, the BCM43907 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 4 on page 27 and is present during a power-on reset. External 32.768 kHz Low-Power Oscillator The BCM43907 uses a secondary low frequency clock for low-power-mode timing. Either the internal lowprecision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one tradeoff caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 4. Table 4: External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768 kHz Frequency accuracy ±200 ppm Duty cycle 30–70 % Input signal amplitude 200–3300 mV, p-p Signal type Square-wave or sine-wave – >100k <5 Ω pF <10,000 ppm Input impedancea Clock jitter (during initial start-up) a. When power is applied or switched off. Broadcom® March 12, 2016 • 43907-DS104-R Page 27 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Applications Subsystem Section 4: Applications Subsystem Overview The Applications subsystem contains the general use CPU, memory, the standalone DMA core, the cryptography core, and the majority of the external interfaces. Applications CPU and Memory Subsystem This subsystem has an integrated 32-bit ARM Cortex-R4 processor with an internal 32 KB D-cache and an internal 32 KB I-cache. The ARM Cortex-R4 is a low-power processor that features a low gate count, low interrupt latency, and low-cost debugging capabilities. It is intended for deeply embedded applications that require fast interrupt response features. The ARM Cortex-R4 implements the ARM v7-R architecture and supports the Thumb-2 instruction set. At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on a MIPS/µW basis. It also supports integrated sleep modes. Using multiple technologies to reduce cost, the ARM Cortex-R4 enables improved memory utilization, reduced pin overhead, and reduced silicon area. It also has extensive debugging features, including real-time tracing of program execution. On-chip memory for the CPU includes 1 MB SRAM, 640 KB ROM, and an 8 KB RAM powered independently of the application subsystem. Memory-to-Memory DMA Core The BCM43907 memory-to-memory DMA (M2MDMA) engine contains eight DMA channel pairs, each containing one transmit/pull engine and one receive/push engine. The DMA engine provides general purpose data movement between memories that can be on the device, attached directly to the device, or accessed through a host interface. The transmit/pull engine reads data from the source memory and immediately passes it to the paired receive/push engine, which proceeds to write it to the destination memory. Multiple masters can program the individual channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters. Broadcom® March 12, 2016 • 43907-DS104-R Page 28 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Cryptography Core Cryptography Core This core provides general purpose data movement between memories, which may be either on the device, attached directly to the device, or accessed through a host interface. The transmit/pull engine reads data from the source memory and passes it immediately to the paired receive/push engine that proceeds to write it to the destination memory. Multiple masters may program the individual channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters. The cryptography block provides a hardware accelerator for enciphering and deciphering data that has undergone processing using standards-based encryption algorithms. The cryptography block includes the following primary features: • Encryption and hash engines that support single pass AUTH-ENC or ENC-AUTH processing. • A scalable AES module that supports CBC, ECB, CTR, CFB, OFB, and XTS encryption with 128-, 192-, and 256-bit key sizes. • A scalable DES module that supports DES and 3DES in ECB and CBC modes. • An RC4 stream cipher module that supports state initialization, state update, and key-stream generation. • MD5, SHA1, SHA224, and SHA256 engines that support pure hash or HMAC operations. • A built-in 512-byte key cache for locally protected key storage. OTP memory is used to store authentication keys. Broadcom® March 12, 2016 • 43907-DS104-R Page 29 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Applications Subsystem External Interfaces Section 5: Applications Subsystem External Interfaces Ethernet MAC Controller (MII/RMII) The BCM43907 integrates a high performance Ethernet MAC controller. The controller interfaces to an external PHY either over a Media Independent Interface (MII) or a Reduced Media Independent Interface (RMII). The controller can transmit and receive data at 10 Mbps and 100 Mbps. GPIO There are 17 general-purpose I/O (GPIO) pins available on the BCM43907. The GPIOs can be used to connect to various external devices. Upon power-up and reset, these pins are tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other functions. Apart from other functions, GPIOs are used to set bootstrap options and use the JTAG interface for debugging during software development. Broadcom Serial Control The BCM43907 has two Broadcom Serial Control (BSC2) master interfaces for external communication with codecs, DACs, NVRAM, etc. The I/O pads can be configured as pull-ups or pull-ups can be installed on the reference design to support a multimaster on an open drain bus. I2S The BCM43907 has two I2S interfaces for audio signal data. The two interfaces are identical. Each interface supports both Master and Slave modes. The following signals apply to the first I2S interface: • I2S bit clock: I2S_SCLK0 (sometimes referred to as I2S_BITCLK) • I2S word select: I2S_LRCK0 (sometimes referred to as I2S_WS) • I2S serial data out: I2S_SDATAO0 • I2S serial data in: I2S_SDATAI0 2. Broadcom Serial Control is an I2C compatible interface. Broadcom® March 12, 2016 • 43907-DS104-R Page 30 BROADCOM CONFIDENTIAL I2S BCM43907 Preliminary Data Sheet • I2S master clock: I2S_MCLK0 The following signals apply to the second I2S interface: • I2S bit clock: I2S_SCLK1 (sometimes referred to as I2S_BITCLK) • I2S word select: I2S_LRCK1 (sometimes referred to as I2S_WS) • I2S serial data out: I2S_SDATAO1 • I2S serial data in: I2S_SDATAI1 • I2S master clock: I2S_MCLK1 I2S_SDATAO0 and I2S_SDATAO1 are outputs. I2S_MCLK, I2S_SCLK and I2S_LRCLK can be configured as either inputs or outputs depending on whether the master clock source is on- or off-chip and whether the I2S is operating in Slave or Master mode. Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit-clock cycle after the I2S_LRCK transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S_LRCK is low, and right-channel data is transmitted when I2S_LRCK is high. An embedded 128 × 32-bit single-port SRAM for data processing enhances the performance of the interface. An audio PLL generates an internal master clock (for I2S_MCLK0 and I2S_MCLK1) that provides support for various sampling rates. Broadcom® March 12, 2016 • 43907-DS104-R Page 31 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet JTAG and ARM Serial Wire Debug Table 5 shows the MCLK rates (in MHz) associated with each of the various sample rates. In the table, FS refers to the sample rate in kHz and typical MCLK rates are shaded. Table 5: Variable Sample Rate and MCLK Rate Supporta MCLK Rate (MHz)b Sample Rate (kHz) 128 × FS 192 × FS 256 × FS 384 × FS 512 × FS 640 × FS 768 × FS 1152 × FS 8 1.024 1.536 2.048 3.072 4.096 5.12 6.144 9.216 11.025 1.4112 2.1168 2.8224 4.2336 5.6448 7.056 8.4672 12.7008 12 1.536 2.304 3.072 4.608 6.144 7.68 9.216 13.824 16 2.048 3.072 4.096 6.144 8.192 10.24 12.288 18.432 22.05 2.8224 4.2336 5.6448 8.4672 11.2896 14.112 16.9344 25.4016 24 3.072 4.608 6.144 9.216 12.288 15.36 18.432 27.648 32 4.096 6.144 8.192 12.288 16.384 20.48 24.576 36.864 44.1 5.6448 8.4672 11.2896 16.9344 22.5792 28.224 33.8688 – 48 6.144 9.216 12.288 18.432 24.576 30.72 36.864 – 64 8.192 12.288 16.384 24.576 32.768 – – – 88.2 11.2896 16.9344 22.5792 33.8688 – – – – 96 12.288 18.432 24.576 36.864 – – – – 192 24.576 36.864 – – – – – – a. All data in the table assumes a crystal frequency of 37.4 MHz. b. MCLK frequency errors are less than 1 ppb. For an MCLK specification, see Table 44 on page 104. An external MCLK source can be provided to the device instead of using the internal MCLK source. The BCM43907 needs an external clock source input on the slave clock pin for the I2S interface to work properly in Slave mode. The slave clock frequency is dependent upon the audio sample rate and the external I2S codec. JTAG and ARM Serial Wire Debug The BCM43907 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. The BCM43907 also supports ARM Serial Wire Debug (SWD) for connecting a JTAG debugger directly to both ARM Cortex-R4s. For SWD, the combination of a clock and a bidirectional signal (on a single pin) provides normal JTAG debug and test functionality. The reduced pin-count SWD interface is a high-performance alternative to the JTAG interface. Broadcom® March 12, 2016 • 43907-DS104-R Page 32 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet PWM Table 6 shows the JTAG_SEL and TAP_SEL states for test and debug function selection. Test and debug function selection is independent of the debugging interface (JTAG or SWD) being used. Table 6: JTAG_SEL and TAP_SEL States for Test and Debug Function Selection JTAG_SEL State TAP_SEL State Test and Debug Function 0 0 JTAG not used. 0 1 JTAG not used. 1 0 Access the LV tap directly for ATE and bring-up. 1 1 Access either of the ARM Cortex-R4’s directly via either the 5-pin JTAG port or the 2-pin SWD configuration. PWM The BCM43907 provides up to six independent pulse width modulation (PWM) channels. The following features apply to the PWM channels: • Each channel is a square wave generator with a programmable duty cycle. • Each channel generates its duty cycle by dividing down the input clock. • Both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register. • Each channel can work independently or update simultaneously. • Pairs of PWM outputs can be inverted for devices that need a differential output. • Continuous or single pulses can be generated. • The input clock can either be a high-speed clock from a PLL channel or a lower speed clock at the crystal frequency. Real-Time Clock The BCM43907 provides a real-time clock (RTC) provided that an accurate 32.768 kHz crystal is used. The RTC generates date/time using the 32.768 kHz reference and is always powered on when the chip is on, except while in Hibernation mode. The RTC has a precision of seconds and will display the calendar day and time provided the initial start time is programmed correctly. The second, minute, hour, day, month, year, and 24-hour mode can be set individually. Interrupts can be set on any periodic time event or on specific time events. The PMU uses the RTC interrupt to determine when to wake up the chip. Broadcom® March 12, 2016 • 43907-DS104-R Page 33 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO 3.0 SDIO 3.0 SDIO 3.0—Device Mode Description The BCM43907 WLAN section supports SDIO version 3.0, including the new UHS-I modes: • DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). • HS: High-speed up to 50 MHz (3.3V signaling). • SDR12: SDR up to 25 MHz (1.8V signaling). • SDR25: SDR up to 50 MHz (1.8V signaling). Note: The BCM43907 is backward compatible with SDIO v2.0 host interfaces. The following three functions are supported: • Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B) • Function 1 Backplane Function to access the internal SoC address space (max. BlockSize/ByteCount = 64B) • Function 2 WLAN Function for efficient WLAN packet transfer through DMA (max. BlockSize/ByteCount = 512B) Broadcom® March 12, 2016 • 43907-DS104-R Page 34 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO 3.0 SDIO Pins Table 7: SDIO Pin Descriptions SD 4-Bit Mode SD 1-Bit Mode DATA0 Data line 0 DATA DATA1 Data line 1 or Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait DATA3 Data line 3 Not used N/C Data line CLK Clock CLK Clock CMD Command line CMD Command line Figure 7: Signal Connections to an SDIO Host (SD 4-Bit Mode) CLK SD Host CMD BCM43907 DAT[3:0] Figure 8: Signal Connections to an SDIO Host (SD 1-Bit Mode) CLK CMD SD Host DATA BCM43907 IRQ RW Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four data (DATA) lines and the command (CMD) line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host’s internal pull-ups. Broadcom® March 12, 2016 • 43907-DS104-R Page 35 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet S/PDIF SDIO 3.0—Host Mode The BCM43907 WLAN section supports SDIO version 3.0, including the new UHS-I modes: • DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). • HS: High-speed up to 50 MHz (3.3V signaling). • SDR12: SDR up to 25 MHz (1.8V signaling). • SDR25: SDR up to 50 MHz (1.8V signaling). Note: The BCM43907 is backward compatible with SDIO v2.0 devices. In this mode, the device supports the following features: • ADMA2. • Out-of-band signaling for card detection, write protection, and I/O voltage levels (which are available on GPIOs). • Dynamic, specification-compliant shifting from 3.3V to 1.8V I/Os. S/PDIF S/PDIF is a serial audio data transport format used to connect consumer audio devices such as CD players, DVD players, and surround-sound receivers. Although S/PDIF can be used to transport uncompressed audio formats, the primary use case for the BCM43907 S/PDIF interface is to transport multichannel compressed audio for surround-sound applications, especially Dolby Digital and DTS, to an auxiliary external audio processor. The BCM43907 can support two S/PDIF interfaces via the I2S_SDATA00 and I2S_SDATA01 pins. Because each S/PDIF interface uses an I2S data line, only I2S or S/PDIF functionality can be enabled on each I2S interface. Each S/PDIF interface has the following key requirements: • S/PDIF transmissions that conform with IEC 60958-1 (receiver not required). • Support for linear PCM audio data that conforms with IEC 60948-3. • Support for nonlinear PCM audio data that conforms with IEC 60948-3. • Support for priority payload formats that include IEC 61937-3 (AC-3) and IEC 61937-5 (DTS). • Support for sample rates from 32 kHz to 192 kHz. • Support for 16, 20, and 24-bit audio samples. • Support for only one concurrent compressed audio stream. Broadcom® March 12, 2016 • 43907-DS104-R Page 36 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SPI Flash SPI Flash The SPI flash interface supports the following features: • A SPI-compatible serial bus. • An 80 MHz (maximum) clock frequency. • Quad I/O, which provides increased throughput to 40 MB/s. • Support for either ×1 or ×4 addresses with ×4 data. • 3-bytes and 4-byte addressing modes. • A configurable dummy-cycle count that is programmable from 1 to 15. • Programmable instructions output to serial flash. • An option to change the sampling edge from rising-edge to falling-edge for read-back data when in highspeed mode. UART A high-speed 4-wire CTS/RTS UART interface can be enabled by software and has dedicated pins. Provided primarily for debugging during development, this UART enables the BCM43907 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 × 8 in each direction. There are two low-speed UART interfaces on the BCM43907. Each functions as a standard 2-wire UART. They are also enabled as alternate functions on GPIOs and can be enabled independently of the 4-wire fast UART. Broadcom® March 12, 2016 • 43907-DS104-R Page 37 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB 2.0 USB 2.0 Overview The USB 2.0 host controller (HC) and device controller (DC) interface to a backplane via Advanced eXtensible Interface (AXI) and Advanced Peripheral Bus (APB). They interface externally through a USB 2.0 and HSIC interfaces. Figure 9 shows the topology of the USB 2.0 core. Figure 9: Topology of the USB 2.0 Core AXI/APB USB Device Controller APB USB Host Controller UTMI/ULPI Host/ Device Select UTMI/ULPI Multiplexer UTMI/ULPI USB 2.0 PHY Chip Boundary USB I/F The BCM43907 contains both a USB 2.0 HC and DC. Therefore, it can operate in the host-only, device-only, and dual-role device (DRD) modes. In DRD mode, the BCM43907 can be configured as either the host or a device on the fly but must remain in the same mode until the next boot cycle. The restriction that the host or device mode remains fixed during a boot cycle is what differentiates DRD from On-the-Go (OTG). The state of the USB2_DSEL pin sets the mode as either host or device for USB Type A and Type B connectors. For a USB Micro-AB connector, the USB2_DSEL pin sets the mode as either host or device while the overall mode is DRD. Broadcom® March 12, 2016 • 43907-DS104-R Page 38 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB 2.0 Table 8 shows the supported application cases. The table also shows the USB mode and PHY type, the connector type, and the USB2_DSEL state associated with each case. Table 8: USB Application Cases Application Case Shorthand Mode PHY DRD + USB 2.0 PHY DRD-Host USB 2.0 0 DRD-Device USB 2.0 1 Type: Micro-AB Connect USB2_DSEL to the ID pin of the Micro-AB receptacle. Host USB 2.0 0 Type A USB 2.0 1 Type B Host + USB 2.0 PHY Device + USB2.0 PHY Device USB2_DSEL Connector Information Note: In host mode, the USB core can process an overcurrent event and take the appropriate action. The overcurrent event is input into the BCM43907 via the alternative mode pin USB20H_CTL. Figure 10 shows the BCM43907 configured to operate in DRD mode with a USB 2.0 PHY. Broadcom® March 12, 2016 • 43907-DS104-R Page 39 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB 2.0 Figure 10: BCM43907 Configured as a DRD + USB 2.0 PHY AXI/APB PPC EHC/OHC DWDC/DMA OVC UTMI UTMI Multiplexer UTMI Demulitplexer VBUS UTMI USB 2.0 PHY D+/D– 5V VBUS Switch USB 2.0 Micro-AB ID Connector USB2_DSEL Chip Boundary EHC: OHC: OVC: PPC: UTMI: Enhanced Host Controller Open Host Controller Overcurrent indication Port power control USB USB 2.0 Host or Device The following information pertains to Figure 10: • The Micro-AB receptacle connects the BCM43907 to an external host or device. • The Micro-AB connector ID pin is connected to the BCM43907 USB2_DSEL pin. • The BCM43907 GPIO_9 pin is high in order to select the USB 2.0 PHY. • The PPC line indicates whether the USB 2.0 host controller supports port power control. • The OVC line is used to indicate an overcurrent condition. • Standard differential signal lines D+ (DP) and D– (DM) are used for the USB 2.0 interface Broadcom® March 12, 2016 • 43907-DS104-R Page 40 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB 2.0 USB 2.0 Features The following capabilities and features apply to the BCM43907 USB 2.0 PHY: • Compliant with the UTMI+ level 2 specification. • Functions as a host, device, or OTG PHY. • Supports high speed (HS) at 480 Mbps, full speed (FS) at 12 Mbps, and low speed (LS) at 1.5 Mbps. • Integrates pull-up and pull-down terminations with resistor support (per an engineering change notice to the USB 2.0 specification). • Contains a calibrated 45Ω termination for HS TX/RX. • Uses half-duplex differential data signaling with NRZI encoding. • Recovers the data and clock from the data stream. • Integrates a 960 MHz PLL with a single-ended reference clock. • Supports host resume and remote wake-up. • Supports L1 and L2 suspend, shallow sleep, and Link-Power Management (LPM). • Supports legacy USB 1.1 devices through a serial interface. • Supports dribble bits. • Supports LS keep-alive packets (LS EOP). • Support HS keep-alive packets (HS SYNC). • Contains an onboard BERT for self-testing (PRBS and fixed patterns). • Dissipates a maximum power of 150 mW for 1-port in loop-back mode. • Contains an integrated 3.3V to 1.2V LDO. • Uses 3.3V. Broadcom® March 12, 2016 • 43907-DS104-R Page 41 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Global Functions Section 6: Global Functions External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external colocated wireless device, such as Bluetooth, to manage wireless medium sharing for optimum performance. Figure 11 shows the coexistence interface. Figure 11: Broadcom 2-Wire External Coexistence Interface BCM43907 WLAN GCI BT\IC SECI_OUT SECI_IN UART_IN UART_OUT NOTES: SECI_OUT/BT_TXD and SECI_IN/BT_RXD are multiplexed on the GPIOs. The 2-wire coexistence interface is intended for future compatibility with the BT SIG 2-wire interface that is being standardized for Core 4.1. One-Time Programmable Memory Various hardware configuration parameters can be stored in an internal 6144-bit (768 bytes) One-Time Programmable (OTP) memory that is read by system software after a device reset. In addition, customerspecific parameters, including the system vendor ID and MAC address can be stored, depending on the specific board design. The initial state of all bits in an unprogrammed OTP memory device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP memory array can be programmed in a single write-cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits that are still in the 0 state can be altered during each programming cycle. Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file. The nvram.txt file is provided with the reference board design package. Broadcom® March 12, 2016 • 43907-DS104-R Page 42 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Hibernation Block Hibernation Block The Hibernation (HIB) block is a self-contained power domain that can be used to completely shut down the rest of the BCM43907. This optional block uses the HIB_REG_ON_OUT pin to drive the REG_ON pin. Therefore, for the HIB block to work as designed, the HIB_REG_ON_OUT pin must be connected to the REG_ON pin. To use the HIB block, software programs the HIB block with a wake count and then asserts a signal indicating that the chip should be put into hibernation. After assertion, the HIB block drives HIB_REG_ON_OUT low for the number of 32 kHz clock cycles programmed as the wake count. After the wake-count timer expires, HIB_REG_ON_OUT is driven high. Other than the logic state of the HIB block, no state is saved in the BCM43907 during hibernation. System Boot Sequence The following general sequence occurs after a BCM43907 is powered on: 1. Either REG_ON or HIB_REG_ON_IN is asserted. Note: For HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON. 2. The core LDO (CLDO) and LDO3P3 outputs stabilize. 3. The OTP memory bits are used to initialize various functions, such as PMU trimming, package selection, memory size selection, etc. 4. The APP and WLAN cores are powered up. 5. The XTAL is powered up. 6. The APP and WLAN CPU bootup sequences start. Broadcom® March 12, 2016 • 43907-DS104-R Page 43 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Wireless LAN Subsystem Section 7: Wireless LAN Subsystem WLAN CPU and Memory Subsystem The BCM43907 WLAN section includes an integrated 32-bit ARM Cortex-R4 processor with internal RAM and ROM. The ARM Cortex-R4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response features. Delivering more than a 30% performance gain over ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb-2 instruction set. At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It also supports integrated sleep modes. On-chip memory for this CPU includes 576 KB of SRAM and 448 KB of ROM. IEEE 802.11n MAC The BCM43907 WLAN media access controller (MAC) is designed to support high-throughput operation with low power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power-saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 12. The following sections provide an overview of the important MAC modules. Broadcom® March 12, 2016 • 43907-DS104-R Page 44 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet IEEE 802.11n MAC Figure 12: WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TX-FIFO 32 KB PMQ RX-FIFO 10 KB PSM PSM UCODE Memory IFS Backoff, BTCX WEP TKIP, AES, WAPI TSF SHM BUS IHR NAV EXT- IHR BUS TXE TX A-MPDU RXE RX A-MPDU Shared Memory 6 KB MAC-PHY Interface The BCM43907 WLAN MAC supports features specified in the IEEE 802.11 base standard and amended by IEEE 802.11n. The key MAC features include: • Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT). • Support for power management schemes, including WMM power-save, power-save multipoll (PSMP), and multiphase PSMP operation. • Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware. • Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management. • Support for immediate ACK and Block-ACK policies. • Interframe space timing support, including RIFS. • • Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges. Support for coexistence with Bluetooth and other external radios. • • Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification. Programmable independent basic service set (IBSS) or infrastructure basic service set functionality. • Statistics counters for MIB support. Broadcom® March 12, 2016 • 43907-DS104-R Page 45 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet IEEE 802.11n MAC PSM The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware in order to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, allowing algorithms to be optimized very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications. The PSM fetches instructions from microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables. The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs are colocated with the hardware functions they control and are accessed by the PSM via the IHR bus. The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction literals, and the results are written into the shared memory, scratch-pad memory, or IHRs. There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs) or on the results of ALU operations. WEP The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform encryption and decryption as well as MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP. The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to use. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. Broadcom® March 12, 2016 • 43907-DS104-R Page 46 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet IEEE 802.11n MAC TXE The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with the WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel-access mechanisms. The data received from the DMA engines are stored in transmit FIFOs. The MAC has multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module. The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed. RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO. The RXE module contains filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types. The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS. IFS The IFS module contains the timers required to determine interframe-space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe-spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. When the timer expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the TSF is synchronized to the network. Broadcom® March 12, 2016 • 43907-DS104-R Page 47 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet IEEE 802.11n MAC The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions. TSF The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP. NAV The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carriersense indication. MAC-PHY Interface The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an programming interface that can be controlled either by the host or the PSM to configure and control the PHY. Broadcom® March 12, 2016 • 43907-DS104-R Page 48 BROADCOM CONFIDENTIAL IEEE 802.11™ a/b/g/n PHY BCM43907 Preliminary Data Sheet IEEE 802.11™ a/b/g/n PHY The BCM43907 WLAN digital PHY complies with IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance, handheld applications. The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates optimized implementations of filters, FFTs, and Viterbi-decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sensing and rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier-sensing algorithm provides high throughput for IEEE 802.11b/g hybrid networks with Bluetooth coexistence. The key PHY features include: • Programmable data rates from MCS0–7 in 20 MHz and 40 MHz channels. • Support for Optional Short GI and Green Field modes in TX and RX. • TX and RX LDPC for improved range and power efficiency. • All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive direction. • Support for IEEE 802.11h/k for worldwide operation. • Advanced algorithms for low power consumption and enhanced sensitivity, range, and reliability. • Algorithms to improve performance in the presence of externally received Bluetooth signals. • An automatic gain control scheme for blocking and nonblocking cellular applications. • Closed loop transmit power control. • Digital RF chip calibration algorithms to handle CMOS RF chip process, voltage, and temperature (PVT) variations. • On-the-fly channel frequency and transmit power selection. • Per-packet RX antenna diversity. • Available per-packet channel quality and signal-strength measurements. • Compliance with FCC and other worldwide regulatory requirements. Broadcom® March 12, 2016 • 43907-DS104-R Page 49 BROADCOM CONFIDENTIAL IEEE 802.11™ a/b/g/n PHY BCM43907 Preliminary Data Sheet Figure 13: WLAN PHY Block Diagram Filters and Radio Comp AFE and Radio Radio Control Block Common Logic Block Filters and Radio Comp CCK/DSSS Demodulate Frequency and Timing Synch Carrier Sense, AGC, and Rx FSM Tx FSM OFDM Demodulate Buffers Viterbi Decoder Descramble and Deframe FFT/IFFT MAC Interface Modulation and Coding Frame and Scramble PA Comp Modulate/ Spread COEX Broadcom® March 12, 2016 • 43907-DS104-R Page 50 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN Radio Subsystem Section 8: WLAN Radio Subsystem The BCM43907 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Ten RF control signals are available to drive external RF switches. In addition, these control signals can be used to support optional external 5 GHz band power and low-noise amplifiers. See the reference board schematics for more information. A block diagram of the radio subsystem is shown in Figure 14 on page 52. Note that integrated on-chip baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. Receiver Path The BCM43907 has a wide dynamic range, direct conversion receiver that employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The 2.4 GHz and 5 GHz paths each have a dedicated on-chip low-noise amplifier (LNA). Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively. Linear on-chip power amplifiers deliver high output powers while meeting IEEE 802.11a/b/g/n specifications without the need for external PAs. When using the internal PA, which is required in the 2.4 GHz band and optional in the 5 GHz band, closed-loop output power control is completely integrated. Calibration The BCM43907 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. These calibration routines are performed periodically during the course of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and LOFT calibration for carrier leakage reduction. In addition, I/Q calibration and VCO calibration are performed on-chip. No per-board calibration is required during manufacturing testing. This helps to minimize the test time and cost in large-volume production environments. Broadcom® March 12, 2016 • 43907-DS104-R Page 51 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Calibration Figure 14: Radio Functional Block Diagram WL TX 2.4 GHz Mixer TX Mode Switch WL DAC WL TXLPF WL PA WL DAC WL A-PA WL A-PAD WL TXLPF WL TX 5 GHz Mixer WL RX 5 GHzMixer WLAN BB Voltage Regulators WL ADC WL A-LNA11 WL A-LNA12 WL RXLPF WL ADC TX Mode Switch WL-G-LNA11 WL G-LNA12 WL RXLPF WL RX 2.4 GHz Mixer WL 5 GHz TX WL 5 GHz RX WL 2.4 GHz TX WL 2.4 GHz RX WL LOGEN WL PLL XON Shared XO LPO/Ext LPO/RCAL Broadcom® March 12, 2016 • 43907-DS104-R XOP Page 52 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Pinout and Signal Descriptions Section 9: Pinout and Signal Descriptions Figure 15 shows the bump map of the WLCSP package. Figure 15: 316-Bump WLCSP Map Broadcom® March 12, 2016 • 43907-DS104-R Page 53 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Bump List Bump List Table 9 contains the WLCSP bump names. Table 9: WLCSP Bump Names Bump Name Bump Name 1 NO_CONNECT 36 NO_CONNECT 2 NO_CONNECT 37 NO_CONNECT 3 NO_CONNECT 38 NO_CONNECT 4 NO_CONNECT 39 VSSC 5 NO_CONNECT 40 VSSC 6 VSSC 41 NO_CONNECT 7 NO_CONNECT 42 VSSC 8 NO_CONNECT 43 NO_CONNECT 9 NO_CONNECT 44 NO_CONNECT 10 NO_CONNECT 45 NO_CONNECT 11 NO_CONNECT 46 NO_CONNECT 12 NO_CONNECT 47 NO_CONNECT 13 NO_CONNECT 48 NO_CONNECT 14 VSSC 49 NO_CONNECT 15 VSSC 50 VSSC 16 NO_CONNECT 51 NO_CONNECT 17 NO_CONNECT 52 VSSC 18 NO_CONNECT 53 VSSC 19 NO_CONNECT 54 NO_CONNECT 20 NO_CONNECT 55 NO_CONNECT 21 VSSC 56 VSSC 22 VSSC 57 VSSC 23 NO_CONNECT 58 VSSC 24 NO_CONNECT 59 VSSC 25 VSSC 60 VSSC 26 NO_CONNECT 61 NO_CONNECT 27 NO_CONNECT 62 NO_CONNECT 28 NO_CONNECT 63 NO_CONNECT 29 NO_CONNECT 64 NO_CONNECT 30 NO_CONNECT 65 NO_CONNECT 31 NO_CONNECT 66 NO_CONNECT 32 NO_CONNECT 67 NO_CONNECT 33 NO_CONNECT 68 NO_CONNECT 34 NO_CONNECT 69 NO_CONNECT VSSC 70 NO_CONNECT 35 Broadcom® March 12, 2016 • 43907-DS104-R Page 54 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Bump List Bump Name Bump Name 71 SFL_IO1 111 SR_PVSS 72 SFL_IO3 112 SR_VLX 73 SFL_IO0 113 SR_VDDBAT5V 74 SFL_CS 114 VOUT_CLDO 75 SFL_IO2 115 LDO_VDD1P5 76 SPI0_CLK 116 LDO_VDD1P5 77 SFL_CLK 117 VOUT_3P3_SENSE 78 SPI0_MISO 118 VOUT_3P3 79 VSSC 119 VOUT_3P3 80 SPI1_CS 120 LDO_VDD1P5 81 SPI0_SISO 121 VOUT_CLDO 82 SPI0_CS 122 SR_VDDBAT5V 83 SPI1_CLK 123 SR_PVSS 84 SPI1_MISO 124 SR_PVSS 85 UART0_CTS 125 SR_VDDBAT5V 86 SPI1_SISO 126 VOUT_CLDO 87 UART0_TXD 127 LDO_VDD1P5 88 UART0_RXD 128 LDO_VDDBAT5V 89 I2C1_CLK 129 LDO_VDDBAT5V 90 I2C1_SDATA 130 GPIO_14 91 UART0_RTS 131 GPIO_13 92 I2C0_CLK 132 GPIO_5 93 I2C0_SDATA 133 GPIO_6 94 GPIO_9 134 GPIO_8 95 GPIO_7 135 VSSC 96 VSSC 136 GPIO_4 97 PMU_AVSS 137 GPIO_16 98 SR_VLX 138 VDDC 99 SR_VLX 139 GPIO_2 100 REG_ON 140 GPIO_11 101 SR_VLX 141 GPIO_0 102 SR_VLX 142 GPIO_1 103 VOUT_CLDO_SENSE 143 GPIO_12 104 VSSC 144 GPIO_3 105 VDDIO 145 GPIO_15 106 VOUT_LNLDO 146 GPIO_10 107 VOUT_BBPLLOUT 147 SDIO_DATA_3 108 SR_VDDBAT5V 148 SDIO_DATA_2 109 SR_VLX 149 SDIO_DATA_1 110 SR_PVSS 150 SDIO_DATA_0 Broadcom® March 12, 2016 • 43907-DS104-R Page 55 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Bump List Bump Name Bump Name 151 SDIO_CMD 191 AVSS_AUDIO 152 SDIO_CLK 192 AVDD1P2_AUDIO 153 I2S_MCLK0 193 JTAG_SEL 154 I2S_SCLK0 194 CLK_REQ 155 I2S_SDATAO1 195 VDDIO 156 I2S_SDATAI1 196 RF_SW_CTRL_9 157 VDDIO_I2S 197 VSSC 158 I2S_MCLK1 198 SRSTN 159 VDDIO_I2S 199 VDDIO_RF 160 I2S_SCLK1 200 RF_SW_CTRL_8 161 I2S_SDATAO0 201 RF_SW_CTRL_7 162 I2S_LRCLK1 202 RF_SW_CTRL_6 163 I2S_LRCLK0 203 OTP_VDD3P3 164 I2S_SDATAI0 204 AVDD1P2 165 USB2_DSEL 205 RF_SW_CTRL_3 166 USB2_AVDD33 206 RF_SW_CTRL_4 167 USB2_DP 207 RF_SW_CTRL_5 168 USB2_AVSS 208 VDDIO_RF 169 USB2_RREF 209 VSSC 170 USB2_DM 210 VSSC 171 USB2_DVSS 211 RF_SW_CTRL_2 172 USB2_AVSSBG 212 AVSS 173 USB2_AVDD33LDO 213 LPO_XTAL_IN 174 VDDIO 214 RF_SW_CTRL_1 175 USB2_MONCDR 215 RF_SW_CTRL_0 176 USB2_AVDD33IO 216 VDDC 177 VSSC 217 VDDC 178 VSSC 218 WRF_AFE_GND 179 NO_CONNECT 219 WRF_AFE_GND 180 NO_CONNECT 220 WRF_XTAL_VDD1P2 181 NO_CONNECT 221 WRF_XTAL_VDD1P35 182 VSSC 222 WRF_XTAL_XOP 183 VSSC 223 WRF_SYNTH_VDD3P3 184 USB2_MONPLL 224 WRF_AFE_GND 185 PWM0 225 WRF_AFE_GND 186 PWM1 226 WRF_XTAL_XON 187 PWM4 227 WRF_PMU_VDD1P35 188 PWM5 228 WRF_PMU_VDD1P35 189 PWM3 229 WRF_SYNTH_VDD1P2 190 PWM2 230 WRF_AFE_GND Broadcom® March 12, 2016 • 43907-DS104-R Page 56 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Bump List Bump Name Bump Name 231 WRF_AFE_VDD1P35 271 VDDC 232 WRF_AFE_GND 272 VSSC 233 WRF_RFIN_5G 273 VSSC 234 WRF_AFE_GND 274 VSSC 235 WRF_EXT_TSSIA 275 VDDC 236 WRF_AFE_GND 276 VDDC 237 WRF_GPAIO_OUT 277 VDDC 238 WRF_AFE_GND 278 HIB_REG_ON_OUT 239 WRF_PAOUT_5G 279 HIB_WAKE_B 240 WRF_PA_VDD3P3 280 VDDC 241 WRF_PA_VDD3P3 281 VDDC 242 WRF_AFE_GND 282 HIB_REG_ON_IN 243 WRF_AFE_GND 283 HIB_LPO_SELMODE 244 WRF_TXMIX_VDD 284 RMII_G_TXD3 245 WRF_PAOUT_2G 285 VDDC 246 WRF_RFIN_2G 286 VDDC 247 WRF_AFE_GND 287 VSSC 248 VSSC 288 RMII_MDIO 249 HIB_XTALIN 289 VDDC 250 HIB_XTALOUT 290 VSSC 251 VSSC 291 VSSC 252 VDDC 292 VSSC 253 VSSC 293 RMII_G_COL 254 VDDC 294 RMII_G_TXC 255 VDDIO_SD 295 RMII_G_RXD2 256 VSSC 296 RMII_G_RXD3 257 VDDIO 297 RMII_G_RXC 258 VDDIO 298 RMII_G_CRS 259 VSSC 299 RMII_G_RXD1 260 VSSC 300 RMII_G_TXD2 261 VDDIO 301 VSSC 262 VSSC 302 VSSC 263 VDDIO 303 RMII_G_RXD0 264 VSSC 304 RMII_G_TXD0 265 VSSC 305 VDDIO_RMII 266 VSSC 306 RMII_G_TXEN 267 VDDC 307 VDDIO_RMII 268 VDDC 308 VSSC 269 VDDIO 309 VDDC 270 HIB_VDDO 310 RMII_MDC Broadcom® March 12, 2016 • 43907-DS104-R Page 57 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Bump Name 311 RMII_G_TXD1 312 RMII_G_RXDV 313 VSSC 314 VDDC 315 VSSC 316 VDDC Bump List Broadcom® March 12, 2016 • 43907-DS104-R Page 58 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Signal Descriptions Table 10 provides the signal name, type, and description for each BCM43907 bump. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, and O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Table 10: Signal Descriptions Bump Number Signal Name Type Description Broadcom Serial Control (BSC) Interfaces 92 I2C0_CLK O BSC master clock. 93 I2C0_SDATA I/O BSC serial data 89 I2C1_CLK O BSC master clock 90 I2C1_SDATA I/O BSC serial data 222 WRF_XTAL_XOP I XTAL oscillator input. 226 WRF_XTAL_XON O XTAL oscillator output. 213 LPO_XTAL_IN I External sleep clock input (32.768 kHz). 249 HIB_XTALIN I 3.3V 32 kHz crystal input 250 HIB_XTALOUT O 3.3V 32 kHz crystal output 194 CLK_REQ O Reference clock request Clocks Ethernet MAC Interface (MII/RMII) 297 RMII_G_RXC I MII receive clock 293 RMII_G_COL I MII collision detection 298 RMII_G_CRS I MII carrier sense 294 RMII_G_TXC I MII/RMII transmit clock 304 RMII_G_TXD0 O MII/RMII transmit signal 311 RMII_G_TXD1 O MII/RMII transmit signal 300 RMII_G_TXD2 O MII transmit signal 284 RMII_G_TXD3 O MII transmit signal 303 RMII_G_RXD0 I MII/RMII receive signal 299 RMII_G_RXD1 I MII/RMII receive signal 295 RMII_G_RXD2 I MII receive signal 296 RMII_G_RXD3 I MII receive signal 288 RMII_MDIO I/O MII/RMII management data 310 RMII_MDC O MII/RMII management clock 306 RMII_G_TXEN O MII/RMII transmit enable 312 RMII_G_RXDV I MII/RMII receive data valid Broadcom® March 12, 2016 • 43907-DS104-R Page 59 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Table 10: Signal Descriptions (Cont.) Bump Number Signal Name Type Description GPIO Interface (WLAN) 141 GPIO_0 I/O 142 GPIO_1 I/O 139 GPIO_2 I/O 144 GPIO_3 I/O 136 GPIO_4 I/O 132 GPIO_5 I/O 133 GPIO_6 I/O 95 GPIO_7 I/O 134 GPIO_8 I/O 94 GPIO_9 I/O 146 GPIO_10 I/O 140 GPIO_11 I/O 143 GPIO_12 I/O 131 GPIO_13 I/O 130 GPIO_14 I/O 145 GPIO_15 I/O 137 GPIO_16 I/O Programmable GPIO pins. Ground 218, 219, 224, 225, WRF_AFE_GND 230, 232, 234, 236, 238, 242, 243, 247 GND AFE ground VSSC 6, 14, 15, 21, 22, 25, 35, 39, 40, 42, 50, 52, 53, 56–60, 79, 96, 104, 135, 177, 178, 182, 183, 197, 209, 210, 248, 251, 253, 256, 259, 260, 262, 264–266, 272–274, 287, 290–292, 301, 302, 308, 313, 315 GND Core ground for WLAN and APP sections 110, 111, 123, 124 SR_PVSS GND Power ground 97 PMU_AVSS GND Quiet ground 212 AVSS GND Baseband PLL ground 191 AVSS_AUDIO GND AUDIO PLL ground 168 USB2_AVSS GND USB 2.0 analog ground 172 USB2_AVSSBG GND USB 2.0 analog ground 171 USB2_DVSS GND USB 2.0 digital ground Broadcom® March 12, 2016 • 43907-DS104-R Page 60 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Table 10: Signal Descriptions (Cont.) Bump Number Signal Name Type Description Hibernation Block, Power-Down/Power-Up, and Reset 100 REG_ON I Used by PMU to power up or power down the internal BCM43907 regulators used by the WLAN and APP sections. Also, when deasserted, this pin holds the WLAN and APP sections in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. 282 HIB_REG_ON_IN I Used by the hibernation block to power up or power down the internal BCM43907 regulators. For applications that use the hibernation block, HIB_REG_ON_OUT must connect to REG_ON. Also, when deasserted, this pin holds the WLAN and APP sections in reset. 278 HIB_REG_ON_OUT O REG_ON output signal generated by the hibernation block. 279 HIB_WAKE_B I Wake up chip from hibernation mode. 283 HIB_LPO_SELMODE I Select precise or coarse 32 kHz clock. 198 SRSTN I System reset. This active-low signal resets the backplanes. 153 I2S_MCLK0 I/O M clock 154 I2S_SCLK0 I/O S clock 163 I2S_LRCLK0 I/O LR clock 164 I2S_SDATAI0 I I2S data input 161 I2S_SDATAO0 O I2S data output 158 I2S_MCLK1 I/O M clock 160 I2S_SCLK1 I/O S clock 162 I2S_LRCLK1 I/O LR clock 156 I2S_SDATAI1 I I2S data input 155 I2S_SDATAO1 O I2S data output JTAG_SEL I JTAG select. This pin must be connected to ground if the JTAG interface is not used. – No connect I2S Interface JTAG Interface 193 No Connects NO_CONNECT 1–5, 7–13, 16–20, 23, 24, 26–34, 36–38, 41, 43–49, 51, 54, 55, 61–70, 179– 181 Broadcom® March 12, 2016 • 43907-DS104-R Page 61 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Table 10: Signal Descriptions (Cont.) Bump Number Signal Name Type Description Power Supplies (Miscellaneous) 203 OTP_VDD3P3 PWR OTP 3.3V supply 138, 216, 217, 252, VDDC 254, 267, 268, 271, 275–277, 280, 281, 285, 286, 289, 309, 314, 316 PWR 1.2V core supply for WLAN 105, 174, 195, 257, VDDIO 258, 261, 263, 269 PWR I/O supply 199, 208 VDDIO_RF PWR I/O supply for RF switch control pads (3.3V). 157, 159 VDDIO_I2S PWR I/O supply for I2S 305, 307 VDDIO_RMII PWR I/O supply for RMII 255 VDDIO_SD PWR I/O supply for SDIO 270 HIB_VDDO PWR I/O supply for hibernation block 204 AVDD1P2 PWR 1.2V supply for baseband PLL 192 AVDD1P2_AUDIO PWR 1.2V supply for audio PLL 166 USB2_AVDD33 PWR 3.3V supply for USB 2.0 173 USB2_AVDD33LDO PWR 3.3V supply for USB 2.0 176 USB2_AVDD33IO PWR 3.3V supply for USB 2.0 Power Supplies (WLAN) 223 WRF_SYNTH_VDD3P3 PWR Synthesizer VDD 3.3V supply 240, 241 WRF_PA_VDD3P3 227, 228 WRF_PMU_VDD1P35 PWR PMU 1.35V supply 244 WRF_TXMIX_VDD PWR 2.4 GHz and 5 GHz PA 3.3V VBAT supply PWR 3.3V supply for TX mixer 229 WRF_SYNTH_VDD1P2 PWR 1.2V supply for synthesizer 231 WRF_AFE_VDD1P35 PWR 1.35V supply for the analog front end (AFE) 185 PWM0 O Pulse width modulation bit 0. 186 PWM1 O Pulse width modulation bit 1 190 PWM2 O Pulse width modulation bit 2 189 PWM3 O Pulse width modulation bit 3 187 PWM4 O Pulse width modulation bit 4 188 PWM5 O Pulse width modulation bit 5 PWM Interface Broadcom® March 12, 2016 • 43907-DS104-R Page 62 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Table 10: Signal Descriptions (Cont.) Bump Number Signal Name Type Description RF Signal Interface (WLAN) 246 WRF_RFIN_2G I 2.4 GHz WLAN receiver input 233 WRF_RFIN_5G I 5 GHz WLAN receiver input 245 WRF_PAOUT_2G O 2.4 GHz WLAN PA output 239 WRF_PAOUT_5G O 5 GHz WLAN PA output 235 WRF_EXT_TSSIA I 5 GHz TSSI input from an optional external power amplifier/power detector 237 WRF_GPAIO_OUT I/O Analog GPIO Programmable RF switch control lines. The control lines are programmable via the driver and nvram.txt file. RF Switch Control Lines 215 RF_SW_CTRL_0 O 214 RF_SW_CTRL_1 O 211 RF_SW_CTRL_2 O 205 RF_SW_CTRL_3 O 206 RF_SW_CTRL_4 O 207 RF_SW_CTRL_5 I/O 202 RF_SW_CTRL_6 I/O 201 RF_SW_CTRL_7 I/O 200 RF_SW_CTRL_8 I/O 196 RF_SW_CTRL_9 I/O 152 SDIO_CLK I/O SDIO cock 151 SDIO_CMD I/O SDIO command line 150 SDIO_DATA_0 I/O SDIO data line 0 149 SDIO_DATA_1 I/O SDIO data line 1 148 SDIO_DATA_2 I/O SDIO data line 2 147 SDIO_DATA_3 I/O SDIO data line 3 SDIO Interface S/PDIF Interface Note: Supported via 161 (I2S_SDATAO0) and 155 (I2S_SDATAO1). SPI Flash Interface 77 SFL_CLK O Flash clock 73 SFL_IO0 I/O Flash data 71 SFL_IO1 I/O Flash data 75 SFL_IO2 I/O Flash data 72 SFL_IO3 I/O Flash data 74 SFL_CS O Flash slave select Broadcom® March 12, 2016 • 43907-DS104-R Page 63 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Signal Descriptions Table 10: Signal Descriptions (Cont.) Bump Number Signal Name Type Description SPI Interfaces Note: Each SPI interface can alternatively be configured and used as a BSC interface. 76 SPI0_CLK O SPI clock 78 SPI0_MISO I SPI data master in 81 SPI0_SISO O SPI data master out 82 SPI0_CS O SPI slave select 83 SPI1_CLK O SPI clock 84 SPI1_MISO I SPI data master in 86 SPI1_SISO O SPI data master out 80 SPI1_CS O SPI slave select UART0_CTS I UART clear-to-send UART Interface 85 91 UART0_RTS O UART request-to-send 88 UART0_RXD I UART serial input 87 UART0_TXD O UART serial output 170 USB2_DM I/O USB 2.0 data 167 USB2_DP I/O USB 2.0 data 169 USB2_RREF I USB 2.0 reference resistor connection 175 USB2_MONCDR O USB 2.0 CDR monitor 184 USB2_MONPLL O USB 2.0 PLL monitor 165 USB2_DSEL I USB 2.0 host and device mode selection 108, 113, 122, 125 SR_VDDBAT5V I VBAT. 98, 99, 101, 102, 109, 112 O CBUCK switching regulator output 115, 116, 120, 127 LDO_VDD1P5 I LNLDO input 128, 129 LDO_VDDBAT5V I LDO VBAT 221 WRF_XTAL_VDD1P35 I XTAL LDO input (1.35V) 220 WRF_XTAL_VDD1P2 O XTAL LDO output (1.2V) 106 VOUT_LNLDO O Output of LNLDO 114, 121, 126 VOUT_CLDO O Output of core LDO USB 2.0 Voltage Regulators (Integrated) SR_VLX 118, 119 VOUT_3P3 O LDO 3.3V output 117 VOUT_3P3_SENSE O Voltage sense pin for LDO 3.3V output 103 VOUT_CLDO_SENSE O Voltage sense pin for core LDO 107 VOUT_BBPLLOUT Output of baseband PLL O Broadcom® March 12, 2016 • 43907-DS104-R Page 64 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet GPIO Signals and Strapping Options S e c t i o n 1 0 : G PI O S i g n a l s a n d S t r a p p i n g O p t i o ns Overview This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in Table 12 on page 67. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground, using a 10 kΩ resistor or less. Note: Refer to the reference board schematics for more information. Weak Pull-Down and Pull-Up Resistances At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of VDDO) are 37.99 kΩ, 44.57 kΩ, and 51.56 kΩ, respectively. At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-up resistances (for a pin voltage of 0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively. Broadcom® March 12, 2016 • 43907-DS104-R Page 65 BROADCOM CONFIDENTIAL Strapping Options BCM43907 Preliminary Data Sheet Strapping Options Table 11 provides the strapping options. Table 11: Strapping Options Pin Name Strap Bump # Default Internal Pull During Strap GPIO_1 GSPI_MODE 142 PD GPIO_7 WCPU_BOOT_MODE 95 PD Boot from SoC SROM or SoC SRAM GPIO_11 ACPU_BOOT_MODE 140 PD Boot from tightly coupled memory (TCM) ROM or TCM RAM GPIO_13 SDIO_MODE 131 PD Select either SDIO host mode or SDIO device mode GPIO_15 VTRIM_EN 145 PD Enable PMU voltage trimming RF_SW_CTRL_5 DAP_CLK_SEL 207 PD Select XTAL clock or the test clock (tck) for the debug access port (DAP) RF_SW_CTRL_7 RSRC_INIT_MODE 201 PD PMU resource initialization mode selection Description Enable gSPI interface Broadcom® March 12, 2016 • 43907-DS104-R Page 66 BROADCOM CONFIDENTIAL Alternate GPIO Signal Functions BCM43907 Preliminary Data Sheet Alternate GPIO Signal Functions Table 12 provides the alternate signal functions of the GPIO signals. Table 12: Alternate GPIO Signal Functions GPIO Default JTAG_SEL Default Pull HOLD/PDLOW/PDHIGH Strap Comments GPIO_0 USB20H_CTL – No pull HOLD – 8 mA GPIO_1 – – Down HOLD GSPI_MODE 8 mA GPIO_2 GCI_GPIO(0) JTAG_TCK No pull HOLD – 8 mA GPIO_3 GCI_GPIO(1) JTAG_TMS No pull HOLD – 8 mA GPIO_4 GCI_GPIO(2) JTAG_TDI No pull HOLD – 8 mA GPIO_5 GCI_GPIO(3) JTAG_TDO No pull HOLD – 8 mA GPIO_6 GCI_GPIO(4) JTAG_TRST No pull HOLD – 8 mA GPIO_7 – – Down HOLD WCPU_BOOT_MODE 8 mA GPIO_8 GPIO_8 – No pull HOLD – 8 mA GPIO_9 GPIO_9 – Down HOLD – 8 mA GPIO_10 GPIO_10 – No pull HOLD – 8 mA GPIO_11 – – Down HOLD ACPU_BOOT_MODE 8 mA GPIO_12 GPIO_12 – No pull HOLD – 8 mA GPIO_13 – – Down HOLD SDIO_MODE 8 mA GPIO_14 GPIO_14 – No pull HOLD – 8 mA GPIO_15 – – Down HOLD VTRIM_EN 8 mA GPIO_16 – – No pull HOLD – 8 mA Broadcom® March 12, 2016 • 43907-DS104-R Page 67 BROADCOM CONFIDENTIAL Pin Multiplexing BCM43907 Preliminary Data Sheet Se c t i o n 11 : P i n M u l t ip l e x i n g Table 13 shows the pin multiplexing functions. Table 13: Pin Multiplexing Function Pin 1 2 3 4 5 6 7 8 9 10 11 GPIO_0 GPIO_0 UART0_RXD I2C1_SDATA PWM0 SPI1_MISO PWM2 GPIO_12 GPIO_8 – PWM4 USB20H_CTL GPIO_1 GPIO_1 UART0_TXD I2C1_CLK PWM1 SPI1_CLK PWM3 GPIO_13 GPIO_9 – PWM5 – GPIO_2 GPIO_2 – – GCI_GPIO_0 – – – – TCK – – GPIO_3 GPIO_3 – – GCI_GPIO_1 – – – – TMS – – GPIO_4 GPIO_4 – – GCI_GPIO_2 – – – – TDI – – GPIO_5 GPIO_5 – – GCI_GPIO_3 – – – – TDO – – GPIO_6 GPIO_6 – – GCI_GPIO_4 – – – – TRST_L – – GPIO_7 GPIO_7 UART0_ RTS_OUT PWM1 PWM3 SPI1_CS I2C1_CLK GPIO_15 GPIO_11 PMU_TEST_ O – PWM5 GPIO_8 GPIO_8 SPI1_MISO PWM2 PWM4 UART0_RXD – GPIO_16 GPIO_12 TAP_SEL_P I2C1_SDATA PWM0 GPIO_9 GPIO_9 SPI1_CLK PWM3 PWM5 UART0_TXD – GPIO_0 GPIO_13 – I2C1_CLK PWM1 GPIO_10 GPIO_10 SPI1_MOSI PWM4 I2C1_SDATA UART0_ CTS_IN PWM0 GPIO_1 GPIO_14 PWM2 SDIO_SEP_ INT SDIO_SEP_ INT_0D GPIO_11 GPIO_11 SPI1_CS PWM5 I2C1_CLK UART0_ RTS_OUT PWM1 GPIO_7 GPIO_15 PWM3 – – GPIO_12 GPIO_12 I2C1_SDATA UART0_RXD SPI1_MISO PWM2 PWM4 GPIO_8 GPIO_16 PWM0 SDIO_SEP_ INT_0D SDIO_SEP_ INT GPIO_13 GPIO_13 I2C1_CLK UART0_TXD SPI1_CLK PWM3 PWM5 GPIO_9 GPIO_0 PWM1 – – GPIO_14 GPIO_14 PWM0 UART0_ CTS_IN SPI1_MOSI I2C1_SDATA – GPIO_10 – PWM4 – PWM2 GPIO_15 GPIO_15 PWM1 UART0_ RTS_OUT SPI1_CS I2C1_CLK – GPIO_11 GPIO_7 PWM5 – PWM3 GPIO_16 GPIO_16 UART0_ CTS_IN PWM0 PWM2 SPI1_MOSI I2C1_SDATA GPIO_14 GPIO_10 RF_ DISABLE_L – PWM4 SDIO_CLK SDIO_CLK – – – – – – – SDIO_AOS_ CLK – – SDIO_CMD SDIO_CMD – – – – – – – SDIO_AOS_ CMD – – Broadcom® March 12, 2016 • 43907-DS104-R Page 68 BROADCOM CONFIDENTIAL Pin Multiplexing BCM43907 Preliminary Data Sheet Table 13: Pin Multiplexing Function Pin 1 2 3 4 5 6 7 8 9 10 11 SDIO_ DATA_0 SDIO_D0 – – – – – – – SDIO_AOS_ D0 – – SDIO_ DATA_1 SDIO_D1 – – – – – – – SDIO_AOS_ D1 – – SDIO_ DATA_2 SDIO_D2 – – – – – – – SDIO_AOS_ D2 – – SDIO_ DATA_3 SDIO_D3 – – – – – – – SDIO_AOS_ D3 – – RF_SW_ CTRL_5 RF_SW_ CTRL_5 GCI_GPIO_5 – – – – – – – – – RF_SW_ CTRL_6 RF_SW_ CTRL_6 UART_ DBG_RX SECI_IN – – – – – – – – RF_SW_ CTRL_7 RF_SW_ CTRL_7 UART_ DBG_TX SECI_OUT – – – – – – – – RF_SW_ CTRL_8 RF_SW_ CTRL_8 SECI_IN UART_ DBG_RX – – – – – – – – RF_SW_ CTRL_9 RF_SW_ CTRL_9 SECI_OUT UART_ DBG_TX – – – – – – – – PWM0 PWM0 GPIO_2 GPIO_18 – – – – – – – – PWM1 PWM1 GPIO_3 GPIO_19 – – – – – – – – PWM2 PWM2 GPIO_4 GPIO_20 – – – – – – – – PWM3 PWM3 GPIO_5 GPIO_21 – – – – – – – – PWM4 PWM4 GPIO_6 GPIO_22 – – – – – – – – PWM5 PWM5 GPIO_8 GPIO_23 – – – – – – – – SPI0_MISO SPI0_MISO GPIO_17 GPIO_24 – – – – – – – – SPI0_CLK SPI0_CLK GPIO_18 GPIO_25 – – – – – – – – SPI0_MOSI SPI0_MOSI GPIO_19 GPIO_26 – – – – – – – – SPI0_CS SPI0_CS GPIO_20 GPIO_27 – – – – – – – – I2C0_SDATA I2C0_SDATA GPIO_21 GPIO_28 – – – – – – – – I2C0_CLK I2C0_CLK GPIO_22 GPIO_29 – – – – – – – – I2S_MCLK0 I2S_MCLK0 GPIO_23 GPIO_0 – – – – – – – – I2S_SCLK0 I2S_SCLK0 GPIO_24 GPIO_2 – – – – – – – – I2S_LRCLK0 I2S_LRCLK0 GPIO_25 GPIO_3 – – – – – – – – Broadcom® March 12, 2016 • 43907-DS104-R Page 69 BROADCOM CONFIDENTIAL Pin Multiplexing BCM43907 Preliminary Data Sheet Table 13: Pin Multiplexing Function Pin 1 2 3 4 5 6 7 8 9 10 11 I2S_S DATAI0 I2S_ SDATAI0 GPIO_26 GPIO_4 – – – – – – – – I2S_ SDATAO0 I2S_ SDATAO0 GPIO_27 GPIO_5 – – – – – – – – I2S_ SDATAO1 I2S_ SDATAO1 GPIO_28 GPIO_6 – – – – – – – – I2S_SDATAI1 I2S_SDATAI1 GPIO_29 GPIO_8 – – – – – – – – I2S_MCLK1 I2S_MCLK1 GPIO_30 GPIO_17 – – – – – – – – I2S_SCLK1 I2S_SCLK1 GPIO_31 GPIO_30 – – – – – – – – I2S_LRCLK1 I2S_LRCLK1 GPIO_0 GPIO_31 – – – – – – – – Broadcom® March 12, 2016 • 43907-DS104-R Page 70 BROADCOM CONFIDENTIAL I/O States BCM43907 Preliminary Data Sheet Section 12: I/O States Table 14 provides I/O state information for the signals listed. The following notations are used in Table 14: • I: Input signal • O: Output signal • I/O: Input/Output signal • PU = Pulled up • PD = Pulled down • NoPull = Neither pulled up nor pulled down Table 14: I/O States Ball Name I/O Keepera Active Mode Low Power State/Sleep Power-downb (All Power Present) (REG_ON Held Low) Out-of-Reset; Before Software Download (REG_ON High) Power Rail HIB_REG_ON_IN I N Input; PD (Pull-down can Input; PD (Pull-down can Input be disabled.) be disabled.) Input – REG_ON I N Input; PD (Pull-down can Input; PD (Pull-down can Input; PD (of 200 kΩ) be disabled.) be disabled.) Input; PD (of 200 kΩ) – CLK_REQ I/O Y Open drain or push-pull Open drain or push-pull High-Z, NoPull (programmable). Active (programmable). Active high. high. Open drain; active high VDDO GPIO_0 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_1 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_2 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO Broadcom® March 12, 2016 • 43907-DS104-R Page 71 BROADCOM CONFIDENTIAL I/O States BCM43907 Preliminary Data Sheet Table 14: I/O States Low Power State/Sleep Power-downb (All Power Present) (REG_ON Held Low) Out-of-Reset; Before Software Download (REG_ON High) Power Rail Ball Name I/O Keepera Active Mode GPIO_3 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_4 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_5 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_6 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_7 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_8 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_9 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_10 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_11 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD VDDIO GPIO_12 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_13 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO Broadcom® March 12, 2016 • 43907-DS104-R Page 72 BROADCOM CONFIDENTIAL I/O States BCM43907 Preliminary Data Sheet Table 14: I/O States Low Power State/Sleep Power-downb (All Power Present) (REG_ON Held Low) Out-of-Reset; Before Software Download (REG_ON High) Power Rail Ball Name I/O Keepera Active Mode GPIO_14 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_15 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO GPIO_16 I/O Y Input/Output; PU, PD, or Input/Output; PU, PD, or High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull VDDIO RF_SW_CTRL (0 to 9) I/O Y Output; NoPull Output; NoPull VDDIO_RF Output; NoPull High-Z a. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be driven to prevent leakage due to floating pad (WL_REG_ON, for example). b. In the power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied. Broadcom® March 12, 2016 • 43907-DS104-R Page 73 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Electrical Characteristics Section 13: Electrical Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 15 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 15: Absolute Maximum Ratings Parameter Symbol Value Unit DC supply for VBAT and PA driver supply a VBAT –0.5 to +5.5 V DC supply voltage for digital I/O VDDIO –0.5 to 3.9 V DC supply voltage for I S I/O VDDIO_I2S –0.5 to 3.9 V DC supply voltage for RF switch I/O VDDIO_RF –0.5 to 3.9 V 2 DC supply voltage for Ethernet I/O VDDIO_RMII –0.5 to 3.9 V DC supply voltage for SDIO I/O VDDIO_SD –0.5 to 3.9 V DC input supply voltage for CLDO, LNLDO, and BBPLL LDOb – –0.5 to 1.575 V 3.3V DC supply for USB USB2_AVDD33 –0.5 to 3.9 USB2_AVDD33LDO USB2_AVDD33IO V 3.3V DC supply voltage for RF analogc VDD3P3RF –0.5 to 3.6 V 1.35V DC supply voltage for RF analogd VDD1P35RF –0.5 to 1.5 V 1.2V DC supply voltage for RF analoge VDD1P2RF –0.5 to 1.26 V 1.2V DC supply voltage for analog circuitsf VDD1P2A –0.5 to 1.26 V DC supply voltage for the coreg VDDC –0.5 to 1.32 V DC supply voltage for OTP memory OTP_VDD3P3 –0.5 to 3.9 V Maximum undershoot voltage for I/O Vundershoot –0.5 V Maximum junction temperature Tj 125 °C a. For the SR_VDDBAT5V and LDO_VDDBAT5V supplies. b. For the LDO_VDD1P5 and WRF_XTAL_VDD1P35 supplies. c. For the WRF_SYNTH_VDD3P3, WRF_PA_VDD3P3, and WRF_TXMIX_VDD supplies. Broadcom® March 12, 2016 • 43907-DS104-R Page 74 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet d. e. f. g. Environmental Ratings For WRF_PMU_VDD1P35 and WRF_AFE_VDD1P35 supplies. For the WRF_SYNTH_VDD1P2 supply. For the AVDD1P2_AUDIO, AVDD1P2, and HSIC_AVDD12 supplies. For the VDD, HSIC_DVDD12, and HSIC2_DVDD2 supplies. Environmental Ratings The environmental ratings are shown in Table 16. Table 16: Environmental Ratings Characteristic Value Units Conditions/Comments Ambient temperature (TA) –30 to +85 °C Functional operation Storage temperature –40 to +125 °C – Relative humidity Less than 60 % Storage Less than 85 % Operation Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 17: ESD Specifications ESD Rating Unit Pin Type Symbol Condition ESD, Handling Reference: NQY00083, Section 3.4, Group D9, Table B ESD_HAND_HBM Human body model contact discharge per JEDEC EID/JESD22-A114 CDM ESD_HAND_CDM Charged device model contact discharge per 250 JEDEC EIA/JESD22-C101 Broadcom® March 12, 2016 • 43907-DS104-R 1.5 kΩ V V Page 75 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Recommended Operating Conditions and DC Characteristics Recommended Operating Conditions and DC Characteristics Caution! Functional operation is not guaranteed outside of the limits shown in Table 18. Operation outside these limits for extended periods can adversely affect long-term reliability of the device. Table 18: Recommended Operating Conditions and DC Characteristics Value Parameter Symbol Minimum Typical Maximum Unit DC supply voltage for VBAT VBAT 2.3a 3.6 4.8 V DC supply voltage for digital I/O VDDIO 1.71 – 3.63 V DC supply voltage for I S I/O VDDIO_I2S 1.71 – 3.63 V DC supply voltage for RF switch I/Os VDDIO_RFb 3.13 3.3 3.6 V 2 DC supply voltage for Ethernet I/O VDDIO_RMII 1.71 – 3.63 V DC supply voltage for SDIO I/O VDDIO_SD 1.71 – 3.63 V 1.3 1.35 1.5 V 3.3 3.63 V DC input supply voltage for CLDO, LNLDO, – and BBPLL LDO 3.3V DC supply for USB USB2_AVDD33 2.97 USB2_AVDD33LDO USB2_AVDD33IO 3.3V DC supply voltage for RF analog VDD3P3RFc 3 3.3 3.45 V 1.35V DC supply voltage for RF analog VDD1P35RFc 1.3 1.35 1.5 V 1.2V DC supply voltage for RF analog VDD1P2RFc 1.1 1.2 1.26 V 1.2V DC supply voltage for analog VDD1P2Ac 1.1 1.2 1.26 V DC supply voltage for core VDDC 1.14 1.2 1.26 V DC supply voltage for OTP memory OTP_VDD3P3b 2.97 3.3 3.63 V DC supply voltage for TCXO input buffer WRF_TCXO_VDDc 1.62 1.8 1.98 V Internal POR threshold Vth_POR 0.4 – 0.7 V Input high voltage VIH 1.27 – – V SDIO Interface I/O Pins For VDDIO_SD = 1.8V: Input low voltage VIL – – 0.58 V Output high voltage @ 2 mA VOH 1.40 – – V Output low voltage @ 2 mA VOL – – 0.45 V Input high voltage VIH 0.625 × VDDIO – – V Input low voltage VIL – – 0.25 × VDDIO V For VDDIO_SD = 3.3V: Broadcom® March 12, 2016 • 43907-DS104-R Page 76 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Recommended Operating Conditions and DC Characteristics Table 18: Recommended Operating Conditions and DC Characteristics (Cont.) Value Parameter Symbol Minimum Typical Maximum Unit Output high voltage @ 2 mA VOH 0.75 × VDDIO – – V Output low voltage @ 2 mA VOL – 0.125 × VDDIO V Input high voltage VIH 0.65 × VDDIO – – V Input low voltage VIL – 0.35 × VDDIO V – Other Digital I/O Pins For VDDIO = 1.8V: – Output high voltage @ 2 mA VOH VDDIO – 0.45 – – V Output low voltage @ 2 mA VOL – – 0.45 V Input high voltage VIH 2.00 – – V For VDDIO = 3.3V: Input low voltage VIL – – 0.80 V Output high voltage @ 2 mA VOH VDDIO – 0.4 – – V Output low voltage @ 2 mA VOL – – 0.40 V Output high voltage @ 2 mA VOH VDDIO – 0.4 – – V Output low voltage @ 2 mA VOL – – 0.40 V CIN – – 5 pF RF Switch Control Output Pinsd For VDDIO_RF = 3.3V: Input capacitance a. The BCM43907 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3V < VBAT < 4.8V. b. VDD3P3RF, which is an internally generated supply, can drive this node. There is sufficient current and the appropriate state is maintained during hibernation and sleep cycles. c. Internally generated supply. d. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. Broadcom® March 12, 2016 • 43907-DS104-R Page 77 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power Supply Segments Power Supply Segments The digital I/O's are placed in physical segments. The supply voltage for each segment can be independently selected. Table 19 shows the power supply segments and the I/O pins associated with each segment. Table 19: Power Supply Segments Power Supply Segment Pins VDDIO CLK_REQ, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, GPIO_15, GPIO_16, I2C0_CLK, I2C0_SDATA, I2C1_CLK, I2C1_SDATA, JTAG_SEL, PWM0, PWM1, PWM2, PWM3, PWM4, PWM5, SFL_CLK, SFL_CS, SFL_IO0, SFL_IO1, SFL_IO2, SFL_IO3, SPI0_CLK, SPI0_CS, SPI0_MISO, SPI0_SISO, SPI1_CLK, SPI1_CS, SPI1_MISO, SPI1_SISO, SRSTN, UART0_CTS, UART0_RTS, UART0_RXD, UART0_TXD, USB2_DSEL VDDIO_I2S I2S_LRCLK0, I2S_LRCLK1, I2S_MCLK0, I2S_MCLK1, I2S_SCLK0, I2S_SCLK1, I2S_SDATAI0, I2S_SDATAI1, I2S_SDATAO0, I2S_SDATAO1 VDDIO_RF RF_SW_CTRL_0, RF_SW_CTRL_1, RF_SW_CTRL_2, RF_SW_CTRL_3, RF_SW_CTRL_4, RF_SW_CTRL_5, RF_SW_CTRL_6, RF_SW_CTRL_7, RF_SW_CTRL_8, RF_SW_CTRL_9 VDDIO_RMII RMII_G_COL, RMII_G_CRS, RMII_G_RXC, RMII_G_RXD0, RMII_G_RXD1, RMII_G_RXD2, RMII_G_RXD3, RMII_G_RXDV, RMII_G_TXC, RMII_G_TXD0, RMII_G_TXD1, RMII_G_TXD2, RMII_G_TXD3, RMII_G_TXEN, RMII_MDC, RMII_MDIO Ethernet MAC Controller (MII/RMII) DC Characteristics Table 20: MII Recommended Operating Condition Parameter Symbol Minimum Maximum Units Supply voltage GMAC_VDDIO (MII/RMII) 3.14 3.47 V GPIO, UART, and JTAG Interfaces DC Characteristics Table 21: GPIO, UART, and JTAG Interfaces Parameter Symbol Minimum Maximum Logic input high voltage VIH 2.0 VDDIO + 0.5 V – Logic input low voltage VIL –0.5 0.8 V – Logic output high voltage VOH 2.4 – V – Logic output low voltage VOL – 0.4 V – Broadcom® March 12, 2016 • 43907-DS104-R Units Conditions Page 78 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN RF Specifications Section 14: WLAN RF Specifications Introduction The BCM43907 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radio. Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 16: “Environmental Ratings,” on page 75 and Table 18: “Recommended Operating Conditions and DC Characteristics,” on page 76. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Figure 16: Port Locations for WLAN Testing BCM43907 Chip Output Port 2.4 GHz WLAN TX (WRF_PAOUT_2G) 2.4 GHz WLAN RX (WRF_RFIN_2G) Chip Input Port Diplexer Chip Output Port 5 GHz WLAN TX (WRF_PAOUT_5G) RF Port TR Switch 5 GHz WLAN RX (WRF_RFIN_5G) Chip Input Port Broadcom® March 12, 2016 • 43907-DS104-R Page 79 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet 2.4 GHz Band General RF Specifications 2.4 GHz Band General RF Specifications Table 22: 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum Unit TX/RX switch time Including TX ramp down – – 5 µs RX/TX switch time Including TX ramp up – – 2 µs Power-up and power-down ramp time DSSS/CCK modulations – – <2 µs WLAN 2.4 GHz Receiver Performance Specifications Note: The specifications shown in Table 23 apply at the chip ports, unless otherwise defined. Table 23: WLAN 2.4 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range – 2400 – 2500 MHz – –98.9 – dBm – –96.0 – dBm RX sensitivity IEEE 802.11b 1 Mbps DSSS (8% PER for 1024 octet 2 Mbps DSSS PSDU) 5.5 Mbps DSSS – –93.9 – dBm 11 Mbps DSSS – –90.4 – dBm RX sensitivity IEEE 802.11g 6 Mbps OFDM (10% PER for 1024 octet 9 Mbps OFDM PSDU) 12 Mbps OFDM – –95.0 – dBm – –93.8 – dBm – –92.7 – dBm 18 Mbps OFDM – –90.3 – dBm 24 Mbps OFDM – –87.1 – dBm 36 Mbps OFDM – –83.6 – dBm 48 Mbps OFDM – –79.3 – dBm 54 Mbps OFDM – –78.0 – dBm Broadcom® March 12, 2016 • 43907-DS104-R Page 80 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 23: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11n 20 MHz channel spacing for all MCS rates (10% PER for 4096 octet MCS0 – PSDU) a Defined for default MCS1 – parameters: 800 ns GI and MCS2 – non-STBC. MCS3 – Input in-band IP3 Maximum receive level @ 2.4 GHz –94.6 – dBm –92.1 – dBm –89.8 – dBm –86.6 – dBm MCS4 – –83.0 – dBm MCS5 – –78.3 – dBm MCS6 – –76.6 – dBm MCS7 – –75.0 – dBm Maximum LNA gain – –8 – dBm Minimum LNA gain – +9 – dBm @ 1, 2 Mbps (8% PER, 1024 octets) –3.5 – – dBm @ 5.5, 11 Mbps (8% PER, 1024 octets) –9.5 – – dBm @ 6, 9, 12 Mbps (10% PER, 1024 octets) –9.5 – – dBm @ MCS0–2 rates (10% PER, 4095 octets) –9.5 – – dBm @ 18, 24, 36, 48, 54 Mbps (10% PER, 1024 octets) –14.5 – – dBm @ MCS3–7 rates (10% PER, 4095 octets) –14.5 – – dBm Adjacent channel rejectionDSSS (Difference between interfering and desired signal at 8% PER for 1024 octet PSDU with desired signal level as specified in Condition/Notes.) Desired and interfering signal 30 MHz apart Adjacent channel rejectionOFDM (Difference between interfering and desired signal (25 MHz apart) at 10% PER for 1024 octet PSDU with desired signal level as specified in Condition/Notes.) 1 Mbps DSSS –74 dBm 35 – – dB 2 Mbps DSSS –74 dBm 35 – – dB Desired and interfering signal 25 MHz apart 5.5 Mbps DSSS –70 dBm 35 – – dB 11 Mbps DSSS –70 dBm 35 – – dB 6 Mbps OFDM –79 dBm 16 – – dB 9 Mbps OFDM –78 dBm 15 – – dB 12 Mbps OFDM –76 dBm 13 – – dB 18 Mbps OFDM –74 dBm 11 – – dB 24 Mbps OFDM –71 dBm 8 – – dB 36 Mbps OFDM –67 dBm 4 – – dB 48 Mbps OFDM –63 dBm 0 – – dB 54 Mbps OFDM –62 dBm –1 – – dB Broadcom® March 12, 2016 • 43907-DS104-R Page 81 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 23: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection MCS0–7 (Difference between interfering and desired signal (25 MHz apart) at 10% PER for 4096 octet PSDU with desired signal level as specified in Condition/Notes.) MCS0 –79 dBm 16 – – dB MCS1 –76 dBm 13 – – dB MCS2 –74 dBm 11 – – dB MCS3 –71 dBm 8 – – dB MCS4 –67 dBm 4 – – dB MCS5 –63 dBm 0 – – dB MCS6 –62 dBm –1 – – dB MCS7 –61 dBm –2 – – dB Maximum receiver gain – – – 66 – dB Gain control step – – – 3 – dB c Range –95 dBm to –30 dBm –5 – 5 dB Range above –30 dBm –8 – 8 dB Return loss Zo = 50Ω, across the dynamic range 10 11.5 13 dB Receiver cascaded noise figure At maximum gain – 4 – dB RSSI accuracy b a. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop. b. The minimum and maximum values shown have a 95% confidence level. c. –95 dBm with calibration at time of manufacture, –92 dBm without calibration. Broadcom® March 12, 2016 • 43907-DS104-R Page 82 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in Table 24 apply at the chip ports. Table 24: WLAN 2.4 GHz Transmitter Performance Specifications Parameter Frequency range EVMa RF port TX power (highest power setting, 25°C, and VBAT = 3.6) OFDM EVMb (25°C, VBAT = 3.6V) Phase noise Condition/Notes Minimum Typical Maximum Unit – 2400 – 2500 MHz DSS/CCK –9 dB – 20.5 – dBm OFDM, BPSK –8 dB – 20 – dBm OFDM, QPSK –13 dB – 20 – dBm OFDM, 16-QAM –19 dB – 19 – dBm OFDM, 64-QAM (R = 3/4) –25 dB – 19 – dBm OFDM, 64-QAM (MCS7, HT20) –27 dB – 18.5 – dBm OFDM, BPSK 5 dBm –29 –31 – dB OFDM, 64-QAM 5 dBm –31 –33 – dB MCS7 5 dBm –33 –35 – dB 0.45 – Degrees 10 – – dB 37.4 MHz crystal, integrated from – 10 kHz to 10 MHz TX power control dynamic – range Closed-loop TX power variation at highest power level setting Across full temperature and voltage range. Applies to 10 dBm to 20 dBm output power range. – – ±1.5 dB Carrier suppression – 15 – – dBc Gain control step – – 0.25 – dB – 6 – dB Return loss at Chip port TX Zo = 50Ω a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power). The ratio (dB) in the Conditions/Notes column is the EVM. b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/ Notes column is the TX power specification in dBm. WLAN 5 GHz Receiver Performance Specifications Note: Unless otherwise noted, the values shown in Table 25 apply at the chip ports. Broadcom® March 12, 2016 • 43907-DS104-R Page 83 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 25: WLAN 5 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit – 4900 – 5845 MHz 6 Mbps OFDM RX sensitivity IEEE 802.11a (10% PER 9 Mbps OFDM for 1000 octet PSDU) 12 Mbps OFDM – –93.6 – dBm – –92.4 – dBm – –91.3 – dBm 18 Mbps OFDM – –88.9 – dBm 24 Mbps OFDM – –85.7 – dBm 36 Mbps OFDM – –82.3 – dBm 48 Mbps OFDM – –77.9 – dBm 54 Mbps OFDM – –76.6 – dBm Frequency range a a RX sensitivity IEEE 802.11n (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. a RX sensitivity IEEE 802.11n (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. 20 MHz channel spacing for all MCS rates MCS0 – –93.2 – dBm MCS1 – –90.7 – dBm MCS2 – –88.4 – dBm MCS3 – –85.2 – dBm MCS4 – –81.6 – dBm MCS5 – –76.9 – dBm MCS6 – –75.2 – dBm MCS7 – –73.6 – dBm 40 MHz channel spacing for all MCS rates MCS0 – –90.3 – dBm MCS1 – –87.5 – dBm MCS2 – –84.9 – dBm MCS3 – –81.8 – dBm MCS4 – –78.3 – dBm MCS5 – –73.9 – dBm MCS6 – –72.7 – dBm MCS7 – –71.2 – dBm Maximum LNA gain – –12 – dBm Minimum LNA gain – +4 – dBm Maximum receive level @ @ 6, 9, 12 Mbps 5 GHz (10% PER, 1024 octets) –9.5 – – dBm @ MCS0–2 rates (10% PER, 4095 octets) –9.5 – – dBm @ 18, 24, 36, 48, 54 Mbps (10% PER, 1024 octets) –14.5 – – dBm @ MCS3–7 rates (10% PER, 4095 octets) –14.5 – – dBm Input in-band IP3 Broadcom® March 12, 2016 • 43907-DS104-R Page 84 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 25: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Adjacent channel rejection (Difference between interfering and desired signal (20 MHz apart) at 10% PER for 1000 octet PSDU with desired signal level as specified in Condition/Notes) 6 Mbps OFDM –79 dBm 16 – – dB 9 Mbps OFDM –78 dBm 15 – – dB 12 Mbps OFDM –76 dBm 13 – – dB 18 Mbps OFDM –74 dBm 11 – – dB 24 Mbps OFDM –71 dBm 8 – – dB 36 Mbps OFDM –67 dBm 4 – – dB 48 Mbps OFDM –63 dBm 0 – – dB 54 Mbps OFDM –62 dBm –1 – – dB 65 Mbps OFDM –61 dBm –2 – – dB 6 Mbps OFDM –78.5 dBm 32 – – dB 9 Mbps OFDM –77.5 dBm 31 – – dB 12 Mbps OFDM –75.5 dBm 29 – – dB 18 Mbps OFDM –73.5 dBm 27 – – dB 24 Mbps OFDM –70.5 dBm 24 – – dB 36 Mbps OFDM –66.5 dBm 20 – – dB 48 Mbps OFDM –62.5 dBm 16 – – dB 54 Mbps OFDM –61.5 dBm 15 – – dB 65 Mbps OFDM –60.5 dBm Alternate adjacent channel rejection (Difference between interfering and desired signal (40 MHz apart) at 10% PER for 1000b octet PSDU with desired signal level as specified in Condition/Notes) Minimum Typical Maximum Unit 14 – – dB Maximum receiver gain – – 66 – dB Gain control step – – 3 – dB RSSI accuracyc Range –92 dBm to –30 dBm –5 – 5 dB Range above –30 dBm –8 – 8 dB Return loss Zo = 50Ω, across the dynamic range 10 – 13 dB – 5 – dB Receiver cascaded noise At maximum gain figure a. For PCIE derate the 5 GHz RX sensitivity by 1.5 dB b. For 65 Mbps, the size is 4096. c. The minimum and maximum values shown have a 95% confidence level. Broadcom® March 12, 2016 • 43907-DS104-R Page 85 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN 5 GHz Transmitter Performance Specifications WLAN 5 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in Table 26 apply at the chip ports. Table 26: WLAN 5 GHz Transmitter Performance Specifications Parameter Frequency range Condition/Notes Minimum Typical Maximum Unit – 4900 – 5845 MHz OFDM, QPSK –13 dB – 20 – dBm OFDM, 16-QAM –19 dB – 18.5 – dBm OFDM, 64-QAM (R = 3/4) –25 dB – 17 – dBm OFDM, 64-QAM (MCS7, HT20) –27 dB – 16.5 – dBm OFDM, BPSK 0 dBm – –30 – dB OFDM,64-QAM 0 dBm – –33 – dB MCS7 0 dBm – –34 – dB – 0.5 – Degrees TX power control dynamic – range 10 – – dB Across full-temperature and voltage Closed loop TX power variation at highest power range. Applies across 10 to 20 dBm output power range. level setting – – ±2.0 dB Carrier suppression 15 – – dBc EVMa RF port TX power (highest power setting, 25°C, and VBAT = 3.6) OFDM EVMb (25°C, VBAT = 3.6V) Phase noise 37.4 MHz Crystal, Integrated from 10 kHz to 10 MHz – Gain control step – – 0.25 – dB Return loss Zo = 50Ω – 6 – dB a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power). The ratio (dB) in the Conditions/Notes column is the EVM. b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/ Notes column is the TX power specification in dBm. General Spurious Emissions Specifications This section provides the TX and RX spurious emissions specifications for the WLAN 2.4 GHz and 5 GHz bands. The recommended spectrum analyzer settings for the spurious emissions specifications are provided in Table 27. Table 27: Recommended Spectrum Analyzer Settings Parameter Setting Resolution bandwidth (RBW) 1 MHz Broadcom® March 12, 2016 • 43907-DS104-R Page 86 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet General Spurious Emissions Specifications Table 27: Recommended Spectrum Analyzer Settings Parameter Setting Video bandwidth (VBW) 1 MHz Sweep Auto Span 100 MHz Detector Maximum peak Trace Maximum hold Modulation OFDM Transmitter Spurious Emissions Specifications 2.4 GHz Band Spurious Emissions 20-MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/18 specifications for channel 2442 are listed in Table 28. • • • • AFE=VCO/18 AFE=VCO/16 AFE=VCO/8 AFE=VCO/6 Broadcom® March 12, 2016 • 43907-DS104-R Page 87 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet General Spurious Emissions Specifications Table 28: 2.4 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications a Frequency (Fch; MHz) Channel 2442 Spurious Frequency Power (dBm) Typical (dBm) Maximum (dBm) HD2 –5 –58.7 –56.6 HD3 –5 –71.7 –68.9 HD4 –5 –57.2 –50.2 VCO –5 –45.7 –43.7 VCOx2 –5 –71.5 –69.0 VCOx3 –5 –85.2 –74.1 AFEx3 –5 – – AFEx4 –5 – – AFEx5 –5 – – AFEx6 –5 –78.4 –73.5 AFEx7 –5 –77.3 –76.1 AFEx8 –5 –73.6 –73.4 AFEx9 –5 –70.9 –69.9 AFEx10 –5 –81.1 –78.8 AFEx11 –5 –70.3 –69.1 AFEx13 –5 –72.0 –71.0 AFEx14 –5 –76.2 –73.8 AFEx15 –5 –79.3 –73.6 AFEx16 –5 –82.5 –77.9 AFEx17 –5 –85.3 –77.7 AFEx19 –5 –83.4 –77.6 AFEx20 –5 –83.9 –76.5 AFEx21 –5 –78.7 –74.9 AFEx22 –5 –82.1 –76.2 AFEx23 –5 –87.1 –77.6 a. VCO = 1.5 × Fch, where Fch is the center frequency of the channel. Broadcom® March 12, 2016 • 43907-DS104-R Page 88 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet General Spurious Emissions Specifications 5 GHz Band Spurious Emissions 20-MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/18 specifications for channels 5180, 5500, and 5825 are listed in Table 29. • • • • AFE=VCO/18 AFE=VCO/16 AFE=VCO/8 AFE=VCO/6 Table 29: 5 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications Frequency (Fch; MHz) 5180 a 5500 a 5825 a Spurious Frequency Power (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) HD2 –5 –57.1 –56.3 –58.0 –56.9 –59.6 –58.3 HD3 –5 –71.8 –71.0 –70.8 –70.1 –69.6 –69.1 VCO –5 –62.6 –54.2 –54.3 –54.0 –50.7 –50.3 VCOx2 –5 –74.7 –72.4 –76.2 –69.9 –71.2 –67.0 VCOx3 –5 –57.1 –56.3 –58.0 –56.9 –59.6 –58.3 AFEx2 –5 –81.6 –80.5 –81.5 –80.6 –81.0 –80.0 AFEx4 –5 –81.2 –80.1 –81.3 –80.4 –80.8 –80.0 AFEx6 –5 –80.9 –80.0 –80.7 –80.0 –80.5 –80.0 AFEx12 –5 – – – – – – AFEx15 –5 – – – – – – Fch + AFE –5 –75.6 –74.7 –76.4 –75.5 –76.1 –75.0 Fch + AFEx2 –5 –77.1 –76.2 –77.1 –76.2 –76.5 –75.6 Fch + AFEx3 –5 –76.8 –74.5 –77.1 –74.9 –76.4 –75.9 Fch – AFE –5 –76.6 –75.6 –76.4 –75.5 –75.5 –75.5 Fch – AFEx2 –5 –77.3 –76.1 –76.8 –75.5 –76.8 –76.3 Fch – AFEx3 –5 –77.9 –76.5 –77.2 –76.5 –76.0 –75.9 a. VCO = (2/3) × Fch, where Fch is the center frequency of the channel. Broadcom® March 12, 2016 • 43907-DS104-R Page 89 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet General Spurious Emissions Specifications 40-MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/9 specifications for channels 5190, 5510, and 5795 are listed in Table 30. • • • • AFE=VCO/18 AFE=VCO/16 AFE=VCO/8 AFE=VCO/6 Table 30: 5 GHz Band, 40-MHz Channel Spacing TX Spurious Emissions Specifications Frequency (Fch; MHz) 5190 a 5510 b 5795 b Spurious Frequency Power (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) HD2 –5 –56.9 –56.4 –58.5 –57.3 –58.7 –57.3 HD3 –5 –72.2 –71.7 –72.3 –71.7 –71.7 –71.2 VCO –5 –50.6 –50.0 –53.7 –53.4 –51.4 –50.7 VCOx2 –5 –71.1 –69.8 –76.9 –70.0 –74.5 –67.9 VCOx3 –5 –75.9 –75.1 –58.5 –57.3 –58.7 –57.3 AFEx2 –5 –81.0 –79.8 –81.2 –79.8 –81.4 –80.2 AFEx4 –5 –79.0 –77.7 –80.0 –78.9 –78.3 –77.5 AFEx6 –5 –76.8 –75.3 –78.5 –76.2 –80.8 –75.2 AFEx12 –5 – – –74.5 –73.6 –79.0 –77.8 AFEx15 –5 –76.1 –72.9 –73.9 –71.1 –70.6 –70.5 Fch + AFE –5 –78.7 –76.1 –78.6 –77.7 –77.5 –75.9 Fch + AFEx2 –5 –78.5 –76.2 –78.0 –77.2 –76.3 –73.4 Fch + AFEx3 –5 – – –78.6 –78.0 –78.2 –77.6 Fch – AFE –5 –79.0 –77.3 –78.6 –77.3 –79.1 –78.3 Fch – AFEx2 –5 –79.0 –78.0 –79.2 –78.6 –79.2 –78.6 Fch – AFEx3 –5 – – –79.7 –79.0 –79.6 –79.0 a. VCO = (3/4) x Fch, where Fch is the center frequency of the channel. b. VCO = (2/3) × Fch, where Fch is the center frequency of the channel. Receiver Spurious Emissions Specifications Table 31: 2G and 5G General Receiver Spurious Emissions Band Frequency Range Typical Maximum Unit 2G 2.4 GHz < f < 2.5 GHz –75.5 –74.1 dBm 3.6 GHz < f < 3.8 GHz –52.8 –50.9 dBm 5150 MHz < f < 5850 MHz –57.7 –56.1 dBm 3.45 GHz < f < 3.9 GHz –48.6 –47.6 dBm 5G Broadcom® March 12, 2016 • 43907-DS104-R Page 90 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Internal Regulator Electrical Specifications Section 15: Internal Regulator Electrical Specifications Core Buck Switching Regulator Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Note: Functional operation is not guaranteed outside of the specification limits provided in this section. Table 32: Core Buck Switching Regulator (CBUCK) Specifications Specification Notes Min. Typ. Max. Unit Input supply voltage (DC) DC voltage range inclusive of disturbances. 3.0 3.6 4.8a V PWM mode switching frequency CCM, load > 100 mA VBAT = 3.6V. – 4 – MHz PWM output current – – – 550 mA Output current limit – – 1400 – mA Output voltage range Programmable, 30 mV steps. Default = 1.35V. 1.2 1.35 1.5 V PWM output voltage DC accuracy Includes load and line regulation. Forced PWM –4 mode. – 4 % PWM ripple voltage, static Measure with 20 MHz bandwidth limit. – Static load. Max. ripple based on VBAT = 3.6V, Vout = 1.35V, Fsw = 4 MHz, 2.2 μH inductor with min. effective L > 1.05 μH, cap. + board total – ESR < 20 mΩ, Cout > 1.9 μF, ESL<200 pH 7 20 mVpp PWM mode peak efficiency Peak efficiency at 200 mA load. 78 86 – % PFM mode efficiency 10 mA load current. 70 81 – % Start-up time from power down VIO already ON and steady. Time from – REG_ON rising edge to CLDO reaching 1.2V. 400 500 µs External inductor 0806 size, 2.2 µH, DCR = 0.11Ω, ACR = 1.18Ω @ 4 MHz. 2.2 – µH External output capacitor Ceramic, X5R, 0402, ESR <30 mΩ at 4 MHz, 2.0b 4.7 µF ±20%, 6.3V. 4.7 10c µF External input capacitor For SR_VDDBAT5V pin, ceramic, X5R, 0603, 0.67b 4.7 ESR < 30 mΩ at 4 MHz, ±4.7 µF ±20%, 6.3V. – µF – µs Input supply voltage ramp-up time 0 to 4.3V. – 40 – a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® March 12, 2016 • 43907-DS104-R Page 91 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet 3.3V LDO (LDO3P3) c. Total capacitance includes those connected at the far end of the active load. 3.3V LDO (LDO3P3) Table 33: LDO3P3 Specifications Specification Notes Min. Input supply voltage, Vin Min. = Vo + 0.2V = 3.5V dropout voltage 3.0 requirement must be met under maximum load for performance specifications. Typ. Max. Units 3.6 4.8a V Output current – 0.001 – 450 mA Nominal output voltage, Vo Default = 3.3V. – 3.3 – V Dropout voltage At max. load. – – 200 mV Output voltage DC accuracy Includes line/load regulation. –5 – +5 % Quiescent current No load. – – 85 µA Line regulation Vin from (Vo + 0.2V) to 4.8V, max. load. – – 3.5 mV/V Load regulation Load from 1 mA to 450 mA. – – 0.3 mV/mA PSRR Vin ≥ Vo + 0.2V, Vo = 3.3V, Co = 4.7 µF, Max load, 100 Hz to 100 kHz. 20 – – dB LDO turn-on time Chip already powered up. – 160 250 µs External output capacitor, Co Ceramic, X5R, 0402, (ESR: 5 mΩ–240 mΩ), ± 10%, 10V. 1.0b 4.7 10 µF External input capacitor For LDO_VDDBAT5V pin (shared with – band gap) ceramic, X5R, 0402, (ESR: 30mΩ–200 mΩ), ± 10%, 10V. Not needed if sharing 4.7 µF VBAT capacitor with SR_VDDBAT5V. 4.7 – µF a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® March 12, 2016 • 43907-DS104-R Page 92 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet CLDO CLDO Table 34: CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output current – 0.2 – 350 mA Output voltage, Vo Programmable in 10 mV steps. Default = 1.2.V. 0.95 1.2 1.26 V Dropout voltage At max. load. – – 150 mV Output voltage DC accuracy Includes line/load regulation. –4 – +4 % Quiescent current No load. – 26 – µA 200 mA load. – 2.48 – mA Line regulation Vin from (Vo + 0.15V) to 1.5V, maximum load. – – 5 mV/V Load regulation Load from 1 mA to 300 mA. – 0.02 0.05 mV/mA Leakage current Power down. – 10 40 µA 6 µA Bypass mode. – 2 PSRR @1 kHz, Vin ≥ 1.35V, Co = 4.7 µF. 20 – Start-up time of PMU VIO up and steady. Time from the REG_ON – rising edge to the CLDO reaching 1.2V. – 700 µs LDO turn-on time LDO turn-on time when the rest of the chip is up. – 140 180 µs External output capacitor, Co Total ESR: 5 mΩ–240 mΩ. 3.76a 4.7 – µF External input capacitor Only use an external input capacitor at the – LDO_VDD1P5 pin if it is not supplied from the CBUCK output. 2.2 µF 1 dB a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® March 12, 2016 • 43907-DS104-R Page 93 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet LNLDO LNLDO Table 35: LNLDO Specifications Specification Notes Input supply voltage, Vin Min. Typ. Max. Units Min. VIN = VO + 0.15V = 1.35V (where VO = 1.3 1.2V)dropout voltage requirement must be met under maximum load. 1.35 1.5 V Output current – 0.1 – 150 mA Output voltage, Vo Programmable in 25 mV steps. Default = 1.2V. 1.1 1.2 1.275 V Dropout voltage At maximum load. – – 150 mV Output voltage DC accuracy Includes line/load regulation. –4 – +4 % Quiescent current No load. – 44 – µA Max. load. – 970 990 µA Line regulation Vin from (Vo + 0.1V) to 1.5V, 150 mA load. – – 5 mV/V Load regulation Load from 1 mA to 150 mA. – 0.02 0.05 mV/mA Leakage current Power-down. – – 10 µA Output noise @30 kHz, 60–150 mA load Co = 2.2 µF. @100 kHz, 60–150 mA load Co = 2.2 µF. – – 60 35 nV/rt Hz nV/rt Hz PSRR @ 1kHz, Input > 1.35V, Co= 2.2 µF, Vo = 1.2V. 20 – – dB LDO turn-on time LDO turn-on time when the rest of the chip – is up. 140 180 µs 2.2 4.7 µF 1 2.2 µF External output capacitor, Co Total ESR (trace/capacitor): 5 mΩ–240 mΩ. External input capacitor 0.5a Only use an external input capacitor at the – LDO_VDD1P5 pin if it is not supplied from the CBUCK output. Total ESR (trace/capacitor): 30 mΩ– 200 mΩ. a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® March 12, 2016 • 43907-DS104-R Page 94 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet BBPLL LDO BBPLL LDO Table 36: BBPLL LDO Specifications Parameter Conditions and Comments Min. Input supply voltage, Vin Min. Vin= Vo + 0.15V = 1.35V (for Vo = 1.2V). 1.3 Typ. Max. Units 1.35 1.5 V 1.2 1.275 V The dropout voltage requirement must be met under maximum load. Output voltage, Vo Programmable in 25 mV steps. Default = 1.2V. 1.1 Dropout voltage At max. load – – 150 mV Output voltage DC accuracy Includes line/load regulation. –4 – +4 % Output current Peak load = 80 mA, average = 35 mA 0.1 – 55 mA Quiescent current No load – 10 12 µA 55 mA load – 550 570 µA Line regulation Vin from (Vo + 0.15V) to 1.5V; 200 mA load – – 5 mV/V Load regulation load from 1mA to 200 mA; Vin ≥ (Vo + 0.15V) – 0.025 0.045 mV/mA Leakage current Powered down. Junction temperature is 85°C. – 5 20 µA Bypass mode – 0.2 1.5 µA PSRR @1 kHz, Vin ≥ Vo + 0.15V, Co = 4.7 µF 20 – – dB Start-up time of PMU VIO up and steady. Time from REG_ON rising – edge to CLDO reaching 99% of Vo. 530 700 us LDO turn-on time The LDO turn-on time when the rest of the chip – is up. 140 180 us Inrush current Vin=Vo+0.15V to 1.5V, Co=0.47uF, no load – 60 70 mA External output capacitor, Co Ceramic, X5R, size 0201, max. 6.3V, 20% tolerance 0.27 0.47 – µF External input capacitor Only use an external input capacitor at the – LDO_VDD1P5 pin if it is not supplied from the CBUCK output. 1 – µF Broadcom® March 12, 2016 • 43907-DS104-R Page 95 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet System Power Consumption Section 16: System Power Consumption Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Note: Unless otherwise stated, these values apply for the conditions specified in Table 18: “Recommended Operating Conditions and DC Characteristics,” on page 76. WLAN Current Consumption The tables in this subsection show the typical, total current used by the BCM43907. Current values may be measured with the APPS core powered off. The first column of the table, the mode description, will state the power condition of the APPS core. 2.4 GHz Mode Table 37: 2.4 GHz Mode WLAN Current Consumption VDDIO = VBAT = 3.6V a VDDIO_HIB = 3.3V a, b, c (µA) (µA) Mode Sleep Modes Radio off d 3 3 Sleep e, f 6 160 IEEE Power Save, DTIM=1, single RX, APPS powered down g 2180 160 IEEE Power Save, DTIM=3, single RX, APPS powered down h 680 160 IEEE Power Save, DTIM=9, single RX, APPS powered down 233 160 Continuous RX mode MCS7, HT20, 1SS, APPS powered up i, j 57,200 60 CRS-HT20, APPS powered up k 55,200 60 Continuous TX mode 1 Mbps, APPS powered up l 336,000 60 Continuous TX mode MCS7, HT20, 1SS, 1 TX, APPS powered up l 337,900 60 Active Modes Ping Modes Ping to associated access point l 336,000 60 Sleep 6 160 a. Typical silicon. b. VIO is specified with all pins idle (not switching) and not driving any loads. c. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD. Broadcom® March 12, 2016 • 43907-DS104-R Page 96 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN Current Consumption d. REG_ON is low or the device is in hibernation, and all supplies are present. e. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up. f. Inter-beacon current. g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals. h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals. i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. j. Measured using packet engine test mode. k. Carrier sense (CCA) when no carrier present. l. Duty cycle is 100%. 5 GHz Mode Table 38: 5 GHz Mode WLAN Current Consumption VDDIO = VDDIO_HIB VBAT = 3.6V a = 3.3V a, b, c (µA) (µA) Mode Sleep Modes Radio off d 3 3 Sleep e, f 6 160 IEEE Power Save, DTIM=1, single RX, APPS powered down g 1390 160 IEEE Power Save, DTIM=3, single RX, APPS powered down h 470 160 IEEE Power Save, DTIM=9, single RX, APPS powered down 160 160 Continuous RX mode MCS7, HT20, 1SS, APPS powered up i, j 72,400 60 Continuous RX mode MCS7, HT40, 1SS, APPS powered up i, j 84,700 60 CRS-HT20, APPS powered up k 70,200 60 CRS-HT40, APPS powered up k 79,500 60 Continuous TX mode MCS7, HT20, 1SS, 1 TX, APPS powered up l 326,000 60 Continuous TX mode MCS7, HT40, 1SS, 1 TX, APPS powered up l 311,000 60 Ping to associated access point l 327,000 60 Sleep 6 160 Active Modes Ping Modes a. b. c. d. e. Typical silicon. VIO is specified with all pins idle (not switching) and not driving any loads. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD. REG_ON is low or the device is in hibernation, and all supplies are present. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up. f. Inter-beacon current. g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals. h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals. i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. j. Measured using packet engine test mode. Broadcom® March 12, 2016 • 43907-DS104-R Page 97 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet WLAN Current Consumption k. Carrier sense (CCA) when no carrier present. l. Duty cycle is 100%. Broadcom® March 12, 2016 • 43907-DS104-R Page 98 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Interface Timing and AC Characteristics S e c t i o n 1 7 : I n t e r f a c e Ti m i n g a n d A C C h a r a c t e ri s t i c s Ethernet MAC (MII/RMII) Interface Timing MII Receive Packet Timing Figure 17 and Table 39 provide the MII receive packet timing. Figure 17: MII Receive Packet Timing t404 t402 t401 t403 RXC RXDV RXD[3:0] Table 39: MII Receive Packet Timing Parameters Parameter Description t401 RXDV and RXD[3:0] to RXC rising setup time 10 t402 RXC clock period (10BASE-T mode) – 400 – ns RXC clock period (100BASE-TX mode) – 40 – ns RXC low/high time (10BASE-T mode) 160 – 240 ns RXC low/high time (100BASE-TX mode) 16 – 24 ns t403 Minimum Typical Maximum Units – – ns t404 RXDV and RXD[3:0] to RXC rising hold time 10 – – ns – Duty cycle 50 60 % 40 Broadcom® March 12, 2016 • 43907-DS104-R Page 99 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Ethernet MAC (MII/RMII) Interface Timing MII Transmit Packet Timing Figure 18 and Table 40 provide the MII transmit packet timing. Figure 18: MII Transmit Packet Timing TXC TXEN TXD[3:0] Table 40: MII Transmit Packet Timing Parameters Parameter Description Minimum Typical Maximum Units t405 TXC high to TXEN and TXD[3:0] valid 0 – 25 ns t406 TXC high to TXEN and TXD[3:0] invalid (hold) 0 – – ns Broadcom® March 12, 2016 • 43907-DS104-R Page 100 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Ethernet MAC (MII/RMII) Interface Timing RMII Receive Packet Timing Figure 19 and Table 41 provide the RMII receive packet timing. Figure 19: RMII Receive Packet Timing REF_CLK CRS_DV RXD[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X 0 RXD[0] 0 0 0 0 0 0 0 1 1 1 1 1 1 1 X X X X X X 0 /J/ /K/ Preamble SFD Data Table 41: RMII Receive Packet Timing Parameter Symbol Minimum Typical Maximum Unit REF_CLK Cycle Time – – 20 – ns RXD[1:0], RXER, CRS_DV Output delay from REF_CLK rising – 2 – 10 ns Notes: 1. In 10 Mbps mode, there are ten REF_CLK periods per data period. 2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering. Broadcom® March 12, 2016 • 43907-DS104-R Page 101 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Ethernet MAC (MII/RMII) Interface Timing RMII Transmit Packet Timing Figure 20 and Table 42 provide the RMII transmit packet timing. Figure 20: RMII Transmit Packet Timing REF_CLK TX_EN TXD[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X 0 TXD[0] 0 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X 0 Preamble SFD Data Table 42: RMII Transmit Packet Timing Parameters Parameter Symbol Minimum Typical Maximum Unit REF_CLK Cycle Time – – 20 – ns TXEN, TXER, TXD[1:0] setup time to REF_CLK rising TXEN_SETUP 4 – – ns TXEN, TXER, TXD[1:0] hold time from REF_CLK rising TXEN_HOLD 2 – – ns Notes: 1. TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted. 2. In 10 Mbps mode, there are ten REF_CLK periods per data period. Broadcom® March 12, 2016 • 43907-DS104-R Page 102 BROADCOM CONFIDENTIAL I2S Master and Slave Mode TX Timing BCM43907 Preliminary Data Sheet I2S Master and Slave Mode TX Timing Figure 21 and Table 43 on page 103 provide the I2S Master mode transmitter timing. Figure 21: I2S Master Mode Transmitter Timing T t HC = 0.35T t RC I2S_SCLK V t LC = 0.35T t htr = 0 V H = 2.0V L = 0.8V t dtr = 0.8T I2S_SDATO and I2S_LRCK T = Clock period. Ttr = Minimum allowed clock period for transmitter. T > Ttr. tRC is only relevant for transmitters in Slave mode. Figure 22 and Table 43 on page 103 provide the I2S Slave mode receiver timing. Figure 22: I2S Slave Mode Receiver Timing T tHC = 0.35T V tLC = 0.35T I2S_SCLK V tsr = 0.2T H = 2.0V L = 0.8V thr = 0 I2S_SDATAI and I2S_LRCK T = Clock period. Tr = Minimum allowed clock period for the transmitter. T > Tr. Table 43: Timing for I2S Transmitters and Receivers Transmitter Lower Limit Parameter Clock period T Minimum Ttr Upper Limit Maximum – Receiver Minimum – Maximum – Lower Limit Minimum Ttr Maximum – Slave mode: Broadcom® March 12, 2016 • 43907-DS104-R Page 103 BROADCOM CONFIDENTIAL I2S Master and Slave Mode TX Timing BCM43907 Preliminary Data Sheet Table 43: Timing for I2S Transmitters and Receivers Transmitter Receiver Lower Limit Parameter Minimum Upper Limit Maximum Minimum Lower Limit Maximum Minimum Maximum Clock HIGH, tHC – 0.35Tr – – – 0.35Tr Clock LOW, tLC – 0.35Tr – – – 0.35Tr Clock rise time, tRC – – 0.15Ttr – – – Transmitter delay, tdtr – – – 0.8T – – Transmitter hold time, thtr 0 – – – – – Receiver setup time, tsr – – – – – 0.2Tr Receiver hold time, thr – – – – – 0 Table 44 provides the I2S_MCLK specification. Table 44: I2S_MCLK Specification Parameter Minimum Typical Maximum Unit Frequency range 1 – 40 MHz Frequency accuracy (with respect to the XTAL frequency) – 1 – ppb Tuning resolution – 50 – ppb Tuning range – 1000 – ppm Tuning step size – – 10 ppm Tuning rate – 1 – ppm/ms Baseband jitter (100 Hz to 40 kHz) – – 100 ps rms Wideband jitter (100 Hz to 1 MHz) – – 200 ps rms Figure 23 shows the I2S frame-level timing. Figure 23: I2S Frame-Level Timing 1/fs I2S_LRCLK Left Channel Right Channel I2S_SCLK 1 clock 1 I/O Data 2 1 clock 3 MSB n–2 n–1 n 1 LSB 2 MSB Broadcom® March 12, 2016 • 43907-DS104-R 3 n–2 n–1 n LSB Page 104 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO Interface Timing SDIO Interface Timing SDIO Default-Speed Mode Timing SDIO default-speed (DS) mode timing is shown by the combination of Figure 24 and Table 45. Figure 24: SDIO Bus Timing (Default-Speed Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output tODLY tODLY (max) (min) Table 45: SDIO Bus Timinga Parameters (Default-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb Frequency – Data Transfer mode fPP 0 – 25 MHz Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock low time tTHL – – 10 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 5 – – ns Input hold time tIH 5 – – ns Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines. b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO. Broadcom® March 12, 2016 • 43907-DS104-R Page 105 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO Interface Timing SDIO High-Speed Mode Timing SDIO high-speed (HS) mode timing is shown by the combination of Figure 25 and Table 46. Figure 25: SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tTLH tIH tISU Input Output tODLY tOH Table 46: SDIO Bus Timinga Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb Frequency – Data Transfer Mode fPP 0 – 50 MHz Frequency – Identification Mode fOD 0 – 400 kHz Clock low time tWL 7 – – ns Clock high time tWH 7 – – ns Clock rise time tTLH – – 3 ns Clock low time tTHL – – 3 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 6 – – ns Input hold time tIH 2 – – ns tODLY – – 14 ns Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer Mode Output hold time tOH 2.5 – – ns Total system capacitance (each line) CL – – 40 pF a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines. b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO. Broadcom® March 12, 2016 • 43907-DS104-R Page 106 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO Interface Timing SDIO Bus Timing Specifications in SDR Modes Clock Timing SDIO clock timing in the SDR modes is shown by the combination of Figure 26 and Table 47. Figure 26: SDIO Clock Timing (SDR Modes) tCLK SDIO_CLK tCR tCF tCR Table 47: SDIO Bus Clock Timing Parameters (SDR Modes) Parameter Symbol Minimum Maximum Unit Comments – tCLK 40 – ns SDR12 mode 20 – ns SDR25 mode – tCR, tCF – 0.2 × tCLK ns CCARD = 10 pF Clock duty cycle – 30 70 % – Broadcom® March 12, 2016 • 43907-DS104-R Page 107 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO Interface Timing Device Input Timing SDIO device input timing in the SDR modes is shown by the combination of Figure 27 and Table 48. Figure 27: SDIO Bus Input Timing (SDR Modes) SDIO_CLK tIS tIH CMD input DAT[3:0] input Table 48: SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments tIS 3.00 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.80 – ns CCARD = 5 pF, VCT = 0.975V Broadcom® March 12, 2016 • 43907-DS104-R Page 108 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SDIO Interface Timing Device Output Timing SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of Figure 28 and Table 49. Figure 28: SDIO Bus Output Timing (SDR Modes up to 50 MHz) tCLK SDIO_CLK tODLY tOH CMD input DAT[3:0] input Table 49: SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz) Symbol Minimum Maximum Unit Comments tODLY – 14.0 ns tCLK ≥ 20 ns CL= 40 pF tOH 1.5 – ns Hold time at the tODLY (min.) CL= 15 pF Broadcom® March 12, 2016 • 43907-DS104-R Page 109 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet S/PDIF Interface Timing S/PDIF Interface Timing The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC). Figure 29 shows the S/PDIF interface timing. Figure 29: S/PDIF Interface Timing Clock Data 1 0 0 1 1 0 1 0 0 1 0 Encoded (BMC) Figure 30 shows the S/PDIF data output timing. Figure 30: S/PDIF Data Output Timing tCLK SPDIF_OUT tCR tCF Broadcom® March 12, 2016 • 43907-DS104-R tCR Page 110 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet S/PDIF Interface Timing Table 50 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 30 on page 110). Table 50: SPDIF Biphase Mark Code Timing Parameters Parameter Symbol Minimum Maximum Unit Comments – tCLK 40 – ns 192 kHz sample rate – tCR, tCF – 0.3 × tCLK ns – Duty cycle – 30 70 % – Table 51 provides the S/PDIF biphase mark code sample rate and receiver clock frequency. Table 51: SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency Parameter Symbol Minimum Maximum Unit Comments Sampling frequency fS – 192 kHz 192 kHz sample rate maximum. Component clock frequency fCLOCK – 25 MHz Typical is 128 × fS, max is 192 × fS. Clock is 2× the desired data rate or 2 × 192 kHz × 64 = 24.576 MHz. Broadcom® March 12, 2016 • 43907-DS104-R Page 111 BROADCOM CONFIDENTIAL SPI Flash Timing BCM43907 Preliminary Data Sheet SPI Flash Timing Read-Register Timing Figure 31 shows the SPI flash extended and quad read-register timing. Note: Regarding Figure 31: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration Register operation will output data starting from the least significant byte. Figure 31: SPI Flash Read-Register Timing Extended 0 7 8 9 10 11 12 13 14 15 C LSB DQ0 Command MSB DQ1 LSB High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Quad 0 1 2 3 C LSB DQ[3:0] Command MSB LSB DOUT DOUT DOUT Don’t care MSB Broadcom® March 12, 2016 • 43907-DS104-R Page 112 BROADCOM CONFIDENTIAL SPI Flash Timing BCM43907 Preliminary Data Sheet Write-Register Timing Figure 32 shows the SPI flash extended and quad write-register timing. Note: Regarding Figure 32: 1. All write-register commands except Write Lock Register are supported. 2. The waveform must be extended for each protocol: to 23 for extended and five for quad. 3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte. Figure 32: SPI Flash Write-Register Timing Extended 0 7 8 9 10 11 12 13 14 15 C LSB LSB DQ0 Command DIN MSB Quad DIN DIN DIN DIN DIN DIN DIN DIN MSB 0 1 2 3 C LSB DQ[3:0] LSB DIN Command MSB DIN DIN MSB Broadcom® March 12, 2016 • 43907-DS104-R Page 113 BROADCOM CONFIDENTIAL SPI Flash Timing BCM43907 Preliminary Data Sheet Memory Fast-Read Timing Figure 33 shows the SPI flash extended and quad memory fast-read timing. Note: Regarding Figure 33: 1. 24-bit addressing is used, so A[MAX] = A[23] and A[MIN] = A[0]. 2. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1). 3. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. Figure 33: Memory Fast-Read Timing Extended 0 7 8 Cx C A[MIN] LSB Command DQ0 MSB DQ1 A[MAX] LSB DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy Cycles Quad 0 1 2 Cx C LSB A[MIN] LSB DQ[3:0] Command MSB DOUT A[MAX] DOUT DOUT MSB Dummy Cycles Broadcom® March 12, 2016 • 43907-DS104-R Don’t care Page 114 BROADCOM CONFIDENTIAL SPI Flash Timing BCM43907 Preliminary Data Sheet Memory-Write Timing Figure 34 shows the SPI flash extended and quad memory-write (Page Program) timing. Note: Regarding Figure 34: 1. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1). 2. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. Figure 34: Memory-Write Timing Extended 0 7 8 Cx C LSB A[MIN] LSB DIN Command DQ0 MSB Quad A[MAX] 0 1 DIN DIN DIN DIN DIN DIN DIN DIN MSB 2 Cx C DQ[3:0] LSB A[MIN] LSB Command MSB DIN A[MAX] DIN DIN MSB Broadcom® March 12, 2016 • 43907-DS104-R Page 115 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet SPI Flash Timing SPI Flash Parameters The combination of Figure 35 and Table 52 provide the SPI flash timing parameters. Figure 35: SPI Flash Timing Parameters Diagram T_DVCH Clock (C) T_CHDX Data in (DIN) (DQ1 in Serial [Extended] mode) (DQ[3:0] in Quad mode) T_CLQX Data out (DOUT) (DQ0 in Serial [Extended] mode) (DQ[3:0] in Quad mode) T_CLQV Table 52: SPI Flash Timing Parameters Parameter Description Minimum Maximum Units T_DVCH Data setup time 2 – ns T_CHDX Data hold time 3 – ns T_CLQX Output hold time 1 – ns T_CLQV Output valid time (with a 10 pF load) – 5 ns Broadcom® March 12, 2016 • 43907-DS104-R Page 116 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB PHY Electrical Characteristics and Timing USB PHY Electrical Characteristics and Timing USB 2.0 and USB 1.1 Electrical and Timing Parameters Table 53 provides electrical and timing parameters for USB 2.0. Table 53: USB 2.0 Electrical and Timing Parameters Parameter Symbol Minimum Typical Maximum Units Conditions Baud rate BPS – 480 – Mbps – Unit interval UI – 2083 – ps – Differential input voltage sensitivity VHSDI 300 – – mV Static | VIDP – VIDN | Input common mode voltage range VHSCM –50 – 500 mV – Receiver jitter tolerance THSRX –0.15 – 0.15 UI – Input impedance RIN 40.5 45 49.5 Ω Single ended Output high voltage VHSOH 360 400 440 mV Static condition Output low voltage VHSOL –10 0 10 mV Static condition Output rise time THSR 500 – – ps 10% to 90% Output fall time THSF 500 – – ps 90% to 10% Transmitter jitter THSTX –0.05 – 0.05 UI Transmit output jitter Output impedance RO 45 49.5 Ω Single ended Chirp-J output voltage (differential) VCHIRPJ 700 – 1100 mV HS termination disabled. 1.5 kΩ ± 5% pull-up resistor connected. Chirp-K output voltage (differential) VCHIRPK –900 – –500 mV HS termination disabled. 1.5 kΩ ± 5% pull-up resistor connected. Receiver – HS Mode Transmitter – HS Mode 40.5 Note: Refer to Section 7 of the USB 2.0 specification (www.usb.org) for more information on the receiver eye diagram template. Broadcom® March 12, 2016 • 43907-DS104-R Page 117 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB PHY Electrical Characteristics and Timing Table 54 provides electrical and timing parameters for USB 1.1. Table 54: USB 1.1 FS/LS Electrical and Timing Parameters a Value Parameter Symbol Minimum Typical Maximum Unit Condition FS BPS – 12 – Mbps – LS BPS – 1.5 – Mbps – FS UI – 83.33 – ns – LS UI – 666.67 – ns – Differential input sensitivity VFSDI 200 – – mV Static |VIDP – VIDN | Input common mode range VFSCM 0.8 – 2.5 V – Input impedance ZIN 300 – – kΩ – Input high voltage VFSIH 2.0 – – V Static Input low voltage VFSIL – – 0.8 V Static Output high voltage VFSOH 2.8 – – V Static Output low voltage VFSOL – – 0.3 V Static Output rise/fall time for fast speed TR,TF 4 – 20 ns 10 to 90% Output rise/fall time for low speed TR,TF 75 – 300 ns 10 to 90% Fast-speed jitter FSTX –2 – 2 ns – Low-speed jitter LSTX –25 – 25 ns – Output impedance RO 28 – 44 Ω Single ended Baud Rate Unit Interval Receiver Transmitter a. For more details, refer to the USB 1.1 Specification. Broadcom® March 12, 2016 • 43907-DS104-R Page 118 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB PHY Electrical Characteristics and Timing USB 2.0 Timing Diagrams Figure 36 shows the important timing parameters associated with a post-reset transition to high-speed (HS) operation. Figure 36: USB 2.0 Bus Reset to High-Speed Mode Operation 40 to 60 μs < 100 μs DP 100 to 500 μs Idle HS Data HighSpeed Chirp DM Device K-Chirp Idle 3 to 3.125 ms HS Data > 1.0 ms 100 to 875 μs < 7 ms > 10 ms Start of Reset Device Goes into FullSpeed Mode Start of Host (Hub) Chirp End of Host (Hub) Chirp End of Reset Device Tests for Single-Ended Zero (SE0) State Broadcom® March 12, 2016 • 43907-DS104-R Page 119 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB PHY Electrical Characteristics and Timing Figure 37 shows the USB 2.0 HS Mode transmit timing. Figure 37: USB 2.0 High-Speed Mode Transmit Timing 96 bits DP/DM Latency = 42 bits CLK60 PID TXDATA B0 B1 TXVALID TXREADY XVERSEL 00 OPMODE 00 TERMSEL 0 TX driver is enabled here. Broadcom® March 12, 2016 • 43907-DS104-R Page 120 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet USB PHY Electrical Characteristics and Timing Figure 38 shows the USB 2.0 HS Mode receive timing. Figure 38: USB 2.0 High-Speed Mode Receive Timing Latency = 72 bits 64 bits DP/DM CLK60 RXACTIVE RXVALID B0 RXDATA XVERSEL 00 OPMODE 00 TERMSEL 0 Broadcom® March 12, 2016 • 43907-DS104-R B1 B2 Page 121 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Power-Up Sequence and Timing Section 18: Power-Up Sequence and Ti m i n g Sequencing of Reset and Regulator Control Signals The BCM43907 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 39 and Figure 40 on page 123). The timing values indicated are minimum required values; longer delays are also acceptable. Description of Control Signals • REG_ON: Used by the PMU to power-up the BCM43907. It controls the internal BCM43907 regulators. When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low the regulators are disabled. • HIB_REG_ON_IN: Used by the Hibernation (HIB) block to power up the internal BCM43907 regulators. If the HIB_REG_ON_IN pin is low, the regulators are disabled. For the HIB_REG_ON_IN pin to work as designed, HIB_REG_ON_OUT must be connected to REG_ON. Note: The BCM43907 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Note: The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO should not be present first or be held high before VBAT is high. Broadcom® March 12, 2016 • 43907-DS104-R Page 122 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Sequencing of Reset and Regulator Control Signals Control Signal Timing Diagrams Figure 39: REG_ON = High, No HIB_REG_ON_OUT Connection to REG_ON 32.678 kHz Sleep Clock VBAT VDDIO ~ 2 Sleep Cycles REG_ON HIB_REG_ON_IN Figure 40: HIB_REG_ON_IN = High, HIB_REG_ON_OUT Connected to REG_ON 32.678 kHz Sleep Clock VBAT VDDIO ~ 2 Sleep Cycles HIB_REG_ON_IN Broadcom® March 12, 2016 • 43907-DS104-R Page 123 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Thermal Information Section 19: Thermal Information Package Thermal Characteristics Table 55: Package Thermal Characteristicsa Characteristic WLCSP JA (°C/W) (value in still air) 33.74 JB (°C/W) 5.5 JC (°C/W) 1.74 JT (°C/W) 5.86 JB (°C/W) 11.52 Maximum Junction Temperature Tj (°C) 116.7 Maximum power dissipation (W) 1.38 a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7. Air velocity is 0 m/s. Junction Temperature Estimation and PSIJT Versus THETAJC Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is: TJ = TT + P x JT Where: • TJ = Junction temperature at steady-state condition (°C) • TT = Package case top center temperature at steady-state condition (°C) • P = Device power dissipation (Watts) • JT = Package thermal characteristics; no airflow (°C/W) Environmental Characteristics For environmental characteristics data, see Table 16: “Environmental Ratings,” on page 75. Broadcom® March 12, 2016 • 43907-DS104-R Page 124 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Mechanical Information Section 20: Mechanical Information Figure 41: WLCSP Package Broadcom® March 12, 2016 • 43907-DS104-R Page 125 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Ordering Information S e c t i o n 2 1 : O rd e r i n g I n f o r m a t i o n Part Number Package Description Operating Ambient Temperature BCM43907KWBG 4.583 mm x 5.533 mm, 316-pin WLCSP – –30°C to +85°C Broadcom® March 12, 2016 • 43907-DS104-R Page 126 BROADCOM CONFIDENTIAL BCM43907 Preliminary Data Sheet Broadcom® reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. Broadcom Web: www.broadcom.com Corporate Headquarters: San Jose, CA © 2016 by Broadcom. All rights reserved. 43907-DS104-R March 12, 2016