CY7C1351F 4-Mb (128K x 36) Flow-through SRAM with NoBL™ Architecture Features • Burst Capability—linear or interleaved burst order • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 36 common I/O architecture • Low standby power Functional Description[1] The CY7C1351F is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). • 2.5V / 3.3V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 7.5 ns (for 117-MHz device) — 8.0 ns (for 100-MHz device) Write operations are controlled by the four Byte Write Select (BW[A:D]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. — 11.0 ns (for 66-MHz device) • Clock Enable (CEN) pin to suspend operation Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP and 119 BGA packages Logic Block Diagram ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BWA WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWB BWC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S BWD WE OE CE1 CE2 CE3 ZZ INPUT REGISTER D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPA DQPB DQPC DQPD E E READ LOGIC SLEEP Control 1 Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05210 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 12, 2004 CY7C1351F Selection Guide 133 MHz 117 MHz 100 MHz 66 MHz Unit 6.5 225 40 7.5 220 40 8.0 205 40 11.0 195 40 ns mA mA Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Pin Configurations Document #: 38-05210 Rev. *B OE ADV/LD 87 86 85 45 46 47 48 49 50 A A A A A 41 VDD A 40 VSS A 39 NC A CEN 88 38 NC 44 37 A0 43 36 A1 NC 35 A 42 34 A NC 33 81 WE 89 82 CLK 90 NC VSS 91 A VDD 92 83 CE3 93 84 BWA 94 NC BWC 96 BWB BWD 97 95 CE2 98 A CE1 32 BYTE D A NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A VDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1351F 31 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 99 100 A 100-lead TQFP DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Page 2 of 15 CY7C1351F Pin Configurations (continued) 119-Ball BGA 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B C NC NC CE2 A A A ADV/LD VDD A A CE3 A NC NC D DQC DQPC VSS NC VSS DQPB DQB E F DQC VDDQ DQC DQC VSS VSS CE1 OE VSS VSS DQB DQB DQB VDDQ G H J DQC DQC VDDQ DQC DQC VDD BWC VSS VSS NC WE VDD BWB VSS VSS DQB DQB VDD DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS CEN A1 VSS VSS DQA DQA VDDQ DQA P DQD DQPD VSS A0 VSS DQPA DQA R T NC NC A MODE A VDD NC A A A NC NC NC U VDDQ NC NC NC NC NC VDDQ ZZ Pin Definitions Name TQFP BGA 37,36,32,33,34, 35,44,45,46,47, 48,49,50,81,82, 99,100 P4,N4,A2,C2, R2,A3,B3,C3, T3,T4,A5,B5, C5,T5,A6,C6, R6 InputAddress Inputs used to select one of the 128K address loSynchronous cations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. 93,94,95,96 L5,G5,G3,L3 InputByte Write Inputs, active LOW. Qualified with WE to conduct Synchronous writes to the SRAM. Sampled on the rising edge of CLK. WE 88 H4 InputWrite Enable Input, active LOW. Sampled on the rising edge Synchronous of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD 85 B4 InputAdvance/Load Input. Used to advance the on-chip address Synchronous counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK 89 K4 CE1 98 E4 InputChip Enable 1 Input, active LOW. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. CE2 97 B2 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. A0, A1, A BW[A:D] Document #: 38-05210 Rev. *B I/O Input-Clock Description Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Page 3 of 15 CY7C1351F Pin Definitions Name TQFP BGA CE3 92 B6 InputChip Enable 3 Input, active LOW. Sampled on the rising edge Synchronous of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE 86 F4 InputOutput Enable, asynchronous input, active LOW. Combined Asynchronous with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN 87 M4 InputClock Enable Input, active LOW. When asserted LOW the Synchronous Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ 64 T7 InputZZ “sleep” Input. This active HIGH input places the device in Asynchronous a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. 52,53,56,57,58, 59,62,63,68,69, 72,73,74,75,78, 79,2,3,6,7,8,9, 12,13,18,19,22, 23,24,25,28,29 K6,L6,M6,N6, K7,L7,N7,P7, E6,F6,G6,H6, D7,E7,G7,H7, D1,E1,G1,H1, E2,F2,G2,H2, K1,L1,N1,P1, K2,L2,M2,N2 I/OBidirectional Data I/O Lines. As inputs, they feed into an Synchronous on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. 51,80,1,30 P6,D6,D2,P2 I/OBidirectional Data Parity I/O Lines. Functionally, these signals Synchronous are identical to DQs. During write sequences, DQP[A:D] is controlled by BW[A:D] correspondingly. 31 R3 15,41,65,91 J2,C4,J4,R4, J6 DQs DQP[A:D] MODE VDD VDDQ 4,11,20,27,54, 61,70,77 I/O Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Power supply inputs to the core of the device. A1,F1,J1,M1, I/O Power Sup- Power supply for the I/O circuitry. U1,A7,F7,J7, ply M7,U7 VSS 5,10,17,21,26, D3,E3,F3,H3, 40,55,60,67,71, J3,K3,M3,N3, 76,90, P3,D5,E5,F5, H5,J5,K5,M5, N5,P5 Ground NC 14,16,38,39,42, B1,C1,R1,T1, 43,66,83,84 T2,U2,U3,A4, D4,G4,L4,U4, U5,T6,U6,B7, C7,R5,R7,T7 – Document #: 38-05210 Rev. *B Description Ground for the device. No Connects. Not Internally connected to the die. Page 4 of 15 CY7C1351F Functional Overview The CY7C1351F is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:D] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The CY7C1351F has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the Document #: 38-05210 Rev. *B beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:D]. On the next clock rise the data presented to DQs and DQP[A:D] (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BW[A:D] signals. The CY7C1351F provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1351F is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:D] inputs. Doing so will three-state the output drivers. As a safety precaution, DQs and DQP[A:D].are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1351F has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:D] inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 5 of 15 CY7C1351F Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ ZZ > VDD − 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to snooze current This parameter is sampled tRZZI ZZ inactive to exit snooze current This parameter is sampled Min. Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC ns 0 ns Truth Table[2, 3, 4, 5, 6, 7, 8 ] Address Used CE1 CE2 CE3 ZZ ADV/LD WE Deselect Cycle None H X X L L X Deselect Cycle None X X H L L X X X L L->H Three-state Deselect Cycle None X L X L L X X X L L->H Three-state Three-state Operation Continue Deselect Cycle BWX OE X X CEN CLK DQ L L->H Three-state None X X X L H X X X L L->H External L H L L L H X L L L->H Data Out (Q) Next X X X L H X X L L L->H Data Out (Q) External L H L L L H X H L L->H Three-state Next X X X L H X X H L L->H Three-state External L H L L L L L X L L->H Data In (D) WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D) NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Three-state WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Three-state IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H – SNOOZE MODE None X X X H X X X X X X Three-state READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) Notes: 2. X = Don’t Care.” H= Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3. Write is defined by BW[A:D], and WE. See truth table for Read/Write. 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. The DQs and DQP[A:D] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state when OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active. Document #: 38-05210 Rev. *B Page 6 of 15 CY7C1351F Partial Truth Table for Read/Write [2, 3, 9] Function Read WE H BWA X BWB X BWC X BWD X Read H X X X X Write – No bytes written L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) L L H H H L H L H H Write Byte C– (DQC and DQPC) L H H L H Write Byte D– (DQD and DQPD) L H H H L Write All Bytes L L L L L Note: 9. Table only lists a partial listing of the byte write combinatios. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05210 Rev. *B Page 7 of 15 CY7C1351F Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Ambient Range Temperature (TA) Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V Com’l Ind’l 0°C to +70°C −40°C to +85°C VDD VDDQ 3.3V - 5%/+10% 2.5V - 5% to VDD Electrical Characteristics Over the Operating Range [10,11] Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VOL VIH VIL IX Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3V V Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3V V Voltage[10] VDDQ = 3.3V –0.3 0.8 V Input LOW Voltage[10] VDDQ = 2.5V –0.3 0.7 V Input Load Current (except ZZ and MODE) GND ≤ VI ≤ VDDQ −5 5 µA Input = VSS –30 Input LOW Input Current of MODE Input = VDD Input Current of ZZ Input = VSS GND ≤ VI ≤ VDD, Output Disabled IOZ Output Leakage Current Output Short Circuit Current VDD = Max., VOUT = GND IDD VDD Operating Supply Current ISB1 Automatic CE Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC –5 Automatic CE Power-down Current—CMOS Inputs 30 µA 5 µA –300 µA 7.5-ns cycle, 133 MHz 225 mA 8.5-ns cycle, 117 MHz 220 mA 10-ns cycle, 100 MHz 205 mA 15-ns cycle, 66 MHz 195 mA VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VIH or VIN ≤ VIL, f = fMAX, 8.5-ns cycle, 117 MHz inputs switching 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB2 µA µA –5 Input = VDD IOS µA 5 VDD = Max, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 90 mA 85 mA 80 mA 60 mA 40 mA Shaded areas contain advance information. Notes: 10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05210 Rev. *B Page 8 of 15 CY7C1351F Electrical Characteristics Over the Operating Range (continued)[10,11] Parameter ISB3 Description Test Conditions Automatic CE Power-down Current—CMOS Inputs Min. Max. Unit 75 mA VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 8.5-ns cycle, 117 MHz f = fMAX, inputs switching 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB4 VDD = Max, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Automatic CE Power-down Current—TTL Inputs 70 mA 65 mA 45 mA 45 mA Thermal Resistance[12] Parameters Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package BGA Package Unit 41.83 47.63 °C/W 9.99 11.71 °C/W Capacitance[12] Parameter Description Test Conditions CIN Input Capacitance CCLOCK Clock Input Capacitance CI/O I/O Capacitance TQFP Package BGA Package Unit 5 5 pF 5 5 pF 5 7 pF TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ=3.3V AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω INCLUDING JIG AND SCOPE 10% 90% 10% 90% ≤ 1ns ≤ 1ns VL = 1.5V (a) ALL INPUT PULSES VDD (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R =1538Ω VL = 1.25V (a) ALL INPUT PULSES VDD INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% ≤ 1ns ≤ 1ns (c) Note: 12. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05210 Rev. *B Page 9 of 15 CY7C1351F Switching Characteristics Over the Operating Range[17, 18] 133 MHz Parameter tPOWER Description VDD(Typical) to the first Access[13] 117 MHz 100 MHz 66 MHz Min. Max. Min. Max. Min. Max. Min. Max. Unit 1 1 1 1 ms Clock tCYC Clock Cycle Time 7.5 8.5 10 15 ns tCH Clock HIGH 2.5 3.0 4.0 5.0 ns tCL Clock LOW 2.5 3.0 4.0 5.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise tCLZ Clock to Low-Z[14, 15, 16] tCHZ High-Z14, 15, 16] 3.5 3.5 3.5 5.0 ns OE LOW to Output Valid 3.5 3.5 3.5 6.0 ns tOEV tOELZ tOEHZ Clock to OE LOW to Output Low-Z[14, 15, 16] OE HIGH to Output High-Z[14, 15, 16] 6.5 7.5 8.0 11.0 ns 2.0 2.0 2.0 2.0 ns 0 0 0 0 ns 0 0 3.5 0 3.5 0 ns 3.5 6.0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tALS ADV/LD Set-up Before CLK Rise WE, BW[A:D] Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns 1.5 2.0 2.0 2.0 ns CEN Set-up Before CLK Rise Data Input Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tDS 1.5 2.0 2.0 2.0 ns tCES Chip Enable Set-Up Before CLK Rise 1.5 2.0 2.0 2.0 ns Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns ADV/LD Hold after CLK Rise WE, BW[A:D] Hold After CLK Rise 0.5 0.5 0.5 0.5 ns 0.5 0.5 0.5 0.5 ns 0.5 0.5 0.5 ns tDH CEN Hold After CLK Rise Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES tCENS Hold Times tAH tALH tWEH tCENH Shaded areas contain advance information. Notes: 13. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve Three-state prior to Low-Z under the same system conditions 16. This parameter is sampled and not 100% tested. 17. Timing reference level is 1.5V when VDDQ =3.3V and is 1.25V when VDDQ = 2.5V. 18. Test conditions shown in (a) of AC Test Loads, unless otherwise noted. Document #: 38-05210 Rev. *B Page 10 of 15 CY7C1351F Switching Waveforms Read/Write Waveforms[19, 20, 21] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCES tCEH tCH tCL CEN CE ADV/LD WE BW[A:D] A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tDH WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE NOP, STALL and DESELECT Q(A6) D(A7) WRITE D(A7) DESELECT tDOH tOELZ WRITE D(A1) D(A5) tOEHZ OE COMMAND tCHZ BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) UNDEFINED Cycles[19, 20, 22] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW[A:D] ADDRESS A5 tCHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) tDOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE Document #: 38-05210 Rev. *B STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Page 11 of 15 CY7C1351F Switching Waveforms ZZ Mode Timing[23,24] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1351F-133AC CY7C1351F-133BGC CY7C1351F-133AI CY7C1351F-133BGI 117 CY7C1351F-117AC CY7C1351F-117BGC CY7C1351F-117AI CY7C1351F-117BGI 100 CY7C1351F-100AC CY7C1351F-100BGC CY7C1351F-100AI CY7C1351F-100BGI 66 CY7C1351F-66AC CY7C1351F-66BGC CY7C1351F-66AI CY7C1351F-66BGI Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial 119-Ball BGA 14 x 22 x 2.4 mm 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial 119-Ball BGA 14 x 22 x 2.4 mm Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts. Notes: 19. For this waveform ZZ is tied low. 20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 21. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional. 22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. 23. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 24. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05210 Rev. *B Page 12 of 15 CY7C1351F Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05210 Rev. *B Page 13 of 15 CY7C1351F Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05210 Rev. *B Page 14 of 15 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1351F Document History Page Document Title: CY7C1351F 4-Mb (128K x 36) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05210 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 119833 01/07/03 HGK New Data Sheet *A 123846 01/18/03 AJH Added power-up requirements to AC test loads and waveforms information *B 200664 See ECN SWI Final Data Sheet Document #: 38-05210 Rev. *B Page 15 of 15