HI-8588 January 2001 DESCRIPTION PIN CONFIGURATION The HI-8588 is an ARINC 429 bus interface receiver and is available in a SO 8 pin package. The technology is analog/digital CMOS. The circuitry requires only a 5 volt supply. VCC 1 8 TESTB TESTA 2 7 ROUTB RINB 3 6 ROUTA RINA 4 5 GND The ARINC bus can be connected directly to the chip. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. The TESTA and TESTB inputs bypass the analog for testing purposes. Also if TESTA and TESTB are both taken high, the analog powers down and the digital outputs tri-state allowing wire-or possibilities. Please refer to the HI-8588-10 for applications where an external resistance in series with the ARINC inputs is required for lightning protection or when the digital outputs need to be a logic zero rather than open circuit when TESTA and TESTB are both high. SUPPLY VOLTAGES vcc = 5.0V ± 5% FUNCTION TABLE FEATURES ! Direct ARINC 429 line receiver interface in a small outline package ! Receiver input hystersis at least 2 volts ! Test inputs that bypass analog input and can power down and tri-state outputs ! Plastic and ceramic package options surface mount and DIP ! Mil processing available (DS8588 Rev. A) PIN DESCRIPTION TABLE PIN SYMBOL FUNCTION DESCRIPTION VCC SUPPLY 5 VOLT SUPPLY TESTA LOGIC INPUT CMOS RINB ARINC INPUT RECEIVER B INPUT RINA ARINC INPUT RECEIVER A INPUT GND POWER GROUND ROUTA LOGIC OUTPUT RECEIVER CMOS OUTPUT A ROUTB LOGIC OUTPUT RECEIVER CMOS OUTPUT B TESTB LOGIC INPUT CMOS HOLT INTEGRATED CIRCUITS 1 01/01 HI-8588 FUNCTIONAL DESCRIPTION RECEIVER The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. Figure 1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each have series resistors, typically 35K ohms. They connect to level translators whose resistance to Ground is typically 10K ohms. Therefore, any series resistance added to the inputs will affect the voltage translation. The logic at the output is controlled by the test signal which is generated by the logical OR of theTestA and TestB pins. If TestA and TestB are both One, then the receiver is powered down and the output pins float. The powerdown does not disconnect the internal resistors at the ARINC input. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. TEST ONE S Q ROUTA LATCH TEST R TESTA ' TESTB TESTA RINA RINB ESD PROTECTION AND TRANSLATION NULL TEST ZERO S Q ROUTB LATCH TEST R TESTA ' TESTB TESTB NULL FIGURE 1 - RECEIVER BLOCK DIAGRAM APPLICATION INFORMATION 1 Figure 2 shows a possible application of the HI-8588 interfacing an ARINC receive channel to the HI-6010 which in turn interfaces to an 8-bit bus. 2 6 8 7 4 3 5 1 8 6 2 7 3 4 5 FIGURE 2 - APPLICATION DIAGRAM HOLT INTEGRATED CIRCUITS 2 HI-8588 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Voltages referenced to Ground Supply voltages VCC...................................................7V Supply Voltages VCC........................................5V... ± 5% ARINC input - pins 3 & 4 Voltage at either pin......+29V to -29V Temperature Range Industrial Screening........-40°C to +85°C Hi-Temp Screening.......-55°C to +125°C Military Screening.........-55°C to +125°C DC current per input pin................ ±10mA Power dissipation at 25°C plastic DIL............0.7W ceramic DIL..........0.5W Solder Temperature ........275°C for 10 sec Storage Temperature........-65°C to +150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. OPERATING TEMPERATURE RANGE, supplies floating " " Kohm Kohm V IN = 0 V V IN = 5 V µA µA V = 4.6V OH V = 0.4V OL mA mA pins 2, 8 = 0V; pins 3, 4 open pins 2, 8 = 5V; pins 3, 4 open mA mA HOLT INTEGRATED CIRCUITS 3 HI-8588 OPERATING TEMPERATURE RANGE, defined in Figure 3, C L= 50pF 10V 0V -10V DIFF t plhr t rr t phlr 5V 0V 90% pin 6 10% t plhr t phlr t fr 5V 0V pin 7 FIGURE 3 - RECEIVER TIMING PART PACKAGE TEMPERATURE NUMBER HI-8588PDI HI-8588PDT HI-8588PSI HI-8588PST HI-8588CDI HI-8588CDT HI-8588CDM HI-8588CRI HI-8588CRT HI-8588CRM DESCRIPTION 8 PIN PLASTIC DIP 8 PIN PLASTIC DIP 8 PIN PLASTIC NARROW BODY SOIC 8 PIN PLASTIC NARROW BODY SOIC 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERDIP 8 PIN CERDIP 8 PIN CERDIP RANGE -40°C TO +85°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C HOLT INTEGRATED CIRCUITS 4 FLOW I T I T I T M I T M BURN LEAD IN NO NO NO NO NO NO YES NO NO YES FINISH SOLDER SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER SOLDER SOLDER HI-8588 PACKAGE DIMENSIONS inches (millimeters) 8-PIN PLASTIC DIP Package Type: 8P .385 ± .015 (4.699 ± .381) .250 ± .010 (6.350 ± .254) .100 ± .010 (3.540 ± .254) .300 ± .010 (7.620 ± .254) 7° TYP. .025 ± .010 (.635 ± .254) .135 ± .015 (3.429 ± .381) .1375 ± .0125 (3.493 ± .318) .0115 ± .0035 (.292 ± .089) .055 ± .010 (1.397 ± .254) .019 ± .002 (.483 ± .102) .335 ± .035 (8.509 ± .889) 8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body) Package Type: 8HN .1935 ± .0035 (4.915 ± .085) .0086 ± .0012 (.2184 ± .0305) .236 ± .008 (5.994 ± .203) PIN 1 .1535 ± .0035 (3.90 ± .09) .0165 ± .0035 (.4191 ± .0889) Detail A .055 ± .005 (1.397 ± .127) 0° to 8° .050 ± .010 (1.27 ± .254) .0069 ± .0029 (.1753 ± .0737) .033 ± .017 (.8382 ± .4318) Detail A HOLT INTEGRATED CIRCUITS 5 HI-8588 PACKAGE DIMENSIONS inches (millimeters) 8-PIN CERAMIC SIDE-BRAZED DIP Package Type: 8C .405 ± MAX (10.287 ± MAX) .050 ± .007 (1.270 ± .178) .250 ± .008 (7.366 ± .203) .050 ± .005 (1.270 ± .127) PIN 1 .200 MAX (5.080 MAX) .035 ± .010 (.889 ± .254) BASE PLANE .163 ± .037 (4.140 ± .940) .0105 ± .0015 (.267 ± .038) SEATING PLANE .018 ± .002 (.457 ± .051) .100 ± .003 (2.540 ± .076) .300 ± .010 (7.620 ± .254) 8-PIN CERDIP Package Type: 8D .380 ± .004 (9.652 ± .102) .005 MIN. (.127 MIN.) .248 ± .003 (6.299 ± .076) .039 ± .006 (.991 ± .154) .100 ± .008 (2.540 ± .203) .015 MIN. (.381 MIN.) .200 MAX. (5.080 MAX.) .314 ± .003 (7.976 ± .076) Base Plane .010 ± .006 (.254 ± .152`) Seating Plane .163 ± .037 (4.140 ± .940) .056 ± .006 (1.422 ± .152) .018 ± .006 (.457 ± .152) HOLT INTEGRATED CIRCUITS 6 .350 ± .030 (8.890 ± .762)