Ramtron FM25CL64 64kb fram serial 3v memory Datasheet

FM25CL64
64Kb FRAM Serial 3V Memory
Features
64K bit Ferroelectric Nonvolatile RAM
• Organized as 8,192 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 2.7-3.65V
• 1 µA Standby Current
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Industry Standard Configuration
• Industrial Temperature -40°C to +85°C
• 8-pin SOIC
Description
Pin Configuration
The FM25CL64 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25CL64 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance,
orders of magnitude more endurance than EEPROM.
Also, FRAM exhibits much lower power during
writes than EEPROM since write operations do not
require an internally elevated power supply voltage
for write circuits.
These capabilities make the FM25CL64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
CS
SO
WP
1
8
2
7
3
6
VSS
4
5
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
VDD
HOLD
SCK
SI
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
Ordering Information
FM25CL64-S
8-pin SOIC
The FM25CL64 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25CL64 uses the high-speed
SPI bus, which enhances the high-speed write
capability
of
FRAM
technology.
Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
This product conforms to specifications per the terms of the Ramtron
standard warranty. Production processing does not necessarily include testing of all parameters.
Rev. 2.1
Apr. 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Page 1 of 13
FM25CL64
WP
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
HOLD
SCK
2,048 x 32
FRAM Array
Instruction Register
`
Address Register
Counter
13
SI
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 2.1
Apr. 2003
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the status register. This
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided below. *Note that the
function of /WP is different from the FM25040 where it prevents all writes to the part.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (2.7V to 3.65V)
Ground
Page 2 of 13
FM25CL64
Overview
Serial Peripheral Interface – SPI Bus
The FM25CL64 is a serial FRAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25CL64 and a serial
EEPROM with the same pinout is the FRAM’s
superior write performance.
The FM25CL64 employs a Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25CL64 operates in SPI Mode 0 and 3.
Memory Architecture
When accessing the FM25CL64, the user addresses
8,192 locations of 8 data bits each. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code, and
a two-byte address. The upper 3 bits of the address
range are ‘don’t care’ values. The complete address
of 13-bits specifies each byte address uniquely.
Most functions of the FM25CL64 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25CL64 due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25CL64 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within datasheet tolerances to
prevent incorrect operation.
Rev. 2.1
Apr. 2003
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. It is possible to
connect the two data pins together. Figure 2
illustrates a typical system configuration using the
FM25CL64 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25CL64 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25CL64 supports modes 0 and 3. Figure 4 shows
the required signal relationships for modes 0 and 3.
For both modes, data is clocked into the FM25CL64
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
Page 3 of 13
FM25CL64
SPI
Microcontroller
FM25640
FM25CL64
FM25640
FM25CL64
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0
P1.1
Microcontroller
FM25640
FM25CL64
P1.2
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 2.1
Apr. 2003
Page 4 of 13
FM25CL64
Data Transfer
All data transfers to and from the FM25CL64 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25CL64. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE Write Memory Data
Op-code
0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
WREN - Set Write Enable Latch
The FM25CL64 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 2.1
Apr. 2003
Page 5 of 13
FM25CL64
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25CL64 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Note that on the FM25CL64, /WP only prevents
writing to the Status register, not the memory array.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25CL64 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status register. As described above,
writes to the status register are performed using the
WRSR command and subject to the /WP pin. The
Status register is organized as follows.
Table 2. Status Register
Bit
Name
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The WPEN, BP1 and BP0 control write protection
Rev. 2.1
Apr. 2003
features. They are nonvolatile! The WEL flag
indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the
status register has no effect on its state. This bit is
internally set and cleared via the WREN and WRDI
commands, respectively.
BP1 and BP0 are memory block write protection
bits. They specify portions of memory that are write
protected as shown in the following table.
Table 3.
BP1
0
0
1
1
Block Memory Write Protection
BP0
Protected Address Range
0
None
1
1800h to 1FFFh (upper ¼)
0
1000h to 1FFFh (upper ½)
1
0000h to 1FFFh (all)
Page 6 of 13
FM25CL64
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
register is write protected if WPEN=1 and /WP=0.
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25CL64 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value. The upper 3-bits of the address are ignored. In
total, the 13-bits specify the address of the first data
byte of the write operation. Subsequent bytes are data
and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of 1FFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
Rev. 2.1
Apr. 2003
This scheme provides a write protection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, the WPEN bit is set to 1,
and /WP is set to 0. This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write operation. The following table summarizes the
write protection conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
8th clock). The rising edge of /CS terminates a
WRITE op-code operation.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a twobyte address value. The upper 3-bits of the address
are ignored. In total, the 13-bits specify the address of
the first byte of the read operation. After the op-code
and address are complete, the SI line is ignored. The
bus master issues 8 clocks, with one bit read out for
each. Addresses are incremented internally as long as
the bus master continues to issue clocks. If the last
address of 1FFFh is reached, the counter will roll
over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
A read operation is shown in Figure 10.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
Page 7 of 13
FM25CL64
CS
0
1
2
3
4
5
6
7
0
1
2
X
X
X
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
4
3
2
1
0
7
6
Data
5 4
3
2
1
7
SCK
op-code
SI
0
0
0
0
0
0
1
0
13-bit Address
12 11 10
LSB MSB
MSB
0
LSB
SO
Figure 9. Memory Write
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
X
X
13-bit Address
X 12 11 10
3
4
5
6
7
4
3
2
1
0
0
1
2
3
4
5
Data
4 3
5
6
7
SCK
op-code
SI
0
0
0
0
0
0
1
1
MSB
LSB MSB
SO
7
LSB
6
2
1
0
Figure 10. Memory Read
Applications
The versatility of FRAM technology fits into many
diverse applications. The strength of higher write
endurance and faster writes make FRAM superior to
EEPROM in all but one-time programmable
applications. The advantage is most obvious in data
collection environments where writes are frequent
and data must be nonvolatile.
The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.
1. Data collection. In applications that collect and
save data, FRAM provides a superior alternative to
other solutions. It is more cost effective than battery
backup for SRAM and provides better write attributes
than EEPROM.
2. Configuration. Any nonvolatile memory can
retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the systemstate is altered, the change can be written. This avoids
writing to memory on power-down when the
available time is short and power scarce.
3. High noise environments. Writing to EEPROM
in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability during which the write can be
Rev. 2.1
Apr. 2003
corrupted. The fast write of FRAM is complete
within a microsecond. This time is typically too short
for noise or power fluctuations to disturb it.
4. Time to market. In a complex system, multiple
software routines may need to access the nonvolatile
memory. In this environment the time delay
associated with programming EEPROM adds
complexity to the software development. Each
software routine must wait for complete
programming before allowing access to the next
routine. When time to market is critical, FRAM can
eliminate this simple obstacle. As soon as a write is
issued to the FM25CL64, it is effectively done -- no
waiting.
5. RF/ID. In the area of contactless memory,
FRAM provides an ideal solution. Since RF/ID
memory is powered by an RF field, the long
programming time and high current consumption
needed to write EEPROM is unattractive. FRAM
provides a superior solution. The FM25CL64 is
suitable for multi-chip RF/ID products.
6. Maintenance tracking. In sophisticated systems,
the operating history and system-state during a failure
is important knowledge. Maintenance can be
expedited when this information has been recorded.
Due to the high write endurance, FRAM makes an
ideal system log. In addition, the convenient interface
of the FM25CL64 allows memory to be distributed
throughout the system using minimal additional
resources.
Page 8 of 13
FM25CL64
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and the functional operation of the device at these or any other conditions
above those listed in the operational section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
2.7
3.3
3.65
V
IDD
VDD Supply Current
@ SCK = 1.0 MHz
0.2
0.8
mA
@ SCK = 5.0 MHz
1.4
3.0
@ SCK = 20.0 MHz
5
10.0
ISB
Standby Current
1
µA
ILI
Input Leakage Current
1
µA
ILO
Output Leakage Current
1
µA
VIH
Input High Voltage
0.7 VDD
VDD + 0.5
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH
Output High Voltage
V
VDD – 0.8
@ IOH = -2 mA
0.4
V
VOL
Output Low Voltage
@ IOL = 2 mA
VHYS
Input Hysteresis
0.05 VDD
V
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
4. Characterized but not 100% tested in production.
Rev. 2.1
Apr. 2003
Notes
1
2
3
3
4
Page 9 of 13
FM25CL64
AC Parameters (TA = -40° C to + 85° C, CL = 30pF)
VDD 2.7 to 3.0V
Symbol
fCK
tCH
tCL
tCSU
tCSH
tOD
tODV
tOH
tD
tR
tF
tSU
tH
tHS
tHH
tHZ
tLZ
Notes
1.
2.
3.
Parameter
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
Data In Rise Time
Data In Fall Time
Data Setup Time
Data Hold Time
/Hold Setup Time
/Hold Hold Time
/Hold Low to Hi-Z
/Hold High to Data Active
Min
0
25
25
10
10
Max
18
Min
0
22
22
10
10
Max
20
20
25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
0
60
0
60
50
50
50
50
5
5
10
10
5
5
10
10
20
20
20
20
Notes
1
1
2
1,3
1,3
2
2
tCH + tCL = 1/fCK.
Characterized but not 100% tested in production.
Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
CO
Output capacitance (SO)
CI
Input capacitance
Notes
1.
VDD 3.0 to 3.65V
Min
-
Max
8
6
Units
pF
pF
Notes
1
1
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Equivalent AC Load Circuit
10% and 90% of VDD
5 ns
30% and 70% of VDD
3.3V
1.2K Ω
Output
30 pF
0.95K Ω
Data Retention (VDD = 2.7V to 3.65V unless otherwise specified)
Parameter
Min
Max
Units
Notes
Data Retention
10
Years
1
Notes
1. The relationship between retention, temperature, and the associated reliability level is characterized
separately. Endurance is the guaranteed number of read or write cycles per address that can be
performed while maintaining the specified data retention. It is unlikely to reach this limit for most
applications.
Rev. 2.1
Apr. 2003
Page 10 of 13
FM25CL64
Serial Data Bus Timing
tD
tF
tCSU
tSU
tR
1/fCK
tCL
tCH
tCSH
tH
tODV
tOH
tOD
/Hold Timing
Rev. 2.1
Apr. 2003
Page 11 of 13
FM25CL64
Mechanical Drawing (8-pin SOIC - JEDEC Standard MS-012)
Index
Area
E
H
Pin 1
h
D
45 °
A
e
B
α
L
.10 mm
.004 in.
A1
C
Selected Dimensions
Symbol
A
A1
B
C
D
E
e
H
h
L
α
Dim
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
Min
1.35
0.053
0.10
0.004
0.33
0.013
0.19
0.007
4.80
0.189
3.80
0.150
mm
in.
mm
in.
mm
in.
5.80
0.228
0.25
0.010
0.40
0.016
0°
Nom.
Max
1.75
0.069
0.25
0.010
0.51
0.020
0.25
0.010
5.00
0.197
4.00
0.157
1.27 BSC
0.050
BSC
6.20
0.244
0.50
0.197
1.27
0.050
8°
Refer to JEDEC MS-012 for complete dimensions and notes.
Controlling dimensions in millimeters.
Conversions to inches are not exact.
Rev. 2.1
Apr. 2003
Page 12 of 13
FM25CL64
Revision History
Revision
0.0
0.1
Date
5/10/01
7/5/01
0.2
0.3
10/11/01
1/8/02
2.0
2.1
2/19/03
4/22/03
Rev. 2.1
Apr. 2003
Summary
Initial Release
Updated AC and DC specifications. Changed AC Test Conditions and Load
Circuit.
Added unlimited endurance bullet. Changed Data Retention table.
Changed operating Vdd voltage range to 3.0 – 3.65V. Reduced Idd supply
current limits.
Updated to Production status. Added note to Output Data Valid spec.
Changed operating Vdd voltage range to 2.7 – 3.65V with separate AC timing
specs defined below 3.0V operation. Reduced input leakage spec.
Page 13 of 13