LINER LTC1430CS High power step-down switching regulator controller Datasheet

LTC1430
High Power Step-Down
Switching Regulator Controller
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DESCRIPTIO
FEATURES
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High Power 5V to 3.xV Switching Controller:
Can Exceed 10A Output
All N-Channel External MOSFETs
Constant Frequency Operation—Small Inductor
Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations
High Efficiency: Over 95% Possible
Fixed Frequency Operation
No Low Value Sense Resistor Needed
Outputs Can Drive External FETs with Up to
10,000pF Gate Capacitance
Quiescent Current: 350µA Typ, 1µA in Shutdown
Fast Transient Response
Adjustable or Fixed 3.3V Output
Available in 8- and 16-Lead PDIP and SO Packages
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APPLICATIO S
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Power Supply for P6 and Pentium®
Microprocessors
High Power 5V to 3.xV Regulators
Local Regulation for Dual Voltage Logic Boards
Low Voltage, High Current Battery Regulation
The LTC ®1430 is a high power, high efficiency switching
regulator controller optimized for 5V to 3.xV applications.
It includes a precision internal reference and an internal
feedback system that can provide output regulation of ±1%
over temperature, load current and line voltage shifts. The
LTC1430 uses a synchronous switching architecture with
two N-channel output devices, eliminating the need for a
high power, high cost P-channel device. Additionally, it
senses output current across the drain-source resistance
of the upper N-channel FET, providing an adjustable
current limit without an external low value sense resistor.
The LTC1430 includes a fixed frequency PWM oscillator for
low output ripple under virtually all operating conditions.
The 200kHz free-running clock frequency can be externally
adjusted from 100kHz to above 500kHz. The LTC1430
features low 350µA quiescent current, allowing greater
than 90% efficiency operation in converter designs from
1A to greater than 50A output current. Shutdown mode
drops the LTC1430 supply current to 1µA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
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TYPICAL APPLICATIO
Efficiency
Typical 5V to 3.3V, 10A Application
100
VIN 5V
1N4148
1µF
100Ω
PVCC2
+
4.7µF
PVCC1
SS
0.01µF
NC
SHUTDOWN
RC
7.5k
CC
4700pF
L1, 2.8µH
1k
LTC1430 IFB
SHDN
+
G2
FREQSET
90
M1A, M1B
2 IN PARALLEL
0.1µF
IMAX
M2
PGND
COMP
C1
220pF
0.1µF
G1
VCC
0.1µF
16k
CIN
220µF
×4
COUT
330µF
×6
GND
SENSE –
LTC1430 • TA01
NC
CIN: AVX-TPSE227M010R0100
COUT: AVX-TPSE337M006R0100
L1: ETQP6F1R6SFA
M1A, M1B, M2: MOTOROLA MTD20N03HL
TA = 25°C
VIN = 5V
VOUT = 3.3V
80
70
60
50
40
0.1
SENSE+
FB
3.3V
10A
EFFICIENCY (%)
+
+
1
LOAD CURRENT (A)
10
LTC1430 • TA02
1
LTC1430
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ABSOLUTE
AXI U RATI GS
(Note 1)
Supply Voltage
VCC ....................................................................... 9V
PVCC1, 2 .............................................................. 13V
Input Voltage
IFB ......................................................... – 0.3V to 18V
All Other Inputs ...................... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC1430C .............................................. 0°C to 70°C
LTC1430I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER
PART NUMBER
TOP VIEW
LTC1430CN8
LTC1430CS8
ORDER
PART NUMBER
TOP VIEW
G1
1
16 G2
PVCC1
2
15 PVCC2
PGND
3
14 VCC
G1 1
8
G2
PVCC1 2
7
VCC /PVCC2
GND
4
13 IFB
GND 3
6
COMP
SENSE –
5
12 IMAX
FB 4
5
SHDN
FB
6
11 FREQSET
+
7
10 COMP
SHDN
8
9
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
1430
TJMAX = 150°C, θJA = 100°C/W (N8)
TJMAX = 150°C, θJA = 150°C/W (S8)
SENSE
N PACKAGE
16-LEAD PDIP
LTC1430CN
LTC1430CS
LTC1430IS
SS
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 70°C/W (N)
TJMAX = 150°C, θJA = 110°C/W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
VCC
Supply Voltage
CONDITIONS
●
MIN
PVCC
PVCC1, PVCC2
●
VOUT
Output Voltage
Figure 1
●
VFB
Feedback Voltage
Figure 1, SENSE + and SENSE – Floating (LTC1430C)
Figure 1, SENSE + and SENSE – Floating (LTC1430I)
●
●
∆VOUT
Output Load Regulation
Figure 1, IOUT = 0A to 10A (Note 3) (LTC1430C)
Figure 1, IOUT = 0A to 10A (Note 3) (LTC1430I)
TYP
MAX
UNITS
8
V
13
V
1.265
1.265
1.28
1.29
V
V
●
5
5
20
mV
mV
Output Line Regulation
Figure 1, VCC = 4.75V to 5.25V (Note 3) (LTC1430C) ●
Figure 1, VCC = 4.75V to 5.25V (Note 3) (LTC1430I)
1
1
5
mV
mV
IVCC
Supply Current (VCC Only)
Figure 2, VSHDN = VCC
VSHDN = 0V
350
1
700
10
µA
µA
IPVCC
Supply Current (PVCC)
Figure 2, PVCC = 5V, VSHDN = VCC (Note 4)
VSHDN = 0V
fOSC
Internal Oscillator Frequency
FREQSET Floating (LTC1430C)
FREQSET Floating (LTC1430I)
2
4
3.30
1.25
1.23
●
V
1.5
0.1
●
●
140
130
200
200
mA
µA
260
300
kHz
kHz
LTC1430
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIH
SHDN Input High Voltage
●
VIL
SHDN Input Low Voltage
●
IIN
SHDN Input Current
AV
Error Amplifier Open-Loop DC Gain
(LTC1430I)
●
40
48
gmV
Error Amplifier Transconductance
(LTC1430C)
(LTC1430I)
●
300
650
650
MAX
2.4
V
±0.1
●
UNITS
0.8
V
±1
µA
dB
1200
µMho
µMho
µMho
gmI
ILIM Amplifier Transconductance
(Note 5)
IMAX
IMAX Sink Current
VI(MAX) = VCC (LTC1430C)
VI(MAX) = VCC (LTC1430I)
●
●
8
8
12
12
16
17
µA
µA
ISS
Soft-Start Source Current
VSS = 0 (LTC1430C)
VSS = 0 (LTC1430I)
●
●
–8
–8
–12
–12
–16
–17
µA
µA
tr, ts
Driver Rise/Fall Time
Figure 3, PVCC1 = PVCC2 = 5V
80
250
ns
tNOV
Driver Non-Overlap Time
Figure 3, PVCC1 = PVCC2 = 5V
25
130
250
ns
DCMAX
Maximum Duty Cycle
VCOMP = VCC (LTC1430C)
●
90
96
%
VCOMP = VCC, VFB = 0 (LTC1430I)
VCOMP = VCC, VFB = 1.265V (LTC1430I)
●
●
90
88
96
%
%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: This parameter is guaranteed by correlation and is not tested
directly.
1300
83
Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC1430 operating frequency, operating voltage and the external FETs
used.
Note 5: The ILIM amplifier can sink but cannot source current. Under
normal (not current limited) operation, the ILIM output current will be zero.
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LTC1430
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PI FU CTIO S
(16-Lead Package/8-Lead Package)
G1 (Pin 1/Pin 1): Driver Output 1. Connect this pin to the
gate of the upper N-channel MOSFET, M1. This output will
swing from PVCC1 to PGND. It will always be low when G2
is high.
PVCC1 (Pin 2/Pin 2): Power VCC for Driver 1. This is the
power supply input for G1. G1 will swing from PGND to
PVCC1. PVCC1 must be connected to a potential of at least
PVCC + VGS(ON)(M1). This potential can be generated
using an external supply or a simple charge pump connected to the switching node between the upper MOSFET
and the lower MOSFET; see Applications Information for
details.
PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. It should be connected to a low impedance ground
in close proximity to the source of M2. 8-lead parts have
PGND and GND tied together at pin 3.
GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, GND should be connected to
PGND right at the LTC1430. 8-lead parts have PGND and
GND tied together internally at pin 3.
SENSE –, FB, SENSE + (Pins 5, 6, 7/Pin 4): These three
pins connect to the internal resistor divider and to the
internal feedback node. To use the internal divider to set
the output voltage to 3.3V, connect SENSE + to the positive
terminal of the output capacitor and SENSE – to the negative terminal. FB should be left floating in applications that
use the internal divider. To use an external resistor divider
to set the output voltage, float SENSE + and SENSE – and
connect the external resistor divider to FB.
SHDN (Pin 8/Pin 5): Shutdown. A TTL compatible low
level at SHDN for longer than 50µs puts the LTC1430 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally.
SS (Pin 9/NA): Soft-Start. The SS pin allows an external
capacitor to be connected to implement a soft-start function. An external capacitor from SS to ground controls the
start-up time and also compensates the current limit loop,
allowing the LTC1430 to enter and exit current limit
cleanly. See Applications Information for more details.
4
COMP (Pin 10/Pin 6): External Compensation. The COMP
pin is connected directly to the output of the error amplifier
and the input of the PWM. An RC network is used at this
node to compensate the feedback loop to provide optimum transient response. See Applications Information for
compensation details.
FREQSET (Pin 11/NA): Frequency Set. This pin is used to
set the free running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground will speed up the
oscillator; a resistor to VCC will slow it down. See Applications Information for resistor selection details.
IMAX (Pin 12/NA): Current Limit Set. IMAX sets the threshold for the internal current limit comparator. If IFB drops
below IMAX with G1 on, the LTC1430 will go into current
limit. IMAX has a 12µA pull-down to GND. It can be adjusted
with an external resistor to PVCC or an external voltage
source.
IFB (Pin 13/NA): Current Limit Sense. Connect to the
switched node at the source of M1 and the drain of M2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging IFB. This pin can be
taken up to 18V above GND without damage.
VCC (Pin 14/Pin 7): Power Supply. All low power internal
circuits draw their supply from this pin. Connect to a clean
power supply, separate from the main PVCC supply at the
drain of M1. This pin requires a 4.7µF bypass capacitor.
8-lead parts have VCC and PVCC2 tied together at pin 7 and
require a 10µF bypass to GND.
PVCC2 (Pin 15/Pin 7): Power VCC for Driver 2. This is the
power supply input for G2. G2 will swing from GND to
PVCC2. PVCC2 is usually connected to the main high power
supply. The 8-lead parts have VCC and PVCC2 tied together
at pin 7 and require a 10µF bypass to GND.
G2 (Pin 16/Pin 8): Driver Output 2. Connect this pin to the
gate of the lower N-channel MOSFET, M2. This output will
swing from PVCC2 to PGND. It will always be low when G1
is high.
LTC1430
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BLOCK DIAGRA
DELAY
SHDN
INTERNAL
SHUTDOWN
50µs
FREQSET
PVCC1
G1
PWM
COMP
PVCC2
G2
VCC
PGND
12µA
SS
ILIM
FB
+
–
MIN
+
MAX
–
IMAX
IFB
12µA
FB
+
40mV
20.1k
40mV
SENSE +
12.4k
SENSE –
+
+
LTC1430 • BD
1.26V
TEST CIRCUITS
PVCC = 5V
+
PVCC2
+
PVCC1
SS
0.01µF
NC
SHUTDOWN
C1
220pF
IMAX
G2
SHDN
PGND
COMP
GND
FB MEASUREMENT
M2
+
VOUT
LTC1430
+
SENSE
2.7µH/15A
0.1µF
LTC1430 IFB
FREQSET
CIN
220µF
×4
M1A, M1B
2 IN PARALLEL
G1
VCC
0.1µF
4.7µF
+
1N4148
1µF
100Ω
3.3V
SENSE –
COUT
330µF
×6
NC
1.61k
FB
1k
NC
SENSE+
RC
7.5k
FB
SENSE –
CC
4700pF
NC
M1A, M1B, M2: MOTOROLA MTD20N03HL
CIN: AVX-TPSE227M010R0100
COUT: AVX-TPSE337M006R0100
LTC1430 • F01
Figure 1
5V
PVCC
VSHDN VCC
10µF
SHDN VCC PVCC2 PVCC1
IFB
NC
IMAX
G1
NC
NC
FREQSET
G2
NC
NC
COMP
NC
SS
FB
NC
GND
LTC1430
0.1µF
VCC PVCC1 PVCC2
PGND SENSE – SENSE+
G1
G1 RISE/FALL
10,000pF
LTC1430
GND
G2
PGND
G2 RISE/FALL
10,000pF
LTC1430 • TC03
LTC1430 • TC02
Figure 2
Figure 3
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LTC1430
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APPLICATIO S I FOR ATIO
OVERVIEW
The LTC1430 is a voltage feedback PWM switching regulator controller (see Block Diagram) designed for use in
high power, low voltage step-down (buck) converters. It
includes an onboard PWM generator, a precision reference trimmed to ±0.5%, two high power MOSFET gate
drivers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.
The 16-lead versions of the LTC1430 include a current
limit sensing circuit that uses the upper external power
MOSFET as a current sensing element, eliminating the
need for an external sense resistor.
Also included in the 16-lead version is an internal softstart feature that requires only a single external capacitor
to operate. In addition, 16-lead parts feature an adjustable
oscillator which can run at frequencies from 50kHz to
beyond 500kHz, allowing added flexibility in external component selection. The 8-lead versions do not include
current limit, internal soft-start or frequency adjustability.
THEORY OF OPERATION
Primary Feedback Loop
The LTC1430 senses the output voltage of the circuit at the
output capacitor with the SENSE+ and SENSE– pins and
feeds this voltage back to the internal transconductance
amplifier FB. FB compares the resistor-divided output
voltage to the internal 1.26V reference and outputs an
error signal to the PWM comparator. This is then compared to a fixed frequency sawtooth waveform generated
by the internal oscillator to generate a pulse width modulated signal. This PWM signal is fed back to the external
MOSFETs through G1 and G2, closing the loop. Loop
compensation is achieved with an external compensation
network at COMP, the output node of the FB transconductance amplifier.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the FB
amplifier may not respond quickly enough. MIN compares
the feedback signal to a voltage 40mV (3%) below the
6
internal reference. At this point, the MIN comparator
overrides the FB amplifier and forces the loop to full duty
cycle, set by the internal oscillator at about 90%. Similarly,
the MAX comparator monitors the output voltage at 3%
above the internal reference and forces the output to 0%
duty cycle when tripped. These two comparators prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
Current Limit Loop
The 16-lead LTC1430 devices include yet another feedback loop to control operation in current limit. The current
limit loop is disabled in 8-lead devices. The ILIM amplifier
monitors the voltage drop across external MOSFET M1
with the IFB pin during the portion of the cycle when G1 is
high. It compares this voltage to the voltage at the IMAX pin.
As the peak current rises, the drop across M1 due to its
RDS(ON) increases. When IFB drops below IMAX, indicating
that M1’s drain current has exceeded the maximum level,
ILIM starts to pull current out of the external soft-start
capacitor, cutting the duty cycle and controlling the output
current level. At the same time, the ILIM comparator
generates a signal to disable the MIN comparator to
prevent it from conflicting with the current limit circuit. If
the internal feedback node drops below about 0.8V, indicating a severe output overload, the circuitry will force the
internal oscillator to slow down by a factor of as much as
100. If desired, the turn on time of the current limit loop
can be controlled by adjusting the size of the soft-start
capacitor, allowing the LTC1430 to withstand short overcurrent conditions without limiting.
By using the RDS(ON) of M1 to measure the output current,
the current limit circuit eliminates the sense resistor that
would otherwise be required and minimizes the number of
components in the external high current path. Because
power MOSFET RDS(ON) is not tightly controlled and varies
with temperature, the LTC1430 current limit is not designed to be accurate; it is meant to prevent damage to the
power supply circuitry during fault conditions. The actual
current level where the limiting circuit begins to take effect
may vary from unit to unit, depending on the power
MOSFETs used. See Soft-Start and Current Limit for more
details on current limit operation.
LTC1430
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MOSFET Gate Drive
Gate drive for the top N-channel MOSFET M1 is supplied
from PVCC1. This supply must be above PVCC ( the main
power supply input) by at least one power MOSFET
VGS(ON) for efficient operation. An internal level shifter
allows PVCC1 to operate at voltages above VCC and PVCC,
up to 13V maximum. This higher voltage can be supplied
with a separate supply, or it can be generated using a
simple charge pump as shown in Figure 4. When using a
separate PVCC1 supply, the PVCC input may exhibit a large
inrush current if PVCC1 is present during power up. The
90% maximum duty cycle ensures that the charge pump
will always provide sufficient gate drive to M1. Gate drive
for the bottom MOSFET M2 is provided through PVCC2 for
16-lead devices or VCC/PVCC2 for 8-lead devices. PVCC2
can usually be driven directly from PVCC with 16-lead
parts, although it can also be charge pumped or connected
to an alternate supply if desired. The 8-lead parts require
an RC filter from PVCC to ensure proper operation; see
Input Supply Considerations.
EXTERNAL COMPONENT SELECTION
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC1430 circuits. These should be selected based primarily on threshold and on-resistance considerations; thermal dissipation is often a secondary concern in high
DZ
12V
1N5242
LTC1430 designs that use a doubler charge pump to
generate gate drive for M1 and run from PVCC voltages
below 7V cannot provide enough gate drive voltage to fully
enhance standard power MOSFETs. When run from 5V, a
doubler circuit may work with standard MOSFETs, but the
MOSFET RON may be quite high, raising the dissipation in
the FETs and costing efficiency. Logic level FETs are a
better choice for 5V PVCC systems; they can be fully
enhanced with a doubler charge pump and will operate at
maximum efficiency. Doubler designs running from PVCC
voltages near 4V will begin to run into efficiency problems
even with logic level FETs; such designs should be built
with tripler charge pumps (see Figure 5) or with newer,
super low threshold MOSFETs. Note that doubler charge
pump designs running from more than 7V and all tripler
charge pump designs should include a zener clamp diode
DZ at PVCC1 to prevent transients from exceeding the
absolute maximum rating at that pin.
DZ
12V
1N5242
PVCC
OPTIONAL
USE FOR PVCC ≥ 7V
efficiency designs. Required MOSFET threshold should be
determined based on the available power supply voltages
and/or the complexity of the gate drive charge pump
scheme. In 5V input designs where an auxiliary 12V supply
is available to power PVCC1 and PVCC2, standard MOSFETs
with RDS(ON) specified at VGS = 5V or 6V can be used with
good results. The current drawn from this supply varies
with the MOSFETs used and the LTC1430’s operating
frequency, but is generally less than 50mA.
1N5817
PVCC
1N5817
1N5817
1N4148
PVCC2
PVCC1
G1
10µF
0.1µF
PVCC2
PVCC1
G1
M1
0.1µF
0.1µF
M1
L1
L1
VOUT
G2
VOUT
+
M2
LTC1430
Figure 4. Doubling Charge Pump
G2
COUT
LTC1430 • F04
+
M2
LTC1430
COUT
LTC1430 • F05
Figure 5. Tripling Charge Pump
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LTC1430
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Once the threshold voltage has been selected, RON should
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
In a typical LTC1430 buck converter circuit operating in
continuous mode, the average inductor current is equal to
the output load current. This current is always flowing
through either M1 or M2 with the power dissipation split
up according to the duty cycle:
VOUT
VIN
V
DC (M2) = 1 − OUT
VIN
(VIN − VOUT )
=
VIN
DC (M1) =
The RON required for a given conduction loss can now be
calculated by rearranging the relation P = I2R:
RON (M1) =
=
RON (M2) =
=
PMAX (M1)
DC (M1) • I MAX2
VIN • PMAX (M1)
VOUT • I MAX2
PMAX (M2)
DC (M2) • IMAX2
VIN • PMAX (M2)
(VIN − VOUT ) • I MAX2
PMAX should be calculated based primarily on required
efficiency. A typical high efficiency circuit designed for 5V
in, 3.3V at 10A out might require no more than 3%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
PMAX value of (3.3V • 10A/0.9) • 0.03 = 1.1W per FET and
a required RON of:
5V • 1.1W
RON (M1) =
= 0.017Ω
3.3V • 10A2
5V • 1.1W
RON (M2) =
= 0.032Ω
(5V − 3.3V) • 10A2
8
Note that the required RON for M2 is roughly twice that of
M1 in this example. This application might specify a single
0.03Ω device for M2 and parallel two more of the same
devices to form M1. Note also that while the required RON
values suggest large MOSFETs, the dissipation numbers
are only 1.1W per device or less—large TO-220 packages
and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY (in SO-8) and
Motorola MTD20N03HL (in DPAK) are two small, surface
mount devices with RON values of 0.03Ω or below with 5V
of gate drive; both work well in LTC1430 circuits with up
to 10A output current. A higher PMAX value will generally
decrease MOSFET cost and circuit efficiency and increase
MOSFET heat sink requirements.
Inductor
The inductor is often the largest component in an LTC1430
design and should be chosen carefully. Inductor value and
type should be chosen based on output slew rate requirements and expected peak current. Inductor value is primarily controlled by the required current slew rate. The
maximum rate of rise of the current in the inductor is set
by its value, the input-to-output voltage differential and the
maximum duty cycle of the LTC1430. In a typical 5V to
3.3V application, the maximum rise time will be:
90% •
(VIN − VOUT )
L
AMPS
1.53A I
=
SECOND
µs L
where L is the inductor value in µH. A 2µH inductor would
have a 0.76A/µs rise time in this application, resulting in a
6.5µs delay in responding to a 5A load current step. During
this 6.5µs, the difference between the inductor current and
the output current must be made up by the output capacitor, causing a temporary droop at the output. To minimize
this effect, the inductor value should usually be in the 1µH
to 5µH range for most typical 5V to 3.xV LTC1430 circuits.
Different combinations of input and output voltages and
expected loads may require different values.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current added to half the peakto- peak inductor ripple current. Ripple current is set by the
LTC1430
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inductor value, the input and output voltage and the
operating frequency. If the efficiency is high and can be
approximately equal to 1, the ripple current is approximately equal to:
∆I =
(VIN − VOUT ) • DC
DC =
fOSC • L
VOUT
VIN
fOSC = LTC1430 oscillator frequency
L = inductor value
Solving this equation with our typical 5V to 3.3V application, we get:
1.7 • 0.66
= 2.8AP −P
200kHz • 2µH
Peak inductor current at 10A load:
10A +
2.8A
= 11.4A
2
The inductor core must be adequate to withstand this peak
current without saturating, and the copper resistance in
the winding should be kept as low as possible to minimize
resistive power loss. Note that the current may rise above
this maximum level in circuits under current limit or under
fault conditions in unlimited circuits; the inductor should
be sized to withstand this additional current.
Input and Output Capacitors
A typical LTC1430 design puts significant demands on
both the input and output capacitors. Under normal steady
load operation, a buck converter like the LTC1430 draws
square waves of current from the input supply at the
switching frequency, with the peak value equal to the
output current and the minimum value near zero. Most of
this current must come from the input bypass capacitor,
since few raw supplies can provide the current slew rate to
feed such a load directly. The resulting RMS current flow
in the input capacitor will heat it up, causing premature
capacitor failure in extreme cases. Maximum RMS current
occurs with 50% PWM duty cycle, giving an RMS current
value equal to IOUT/2. A low ESR input capacitor with an
adequate ripple current rating must be used to ensure
reliable operation. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
(3 months) lifetime; further derating of the input capacitor
ripple current beyond the manufacturer’s specification is
recommended to extend the useful life of the circuit.
The output capacitor in a buck converter sees much less
ripple current under steady-state conditions than the input
capacitor. Peak-to-peak current is equal to that in the
inductor, usually a fraction of the total load current. Output
capacitor duty places a premium not on power dissipation
but on ESR. During an output load transient, the output
capacitor must supply all of the additional load current
demanded by the load until the LTC1430 can adjust the
inductor current to the new value. ESR in the output
capacitor results in a step in the output voltage equal to the
ESR value multiplied by the change in load current. A 5A
load step with a 0.05Ω ESR output capacitor will result in
a 250mV output voltage shift; this is a 7.6% output voltage
shift for a 3.3V supply! Because of the strong relationship
between output capacitor ESR and output load transient
response, the output capacitor is usually chosen for ESR,
not for capacitance value; a capacitor with suitable ESR
will usually have a larger capacitance value than is needed
to control steady-state output ripple.
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1430 applications. OS-CON
electrolytic capacitors from Sanyo give excellent performance and have a very high performance/size ratio for an
electrolytic capacitor. Surface mount applications can use
either electrolytic or dry tantalum capacitors. Tantalum
capacitors must be surge tested and specified for use in
switching power supplies; low cost, generic tantalums are
known to have very short lives followed by explosive
deaths in switching power supply applications. AVX TPS
series surface mount devices are popular tantalum capacitors that work well in LTC1430 applications. A common
way to lower ESR and raise ripple current capability is to
parallel several capacitors. A typical LTC1430 application
might require an input capacitor with a 5A ripple current
capacity and 2% output shift with a 10A output load step,
which requires a 0.007Ω output capacitor ESR. Sanyo
9
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OS-CON part number 10SA220M (220µF/10V) capacitors
feature 2.3A allowable ripple current at 85°C and 0.035Ω
ESR; three in parallel at the input and six at the output will
meet the above requirements.
Input Supply Considerations/Charge Pump
The 16-lead LTC1430 requires four supply voltages to
operate: PVCC for the main power input, PVCC1 and PVCC2
for MOSFET gate drive and a clean, low ripple VCC for the
LTC1430 internal circuitry (Figure 6). In many applications, PVCC and PVCC2 can be tied together and fed from
a common high power supply, provided that the supply
voltage is high enough to fully enhance the gate of external
MOSFET M2. This can be the 5V system supply if a logic
level MOSFET is used for M2. VCC can usually be filtered
with an RC from this same high power supply; the low
quiescent current (typically 350µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100Ω and 4.7µF usually provide adequate filtering for VCC.
PVCC2
VCC
PVCC1
PVCC
G1
M1
L1
INTERNAL
CIRCUITRY
VOUT
G2
+
M2
LTC1430 (16-LEAD)
COUT
LTC1430 • F06
Figure 6. 16-Lead Power Supplies
The 8-lead versions of the LTC1430 have the PVCC2 and
VCC pins tied together inside the package (Figure 7). This
pin, brought out as VCC/PVCC2, has the same low ripple
requirements as the 16-lead part, but must also be able to
supply the gate drive current to M2. This can be obtained
by using a larger RC filter from the PVCC pin; 22Ω and 10µF
work well here. The 10µF capacitor must be VERY close to
the part (preferably right underneath the unit) or output
regulation may suffer.
For both versions of the LTC1430, PVCC1 must be higher
than PVCC by at least one external MOSFET VGS(ON) to fully
enhance the gate of M1. This higher voltage can be
provided with a separate supply (typically 12V) which
should power up after PVCC, or it can be generated with a
simple charge pump (Figure 4). The charge pump consists
of a 1N4148 diode from PVCC to PVCC1 and a 0.1µF
capacitor from PVCC1 to the switching node at the drain of
M2. This circuit provides 2PVCC – VF to PVCC1 while M1 is
ON and PVCC – VF while M1 is OFF where VF is the ON
voltage of the 1N4148 diode. Ringing at the drain of M2
can cause transients above 2PVCC at PVCC1; if PVCC is
higher than 7V, a 12V zener diode should be included from
PVCC1 to PGND to prevent transients from damaging the
circuitry at PVCC2 or the gate of M1.
More complex charge pumps can be constructed with the
16-lead versions of the LTC1430 to provide additional
voltages for use with standard threshold MOSFETs or very
low PVCC voltages. A tripling charge pump (Figure 5) can
provide 2PVCC and 3PVCC voltages. These can be connected to PVCC2 and PVCC1 respectively, allowing standard threshold MOSFETs to be used with 5V at PVCC or 5V
logic level threshold MOSFETs to be used with 3.3V at
PVCC. VCC can be driven from the same potential as PVCC2,
allowing the entire system to run from a single 3.3V
supply. Tripling charge pumps require the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit will tend to
rectify any ringing at the drain of M2 and can provide well
more than 3PVCC at PVCC1; all tripling (or higher multiplying factor) circuits should include a 12V zener clamp diode
DZ to prevent overvoltage at PVCC1.
PVCC1
VCC /PVCC2
PVCC
G1
M1
L1
INTERNAL
CIRCUITRY
VOUT
G2
+
M2
LTC1430 (8-LEAD)
Figure 7. 8-Lead Power Supplies
10
COUT
LTC1430 • F07
LTC1430
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Compensation and Transient Response
The LTC1430 voltage feedback loop is compensated at the
COMP pin; this is the output node of the internal gm error
amplifier. The loop can generally be compensated properly with an RC network from COMP to GND and an
additional small C from COMP to GND (Figure 8). Loop
stability is affected by inductor and output capacitor
values and by other factors. Optimum loop response can
be obtained by using a network analyzer to find the loop
poles and zeros; nearly as effective and a lot easier is to
empirically tweak the RC values until the transient recovery
looks right with an output load step. Table 1 shows
recommended compensation components for 5V to 3.3V
applications based on the inductor and output capacitor
values. The values were calculated using multiple paralleled 330µF AVX TPS series surface mount tantalum
capacitors as the output capacitor.
Table 1. Recommended Compensation Network for 5V to 3.3V
Application Using Multiple 330µF AVX Output Capacitors
L1 (µH)
COUT (µF)
RC (kΩ)
CC (µF)
C1 (pF)
1
990
1.8
0.022
820
1
1980
3.6
0.01
470
1
4950
9.1
0.0047
150
1
9900
18
0.0022
82
2.7
990
3.6
0.01
470
2.7
1980
7.5
0.0047
220
2.7
4950
18
0.0022
82
2.7
9900
39
0.001
39
5.6
990
9.1
0.0047
150
5.6
1980
18
0.0022
82
5.6
4950
47
820pF
33
5.6
9900
91
470pF
15
10
990
18
0.0022
82
10
1980
39
0.001
39
10
4950
91
470pF
15
10
9900
180
220pF
10
Output transient response is set by three major factors: the
time constant of the inductor and the output capacitor, the
more impact on overall transient recovery time than the
third; unless the loop compensation is way off, more
improvement can be had by optimizing the inductor and
the output capacitor than by fiddling with the loop com-
pensation components. In general, a smaller value inductor will improve transient response at the expense of ripple
and inductor core saturation rating. Minimizing output
capacitor ESR will also help optimize output transient
response. See Input and Output Capacitors for more
information.
LTC1430
COMP
RC
CC
GND
C1
SGND
LTC1430 • F08
Figure 8. Compensation Pin Hook-Up
Soft-Start and Current Limit
The 16-lead versions of the LTC1430 include a soft-start
circuit at the SS pin; this circuit is used both for initial startup and during current limit operation. The soft-start and
current limit circuitry is disabled in 8-lead versions. SS
requires an external capacitor to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge the external
capacitor. Soft-start functions by clamping the maximum
voltage that the COMP pin can swing to, thereby controlling the duty cycle (Figure 9). The LTC1430 will begin to
operate at low duty cycle as the SS pin rises to about 2V
below VCC. As SS continues to rise, the duty cycle will
increase until the error amplifier takes over and begins to
regulate the output. When SS reaches 1V below VCC the
LTC1430 will be in full operation. An internal switch shorts
the SS pin to GND during shutdown.
The LTC1430 detects the output current by watching the
voltage at IFB while M1 is ON. The ILIM amplifier compares
this voltage to the voltage at IMAX (Figure 10). In the ON
state, M1 has a known resistance; by calculating backwards, the voltage generated at IFB by the maximum
output current in M1 can be determined. As IFB falls below
IMAX, ILIM will begin to sink current from the soft-start pin,
11
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causing the voltage at SS to fall. As SS falls, it will limit the
output duty cycle, limiting the current at the output.
Eventually the system will reach equilibrium, where the
pull-up current at the SS pin matches the pull-down
current in the ILIM amplifier; the LTC1430 will stay in this
state until the overcurrent condition disappears. At this
time IFB will rise, ILIM will stop sinking current and the
internal pull-up will recharge the soft-start capacitor,
restoring normal operation. Note that the IFB pin requires
an external 1k series resistor to prevent voltage transients
at the drain of M2 from damaging internal structures.
The ILIM amplifier pulls current out of SS in proportion to
the difference between IFB and IMAX. Under mild overload
conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
overloads may not trip the current limit circuit at all.
Longer overload conditions will allow the SS pin to reach
a steady level, and the output will remain at a reduced
voltage until the overload is removed. Serious overloads
will generate a larger overdrive at ILIM, allowing it to pull SS
down more quickly and preventing damage to the output
components.
The ILIM amplifier output is disabled when M1 is OFF to
prevent the low IFB voltage in this condition from activating
the current limit. It is re-enabled a fixed 170ns after M1
turns on; this allows for the IFB node to slew back high and
the ILIM amplifier to settle to the correct value. As the
LTC1430 goes deeper into current limit, it will reach a point
where the M1 on-time needs to be cut to below 170ns to
control the output current. This conflicts with the minimum settling time needed for proper operation of the ILIM
amplifier. At this point, a secondary current limit circuit
begins to reduce the internal oscillator frequency, lengthening the off-time of M1 while the on-time remains constant at 170ns. This further reduces the duty cycle, allowing the LTC1430 to maintain control over the output
current.
Under extreme output overloads or short circuits, the ILIM
amplifier will pull the SS pin more than 2V below VCC in a
single switching cycle, cutting the duty cycle to zero. At
this point all switching stops, the output current decays
through M2 and the LTC1430 runs a partial soft-start cycle
and restarts. If the short is still present the cycle will
repeat. Peak currents can be quite high in this condition,
but the average current is controlled and a properly
designed circuit can withstand short circuits indefinitely
with only moderate heat rise in the output FETs. In addition, the soft-start cycle repeat frequency can drop into the
low kHz range, causing vibrations in the inductor which
provide an audible alarm that something is wrong.
0.1µF
PVCC
RIMAX
LTC1430
COMP
IMAX
IFB
1k
FB
VCC
+
12µA
12µA
SS
–
ILIM
VCC
CSS
12µA
SS
LTC1430 • F09
Figure 9. Soft-Start Clamps COMP Pin
CSS
LTC1430
LTC1430 • F10
Figure 10. Current Limit Operation
12
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Oscillator Frequency
The LTC1430 includes an onboard current controlled
oscillator which will typically free-run at 200kHz. An
internal 20µA current is summed with any current in or out
of the FREQSET pin (pin 11), setting the oscillator frequency to approximately 10kHz/µA. FREQSET is internally
servoed to the LTC1430 reference voltage (1.26V). With
FREQSET floating, the oscillator is biased from the internal
20µA source and runs at 200kHz. Connecting a 50k
resistor from FREQSET to ground will sink an additional
25µA from FREQSET, causing the internal oscillator to run
at approximately 450kHz. Sourcing an external 10µA
current into FREQSET will cut the internal frequency to
100kHz. An internal clamp prevents the oscillator from
running slower than about 50kHz. Tying FREQSET to VCC
will cause it to run at this minimum speed.
Shutdown
The LTC1430 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN
stops all internal switching, pulls COMP and SS to ground
internally and turns M1 and M2 off. In shutdown, the
LTC1430 itself will drop below 1µA quiescent current
typically, although off-state leakage in the external
MOSFETs may cause the total PVCC current to be somewhat higher, especially at elevated temperatures. When
SHDN rises again, the LTC1430 will rerun a soft-start cycle
and resume normal operation. Holding the LTC1430 in
shutdown during PVCC power up removes any PVCC1
sequencing constraints.
LAYOUT CONSIDERATIONS
Grounding
Proper grounding is critical for the LTC1430 to obtain
specified output regulation. Extremely high peak currents
(as high as several amps) can flow between the bypass
capacitors and the PVCC1, PVCC2 and PGND pins. These
currents can generate significant voltage differences between two points that are nominally both “ground.” As a
general rule, GND and PGND should be totally separated
on the layout, and should be brought together at only one
point, right at the LTC1430 GND and PGND pins. This
helps minimize internal ground disturbances in the
LTC1430 by keeping PGND and GND at the same potential,
while preventing excessive current flow from disrupting
the operation of the circuits connected to GND. The PGND
node should be as compact and low impedance as possible, with the negative terminals of the input and output
capacitors, the source of M2, the LTC1430 PGND node,
the output return and the input supply return all clustered
at one point. Figure 11 is a modified schematic showing
the common connections in a proper layout. Note that at
10A current levels or above, current density in the PC
board itself can become a concern; traces carrying high
currents should be as wide as possible.
Output Voltage Sensing
The LTC1430 provides three pins for sensing the output
voltage: SENSE+, SENSE– and FB. SENSE+ and SENSE–
connect to an internal resistor divider which is connected
to FB. To set the output of the LTC1430 to 3.3V, connect
SENSE+ to the output as near to the load as practical and
connect SENSE– to the common GND/PGND point. Note
that SENSE– is not a true differential input sense input; it
is just the bottom of the internal divider string. Connecting
SENSE– to the ground near the load will not improve load
regulation. For any other output voltage, the SENSE+ and
SENSE– pins should be floated and an external resistor
string should be connected to FB (Figure 12). As before,
connect the top resistor (R1) to the output as close to the
load as practical and connect the bottom resistor (R2) to
the common GND/PGND point. In both cases, connecting
the top of the resistor divider (either SENSE+ or R1) close
to the load can significantly improve load regulation by
compensating for any drops in PC traces or hookup wires
between the LTC1430 and the load.
Power Component Hook-Up/Heat Sinking
As current levels rise much above 1A, the power components supporting the LTC1430 start to become physically
large (relative to the LTC1430, at least) and can require
special mounting considerations. Input and output capacitors need to carry high peak currents and must have
low ESR; this mandates that the leads be clipped as short
as possible and PC traces be kept wide and short. The
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power inductor will generally be the most massive single
component on the board; it can require a mechanical holddown in addition to the solder on its leads, especially if it
is a surface mount type.
The power MOSFETs used require some care to ensure
proper operation and reliability. Depending on the current
levels and required efficiency, the MOSFETs chosen may
be as large as TO-220s or as small as SO-8s. High
efficiency circuits may be able to avoid heat sinking the
power devices, especially with TO-220 type MOSFETs. As
an example, a 90% efficient converter working at a steady
3.3V/10A output will dissipate only (33W/90%) • 10% =
3.7W. The power MOSFETs generally account for the
SENSE +
majority of the power lost in the converter; even assuming
that they consume 100% of the power used by the
converter, that’s only 3.7W spread over two or three
devices. A typical SO-8 MOSFET with a RON suitable to
provide 90% efficiency in this design can commonly
dissipate 2W when soldered to an appropriately sized
piece of copper trace on a PC board. Slightly less efficient
or higher output current designs can often get by with
standing a TO-220 MOSFET straight up in an area with
some airflow; such an arrangement can dissipate as much
as 3W without a heat sink. Designs which must work in
high ambient temperatures or which will be routinely
overloaded will generally fare best with a heat sink.
NC
LTC1430
VOUT
R1
FB
R2
SENSE –
NC
LTC1430 • F12
Figure 12. Using External Resistors to Set Output Voltages
5V
100Ω
4.7µF
35V
1µF
+
0.1µF
VCC
PVCC2
PVCC1
GND
+
1N4148
PGND
G1
NC
NC
M1B*
M1A*
LTC1430
0.1µF
2.7µH/15A
IMAX
FREQSET
TOTAL
880µF
(220µF
10V × 4)
IFB
3.3V
+
SENSE
C1
220pF
CC
4700pF
SHDN
G2
COMP
FB
SS
RC
7.5k
GND
CSS
0.01µF
GND
M2*
SENSE –
PGND
TOTAL
1980µF
(330µF
6.3V × 6)
PGND
* MOTOROLA MTD20N03HL
Figure 11. Typical Schematic Showing Layout Considerations
14
+
NC
LTC1430 • F11
LTC1430
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
(
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325 –0.015
+0.889
8.255
–0.381
0.400*
(10.160)
MAX
)
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
0.100
(2.54)
BSC
(0.457 ± 0.076)
N8 1098
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.770*
(19.558)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.100
(2.54)
BSC
0.018 ± 0.003
(0.457 ± 0.076)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
N16 1098
15
LTC1430
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
8
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
7
5
6
0.004 – 0.010
(0.101 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
3
2
4
SO8 1298
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.004 – 0.010
(0.101 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0.386 – 0.394*
(9.804 – 10.008)
16
15
13
14
12
11
10
9
0° – 8° TYP
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
0.150 – 0.157**
(3.810 – 3.988)
0.050
(1.270)
BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
S16 1098
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Switching Regulator
1.3V to 3.5V Programmable Output Using Internal 5-Bit DAC
LTC1873
Dual Synchronous Switching Regulator with 5-Bit Desktop VID
1.3V to 3.5V Programmable Core Output Plus I/O Output
LTC1929
2-Phase, Synchronous High Efficiency Converter
Current Mode Ensures Accurate Current Sensing,
VIN Up to 36V, IOUT Up to 40A
Adds 5-Bit Mobile VID to 0.8V Referenced Switching
Regulators
No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
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Linear Technology Corporation
1430fa LT/TP 0500 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1995