[ /Title (CD74 HC597 , CD74 HCT59 7) /Subject (High Speed CMOS CD74HC597, CD74HCT597 Data sheet acquired from Harris Semiconductor SCHS191 High Speed CMOS Logic 8-Bit Shift Register with Input Storage January 1998 Features Description • Buffered Inputs The Harris CD74HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A “low” on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A “low” master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL is high. • Asynchronous Parallel Load • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) PKG. NO. PACKAGE CD74HC597E -55 to 125 16 Ld PDIP E16.3 CD74HCT597E -55 to 125 16 Ld PDIP E16.3 CD74HC597M -55 to 125 16 Ld SOIC M16.15 CD74HCT597M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC597, CD74HCT597 (PDIP, SOIC) TOP VIEW D1 1 16 VCC D2 2 15 D0 D3 3 14 DS D4 4 13 PL D5 5 12 STCP D6 6 11 SHCP D7 7 10 MR GND 8 9 Q7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 1915.1 CD74HC597, CD74HCT597 Functional Diagram DS D0 14 15 1 D1 2 D2 PARALLEL DATA INPUTS 3 D3 8 F/F STORAGE REG. 5 4 D4 D5 6 D6 7 D7 STCP 8-BIT SHIFT REG. 9 Q7 12 11 SHCP PL 13 10 MR FUNCTION TABLE STCP SHCP PL MR FUNCTION ↑ X X X Data Loaded to Input Flip-Flops ↑ X L H Data Loaded from Inputs to Shift Register No Clock Edge X L H Data Transferred from Input Flip-Flops to Shift Register X X L L Invalid Logic, State of Shift Register Indeterminate when Signals Removed X X H L Shift Register Cleared X ↑ H H Shift Register Clocked Qn = Qn-1, Q0 = DS NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High CP Level 2 CD74HC597, CD74HCT597 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC597, CD74HCT597 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA PARAMETER Quiescent Device Current HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA HCT Input Loading Table INPUT UNIT LOADS DS 0.2 Dn 0.3 PL, MR 1.5 STCP, SHCP 1.5 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 360µA max. at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz HC TYPES SHCP Frequency 4 CD74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 70 - - 90 - - 105 - - ns 4.5 14 - - 18 - - 21 - - ns 6 12 - - 15 - - 18 - - ns 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns 2 50 - - 65 - - 75 - - ns 4.5 10 - - 13 - - 15 - - ns 6 9 - - 11 - - 13 - - ns 2 0 - - 0 - - 0 - - ns 4.5 0 - - 0 - - 0 - - ns 6 0 - - 0 - - 0 - - ns 2 3 - - 3 - - 3 - - ns 4.5 3 - - 3 - - 3 - - ns 6 3 - - 3 - - 3 - - ns 2 3 - - 3 - - 3 - - ns 4.5 3 - - 3 - - 3 - - ns 6 3 - - 3 - - 3 - - ns fMAX 4.5 25 - - 20 - - 16 - - MHz SHCP Pulse Width tW 4.5 20 - - 25 - - 30 - - ns STCP Pulse Width tW 4.5 13 - - 16 - - 20 - - ns MR Pulse Width tW 4.5 18 - - 23 - - 27 - - ns PL Pulse Width tW 4.5 16 - - 20 - - 24 - - ns STCP to SHCP Setup Time tSU 4.5 24 - - 30 - - 36 - - ns SHCP Pulse Width STCP Pulse Width MR Pulse Width PL Pulse Width STCP to SHCP Setup Time DS to SHCP Setup Time Dn to STCP Setup Time STCP to SHCP Setup Time DS to SHCP Hold Time Dn to STCP Hold Time MR to SHCP Removal Time tW tW tW tSU tSU tH tH tREM HCT TYPES SHCP Frequency 5 CD74HC597, CD74HCT597 Prerequisite for Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DS to SHCP Setup Time Dn to STCP Setup Time tH 4.5 10 - - 13 - - 15 - - ns STCP to SHCP Hold Time tH 4.5 0 - - 0 - - 0 - - ns DS to SHCP Hold Time Dn to STCP Hold Time tH 4.5 3 - - 3 - - 3 - - ns MR to SHCP Removal Time tREM 4.5 10 - - 13 - - 15 - - ns Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay STCP to Q7 MR to Q7 Output Transition Time Input Capacitance Power Dissipation Capacitance, (Notes 4, 5) -40oC to 85oC -55oC to 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 175 - 220 - 265 ns SHCP to Q7 PL to Q7 25oC TEST CONDITIONS tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 17 - - - - - ns CL = 50pF 6 - - 34 - 43 - 51 ns CL = 50pF 2 - - 240 - 300 - 360 ns 4.5 - - 48 - 60 - 72 ns CL =15pF 5 - 20 - - - - - ns CL = 50pF 6 - - 41 - 51 - 61 ns CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns CI CL = 50pF - - - 10 - 10 - 10 pF CPD - 5 - 13.5 - - - - - pF CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 4.5 - - 48 72 ns CL = 15pF 5 - 20 - - ns CL = 50pF 4.5 - - 56 CL = 15pF 5 - 23 - HCT Propagation Delay tPLH, tPHL SHCP to Q7 PL to Q7 STCP to Q7 tPLH, tPHL tPLH, tPHL 6 60 - - - 70 - - - 84 ns - ns CD74HC597, CD74HCT597 Switching Specifications Input tr, tf = 6ns PARAMETER MR to Q7 Output Transition Time Input Capacitance Power Dissipation Capacitance, (Notes 4, 5) (Continued) 25oC -40oC to 85oC -55oC to 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 18 - - - - - ns tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns CI CL = 50pF - - - 10 - 10 - 10 pF CPD - 5 - 18.5 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = CPD VCC2 fi + Σ (CL VCC2 fo) where: fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% tfCL = 6ns 2.7V 1.3V 0.3V 0.3V GND 1.3V 1.3V GND tWH tWL tWH tWL I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 CD74HC597, CD74HCT597 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8 CD74HC597, CD74HCT597 Timing Diagram SHIFT CLOCK SHCP SERIAL DATE DS MASTER RESET MR PARALLEL LOAD PL STORAGE CLOCK STCP PARALLEL DATA INPUTS D0 H L L D1 L L L D2 H L L D3 L L L D4 H L H D5 H L H D6 L L L D7 H H H Q7 L L H L H H L H L H L H L L L H L H H RESET SHIFT REGISTER SERIAL SHIFT LOAD FLIP-FLOPS SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER LOAD FLIP-FLOPS 9 SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER SERIAL SHIFT PARALLEL LOAD FLIP-FLOPS AND SHIFT REGISTER IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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