NSC DP83955A Lite repeater interface controller Datasheet

DP83955A/DP83956A LERIC TM
LitE Repeater Interface Controller
General Description
The DP83955/56 LitE Repeater Interface Controller
(LERIC) may be used to implement an IEEE 802.3 multiport
repeater unit. It fully satisfies the IEEE 802.3 repeater specification including the functions defined by the repeater, segment partition and jabber lockup protection state machines.
The LERIC has an on-chip phase-locked-loop (PLL) for
Manchester data decoding, a Manchester encoder, and an
Elasticity Buffer for preamble regeneration.
Each LERIC can connect up to 7 cable segments via its
network interface ports. One port is fully Attachment Unit
Interface (AUI) compatible and is able to connect to an external Medium Attachment Unit (MAU) using the maximum
length of AUI cable. The other 6 ports have integrated
10BASE-T transceivers. These transceiver functions may
be bypassed so that the LERIC may be used with external
transceivers, such as National’s DP8392 coaxial transceiver. In addition, large repeater units may be constructed by
cascading LERICs together over the Inter-LERICTM or InterRICTM bus.
The LERIC is configurable for specific applications. It provides port status information for LED array displays. Additionally, the LERIC has a mP interface to provide individual
port status, configuration, and port enable/disable functions.
The DP83956 has all the features of the DP83955, except
that two of the bidirectional signals on DP83955 are
changed to unidirectional signals on DP83956, and one
more signal is added to DP83956 to accommodate the addition of bus transceivers for cascading a greater number of
LERICs in large repeater applications.
Specifications enclosed describe both the DP83955 and the
DP83956 unless otherwise noted.
For IEEE 802.3 multiport repeater applications which require conformance to the IEEE 802.3 Draft Repeater Management options, the DP83950 Repeater Interface Controller (RICTM ) is recommended especially for highly-managed
hub requirements.
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Compliant with the IEEE 802.3 Repeater Specification
7 network connections (ports) per chip
Selectable on-chip twisted-pair transceivers
Cascadable for large multiple RIC/LERIC hub
applications
Compatible with AUI compliant transceivers
On-chip Elasticity Buffer, Manchester encoder and
decoder
Separation Partition state machines for each port
Provides port status information for LED displays
including: receive, collision, partition, polarity, and link
status
Power-up configuration optionsÐRepeater and Partition
Specifications, Transceiver Interface, Status Display,
Processor Operations
Simple processor interface for repeater management
and port disable
Per port receive squelch level selection
CMOS process for low power dissipation
Single 5V supply
1.0 System Diagram
Simple LERIC Hub
TL/F/11240 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Inter-LERICTM , Inter-RICTM , LERICTM and RICTM are trademarks of National Semiconductor Corporation.
PALÉ is a registered trademark of and used under license from Advanced Micro Devices, Inc.
GALÉ is a registered trademark of Lattice Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/11240
RRD-B30M105/Printed in U. S. A.
DP83955A/DP83956A LERIC LitE Repeater Interface Controller
July 1993
Table of Contents
1.0 SYSTEM DIAGRAMÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1
6.0 PORT BLOCK FUNCTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35
2.0 CONNECTION DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3
6.1 Transceiver Functions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35
6.2 Segment Partition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37
3.0 PIN DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
6.3 Port Status Register FunctionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37
4.0 BLOCK DIAGRAM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
7.0 RIC REGISTER DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
5.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
7.1 LERIC Register Address MapÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
5.1 Overview of LERIC FunctionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
7.2 LERIC Status RegisterÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
5.2 Description of Repeater Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀ18
7.3 Port Status and Configuration RegistersÀÀÀÀÀÀÀÀÀÀ41
5.3 Examples of Packet Repetition Scenarios ÀÀÀÀÀÀÀÀ22
8.0 ABSOLUTE MAXIMUM RATINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ42
5.4 Description of Hardware Connection
for Cascading ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
9.0 DC ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀ42
5.5 Processor and Display Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
10.0 SWITCHING CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43
5.6 Processor and Display Interface Hardware
Connection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31
11.0 AC TIMING TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ51
12.0 PHYSICAL DIMENSIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53
2
2.0 Connection Diagrams
Pin Table for DP83955
(Configured as Port 1 Full AUI, and Ports 2 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
TXO4 a
1
TXO7 a
22
RXM
43
TXO2 a
TXO4Pb
2
TXO7b
23
IRD
44
TXO2Pb
64
65
GND
3
TXO7P a
24
IRC
45
GND
66
VCC
4
RXI7 a
25
STR
46
VCC
67
TXO5Pb
5
RXI7b
26
DFS
47
TXO3Pb
68
TXO5 a
6
GND
27
BUFEN
48
TXO3 a
69
TXO5b
7
VCC
28
ACKO
49
TXO3b
70
71
72
TXO5P a
8
IRE
29
CD1 a
50
TXO3P a
RXI5 a
9
ACTN
30
CD1b
51
RXI3 a
RXI5b
10
ANYXN
31
RX1 a
52
RXI3b
73
GND
11
COLN
32
RX1b
53
GND
74
VCC
12
D7
33
VCC
54
VCC
75
RXI6 a
13
D6
34
GND
55
CLK
76
RXI6b
14
D5
35
TX1 a
56
MLOAD
77
TXO6P a
15
D4
36
TX1b
57
WR
78
TXO6b
16
D3
37
GND
58
RD
79
TXO6 a
17
D2
38
VCC
59
ACKI
80
TXO6Pb
18
D1
39
RXI2 a
60
RXI4 a
81
GND
19
D0
40
RXI2b
61
RXI4b
82
62
TXO4P a
83
63
TXO4b
84
VCC
20
VCC
41
TXO2P a
TXO7Pb
21
GND
42
TXO2b
TL/F/11240 – 2
Top View
3
2.0 Connection Diagrams (Continued)
Pin Table for DP83955
(Configured as Port 1 Full AUI, Ports 2 – 3 AUI, and Ports 4 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
TXO4 a
1
TXO7 a
22
RXM
43
TX2 a
TXO4Pb
2
TXO7b
23
IRD
44
TX2b
64
65
GND
3
TXO7P a
24
IRC
45
GND
66
VCC
4
RXI7 a
25
STR
46
VCC
67
TXO5Pb
5
RXI7b
26
DFS
47
TX3b
68
TXO5 a
6
GND
27
BUFEN
48
TX3 a
69
TXO5b
7
VCC
28
ACKO
49
CD3b
70
71
72
TXO5P a
8
IRE
29
CD1 a
50
CD3 a
RXI5 a
9
ACTN
30
CD1b
51
RX3b
RXI5b
10
ANYXN
31
RX1 a
52
RX3 a
73
GND
11
COLN
32
RX1b
53
GND
74
VCC
12
D7
33
VCC
54
VCC
75
RXI6 a
13
D6
34
GND
55
CLK
76
RXI6b
14
D5
35
TX1 a
56
MLOAD
77
TXO6P a
15
D4
36
TX1b
57
WR
78
TXO6b
16
D3
37
GND
58
RD
79
TXO6 a
17
D2
38
VCC
59
ACKI
80
TXO6Pb
18
D1
39
RX2b
60
RXI4 a
81
GND
19
D0
40
RX2 a
61
RXI4b
82
62
TXO4P a
83
63
TXO4b
84
VCC
20
VCC
41
CD2 a
TXO7Pb
21
GND
42
CD2b
TL/F/11240 – 3
Top View
4
2.0 Connection Diagrams (Continued)
Pin Table for DP83955
(Configured as Port 1 Full AUI, Ports 2 – 5 AUI, and Ports 6 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
TX4 a
1
TXO7 a
22
RXM
43
TX2 a
TX4b
2
TXO7b
23
IRD
44
TX2b
64
65
GND
3
TXO7P a
24
IRC
45
GND
66
VCC
4
RXI7 a
25
STR
46
VCC
67
TX5b
5
RXI7b
26
DFS
47
TX3b
68
TX5 a
6
GND
27
BUFEN
48
TX3 a
69
CD5b
7
VCC
28
ACKO
49
CD3b
70
71
72
CD5 a
8
IRE
29
CD1 a
50
CD3 a
RX5b
9
ACTN
30
CD1b
51
RX3b
RX5 a
10
ANYXN
31
RX1 a
52
RX3 a
73
GND
11
COLN
32
RX1b
53
GND
74
VCC
12
D7
33
VCC
54
VCC
75
RXI6 a
13
D6
34
GND
55
CLK
76
RXI6b
14
D5
35
TX1 a
56
MLOAD
77
TXO6P a
15
D4
36
TX1b
57
WR
78
TXO6b
16
D3
37
GND
58
RD
79
TXO6 a
17
D2
38
VCC
59
ACKI
80
TXO6Pb
18
D1
39
RX2b
60
RX4b
81
GND
19
D0
40
RX2 a
61
RX4 a
82
62
CD4 a
83
63
CD4b
84
VCC
20
VCC
41
CD2 a
TXO7Pb
21
GND
42
CD2b
TL/F/11240 – 4
Top View
5
2.0 Connection Diagrams (Continued)
Pin Table for DP83955
(Configured as Port 1 Full AUI, Ports 2 – 7 AUI)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
TX4 a
1
TX7 a
22
RXM
43
TX2 a
TX4b
2
CD7b
23
IRD
44
TX2b
64
65
GND
3
CD7 a
24
IRC
45
GND
66
VCC
4
RX7b
25
STR
46
VCC
67
TX5b
5
RX7 a
26
DFS
47
TX3b
68
TX5 a
6
GND
27
BUFEN
48
TX3 a
69
CD5b
7
VCC
28
ACKO
49
CD3b
70
71
72
CD5 a
8
IRE
29
CD1 a
50
CD3 a
RX5b
9
ACTN
30
CD1b
51
RX3b
RX5 a
10
ANYXN
31
RX1 a
52
RX3 a
73
GND
11
COLN
32
RX1b
53
GND
74
VCC
12
D7
33
VCC
54
VCC
75
RX6b
13
D6
34
GND
55
CLK
76
RX6 a
14
D5
35
TX1 a
56
MLOAD
77
CD6 a
15
D4
36
TX1b
57
WR
78
CD6b
16
D3
37
GND
58
RD
79
TX6 a
17
D2
38
VCC
59
ACKI
80
TX6b
18
D1
39
RX2b
60
RX4b
81
GND
19
D0
40
RX2 a
61
RX4 a
82
62
CD4 a
83
63
CD4b
84
VCC
20
VCC
41
CD2 a
TX7b
21
GND
42
CD2b
TL/F/11240 – 5
Top View
6
2.0 Connection Diagrams (Continued)
Pin Table for DP83956
(Configured as Port 1 Full AUI, Ports 2 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
GND
1
VCC
21
RXM
41
VCC
61
VCC
NC
2
PKEN
22
IRD
42
RXI2 a
62
CLK
81
82
VCC
3
IRE
23
IRC
43
RXI2b
63
MLOAD
83
RXI6 a
4
ACTNS
24
STR
44
TXO2P a
64
WR
84
RXI6b
5
ACTND
25
DFS
45
TXO2b
65
RD
85
TXO6P a
6
ANYXNS
26
BUFEN
46
TXO2 a
66
ACKI
86
TXO6b
7
ANYXND
27
ACKO
47
TXO2Pb
67
RXI4 a
87
88
TXO6 a
8
COLN
28
CD1 a
48
NC
68
RXI4b
TXO6Pb
9
NC
29
CD1b
49
GND
69
TXO4P a
89
NC
10
NC
30
NC
50
VCC
70
TXO4b
90
GND
11
D7
31
RX1 a
51
TXO3Pb
71
TXO4 a
91
92
VCC
12
D6
32
RX1b
52
TXO3 a
72
TXO4Pb
TXO7Pb
13
D5
33
NC
53
TXO3b
73
GND
93
TXO7 a
14
D4
34
VCC
54
TXO3P a
74
VCC
94
TXO7b
15
D3
35
NC
55
RXI3 a
75
TXO5Pb
95
96
TXO7P a
16
D2
36
GND
56
RXI3b
76
TXO5 a
RXI7 a
17
D1
37
TX1 a
57
GND
77
TXO5b
97
RXI7b
18
D0
38
TX1b
58
NC
78
TXO5P a
98
NC
19
VCC
39
NC
59
NC
79
RXI5 a
99
80
RXI5b
100
GND
20
GND
40
GND
60
NC
Note: DP83956 will change from VLY package to VLJ package approximately Q3, 1993.
TL/F/11240 – 36
Top View
7
2.0 Connection Diagrams (Continued)
Pin Table for DP83956
(Configured as Port 1 Full AUI, Ports 2 – 3, AUI and Ports 4 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
GND
1
VCC
21
RXM
41
VCC
61
VCC
NC
2
PKEN
22
IRD
42
RX2b
62
CLK
81
82
VCC
3
IRE
23
IRC
43
RX2 a
63
MLOAD
83
RXI6 a
4
ACTNS
24
STR
44
CD2 a
64
WR
84
RXI6b
5
ACTND
25
DFS
45
CD2b
65
RD
85
TXO6P a
6
ANYXNS
26
BUFEN
46
TX2 a
66
ACKI
86
TXO6b
7
ANYXND
27
ACKO
47
TX2b
67
RXI4 a
87
88
TXO6 a
8
COLN
28
CD1 a
48
NC
68
RXI4b
TXO6Pb
9
NC
29
CD1b
49
GND
69
TXO4P a
89
NC
10
NC
30
NC
50
VCC
70
TXO4b
90
GND
11
D7
31
RX1 a
51
TX3b
71
TXO4 a
91
92
VCC
12
D6
32
RX1b
52
TX3 a
72
TXO4Pb
TXO7Pb
13
D5
33
NC
53
CD3b
73
GND
93
TXO7 a
14
D4
34
VCC
54
CD3 a
74
VCC
94
TXO7b
15
D3
35
NC
55
RX3b
75
TXO5Pb
95
96
TXO7P a
16
D2
36
GND
56
RX3 a
76
TXO5 a
RXI7 a
17
D1
37
TX1 a
57
GND
77
TXO5b
97
RXI7b
18
D0
38
TX1b
58
NC
78
TXO5P a
98
NC
19
VCC
39
NC
59
NC
79
RXI5 a
99
80
RXI5b
100
GND
20
GND
40
GND
60
NC
Note: DP83956 will change from VLY package to VLJ package approximately Q3, 1993.
TL/F/11240 – 37
Top View
8
2.0 Connection Diagrams (Continued)
Pin Table for DP83956
(Configured as Port 1 Full AUI, Ports 2 – 5, AUI, and Ports 6 – 7 Twisted-Pair)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
GND
1
VCC
21
RXM
41
VCC
61
VCC
NC
2
PKEN
22
IRD
42
RX2b
62
CLK
81
82
VCC
3
IRE
23
IRC
43
RX2 a
63
MLOAD
83
RXI6 a
4
ACTNS
24
STR
44
CD2 a
64
WR
84
RXI6b
5
ACTND
25
DFS
45
CD2b
65
RD
85
TXO6P a
6
ANYXNS
26
BUFEN
46
TX2 a
66
ACKI
86
TXO6b
7
ANYXND
27
ACKO
47
TX2b
67
RX4b
87
88
TXO6 a
8
COLN
28
CD1 a
48
NC
68
RX4 a
TXO6Pb
9
NC
29
CD1b
49
GND
69
CD4 a
89
NC
10
NC
30
NC
50
VCC
70
CD4b
90
GND
11
D7
31
RX1 a
51
TX3b
71
TX4 a
91
92
VCC
12
D6
32
RX1b
52
TX3 a
72
TX4b
TXO7Pb
13
D5
33
NC
53
CD3b
73
GND
93
TXO7 a
14
D4
34
VCC
54
CD3 a
74
VCC
94
TXO7b
15
D3
35
NC
55
RX3 a
75
TX5b
95
96
TXO7P a
16
D2
36
GND
56
RX3b
76
TX5 a
RXI7 a
17
D1
37
TX1 a
57
GND
77
CD5b
97
RXI7b
18
D0
38
TX1b
58
NC
78
CD5 a
98
NC
19
VCC
39
NC
59
NC
79
RX5b
99
80
RX5 a
100
GND
20
GND
40
GND
60
NC
Note: DP83956 will change from VLY package to VLJ package approximately Q3, 1993.
TL/F/11240 – 38
Top View
9
2.0 Connection Diagrams (Continued)
Pin Table for DP83956
(Configured as Port 1 Full AUI, Ports 2 – 7 AUI)
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
GND
1
VCC
21
RXM
41
VCC
61
VCC
NC
2
PKEN
22
IRD
42
RX2b
62
CLK
81
82
VCC
3
IRE
23
IRC
43
RX2 a
63
MLOAD
83
RX6b
4
ACTNS
24
STR
44
CD2 a
64
WR
84
RX6 a
5
ACTND
25
DFS
45
CD2b
65
RD
85
CD6 a
6
ANYXNS
26
BUFEN
46
TX2 a
66
ACKI
86
CD6b
7
ANYXND
27
ACKO
47
TX2b
67
RX4b
87
88
TX6 a
8
COLN
28
CD1 a
48
NC
68
RX4 a
TX6b
9
NC
29
CD1b
49
GND
69
CD4 a
89
NC
10
NC
30
NC
50
VCC
70
CD4b
90
GND
11
D7
31
RX1 a
51
TX3b
71
TX4 a
91
92
VCC
12
D6
32
RX1b
52
TX3 a
72
TX4b
TX7b
13
D5
33
NC
53
CD3b
73
GND
93
TX7 a
14
D4
34
VCC
54
CD3 a
74
VCC
94
CD7b
15
D3
35
NC
55
RX3 a
75
TX5b
95
96
CD7 a
16
D2
36
GND
56
RX3b
76
TX5 a
RX7b
17
D1
37
TX1 a
57
GND
77
CD5b
97
RX7 a
18
D0
38
TX1b
58
NC
78
CD5 a
98
NC
19
VCC
39
NC
59
NC
79
RX5 a
99
80
RX5b
100
GND
20
GND
40
GND
60
NC
Note: DP83956 will change from VLY package to VLJ package approximately Q3, 1993.
TL/F/11240 – 39
Top View
10
3.0 Pin Description
Pin Name
Driver
Type
I/O
Description
NETWORK INTERFACE PINS (On-Chip Transceiver Mode)
RXI2b to RXI7b
TP
RXI2 a to RXI7 a
I
Twisted-Pair Receive Input Negative
TP
I
Twisted-Pair Receive Input Positive
TXOP2b to TXOP7b
TT
O
Twisted-Pair Pre-Emphasis Transmit Output Negative
TXO2b to TXO7b
TT
O
Twisted-Pair Transmit Output Negative
TXO2 a to TXO7 a
TT
O
Twisted-Pair Transmit Output Positive
TXOP2 a to TXOP7 a
TT
O
Twisted-Pair Pre-Emphasis Transmit Output Positive
CD1 a
AL
I
AUI Collision Detect Input Positive
CD1b
AL
I
AUI Collision Detect Input Negative
RX1 a
AL
I
AUI Receive Input Positive
RX1b
AL
I
AUI Receive Input Negative
TX1 a
AD
O
AUI Transmit Output Positive
TX1b
AD
O
AUI Transmit Output Negative
NETWORK INTERFACE PINS (External Transceiver Mode AUI Signal Level Compatibility Selected)
TX2 a to TX7 a
AL
O
Transmit Output Positive
TX2b to TX7b
AL
O
Transmit Output Negative
CD2 a to CD7 a
AL
I
Collision Input Positive
CD2b to CD7b
AL
I
Collision Input Negative
RX2 a to RX7 a
AL
I
Receive Input Positive
RX2b to RX7b
AL
I
Receive Input Negative
CD1 a
AL
I
AUI Collision Detect Input Positive
CD1b
AL
I
AUI Collision Detect Input Negative
RX1 a
AL
I
AUI Receive Input Positive
RX1b
AL
I
AUI Receive Input Negative
TX1 a
AD
O
AUI Transmit Output Positive
TX1b
AD
O
AUI Transmit Output Negative
Note: AD e AUI level and Drive compatible
TP e Twisted-Pair interface compatible
AL e AUI Level compatible
TT e TTL compatible
I e Input
O e Output
11
3.0 Pin Description (Continued)
Pin
Name
Driver
Type
I/O
Description
PROCESSOR BUS PINS
STR
C
O
D(7:0)
TT
B, Z
Display Update STRobe: This signal controls the latching of display data for network ports into the off
chip display latches.
During processor access cycles (read or write is asserted) this signal is inactive (high).
Data Bus:
Display Update Cycles: These pins become outputs providing display data and port address
information.
Processor Access Cycles: Address input D(7:4) and Data input or output D(3:0) is performed via these
pins. The read, write and reset inputs control the direction of the signals.
Note: The data pins remain in their display update function, (i.e., asserted as outputs) unless either the read or write
strobe is asserted.
DFS
C
O
Display Frozen Strobe: The assertion of the DFS signal, active high, at the end of the transmission of
each packet indicates that the status of that packet is frozen on the LEDs until the beginning of the next
received packet or for a maximum of 30 ms.
BUFEN
C
O
BUFfer ENable: This output controls the TRI-STATEÉ operation of the bus transceiver which provides
the interface between the LERIC’s data pins and the processor’s data bus.
Note: The buffer enable output indicates the function of the data pins. When it is high they are performing display update
cycles, when it is low a processor access or MLOAD cycle is occurring.
WR
TT
I
WRite Strobe: Strobe from the CPU used to write an internal register defined by the D(7:4) inputs.
RD
TT
I
ReaD Strobe: Strobe from the CPU used to read an internal register defined by the D(7:4) inputs.
MLOAD
TT
I
Device MLOAD and Reset: When this input is low all of the RIC’s state machines and network ports are
reset and held inactive. On the rising edge of MLOAD the logic levels present on the D(7:0) pins are
latched into the LERIC’s configuration registers. The rising edge of MLOAD also signals the beginning
of the display test operation.
INTER-LERIC BUS PINS
ACKI
TT
I
ACKO
TT
O
IRD
TT
B, Z
ACKnowledge Input: Input to the network ports’ arbitration chain.
ACKnowledge Output: Output from the network ports’ arbitration chain.
Inter-LERIC Data: When asserted as an output this signal provides a serial data stream in NRZ format.
The signal is asserted by a LERIC when it is receiving data from one of its network segments. The
default condition of this signal is to be an input. In this state it may be driven by other devices on the
Inter-LERIC bus.
12
3.0 Pin Description (Continued)
Pin
Name
Driver
Type
I/O
Description
INTER-LERIC BUS PINS (Continued)
IRE
TT
B, Z
Inter-LERIC Enable: When asserted as an output this signal provides an activity framing enable for the
serial data stream. The signal is asserted by a LERIC when it is receiving data from one of its network
segments. The default condition of this signal is to be an input. In this state it may be driven by other
devices on the Inter-LERIC bus.
IRC
TT
B, Z
Inter-LERIC Clock: When asserted as an output this signal provides a clock signal for the serial data
stream. Data (IRD) is changed on the falling edge of the clock. The signal is asserted by a LERIC when it
is receiving data from one of its network segments. The default condition of this signal is to be an input.
When an input, IRD is sampled on the rising edge of the clock. In this state it may be driven by other
devices on the Inter-LERIC bus.
COLN
TT
B, Z
COLlision on Port N: This denotes that a collision is occurring on the port receiving the data packet (Port
N). The default condition of this signal is to be an input. In this state it may be driven by other devices on
the Inter-LERIC bus.
CLK
TT
I
20 MHz Clock Input: This input is used to generate the LERIC’s timing reference for the state machines,
and phase lock loop decoder. The 20 MHz clock should have a 0.01% frequency tolerance and 40% –
60% duty cycle or better (i.e. 50/50 duty cycle).
POWER AND GROUND PINS
VCC
Positive Supply
GND
Negative Supply
EXTERNAL DECODER PINS
RXM
TT
O
Receive Data Manchester Format: This output makes the data, in Manchester format, received by port
N available for test purposes. If not used for testing, this pin should be left open.
Note: TT e TTL compatible
B e Bi-directional
C e CMOS compatible
OD e Open Drain
I e Input
O e Output
Z e TRI-STATE
13
3.0 Pin Description (Continued)
Pin Description for DP83955
Pin
No.
Pin
Name
Driver
Type
I/O
Description
30
ACTN
OD
B
ACTivity on Port N: This is a bidirectional signal. The LERIC asserts this signal when data or
collision information is received from one of its network segments.
The LERIC senses this signal when this LERIC or another LERIC in a multi-LERIC system is
receiving data or collision information.
31
ANYXN
OD
B
Activity on ANY Port EXcluding Port N: This is a bidirectional signal. The LERIC asserts this signal
when a transmit collision is experienced or multiple ports have active collisions on their network
segments.
The LERIC senses this signal when this LERIC or other LERICs in a multi-LERIC system are
experiencing transmit collisions or multiple ports have active collisions on their network segments.
B e Bi-directional
Pin Description for DP83956
Pin
No.
Pin
Name
Driver
Type
I/O
25
ACTND
OD
O
ACTivity on Port N Drive: The LERIC asserts this signal when data or collision information is
received from one of its network segments.
24
ACTNS
TT
I
ACTivity on Port N Sense: The LERIC senses this signal when this LERIC or another LERIC in a
multi-LERIC system is receiving data or collision information.
27
ANYXND
OD
O
Activity on ANY Port EXcluding Port N Drive: The LERIC asserts this signal when a transmit
collision is experienced or multiple ports have active collisions on their network segments.
26
ANYXNS
TT
I
Activity on ANY Port EXcluding Port N Sense: The LERIC senses this signal when this LERIC or
other LERICs in a multi-LERIC system are experiencing transmit collisions or multiple ports have
active collisions on their network segments.
22
PKEN
C
O
PacKet ENable: This signal acts as an active high enable for an external bus transceiver (if
required) for the IRE, IRC, IRD, and COLN signals. When high, the bus transceiver should be
transmitting on to the bus, i.e., this LERIC is driving the IRD, IRE, IRC, and COLN bus lines.
When low, the bus transceiver should receive from the bus.
Description
TT e TTL compatible, C e CMOS compatible, OD e Open Drain, I e Input, O e Output
14
FIGURE 4-1a. LERIC Block Diagram for DP83955
4.0.1 DP83955 BLOCK DIAGRAM
TL/F/11240 – 6
4.0 Block Diagram
15
FIGURE 4-1b. LERIC Block Diagram for DP83956
4.0.2 DP83956 BLOCK DIAGRAM
TL/F/11240 – 40
4.0 Block Diagram (Continued)
16
5.0 Functional Description
transmitted. The transmit data may be either the received
packet’s data field or a preamble/jam pattern consisting of
a 1010 . . . bit pattern.
The IEEE 802.3 repeater specification details a number of
functions a repeater system must perform. These requirements allied with a need for the implementation to be multiport strongly favors the choice of a modular design style. In
such a design, functionality is split between those tasks
common to all data channels and those exclusive to each
individual channel. The LERIC, much like the DP83950 RIC,
follows this approach. Certain functional blocks are replicated for each network attachment (also known as a repeater
port), and others are shared. The following section briefly
describes the functional blocks in the LERIC.
Associated with the main state machine are a series of timers. These ensure various IEEE specification times (referred
to as the TW1 to TW6 times) are fulfilled.
A repeater unit is required to meet the same signal jitter
performance as any receiving node attached to a network
segment. Consequently, a phase locked loop Manchester
decoder is required so that the packet may be decoded, and
the jitter accumulated over the receiving segment eliminated. The decode logic outputs data in NRZ format with an
associated clock and enable. In this form the packet is in a
convenient format for transfer to other devices, such as network controllers and other LERICs, via the Inter-LERIC bus
(described later). The data may then be re-encoded into
Manchester data and transmitted.
Reception and transmission via physical layer transceiver
units causes a loss of bits in the preamble field of a data
packet. The repeater specification requires this loss to be
compensated for. To accomplish this an elasticity buffer is
employed to temporarily store bits in the data field of the
packet.
The sequence of operation is as follows. Soon after the
network segment receiving the data packet has been identified, the LERIC begins to transmit the packet preamble pattern (1010 . . . ) onto the other network segments. While the
preamble is being transmitted the Elasticity Buffer monitors
the decoded received clock and data signals (this is done
via the Inter-LERIC/Inter-RIC bus as described later). When
the start of frame delimiter ‘‘SFD’’ is detected the received
data stream is written into the elasticity buffer. Removal of
data from the buffer for retransmission is not allowed until a
valid length preamble pattern has been transmitted.
5.1 OVERVIEW OF LERIC FUNCTIONS
Segment Specific Block: Network Port
As shown in the Block Diagram, the segment specific blocks
consist of:
1. One or more physical layer interfaces.
2. A logic block required for performing repeater operations
upon that particular segment. This is known as the ‘‘port’’
logic since it is the access ‘‘port’’ the segment has to the
rest of the network.
This function is repeated 7 times in the LERIC (one for each
port) and is shown on the right side of the Block Diagram,
Figure 4-1 .
The physical layer interfaces provided depends upon the
port under examination. Port 1 has an AUI compliant interface for use with AUI compatible transceiver boxes and cable. Ports 2 to 7 may be configured for use with one of two
interfaces: twisted pair or an external transceiver. The former utilizes the LERIC’s on-chip 10BASE-T transceivers,
the latter allows connection to external transceivers. When
using the external transceiver mode the interface is AUI
compatible. Although AUI compatible transceivers are supported the interface is not designed for use with an interface
cable, thus the transceivers are necessarily internal to the
repeater equipment.
Inside the port logic there are 3 distinct functions:
1. The port state machine (PSM) is required to perform data
and collision repetition as described by the repeater
specification, for example, it determines whether this
port should be receiving from or transmitting to its network segment.
2. The port partition logic implements the segment partitioning algorithm. This algorithm is defined by the IEEE
specification and is used to protect the network from
malfunctioning segments.
3. The port status register reflects the current status of the
port. It may be accessed by a system processor to obtain
this status or to perform certain port configuration operations, such as port disable and squelch level selection.
Inter-LERIC/Inter-RIC Bus Interface
The LERIC can be cascaded either to other LERICs or RICs
to facilitate the design of large multiport repeaters. The split
of functions already described allows data packets and collision status to be transferred between multiple LERICs, and
at the same time the multiple LERICs still behave as a single logical repeater. Since all LERICs in a repeater system
are identical and capable of performing any of the repetition
operations, the failure of one LERIC will not cause the failure of the entire system. This is an important issue in large
multiport repeaters.
DP83955’s communicate via a specialized interface known
as the Inter-LERIC bus. DP83956s can communicate with
other DP83956s and/or DP83950s via the Inter-RIC bus.
These allow the data packets to be transferred from the
receiving LERIC to the other LERICs in the system. These
LERICs then transmit the data stream to their segments.
Just as important as data transfer is the notification of collisions occurring across the network. The Inter-LERIC/InterRIC bus has a set of status lines capable of conveying collision information between LERICs to ensure their main state
machines operate in the appropriate manner.
Shared Functional Blocks: Repeater Core Logic
The shared functional blocks consist of the Repeater Main
Status Machine (MSM) and Timers, a 32-bit Elasticity Buffer,
PLL Decoder, and Receive and Transmit Multiplexers.
These blocks perform the majority of the operations needed
to fulfill the requirements of the IEEE repeater specification.
When a packet is received by a port, it is sent via the Receive Multiplexer to the PLL Decoder. Notification of the
data and collision status is sent to the main state machine
via the receive multiplexer and collision activity status signals. This enables the main state machine to determine the
source of the data to be repeated and the type of data to be
LED Interface
Repeater systems usually possess optical displays indicating network activity and the status of specific repeater operations. The LERIC’s display update block provides the system designer with a wide variety of indicators. The display
17
5.0 Functional Description (Continued)
updates are completely autonomous and merely require SSI
logic devices to drive the display devices, usually made up
of light emitting diodes, LEDs. The status display is very
flexible, allowing the user to choose those indicators appropriate for the specification of the equipment. The Display
Frozen Strobe (DFS) may be used to latch the various indicators which are frozen at the end of the activity. The LED
display will be frozen for 30 ms after the end of the activity,
or until a new activity has started, whichever is shorter. Note
that the complete LED display cycle for all the ports takes
approximately 1.6 ms.
Processor Interface
The LERIC’s processor interface allows connection to a
system processor (or a simple read/write logic interface).
Data transfer occurs via a 4-bit bidirectional data bus, and 4bit address bus. Display update cycles and processor accesses occur utilizing the same bus. An on-chip arbiter in
the processor/display block schedules and controls the accesses and ensures the correct information is written into
the display latches. During the display update cycles the
LERIC behaves as a master of its bus. This is the default
state of the bus. Consequently, a TRI-STATE buffer must be
placed between the LERIC and the system processor’s data
bus. This ensures bus contention is avoided during simultaneous display update cycles and processor accesses of
other devices on the system bus. When the processor accesses a LERIC register, the LERIC enables the data buffer
and selects the operation, either input to or output from the
data pins.
TL/F/11240 – 7
FIGURE 5-1. Inter-LERIC/Inter-RIC Bus State Diagram
The LERIC contains two types of interacting state machines. These are:
1. Port State Machines (PSMs). Every network attachment
has its own PSM.
2. Main State Machine (MSM). This state machine controls
the shared functional blocks as shown in the block diagram Figure 4-1 .
Repeater Port and Main State Machines
These two state machines are described in the following
sections. Reference is made to expressions used in the
IEEE 802.3 Repeater specification. For the precise definition of these terms please refer to the IEEE specifications.
To avoid confusion with the LERIC’s implementation, where
references are made to repeater states or terms as described in the IEEE specification, these items are written in
italics . The IEEE state diagram is shown in Figure 5-2 , the
Inter-LERIC/Inter-RIC bus state diagram is shown in Figure
5-1 .
5.2 DESCRIPTION OF REPEATER OPERATIONS
In order to implement a multi-chip repeater system which
behaves as though it were a single logical repeater, special
consideration must be paid to the data path used in packet
repetition. For example, where in the path are specific operations such as Manchester decoding and elasticity buffering
performed. Also the system’s state machines which utilize
available network activity signals, must be able to accommodate the various packet repetition and collision scenarios
detailed in the IEEE 802.3 repeater specification.
18
5.0 Functional Description (Continued)
TL/F/11240 – 8
FIGURE 5-2. IEEE Repeater Main State Diagram
19
5.0 Functional Description (Continued)
Port State Machine (PSM)
Inter-LERIC Bus Operation
There are two primary functions for the PSM as follows:
Overview
The Inter-LERIC Bus, like the Inter-RIC Bus, consists of
eight signals. These signals implement a protocol which
may be used to connect multiple LERICs together. In this
configuration, the logical function of a single repeater is
maintained. The resulting multi-LERIC system is compliant
to the IEEE 802.3 Repeater Specification and may connect
several hundred network segments. An example of a multiLERIC system is shown in Figure 5-3 .
The Inter-LERIC Bus connects multiple LERICs to realize
the following operations:
1. Control the transmission of repeated data and jam signals over the attached segment.
2. Decide whether a port will be the source of data or collision information which will be repeated over the network.
This repeater port is known as PORT N . An arbitration
process is required to enable the repeater to transition
from the IDLE state to the SEND PREAMBLE PATTERN
or RECEIVE COLLISION states, see Figure 5-2 . This process is used to locate the port which will be PORT N for
that particular packet. The data received from this port is
directed to the PLL decoder and transmitted over the
Inter-LERIC bus. If the repeater enters the TRANSMIT
COLLISION state a further arbitration operation is performed to determine which port is PORT M . PORT M is
differentiated from the repeater’s other ports if the repeater enters the ONE PORT LEFT state. In this state
PORT M does not transmit to its segment; where as all
other ports are still required to transmit to their segments.
Port N Identification (which port the repeater receives
data from)
Port M Identification (which port is the last one experiencing a collision)
Data Transfer
RECEIVE COLLISION identification
TRANSMIT COLLISION identification
DISABLE OUTPUT (jabber protection)
The following tables briefly describe the operation of each
bus signal, the conditions required for a LERIC to assert a
signal and which LERICs (in a multi-LERIC system) would
monitor a signal:
Main State Machine (MSM)
The MSM controls the operation of the shared functional
blocks in each LERIC as shown in the block diagram, Figure
4-1 , and it performs the majority of the data and collision
propagation operations as defined by the IEEE specification, these include those shown in Table 5-1.
The interaction of the main and port state machines is visible, in part, by observing the Inter-LERIC bus.
TABLE 5-1. Main State Machine Operations
Function
Preamble
Regeneration
Action
Restore the length of the preamble
pattern to the defined size.
Fragment
Extension
Extend received data or collision
fragments to meet the minimum
fragment length of 96 bits.
Elasticity
Buffer
Control
A portion of the received packet may
require storage in an Elasticity Buffer to
accommodate preamble regeneration.
Jam/
Preamble
Pattern
Generation
In cases of receive or transmit collisions
a LERIC is required to transmit a jam
pattern (1010 . . . ).
TL/F/11240 – 9
*Note 1: This input is tied at a logic high state.
Note: This pattern is the same as that used for
preamble regeneration.
Transmit
Collision
Enforcement
Once the TRANSMIT COLLISION state
is entered a repeater is required to stay
in this state for at least 96 network bit
times.
Data
Encoding
Control
NRZ format data from the elasticity
buffer must be encoded into Manchester
format data prior to retransmission.
Tw1
Enforcement
Enforce the Transmit Recovery Time
specification.
Tw2
Enforcement
Enforce Carrier Recovery Time
specification on all ports with active
collisions.
FIGURE 5-3. LERIC System Topology
20
5.0 Functional Description (Continued)
COLN
ACKI
Function
Input signal to the PSM arbitration
chain. This chain is employed to
identify PORT N and PORT M .
Note: A LERIC which contains PORT N or
PORT M may be identified by its
ACKO signal being low when its ACKI
input is high.
Conditions
required for a
LERIC to drive
this signal
Not Applicable
LERIC
Receiving the
Signal
This is dependent upon the method
used to cascade LERICs, described in
Section 5.3.
Output signal from the PSM arbitration
chain.
Conditions
required for a
LERIC to drive
this signal
This is dependent upon the method
used to cascade LERICs, described in
Section 5.3.
LERIC
Receiving the
Signal
Not Applicable
Conditions
required for a
LERIC to drive
this signal
LERIC
Receiving the
Signal
Conditions
required for a
LERIC to drive
this signal
LERIC
Receiving the
Signal
A LERIC must contain PORT N
or PORT M .
LERIC
Receiving the
Signal
The Signal is monitored by all other
LERICs in the repeater system.
This signal acts as an activity framing
signal for the IRC and IRD signals.
Conditions
required for a
LERIC to drive
this signal
A LERIC must contain PORT N .
LERIC
Receiving the
Signal
The Signal is monitored by all other
LERICs in the repeater system.
Function
Decoded serial data, in NRZ format,
received from the network segment
attached to PORT N .
IRD
This signal denotes there is activity on
PORT N or PORT M .
A LERIC must contain PORT N
or PORT M .
Note: Although this signal normally has only
one source asserting the signal active
it is used in a wired-OR configuration.
Conditions
required for a
LERIC to drive
this signal
A LERIC must contain PORT N .
LERIC
Receiving the
Signal
The signal is monitored by all other
LERICs in the repeater system.
The signal is monitored by all LERICs
in the repeater system.
IRC
Function
ANYXN
Function
Conditions
required for a
LERIC to drive
this signal
Function
ACTN
Function
Denotes PORT N or PORT M is
experiencing a collision.
IRE
ACKO
Function
Function
This signal denotes that a repeater
port that is not Port N or Port M is
experiencing a collision.
Any LERIC which satisifies the above
condition.
Note: This bus line is used in a wired-OR
configuration.
The signal is monitored by all LERICs
in the repeater system.
21
Clock signal associated with IRD and
IRE.
Conditions
required for a
LERIC to drive
this signal
A LERIC must contain PORT N .
LERIC
Receiving the
Signal
The signal is monitored by all other
LERICs in the repeater system.
5.0 Functional Description (Continued)
The Inter-LERIC bus allows multi-LERIC operations to be
performed in exactly the same manner as if there is only a
single LERIC in the system. The simplest way to describe
the operation of Inter-LERIC bus is to see how it is used in a
number of common packet repetition scenarios. Throughout
this description the LERICs are presumed to be operating in
external transceiver mode. This is advantageous for the explanation since the receive, transmit and collision signals
from each network segment are observable. In internal
transceiver mode this is not the case, since the collision
signal for the non-AUI ports is derived by the transceivers
inside the LERIC.
Methods of LERIC Cascading
In order to build multi-LERIC repeaters, PORT N and PORT
M identification must be performed across all the LERICs in
the system. Inside each LERIC the PSMs are arranged in a
logical arbitration chain where Port 1 is the highest and Port
7 the lowest.
The top of the chain, the input to Port 1 is accessible to the
user via the LERIC’s ACKI input pin. The output from the
bottom of the chain becomes the ACKO output pin. In a
single LERIC system PORT N is defined as the highest port
in the arbitration chain with receive or collision activity.
PORT N identification is performed when the repeater is in
the IDLE state. PORT M is defined as the highest port in the
chain with a collision when the repeater leaves the TRANSMIT COLLISION state. In order for the arbitration chain to
function, all that needs to be done is to tie the ACKI signal
to a logic high state. In multi-LERIC systems there are
two methods to propagate the arbitration chain between
LERICs:
The first and most straightforward way is to extend the arbitration chain by daisy-chaining the ACKI –ACKO signals between LERICs. In this approach one LERIC is placed at the
top of the chain (its ACKI input is tied high), then the ACKO
signal from this LERIC is sent to the ACKI input of the next
LERIC and so on. This arrangement is simple to implement
but it places some topological restrictions upon the repeater
system. In particular, when the repeater is constructed using
a backplane with removable printed circuit boards containing the LERICs, if one of the boards is removed then the
ACKI – ACKO chain will be broken and the repeater will not
operate correctly.
The second method of PORT N or M identification avoids
this problem. This second technique relies on an external
parallel arbiter which monitors all of the LERICs’ ACKO signals and responds to the LERIC with the highest priority. In
this scheme each LERIC is assigned with a priority level.
One method of doing this is to assign a priority number
which reflects the position of a LERIC board on the repeater
backplane (i.e., its slot number). When a LERIC experiences
receive activity and the repeater system is in the IDLE state,
the LERIC board will assert ACKO. External arbitration logic
drives the identification number onto an arbitration bus and
the LERIC containing PORT N will be identified. An identical
procedure is used in the TRANSMIT COLLISION state to
identify PORT M . This parallel means of arbitration is not
subject to the problems caused by missing boards (i.e.,
empty slots in the backplane). The logic associated with
asserting this arbitration vector in the various packet repetition scenarios could be implemented in PALÉ or GALÉ type
devices.
To perform PORT N or M arbitration, both of the above
methods employ the same signals: ACKI, ACKO, and
ACTN.
5.3 EXAMPLES OF PACKET REPETITION SCENARIOS
Data Repetition
The simplest packet operation performed over the InterLERIC Bus is data repetition. In this operation a data packet
is received at one port and transmitted to all other segments.
The first task to be performed is PORT N identification. This
is an arbitration process performed by the Port State Machines in the system. In situations where two or more ports
simultaneously receive packets the Inter-LERIC bus operates by choosing one of the active ports and forcing the
others to transmit data. This is done to faithfully follow the
IEEE specification’s allowed exit paths from the IDLE state
(i.e., to the SEND PREAMBLE PATTERN or RECEIVE COLLISION states).
The packet begins with a preamble pattern derived from the
LERIC’s on chip jam/preamble generator. The data received at PORT N is directed through the receive multiplexer to the PLL decoder. Once phase lock has been achieved,
the decoded data, in NRZ format, with its associated clock
and enable signals are asserted onto the IRD, IRE and IRC
Inter-LERIC bus lines. This serial data stream is received
from the bus by all LERICs in the repeater and directed to
their Elasticity Buffers. Logic circuits monitor the data
stream and look for the Start of Frame Delimiter (SFD).
When this has been detected data is loaded into the elasticity buffer for later transmission. This will occur when sufficient preamble has been transmitted and certain internal
state machine operations have been fulfilled.
Figure 5-3 shows two LERICs, A and B, daisy-chained together with LERIC A positioned at the top of the chain. A
packet is received at port B1 of LERIC B and is then repeated by the other ports in the system. Figure 5-4 shows the
functional timing diagram for this packet repetition represented by the signals shown in Figure 5-3. In this example
only two ports in the system are shown, obviously the other
ports also repeat the packet. It also indicates the operation
of the LERICs’ state machines in so far as can be seen by
observing the Inter-LERIC bus. For reference, the repeater’s state transitions are shown in terms of the states defined by the IEEE specification. The location (i.e., which port
it is) of PORT N is also shown. The following section
describes the repeater and Inter-LERIC bus transitions
shown in Figure 5-4 .
22
5.0 Functional Description (Continued)
TL/F/11240 – 10
*Note 1: The activity shown on RXA1 represents the transmitted signal on TXA1 after being looped back by the attached transceiver.
FIGURE 5-4. Data Repetition
23
5.0 Functional Description (Continued)
moves to the RECEIVE COLLISION state when the LERICs
begin to transmit the jam pattern. The repeater remains in
this state until both the following conditions have been fulfilled:
1. At least 96 bits have been transmitted onto the network,
2. The activity has ended.
Under close examination the repeater specification reveals
that the actual end of activity has its own permutations of
conditions:
1. Collision and receive data signals may end simultaneously,
2. Receive data may appear to end before collision signals,
3. Receive data may continue for some time after the end
of the collision signal.
Network segments using coaxial media may experience
spurious gaps in segment activity when the collision signal
goes inactive. This arises from the inter-action between the
receive and collision signal squelch circuits, implemented in
coaxial transceivers, and the properties of the coaxial cable
itself. The repeater specification avoids propagation of
these activity gaps by extending collision activity by the Tw2
wait time. Jam pattern transmission must be sustained
throughout this period. After this, the repeater will move to
the WAIT state unless there is a data signal being received
by PORT N .
The functional timing diagram, Figure 5-5, shows the operation of a repeater system during a receive collision. The
system configuration is the same as earlier described and is
shown in Figure 5-3 .
The LERICs perform the same PORT N arbitration and data
repetition operations as previously described. The system is
notified of the receive collision on port B1 by the COLN bus
signal going active. This is the signal which informs the main
state machines to output the jam pattern rather than the
data held in the elasticity buffers. Once a collision has occurred the IRC, IRD and IRE bus signals may become undefined. When the collision has ended and the Tw2 operation
performed, the repeater moves to the WAIT state.
The repeater is stimulated into activity by the data signal
received by port B1. The LERICs in the system are alerted
to forthcoming repeater operation by the falling edges on
the ACKI – ACKO daisy chain and the ACTN bus signal. Following a defined start up delay the repeater moves to the
SEND PREAMBLE state. The LERIC system utilizes the
start up delay to perform port arbitration. When packet
transmission begins the LERIC system enters the REPEAT
state. The expected, for normal packet repetition, sequence
of repeater states, SEND PREAMBLE , SEND SFD and
SEND DATA is followed but is not visible upon the InterLERIC bus. They are merged together into a single REPEAT
state. This is also true for the WAIT and IDLE states, they
appear as a combined Inter-LERIC bus IDLE state.
Once a repeat operation has begun (i.e., the repeater
leaves the IDLE state) it is required to transmit at least
96 bits of data or jam/preamble onto its network segments.
If the duration of the received signal from PORT N is smaller
than 96 bits, the repeater transitions to the RECEIVE COLLISION state (described later). This behavior is known as
fragment extension.
After the packet data has been repeated, including the emptying of the LERICs’ elasticity buffers, the LERIC performs
the Tw1 transmit recovery operation. This is performed during the WAIT state shown in the repeater state diagram.
Receive Collisions
A receive collision is a collision which occurs on the network
segment attached to PORT N (i.e., the collision is ‘‘received’’ in a similar manner as a data packet is received and
then repeated to the other network segments). Not surprisingly, receive collision propagation follows a similar sequence of operations as is found with data repetition:
An arbitration process is performed to find PORT N and a
preamble/jam pattern is transmitted by the repeater’s other
ports. When PORT N detects a collision on its segment the
COLN Inter-LERIC bus signal is asserted. This forces all the
LERICs in the system to transmit a preamble/jam pattern to
their segments. This is important since they may be already
transmitting data from their elasticity buffers. The repeater
24
5.0 Functional Description (Continued)
TL/F/11240 – 11
*Note 1: SEND PREAMBLE, SEND SFD, SEND DATA
FIGURE 5-5. Receive Collision
25
5.0 Functional Description (Continued)
reception by port A1. Port B1 experiences a collision, since
it is not PORT N it asserts ANYXN. This alerts the main
state machines in the system to switch from data to jam
pattern transmission.
Port A1 is also monitoring the ANYXN bus line. Its assertion
forces A1 to relinquish its PORT N status, start transmitting,
stop asserting ACTN and release its hold on the PSM arbitration signals (ACKO A and ACKI B). The first bit it transmits will be a Manchester encoded ‘‘1’’ in the jam pattern.
Since port B1 is the only port with a collision, it attains
PORT M status and stops asserting ANYXN. It does however assert ACTN, and exert its presence upon the PSM arbitration chain (forces ACKO B low). The MSMs ensure that
ANYXN stays active and thus forces all of the ports, including PORT M , to transmit to their segments.
After some time port A1 experiences a collision. This arises
from the presence of the packet being received from port
A1’s segment plus the jam signal the repeater is now transmitting onto this segment. Two packets on one segment
results in a collision. PORT M now moves from B1 to A1.
Port A1 fulfills the same criteria as B1 (i.e., it has an active
collision on its segment), but in addition it is higher in the
arbitration chain. This priority yields no benefits for port A1
since the ANYXN signal is still active. There are now two
sources driving ANYXN, the MSMs and the collision on port
B1.
Eventually the collision on port B1 ends and the ANYXN
extension by the MSMs expires. There is only one collision
on the network (this may be deduced since ANYXN is inactive) so the repeater will move to the ONE PORT LEFT
state. The LERIC system treats this state in a similar manner to a receive collision with PORT M fulfilling the role of
the receiving port. The difference from a true receive collision is that the switch from packet data to the jam pattern
has already been made (controlled by ANYXN). Thus the
state of COLN has no effect upon repeater operations. In
common with the operation of the RECEIVE COLLISION
state, the repeater remains in this condition until the collision and receive activity on PORT M subside. The packet
repetition operation completes when the Tw1 recovery time
in the WAIT state has been performed.
Transmit Collisions
A transmit collision is a collision that is detected upon a
segment to which the repeater system is transmitting. The
port state machine monitoring the colliding segment asserts
the ANYXN bus signal. The assertion of ANYXN causes
PORT M arbitration to begin. The repeater moves to the
TRANSMIT COLLISION state when the port which had
been PORT N starts to transmit a Manchester encoded 1
on to its network segment. While in the TRANSMIT COLLISION state all ports of the repeater must transmit the
1010 . . . jam pattern and PORT M arbitration is performed.
Each LERIC is obliged, by the IEEE specification, to ensure
all of its ports transmit for at least 96 bits once the TRANSMIT COLLISION state has been entered. This transmit activity is enforced by the ANYXN bus signal. While ANYXN is
active all LERIC ports will transmit jam. To ensure this situation lasts for at least 96 bits, the MSMs inside the LERICs
assert the ANYXN signal throughout this period. After this
period has elapsed, ANYXN will only be asserted if there
are multiple ports with active collisions on their network segments.
There are two posible ways for a repeater to leave the
TRANSMIT COLLISION state. The most straightforward is
when network activity (i.e., collisions and their Tw2 extensions) end before the 96-bit enforced period expires. Under
these conditions the repeater system may move directly to
the WAIT state when 96 bits have been transmitted to all
ports. If the MSM enforced period ends and there is still one
port experiencing a collision the ONE PORT LEFT state is
entered. This may be seen on the Inter-LERIC bus when
ANYXN is deasserted and PORT M stops transmitting to its
network segment. In this circumstance the Inter-LERIC bus
transitions to the RECEIVE COLLISION state. The repeater
will remain in this state while PORT M’s collision, Tw2 collision extension and any receive signals are present. When
these conditions are not true, packet repetition finishes and
the repeater enters the WAIT state.
Figure 5-6 shows a multi-LERIC system operating under
transmit collision conditions. There are many different scenarios which may occur during a transmit collision, this figure illustrates one of these. The diagram begins with packet
Note: In transmit collision conditions COLN will only go active if the LERIC
which contained PORT N at the start of packet repetition contains
PORT M during the TRANSMIT COLLISION and ONE PORT LEFT
states.
26
5.0 Functional Description (Continued)
TL/F/11240 – 12
FIGURE 5-6. Transmit Collision
27
5.0 Functional Description (Continued)
Figure 5-7 shows the effect of a jabber length packet upon a
LERIC based repeater system. The JABBER PROTECT
state is entered from the SEND DATA state. While the Tw4
period is observed the Inter-LERIC bus displays the IDLE
state. This is misleading since new packet activity or continuous activity (as shown in the diagram) does not result in
packet repetition. This may only occur when the Tw4 requirement has been satisfied.
Jabber Protection
A repeater is required to disable transmit activity if the
length of its current transmission reaches the jabber protect
limit. This is defined by the IEEE specification’s Tw3 time.
The repeater disables output for a time period defined by
the Tw4 specification, after this period normal operation
may resume.
TL/F/11240 – 13
*Note 1: The IEEE Specification does not have a jabber protect state defined in its main state diagram, this behavior is defined in an additional MAU Jabber Lockup
Protection state diagram.
FIGURE 5-7. Jabber Protect
28
5.0 Functional Description (Continued)
bus but not both at the same time. Thus a single bidirectional input/output pin is adequate for each of these
signals. When an external bus transceiver is used with
these signals, the Packet Enable ‘‘PKEN’’, an output pin
of LERIC, performs the function of a drive enable and
sense disable.
5.4 DESCRIPTION OF HARDWARE CONNECTION
FOR CASCADING
5.4.1 DP89355 on the Inter-LERIC Bus
When considering the hardware interface the Inter-LERIC
bus may be viewed as consisting of three groups of signals:
1. Port Arbitration chain, namely: ACKI and ACKO. These
signals are either used as point-to-point links or with external arbitration logic. In both cases the load on these
signals will not be large so that the on-chip drivers are
adequate.
2. Simultaneous drive and sense signals, namely: ACTN
and ANYXN. Potentially these signals may be driven by
multiple devices. It should be noticed that due to the
nature of these signals, transceivers cannot be implemented for the purpose of cascading; however, bench
evaluation indicates that LERICs can be cascaded together as long as the total load capacitance is 100 pF or
less.
3. Drive or sense signals (i.e., IRE, IRD, IRC and COLN).
Only one device asserts these signals at any instance in
time. The unidirectional nature of information transfer on
the IRE, IRD, IRC and COLN signals means a LERIC is
either driving these signals or receiving them from the
bus but not both at the same time. Thus a single bidirectional input/output pin is adequate for each of these signals.
5.5 PROCESSOR AND DISPLAY INTERFACE
The processor interface pins, which include the data bus,
address bus and control signals, actually perform three operations which are multiplexed on these pins. These operations are:
1. The MLOAD Operation, which performs a power up initialization cycle upon the LERIC.
2. Display Update Cycles, which are refresh operations for
updating the display LEDs.
3. Processor Access Cycles, which allow mP’s (or simple
logic) to communicate with the LERIC’s registers.
These three operations are described below.
MLOAD Operation
The MLOAD Operation is a hardware initialization procedure
performed at power on. It loads vital device configuration
information into on chip configuration registers. In addition
to its configuration function the MLOAD pin is the LERIC’s
reset input. When MLOAD is low all of the LERIC’s repeater
timers, state machines and segment partition logic are reset.
The MLOAD Operation may be accomplished by attaching
the appropriate set of pull up and pull down resistors to the
data and register address pins to assert logic high or low
signals onto these pins, and then providing a rising edge on
the MLOAD pin as is shown in Figure 5-8. The mapping of
chip functions to the configuration inputs is shown in Table
5-2. Such an arrangement may be performed using a simple
resistor, capacitor, diode network. Performing the MLOAD
Operation in this way enables the configuration of a LERIC
that is in a simple repeater system (one without a processor).
Alternatively, in a complex repeater system the MLOAD Operation may be performed using a processor write cycle.
This would require the MLOAD pin be connected to the
CPU’s write strobe via some decoding logic, and included in
the processor’s memory map.
5.4.2 DP83956 Using the Inter-RIC Bus
When considering the hardware interface the Inter-LERIC
bus may be viewed as consisting of three groups of signals:
1. Port Arbitration chain, namely: ACKI and ACKO. These
signals are either used as point to point links or with
external arbitration logic. In both cases the load on these
signals will not be large so that the on-chip drivers are
adequate.
2. The need for simultaneous sense and drive capabilities
on the ACTN and ANYXN signals and the desire to allow
operation with external bus transceivers makes it necessary for these bus signals to each have a pair of pins,
one to drive the bus and the other to sense the bus. The
Inter-LERIC bus on the DP83956 has been designed to
connect LERICs together directly or via external bus
transceivers. The latter is advantageous in large repeaters. When external bus transceivers are used they must
be open collector/open drain to allow wire-ORing of the
signals.
3. Drive or sense signals, i.e., IRE, IRD, IRC and COLN.
Only one device asserts these signals at any instance in
time. The unidirectional nature of information transfer on
the IRE, IRD, IRC and COLN signals means a LERIC is
either driving these signals or receiving them from the
TL/F/11240 – 14
FIGURE 5-8. MLOAD Operation
29
5.0 Functional Description (Continued)
TABLE 5-2. Pin Definitions for Options in the MLOAD Operation
Pin
Name
Programming
Function
D0
D1
BYPAS1
BYPAS2
Effect When
Bit is 0
Effect When
Bit is 1
Function
BYPAS2
BYPAS1
0
0
All ports (2 to 7) use the external
Transceiver Interface.
Information
0
1
Ports 2 and 3 use the external interface, 4
to 7 use the internal 10BASE-T
transceivers.
1
0
Ports 2 to 5 use the external interface, 6
and 7 use the internal 10BASE-T
transceivers.
1
1
All ports (2 to 7) use the internal
10BASE-T transceivers.
These configuration bits select which of the repeater ports (numbers 2
to 7) are configured to use the on-chip internal 10BASE-T transceivers
or the external transceiver interface. The external transceiver interface
operates using AUI compatible signal levels.
D2
Resv.
Not
Permitted
Required
D3
EPOLSW
Not Selected
Selected
D4
Resv.
Not
Permitted
Required
D5
TXONLY
Selected
Not Selected
D6
CCLIM
63
31
The partition specification requires a port to be partitioned after a certain
number of consecutive collisions. The LERIC has two values available
to allow users to customize the partitioning algorithm to their
environment. Please refer to the Partition State Machine, in data sheet
section 7.3.
D7
MIN/MAX
Minimum
Mode
Maximum
Mode
The operation of the display update block is controlled by the value of
this configuration bit, as described in the Display Update Cycles section.
Enables the polarity switching of the receive squelch upon detection of
polarity reversal of the incoming data.
This configuration bit allows the on-chip partition algorithm to restrict
segment reconnection, as described in the Partition State Machine.
30
5.0 Functional Description (Continued)
The signals provided and their timing relationships have
been designed to interface directly with 74LS259 type addressable latches. The number of latches used being dependent upon the complexity of the display. Since the latches are octal, a pair of latches is needed to display each type
of segment specific data (7 ports means 7 latch bits). The
accompanying Tables 5-3 and 5-4 show the function of the
interface pins in minimum and maximum modes. Figure 5-10
shows the location of each port’s status information when
maximum mode is selected. This may be compared with the
connection diagram (Figure 5-9) .
Immediately following the MLOAD Operation (when the
MLOAD pin transitions to a high logic state), the display
logic performs an LED test operation. This operation lasts
one second and while it is in effect all of the utilized LEDs
will blink on. Thus an installation engineer is able to test the
operation of the display by forcing the LERIC into a reset
cycle (MLOAD forced low). The rising edge on the MLOAD
pin starts the LED test cycle. During the LED test cycle
the LERIC does not perform packet repetition operations.
The status display possesses a capability to lengthen the
time an LED is active. At the end of the repetition of a packet, the display is frozen showing the current activity. This
freezing lasts for 30 ms or until a subsequent packet is repeated. Thus at low levels of packet activity the display
stretches activity information to make it discernable to the
human eye. At high traffic rates the relative brightness of
the LEDs indicates those segments with high or low activity.
5.6 PROCESSOR AND DISPLAY INTERFACE
HARDWARE CONNECTION
Display Update Cycles
The LERIC possesses control logic and interface pins which
may be used to provide status information concerning activity on the attached network segments and the current status
of repeater functions. These status cycles are completely
autonomous and require only simple support circuitry to produce the data in a form suitable for a light emitting diode
‘‘LED’’ display. The display may be used in one of two
modes:
1. Minimum ModeÐGeneral Repeater Status LEDs
2. Maximum ModeÐIndividual Port Status LEDs
Minimum mode, intended for simple LED displays, makes
available four status indicators. The first LED denotes
whether the LERIC has been forced to activate its jabber
protect functions. The remaining 3 LEDs indicate if any of
the LERIC’s network segments are: (1) experiencing a collision, (2) receiving data, (3) currently partitioned. When minimum display mode is selected the only external components required are a 74LS374 type latch, the LEDs and their
current limiting resistors.
Maximum mode differs from minimum mode by providing
display information specific to individual network segments.
This information denotes the collision activity, packet reception and partition status of each segment. In the case of
10BASE-T segments the link integrity status and polarity of
the received data are also made available. The wide variety
of information available in maximum mode may be used in
its entirety or in part, thus allowing the system designer to
choose the appropriate complexity of status display commensurate with the specification of the end equipment.
TABLE 5-3. Status Display Pin Functions in Minimum Mode
Signal
Pin Name
Mnemonic
Function in MINIMUM MODE
D0
ACOL
Provides status information indicating if there is a collision occurring on one of the segments attached to
this LERIC.
D1
AREC
Provides status information indicating if one of this LERIC’s ports is receiving a data or collision packet
from a segment attached to this LERIC.
D2
JAB
D3
APART
D(7:4)
STR
Provides status information indicating that the LERIC has experienced a jabber protect condition.
Provides status information indicating if one of the LERIC’s segments is partitioned.
No operation
This signal is the latch enable for the 374 type latch.
Note: ACOL e Any Port Collision
AREC e Any Port Reception
JAB e Any Port Jabbering
APART e Port Partitioned
31
5.0 Functional Description (Continued)
TABLE 5-4. Status Display Pin Functions in Maximum Mode
Signal
Pin Name
Function in MAXIMUM MODE
D0
Provides status information concerning the Link Integrity status of 10BASE-T segments. This signal should be
connected to the data inputs of the chosen pair of 74LS259 latches.
D1
Provides status information indicating if there is a collision occurring on one of the segments attached to this LERIC.
This signal should be connected to the data inputs of the chosen pair of 74LS259 latches.
D2
Provides status information indicating if one of this LERIC’s ports is receiving data or a collision packet from its
segment. This signal should be connected to the data inputs of the chosen pair of 74LS259 latches.
D3
Provides status information indicating that the LERIC has experienced a jabber protect condition. Additionally, it
denotes which of its ports are partitioned. This signal should be connected to the data inputs of the chosen pair of
74LS259 latches.
D4
Provides status information indicating if one of this LERIC’s ports is receiving data of inverse polarity. This status
output is only valid if the port is configured to use its internal 10BASE-T transceiver. The signal should be connected to
the data inputs of the chosen pair of 74LS259 latches.
D(7:5)
STR
These signals provide the repeater port address corresponding to the data available on D(4:0).
This signal is the latch enable for the 74LS259 latches.
32
FIGURE 5-9. Maximum Mode LED Display (All Available Status Bits Used)
TL/F/11240 – 15
5.0 Functional Description (Continued)
33
5.0 Functional Description (Continued)
74LS259 Latch Inputs
259 Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
A7
259 Addr S(2 – 0)
000
001
010
011
100
101
110
111
1 (AUI)
LERIC Port Number
2
3
4
5
6
7
LINK
LINK
LINK
LINK
LINK
LINK
LERIC D0
ACOL
LERIC D1
AREC
COL
COL
COL
COL
COL
COL
COL
LERIC D2
JAB
REC
REC
REC
REC
REC
REC
REC
LERIC D3
APART
PART
LERIC D4
PART
PART
PART
PART
PART
PART
BDPOL
BDPOL
BDPOL
BDPOL
BDPOL
BDPOL
Note: This shows the LED Output Functions for the LED Drivers when 74LS259s are used.
ACOL e Any Port Collision, AREC e Any Port Reception, JAB e Any Port Jabbering,
LINK e Port Link, COL e Port Collision, REC e Port Reception, PART e Port Partitioned,
BDPOL e Bad (inverse) Polarity of received data
FIGURE 5-10. Maximum Mode LED Definitions
Processor Access Cycles
Access to the LERIC’s on-chip registers is made via its
processor interface. This utilizes a conventional non-multiplexed address (four bit) and data (four bit) bus. This bus is
also used to provide data and address information to off
chip LED display latches during display update cycles. While
performing these cycles the LERIC behaves as a master of
its data bus. Consequently a TRI-STATE bi-directional bus
transceiver (e.g., 74LS245) must be placed between the
LERIC and any processor bus. Internally each of the
LERIC’s registers is 8 bits, however there are four bits of
data pins (D(3:0)). Each register is accessed on a nibble
basis (4 bits at a time). D(7) of the address pins D(7:4) selects the upper and lower nibbles as described in Section 7.
To access the LERIC’s registers, the processor requests a
register access by asserting the read (RD) or write (WR)
input strobes. The LERIC responds by finishing any current
display update cycle and asserts the TRI-STATE buffer enable signal (BUFEN). If the processor cycle is a write cycle
then the LERIC’s buffers are disabled to prevent contention.
In order to interface to the LERIC a PAL device may be
used to perform the following operations:
1. Generate the LERIC’s read and write strobes,
2. Control the direction signal for the 74LS245.
An example of the processor and display interfaces is
shown in Figure 5-12 .
Description of Data Freeze Strobe (DFS) Pin Operation
DFS has been implemented to assist the user to provide
partial hub management statistics on a per packet per port
basis. The DFS signal is asserted, active high, at the end of
the transmission of each packet, and the status of that
packet is frozen on the LEDs until the beginning of the next
received packet or for a maximum of 30 ms as is shown in
Figure 5-11 .
The DFS signal can be used to latch the LED information
into a shared buffer which acts as an external flag register,
and can be used as a mechanism to trap events.
TL/F/11240–41
FIGURE 5-11. DFS Operation
34
5.0 Functional Description (Continued)
TL/F/11240 – 16
FIGURE 5-12. Processor Connection Diagram
6.0 Port Block Functions
The LERIC has 7 port logic blocks (one for each network
connection). In addition to the packet repetition operations
already described, the port block performs two other functions:
1. The physical connection to the network segment (transceiver function).
2. It provides a means to protect the network from malfunctioning segments (segment partition).
Each port has its own status and configuration register. This
register allows the user to determine the current status of
the port and configure a number of port specific functions.
10BASE-T Transceiver Operation
The LERIC contains virtually all the digital and analog circuits required for connection to 10BASE-T network segments. The only additional active component is an external
driver package. The connection for a LERIC port to a
10BASE-T segment is shown in Figure 6-1. The diagram
shows the components required to connect one of the
LERIC’s ports to a 10BASE-T segment (and lists a few module P/Ns and vendors). The major components are the driver package, a member of the 74ACT family, and an integrated filter-transformer-choke module (or discrete combination
of these functions).
The operation of the 10BASE-T transceiver’s logical functions may be modified by software control. The default
mode of operation is for the transceivers to transmit and
expect reception of link pulses. This may be modified if a
logic one is written to the GDLNK bit of a port’s status register. The port’s transceiver will operate normally but will not
transmit link pulses nor monitor their reception. Thus the
entry to a link fail state and the associated modification of
transceiver operation will not occur.
The on-chip 10BASE-T transceivers automatically detect
and correct the polarity of the received data stream. This
polarity detection scheme relies upon the polarity of the received link pulses and the end of packet waveform. Polarity
detection and correction may be disabled through the
MLOAD operation.
6.1 TRANSCEIVER FUNCTIONS
The LERIC may connect to network segments in three
ways:
1. Over AUI cable to transceiver boxes (Port 1)
2. Directly to board mounted transceivers.
3. To twisted pair cable via a simple interface.
The first method is only supported by LERIC Port 1 (the AUI
port). Options (2) and (3) are available on Ports 2 to 7. The
selection of the desired option is made at device initialization during the MLOAD operation. The Transceiver Bypass
XBYPAS configuration bits are used to determine whether
the ports will utilize the on-chip 10BASE-T transceivers or
bypass these in favor of external transceivers. Four possible
combinations of port utilization are supported (refer to Table
5-2):
1. All ports (2 to 7) use the external Transceiver Interface.
2. Ports 2 and 3 use the external interface, 4 to 7 use the
internal 10BASE-T transceivers.
3. Ports 2 to 5 use the external interface, 6 and 7 use the
internal 10BASE-T transceivers.
4. All ports (2 to 7) use the internal 10BASE-T transceivers.
External Transceiver Operation
LERIC ports 2 to 7 may be connected to media other than
twisted-pair by opting to bypass the on-chip transceivers.
When using external transceivers the user must perform
collision detection and the other functions associated with
an IEEE 802.3 Media Access Unit. Figure 6-2 shows the
connection between a repeater port and a coaxial transceiver using the AUI type interface.
35
6.0 Port Block Functions (Continued)
TL/F/11240 – 17
For typical Filter-Transformer-Choke Modules refer to ETHERNET MAGNETIC VENDORS.
In addition to these, the Valor FL1085 is recommended for HCT Drivers.
FIGURE 6-1. Port Connection to a 10BASE-T Segment
TL/F/11240 – 18
The above diagrams show a LERIC port (numbers 2 to 7) connected to a 10BASE-T and a 10BASE2 segment. The values of any components not indicated above
are to be determined.
FIGURE 6-2. Port Connection to a 10BASE2 Segment (AUI type Interface selected)
36
6.0 Port Block Functions (Continued)
tween such packets. The TXONLY configuration bit is
input on pin D(5) during the MLOAD cycle. If this option is
selected the operation of the state machine branch
marked (3) in Figure 6-3 is affected.
In addition to the autonomous operation of the partition
state machines, the user may reset these state machines. This may be done individually to each port by
writing a logic one to the PART bit in its status register.
The port’s partition state machine and associated counters are reset and the port is reconnected to the network.
6.2 SEGMENT PARTITION
Each of the LERIC ports has a dedicated state machine to
perform the functions defined by the IEEE partition algorithm as shown in Figure 6-3. To allow users to customize
this algorithm for different applications a number of user
selected options are available during device configuration at
power up (the MLOAD cycle).
Two options are provided:
1. The value of consecutive counts required to partition a
segment (the CCLimit specification) may be set at either
31 or 63 consecutive collisions.
2. The operation of the ports’ state machines when reconnecting a segment may also be modified by the user. The
Transmit Only TXONLY configuration bit allows the user
to prevent segment reconnection unless the reconnecting packet is being sourced by the repeater. In this case
the repeater is transmitting on to the segment rather than
the segment transmitting when the repeater is idle. The
normal mode of reconnection does not differentiate be-
6.3 PORT STATUS AND CONFIGURATION
REGISTER FUNCTIONS
Each LERIC port has its own status and configuration register. In addition to providing status concerning the port and
its network segment the register allows the following operations to be performed upon the port:
1. Port disable. When a port is disabled packet transmission and reception between the port’s segment and the
rest of the network is prevented.
2. Selection between normal and reduced squelch levels.
37
6.0 Port Block Functions (Continued)
TL/F/11240 – 19
FIGURE 6-3. IEEE Segment Partition Algorithm
38
7.0 LERIC Registers
lower nibbles of each register. The register map consists of
8 registers as shown in the Register Map in Table 7-1 which
is followed by a summary of the register bits shown in Table
7-2. The definitions for these bits are shown in the detailed
register definitions on the following pages.
7.1 LERIC REGISTER ADDRESS MAP
The LERIC’s registers may be accessed by applying the
required address to the four register address (D(7:4)) input
pins. Pin D(7) makes the selection between the upper and
TABLE 7-1. Register Memory Map
Address D(7:4)
Name
0000
1000
LERIC Status RegisterÐLower Nibble
LERIC Status RegisterÐUpper Nibble
0001
1001
Port 1 Status and Configuration RegisterÐLower Nibble
Port 1 Status and Configuration RegisterÐUpper Nibble
0010
1010
Port 2 Status and Configuration RegisterÐLower Nibble
Port 2 Status and Configuration RegisterÐUpper Nibble
0011
1011
Port 3 Status and Configuration RegisterÐLower Nibble
Port 3 Status and Configuration RegisterÐUpper Nibble
0100
1100
Port 4 Status and Configuration RegisterÐLower Nibble
Port 4 Status and Configuration RegisterÐUpper Nibble
0101
1101
Port 5 Status and Configuration RegisterÐLower Nibble
Port 5 Status and Configuration RegisterÐUpper Nibble
0110
1110
Port 6 Status and Configuration RegisterÐLower Nibble
Port 6 Status and Configuration RegisterÐUpper Nibble
0111
1111
Port 7 Status and Configuration RegisterÐLower Nibble
Port 7 Status and Configuration RegisterÐUpper Nibble
Register Array Bit Map
Address D(7:4)
D(3)
D(2)
D(1)
D(0)
0000
1000
PART
Resv
JAB
Resv
AREC
Resv
ACOL
Resv
0001
1001
PART
DISPT
REC
Resv
COL
Resv
GDLNK
Resv
0010
1010
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQRL
0011
1011
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQL
0100
1100
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQL
0101
1101
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQL
0110
1110
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQL
0111
1111
PART
DISPT
REC
Resv
COL
POL
GDLNK
SQL
39
7.0 LERIC Registers (Continued)
7.2 LERIC STATUS REGISTER
This register contains real time information concerning the operation of the LERIC.
D(3)
D(2)
D(1)
D(0)
D(3)
D(2)
D(1)
D(0)
Resv
Resv
Resv
Resv
APART
JAB
AREC
ACOL
Symbol
Bit
R/W
ACOL
D(0)
R
Any Collisions
0: A collision is occurring at one or more of the LERIC’s ports
1: No collisions
Description
AREC
D(1)
R
Any Receive
0: One of the LERIC’s ports is the current packet or collision receiver
1: No packet or collision reception within this LERIC
JAB
D(2)
R
Jabber Protect
0: The LERIC has been forced into jabber protect state by one of its ports or by another port on the
Inter-LERIC bus (operations)
1: No jabber protect conditions exist
APART
D(3)
R
Any Partition
0: One or more ports are partitioned
1: No ports are partitioned
Resv
D(0)
R
Reserved for future use
Value set at logic one
Resv
D(1)
R
Reserved for future use
Value set at logic one
Resv
D(2)
R
Reserved for future use
Value set at logic one
Resv
D(3)
R
Reserved for future use
Value set at logic one
40
7.0 LERIC Registers (Continued)
7.3 PORT STATUS AND CONFIGURATION REGISTERS
D(3)
D(2)
D(1)
D(0)
D(3)
D(2)
D(1)
D(0)
DISPT
Resv
POL
SQL
PART
REC
COL
GDLNK
Symbol
Bit
R/W
GDLNK
D(0)
R/W
Description
Good Link
0: Link pulses are being received by the port
1: Link pulses are not being received by the port logic
Note: Writing a 1 to this bit will cause the 10BASE-T transceiver not to transmit or monitor the reception of link
pulses. If the internal 10BASE-T transceivers are not selected or if port 1 (AUI port) is read, then this bit is undefined.
COL
D(1)
R
Collision
0: A collision is happening or has occurred during the current packet
1: No collisions have occurred as yet during this packet
REC
D(2)
R
Receive
0: This port is now or has been the receive source of packet or collision information for the current
packet.
1: This port has not been the receive source during the current packet
PART
D(3)
R/W
Partition
0: This port is partitioned
1: This port is not partitioned
Writing a logic one to this bit forces segment reconnection and partition state machine reset. Writing
a zero to this bit has no effect.
SQL
D(0)
R/W
Squelch Level
0: Port operates with normal IEEE receive squelch level
1: Port operates with reduced receive squelch levels
POL
D(1)
R
Polarity
0: Polarity is not inverted
1: Polarity is inverted
Resv
D(2)
R
‘‘Reserved’’
‘‘Value set to logic zero’’
DISPT
D(3)
R/W
Note: This bit has no effect when the external transceiver is selected.
Disable Port
0: Port operates as defined by repeater operations
1: All port activity is prevented
41
8.0 Absolute Maximum Ratings
Storage Temperature Range (TSTG)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
0.5V to 7.0V
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
b 65§ C to a 150§ C
Power Dissipation (PD)
b 0.5V to VCC a 0.5V
b 0.5V to VCC a 0.5V
1.5W
Lead Temperature (TL)
(Soldering, 10 Seconds)
260§ C
ESD Rating
(RZAP e 1.5k, CZAP e 120 pF)
1.5 kV
9.0 DC Specifications TA e 0§ C to a 70§ C, VCC e 5V g 5% unless otherwise specified
Symbol
Description
Conditions
Min
Max
Units
PROCESSOR, LED, TWISTED-PAIR PORTS AND INTER-LERIC INTERFACES
VOH
Minimum High Level
Output Voltage
IOH e b8 mA
VOL
Minimum Low Level
Output Voltage
IOL e 8 mA
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIN
Input Current
VIN e VCC or GND
IOZ
Maximum TRI-STATE Output
Leakage Current
VOUT e VCC
or GND
ICC
Average Supply Current
VIN e VCC or GND
VCC e 5.25V
VOD
Differential Output
Voltage (TX g )
78X Termination and
270X Pulldowns
VOB
Differential Output Voltage
Imbalance (TX g )
78X Termination and
270X Pulldowns
40 mV
Typical
VU
Undershoot Voltage (TX g )
78X Termination and
270X Pulldowns
80 mV
Typical
VDS
Differential Squelch
Threshold (RX g , CD g )
b 175
b 300
mV
VCM
Differential Input
Common Mode Voltage
(RX g , CD g ) (Note 1)
0
5.5
V
3.5
V
0.4
2.0
V
V
0.8
V
b 1.0
1.0
mA
b 10
10
mA
250
mA
g 1200
mV
AUI (PORT 1)
42
g 550
9.0 DC Specifications TA e 0§ C to a 70§ C, VCC e 5V g 5% unless otherwise specified (Continued)
Symbol
Description
Conditions
Min
Max
Units
g 450
g 1200
mV
PSEUDO AUI (PORTS 2–7)
VPOD
Differential Output
Voltage (TX g )
270X Termination and
1 kX Pulldowns
VPOB
Differential Output Voltage
Imbalance (TX g )
270X Termination
and 1 kX Pulldowns
40 mV
Typical
VPU
Undershoot Voltage (TX g )
270X Termination
and 1 kX Pulldowns
80 mV
Typical
VPDS
Differential Squelch
Threshold (RX g , CD g )
b 175
b 300
mV
VPCM
Differential Input
Common Mode Voltage
(RX g , CD g ) (Note 1)
0
5.5
V
g 300
g 585
g 175
g 300
mV
mV
TWISTED-PAIR (PORTS 2–7)
VRON
Minimum Receive Squelch Threshold:
Normal Mode
Reduced Mode
Note 1: This parameter is guaranteed by design and is not tested.
10.0 Switching Characteristics
PORT ARBITRATION TIMING
TL/F/11240 – 20
Number
Parameter
Max
Units
ackilackol
Symbol
T1
ACKI Low to ACKO Low
Min
26
ns
ackihackoh
T2
ACKI High to ACKO High
23
ns
Note: Timing valid with no receive or collision activities.
RECEIVE TIMINGÐAUI PORTS
Receive activity propagation start up and end delays for ports in non 10BASE-T mode
TL/F/11240 – 21
Symbol
Number
Parameter
Max
Units
rxaackol
rxiackoh
T3a
T4a
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
66
235
ns
ns
rxaactnl
rxiactnh
T5a
T6a
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
75
235
ns
ns
Note: ACKI assumed high
Note 1: This time includes EOP.
Note 2: This parameter assumes squelch triggers on negative edge of RX data.
43
Min
10.0 Switching Characteristics (Continued)
RECEIVE TIMING-10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
TL/F/11240 – 22
Symbol
Number
Parameter
rxaackol
rxiackoh
T3t
T4t
rxaactnl
rxiactnh
T5t
T6t
Min
Max
Units
RX Active to ACKO Low
RX Inactive to ACKO High (Note 1)
300
280
ns
ns
RX Active to ACTN Low
RX Inactive to ACTN High (Note 1)
300
280
ns
ns
Note: ACKI assumed high.
Note 1: This time includes EOP.
TRANSMIT TIMINGÐAUI PORTS
Transmit activity propagation start up and end delays for ports in non 10BASE-T mode
TL/F/11240 – 23
Symbol
Number
Max
Units
actnltxa
T15a
ACTN Low to TX Active
Parameter
675
ns
clkitxa
T16a
CLOCK in to TX Active (Note 1)
45
ns
Note: ACKI assumed high.
Note 1: Measurement from previous falling edge of the clock.
44
Min
10.0 Switching Characteristics (Continued)
TRANSMIT TIMINGÐ10BASE-T PORTS
Receive activity propagation start up and end delays for ports in 10BASE-T mode
TL/F/11240 – 24
Symbol
Number
Max
Units
actnltxa
T15t
ACTN Low to TX Active
Parameter
Min
790
ns
clkitxa
T16t
CLOCK in to TX Active (Note 1)
45
ns
Note: ACKI assumed high.
Note 1: Clock not drawn to scale. In this measurement, falling edge of the clock for even ports and rising edge of the clock for odd ports are considered.
COLLISION TIMINGÐAUI PORTS
Collision activity propagation start up and end delays for ports in non 10BASE-T mode
TRANSMIT COLLISION TIMING
TL/F/11240 – 25
Symbol
Number
Max
Units
cdaanyxnl
T30a
CD Active to ANYXN Low
Parameter
85
ns
cdianyxnh
T31a
CD Inactive to ANYXN High (Notes 1, 2)
285
ns
Note 1: TX collision extension has already been performed and no other port is driving ANYXN.
Note 2: Includes TW2.
45
Min
10.0 Switching Characteristics (Continued)
RECEIVE COLLISION TIMING
TL/F/11240 – 26
Symbol
Number
Max
Units
cdacolna
cdicolni
T32a
T33a
CD Active to COLN Low
CD Inactive to COLN High
Parameter
Min
75
215
ns
ns
colnljs
colnhje
T39
T40
COLN Low to Start of JAM
COLN High to End of JAM(Note 1)
400
585
ns
ns
Note 1: Reception ended before COLN goes high.
COLLISION TIMINGÐ10BASE-T PORTS
Collision activity propagation start up and end delays for ports in 10BASE-T mode
TL/F/11240 – 27
Symbol
Number
colaanyl
T30t
Collision Active to ANYXN Low
Parameter
800
ns
colianyh
T31t
Collision Inactive to ANYXN High (Note 1)
450
ns
Note 1: TX collision extension has already been performed and no other port is asserting ANYXN.
46
Min
Max
Units
10.0 Switching Characteristics (Continued)
COLLISION TIMINGÐALL PORTS
TL/F/11240 – 28
Symbol
Number
Parameter
Min
anylmin
anyhtxai
anylsj
T34
T35
T38
ANYXN Low Time
ANYXN High to TX to All Inactive
ANYXN Low to Start of JAM
96
20
Max
Units
370
565
bits
ns
ns
COLLISION TIMINGÐALL PORTS
TL/F/11240 – 29
Symbol
Number
Parameter
actnhtxi
anyhtxoi
T36
T37
ACTN High to TX Inactive
ANYXN High to TX ‘‘One Port Left’’ Inactive
Note: 96 bits of JAM have already been propagated.
47
Min
Max
Units
20
410
200
ns
ns
10.0 Switching Characteristics (Continued)
RESET TIMING
TL/F/11240 – 30
Symbol
Number
Parameter
Min
resdats
T61
Data Setup
20
resdath
T62
Data Hold
20
reslbufl
T63
MLOAD Low to BUFEN Low
reshbufh
T64
MLOAD High to BUFEN High
resw
T65
MLOAD Width
Max
Units
ns
ns
35
35
800
ns
ns
ns
LED STROBE TIMING
TL/F/11240 – 31
Symbol
Number
Parameter
Min
Max
Units
stradrs
T66
Strobe Address Setup
70
100
ns
strdats
T67
Strobe Data Setup
35
55
ns
strdath
T68
Strobe Data Hold
145
165
ns
strw
T69
Strobe Width
30
65
ns
48
10.0 Switching Characteristics (Continued)
REGISTER READ TIMING
TL/F/11240 – 32
Number
Parameter
Min
Max
Units
rdadrs
rdadrh
Symbol
T80
T81
Address Setup from BUFEN Low
Address Hold after RD High
0
0
85
ns
ns
rdlbufl
rdhbufh
T82
T83
RD Low to BUFEN Low
RD High to BUFEN High
80
355
35
ns
ns
bufldatv
rddath
T84
T85
BUFEN Low to Data Valid
Read Data Hold
190
60
ns
ns
rdw
T88
RD Width
650
rdtr
T89
RD Low to D(7:4) TRI-STATE
80
ns
355
ns
Note: Minimum high time between read/write cycles is 100 ns.
REGISTER WRITE TIMING
TL/F/11240 – 33
Symbol
Number
Parameter
Min
Max
Units
wradrs
wradrh
T90
T91
Address Setup from BUFEN Low
Address Hold after WR High
0
0
14
ns
ns
wrlbufl
wrhbufh
T92
T93
WR Low to BUFEN Low
WR High to BUFEN High
80
355
35
ns
ns
wradatv
wrdath
T94
T95
BUFEN Low to Data Valid
Write Data Hold
160
ns
ns
wrdatr
T96
BUFEN Low to Data Latched
245
ns
wrw
T98
WR Width
650
ns
wrtr
T99
WR Low to D(7:0) TRI-STATE
80
Note: Minimum high time between read/write cycles is 100 ns.
49
0
355
ns
10.0 Switching Characteristics (Continued)
INTER-LERIC BUS OUTPUT TIMING
TL/F/11240 – 34
Symbol
Number
Parameter
Min
Max
Units
%
ircoh
T101
IRC Output High Time
40
60
ircol
T102
IRC Output Low Time
40
60
%
ircoc
T103
IRC Output Cycle Time
90
110
ns
actndapkena
T104
ACTNd Active to PKEN Active (Note 1)
500
500
actnolireol
T105
ACTN Output Low to IRE Output Low
ireolirca
T106
IRE Output Low to First Rising Edge of IRC
irdov
T107
IRD Output Valid from IRC
irdos
T108
IRD Output Stable Valid Time
90
ircohireh
T109
IIRC Output High to IRE High
ircclks
T110
Number of IRCs after IRE High
ns
ns
1.8
ms
10
ns
30
70
ns
5
5
clocks
ns
Note 1: This parameter applies to DP83956 only.
INTER-LERIC BUS INPUT TIMING
TL/F/11240 – 35
Symbol
Number
Parameter
Min
Max
Units
ircih
T111
IRC Input High Time
20
ns
ircil
T112
IRC Input Low Time
20
ns
irdisirc
T114
IRD Input Setup to IRC
5
ns
irdihirc
T115
IRD Input Hold from IRC
10
ircihireh
T116
IRC Input High to IRE High
25
50
ns
75
ns
11.0 AC Timing Test Conditions
Input Pulse Levels (Diff.)
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at AUI
side of the pulse transormer.
b 350 mV to b 1315 mV
Input and Output Reference
Levels (Diff.)
50% Point of the Differential
TRI-STATE Reference Levels
Float (DV) g 0.5V
Input Pulse Levels (TTL/CMOS)
GND to 3.0V
Input Rise and Fall Times (TTL/CMOS)
5 ns
Input and Output Reference Levels (TTL/CMOS)
1.5V
Output Load (See Figure Below)
TL/F/11240 – 42
Note 1: 100 pF, include scope and jig capacitance.
Note 2: S1 e Open for timing tests for push pull outputs.
S1 e VCC for VOL test.
S1 e GND for VOH test.
S1 e VCC for High Impedance to active low and active low to High Impedance measurements.
S1 e GND for High Impedance to active high and active high to High Impedance measurements.
Capacitance TA e 25§ C, f e 1 MHz
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
7
pF
COUT
Output Capacitance
7
pF
Derating Factor
Output timings are measured with a purely capacitive load
for 50 pF. The following correction factor can be used for
other loads: CL t 50 pF a 0.3 ns/pF.
TL/F/11240 – 43
Note: In the above diagram, the TX a and TXb signals are taken from the
AUI side of the isolation (pulse transformer). The pulse transformer used for
all testing is the Pulse Engineering PE64103.
51
Physical Dimensions inches (millimeters)
Plastic Chip Carrier (V)
Order Number DP83955AV
NS Package Number V84A
52
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Flatpak
Order Number DP83956AVLJ
NS Package Number VLJ100A
53
DP83955A/DP83956A LERIC LitE Repeater Interface Controller
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Flatpak
Order Number DP83956AVLY
NS Package Number VF100B
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