Renesas HD64F2166 Renesas 16-bit single-chip microcomputer h8s family / h8s/2100 sery Datasheet

REJ09B0078-0300Z
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2168Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2168
H8S/2167
H8S/2166
Rev.3.00
Revision Date: Mar. 12, 2004
HD64F2168
HD64F2167
HD64F2166
Rev. 3.00, 03/04, page ii of xl
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 3.00, 03/04, page iii of xl
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 3.00, 03/04, page iv of xl
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00, 03/04, page v of xl
Preface
This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology's
original architecture as its core, and the peripheral functions required to configure a system, eg PC
server.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit
free running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication
interface (SCI), an I2C bus interface (IIC), an LPC interface (LPC), a D/A converter, an A/D
converter, and I/O ports as on-chip peripheral modules required for system configuration.
A data transfer controller (DTC) is included as a bus master.
A flash memory (F-ZTATTM*) version is available for this LSI’s 256, 384, and 512-kbyte ROM.
The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed
in a single state. This improves the instruction fetch and process speeds.
Two operating modes are provided, offering a choice of address space and single chip
mode/external extended mode. Boot programming into a flash memory, on-chip emulation, and
boundary scan can be selected as special operating modes.
Note: * F-ZTATTM is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who use this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical
circuits, logic circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions and electrical
characteristics.
Rev. 3.00, 03/04, page vi of xl
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the detailed function of a register whose name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 24,
List of Registers.
Rules:
Register name:
The following notation is used for cases when the same or a
similar function, e.g., serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B’xxxx, hexadecimal is H’xxxx, decimal is xxxx.
Signal notation:
An overbar is added to a low-active signal: xxxx
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
H8S/2168 Group manuals:
Document Title
Document No.
H8S/2168 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Programming Manual
ADE-602-083
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
ADE-702-247
H8S, H8/300 Series Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop, Highperformance Debugging Interface Tutorial
ADE-702-231
High-performance Embedded Workshop User's Manual
ADE-702-201
Rev. 3.00, 03/04, page vii of xl
Rev. 3.00, 03/04, page viii of xl
Contents
Section 1 Overview............................................................................................1
1.1
1.2
1.3
Overview........................................................................................................................... 1
Internal Block Diagram..................................................................................................... 2
Pin Description.................................................................................................................. 3
1.3.1 Pin Arrangement .................................................................................................. 3
1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 4
1.3.3 Pin Functions ....................................................................................................... 9
Section 2 CPU....................................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features............................................................................................................................. 15
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 16
2.1.2 Differences from H8/300 CPU ............................................................................ 17
2.1.3 Differences from H8/300H CPU.......................................................................... 17
CPU Operating Modes...................................................................................................... 18
2.2.1 Normal Mode....................................................................................................... 18
2.2.2 Advanced Mode................................................................................................... 20
Address Space................................................................................................................... 22
Register Configuration...................................................................................................... 23
2.4.1 General Registers................................................................................................. 24
2.4.2 Program Counter (PC) ......................................................................................... 25
2.4.3 Extended Control Register (EXR) ....................................................................... 25
2.4.4 Condition-Code Register (CCR).......................................................................... 26
2.4.5 Initial Register Values.......................................................................................... 27
Data Formats..................................................................................................................... 28
2.5.1 General Register Data Formats ............................................................................ 28
2.5.2 Memory Data Formats ......................................................................................... 30
Instruction Set ................................................................................................................... 31
2.6.1 Table of Instructions Classified by Function ....................................................... 32
2.6.2 Basic Instruction Formats .................................................................................... 41
Addressing Modes and Effective Address Calculation..................................................... 43
2.7.1 Register Direct—Rn ............................................................................................ 43
2.7.2 Register Indirect—@ERn .................................................................................... 44
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 44
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+
or @-ERn............................................................................................................. 44
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 44
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 45
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 45
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 46
Rev. 3.00, 03/04, page ix of xl
2.8
2.9
2.7.9 Effective Address Calculation ............................................................................. 47
Processing States............................................................................................................... 49
Usage Notes ...................................................................................................................... 51
2.9.1 Note on TAS Instruction Usage........................................................................... 51
2.9.2 Note on Bit Manipulation Instructions ................................................................ 51
2.9.3 EEPMOV Instruction........................................................................................... 52
Section 3 MCU Operating Modes ..................................................................... 53
3.1
3.2
3.3
3.4
Operating Mode Selection ................................................................................................ 53
Register Descriptions........................................................................................................ 54
3.2.1 Mode Control Register (MDCR) ......................................................................... 54
3.2.2 System Control Register (SYSCR)...................................................................... 55
3.2.3 Serial Timer Control Register (STCR) ................................................................ 56
Operating Mode Descriptions ........................................................................................... 58
3.3.1 Mode 2................................................................................................................. 58
3.3.2 Pin Functions in Each Operating Mode ............................................................... 58
Address Map ..................................................................................................................... 60
Section 4 Exception Handling ........................................................................... 63
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Exception Handling Types and Priority............................................................................ 63
Exception Sources and Exception Vector Table ............................................................... 64
Reset ................................................................................................................................. 66
4.3.1 Reset Exception Handling ................................................................................... 66
4.3.2 Interrupts after Reset............................................................................................ 67
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................ 67
Interrupt Exception Handling ........................................................................................... 68
Trap Instruction Exception Handling................................................................................ 68
Stack Status after Exception Handling.............................................................................. 69
Usage Note........................................................................................................................ 70
Section 5 Interrupt Controller............................................................................ 71
5.1
5.2
5.3
5.4
Features............................................................................................................................. 71
Input/Output Pins.............................................................................................................. 73
Register Descriptions........................................................................................................ 74
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD)........................................... 74
5.3.2 Address Break Control Register (ABRKCR) ...................................................... 75
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 76
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................ 77
5.3.5 IRQ Enable Registers (IER16, IER) .................................................................... 79
5.3.6 IRQ Status Registers (ISR16, ISR)...................................................................... 80
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up
Event Interrupt Mask Register (WUEMR3) ........................................................ 81
Interrupt Sources............................................................................................................... 82
Rev. 3.00, 03/04, page x of xl
5.5
5.6
5.7
5.4.1 External Interrupts ............................................................................................... 82
5.4.2 Internal Interrupts ................................................................................................ 84
Interrupt Exception Handling Vector Table...................................................................... 85
Interrupt Control Modes and Interrupt Operation ............................................................. 88
5.6.1 Interrupt Control Mode 0 ..................................................................................... 90
5.6.2 Interrupt Control Mode 1 ..................................................................................... 92
5.6.3 Interrupt Exception Handling Sequence .............................................................. 94
5.6.4 Interrupt Response Times .................................................................................... 96
5.6.5 DTC Activation by Interrupt................................................................................ 97
Usage Notes ...................................................................................................................... 99
5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 99
5.7.2 Instructions that Disable Interrupts ...................................................................... 100
5.7.3 Interrupts during Execution of EEPMOV Instruction.......................................... 100
5.7.4 IRQ Status Registers (ISR16, ISR) ...................................................................... 100
Section 6 Bus Controller (BSC).........................................................................101
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Features............................................................................................................................. 101
Input/Output Pins .............................................................................................................. 104
Register Descriptions ........................................................................................................ 105
6.3.1 Bus Control Register (BCR) ................................................................................ 105
6.3.2 Bus Control Register 2 (BCR2) ........................................................................... 106
6.3.3 Wait State Control Register (WSCR) .................................................................. 108
6.3.4 Wait State Control Register 2 (WSCR2) ............................................................. 110
Bus Control ....................................................................................................................... 112
6.4.1 Bus Specifications................................................................................................ 112
6.4.2 Advanced Mode................................................................................................... 122
6.4.3 I/O Select Signals................................................................................................. 123
Bus Interface ..................................................................................................................... 124
6.5.1 Data Size and Data Alignment............................................................................. 124
6.5.2 Valid Strobes ....................................................................................................... 126
6.5.3 Basic Operation Timing in Normal Extended Mode ........................................... 127
6.5.4 Basic Operation Timing in Address-Data Multiplex Extended Mode ................. 135
6.5.5 Wait Control ........................................................................................................ 141
Burst ROM Interface......................................................................................................... 145
6.6.1 Basic Operation Timing....................................................................................... 145
6.6.2 Wait Control ........................................................................................................ 146
Idle Cycle.......................................................................................................................... 147
Bus Arbitration.................................................................................................................. 148
6.8.1 Overview.............................................................................................................. 148
6.8.2 Operation ............................................................................................................. 148
6.8.3 Bus Mastership Transfer Timing ......................................................................... 148
Rev. 3.00, 03/04, page xi of xl
Section 7 Data Transfer Controller (DTC)........................................................ 149
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Features............................................................................................................................. 149
Register Descriptions........................................................................................................ 151
7.2.1 DTC Mode Register A (MRA) ............................................................................ 152
7.2.2 DTC Mode Register B (MRB)............................................................................. 153
7.2.3 DTC Source Address Register (SAR).................................................................. 153
7.2.4 DTC Destination Address Register (DAR).......................................................... 153
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 154
7.2.6 DTC Transfer Count Register B (CRB)............................................................... 154
7.2.7 DTC Enable Registers (DTCER)......................................................................... 154
7.2.8 DTC Vector Register (DTVECR)........................................................................ 155
7.2.9 Keyboard Comparator Control Register (KBCOMP).......................................... 156
7.2.10 Event Counter Control Register (ECCR)............................................................. 157
7.2.11 Event Counter Status Register (ECS) .................................................................. 158
DTC Event Counter .......................................................................................................... 159
7.3.1 Event Counter Handling Priority ......................................................................... 160
7.3.2 Usage Notes ......................................................................................................... 161
Activation Sources............................................................................................................ 161
Location of Register Information and DTC Vector Table ................................................ 162
Operation .......................................................................................................................... 165
7.6.1 Normal Mode....................................................................................................... 166
7.6.2 Repeat Mode........................................................................................................ 167
7.6.3 Block Transfer Mode ........................................................................................... 168
7.6.4 Chain Transfer ..................................................................................................... 169
7.6.5 Interrupt Sources.................................................................................................. 170
7.6.6 Operation Timing................................................................................................. 170
7.6.7 Number of DTC Execution States ....................................................................... 171
Procedures for Using DTC................................................................................................ 173
7.7.1 Activation by Interrupt......................................................................................... 173
7.7.2 Activation by Software ........................................................................................ 173
Examples of Use of the DTC ............................................................................................ 174
7.8.1 Normal Mode....................................................................................................... 174
7.8.2 Software Activation ............................................................................................. 174
Usage Notes ...................................................................................................................... 176
7.9.1 Module Stop Mode Setting .................................................................................. 176
7.9.2 On-Chip RAM ..................................................................................................... 176
7.9.3 DTCE Bit Setting................................................................................................. 176
7.9.4 Setting Required on Entering Subactive Mode or Watch Mode.......................... 176
7.9.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter ................. 176
Rev. 3.00, 03/04, page xii of xl
Section 8 I/O Ports .............................................................................................177
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Port 1................................................................................................................................. 183
8.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 183
8.1.2 Port 1 Data Register (P1DR)................................................................................ 184
8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 184
8.1.4 Pin Functions ....................................................................................................... 185
8.1.5 Port 1 Input Pull-Up MOS ................................................................................... 186
Port 2................................................................................................................................. 187
8.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 187
8.2.2 Port 2 Data Register (P2DR)................................................................................ 188
8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 188
8.2.4 Pin Functions ....................................................................................................... 189
8.2.5 Port 2 Input Pull-Up MOS ................................................................................... 190
Port 3................................................................................................................................. 191
8.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 191
8.3.2 Port 3 Data Register (P3DR)................................................................................ 191
8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 192
8.3.4 Pin Functions ....................................................................................................... 192
8.3.5 Port 3 Input Pull-Up MOS ................................................................................... 195
Port 4................................................................................................................................. 196
8.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 196
8.4.2 Port 4 Data Register (P4DR)................................................................................ 196
8.4.3 Pin Functions ....................................................................................................... 197
Port 5................................................................................................................................. 200
8.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 200
8.5.2 Port 5 Data Register (P5DR)................................................................................ 200
8.5.3 Pin Functions ....................................................................................................... 201
Port 6................................................................................................................................. 204
8.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 204
8.6.2 Port 6 Data Register (P6DR)................................................................................ 205
8.6.3 Port 6 Pull-Up MOS Control Register (KMPCR6).............................................. 205
8.6.4 System Control Register 2 (SYSCR2) ................................................................. 206
8.6.5 Noise Canceler Enable Register (P6NCE)........................................................... 206
8.6.6 Noise Canceler Mode Control Register (P6NCMC)............................................ 207
8.6.7 Noise Canceler Cycle Setting Register (P6NCCS) .............................................. 207
8.6.8 Pin Functions ....................................................................................................... 209
8.6.9 Port 6 Input Pull-Up MOS ................................................................................... 213
Port 7................................................................................................................................. 213
8.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... 213
8.7.2 Pin Functions ....................................................................................................... 214
Port 8................................................................................................................................. 217
8.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 217
Rev. 3.00, 03/04, page xiii of xl
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.8.2 Port 8 Data Register (P8DR) ............................................................................... 217
8.8.3 Pin Functions ....................................................................................................... 218
Port 9................................................................................................................................. 222
8.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 222
8.9.2 Port 9 Data Register (P9DR) ............................................................................... 223
8.9.3 Pin Functions ....................................................................................................... 223
Port A................................................................................................................................ 226
8.10.1 Port A Data Direction Register (PADDR)........................................................... 226
8.10.2 Port A Output Data Register (PAODR)............................................................... 227
8.10.3 Port A Input Data Register (PAPIN) ................................................................... 227
8.10.4 Pin Functions ....................................................................................................... 228
8.10.5 Input Pull-Up MOS.............................................................................................. 231
Port B ................................................................................................................................ 232
8.11.1 Port B Data Direction Register (PBDDR) ........................................................... 232
8.11.2 Port B Output Data Register (PBODR) ............................................................... 232
8.11.3 Port B Input Data Register (PBPIN).................................................................... 233
8.11.4 Pin Functions ....................................................................................................... 233
Port C ................................................................................................................................ 235
8.12.1 Port C Data Direction Register (PCDDR) ........................................................... 235
8.12.2 Port C Output Data Register (PCODR) ............................................................... 235
8.12.3 Port C Input Data Register (PCPIN).................................................................... 236
8.12.4 Pin Functions ....................................................................................................... 236
Port D................................................................................................................................ 238
8.13.1 Port D Data Direction Register (PDDDR)........................................................... 238
8.13.2 Port D Output Data Register (PDODR)............................................................... 239
8.13.3 Port D Input Data Register (PDPIN) ................................................................... 239
8.13.4 Pin Functions ....................................................................................................... 240
8.13.5 Input Pull-Up MOS.............................................................................................. 242
Port E ................................................................................................................................ 243
8.14.1 Port E Data Direction Register (PEDDR)............................................................ 243
8.14.2 Port E Output Data Register (PEODR)................................................................ 243
8.14.3 Port E Input Data Register (PEPIN) .................................................................... 244
8.14.4 Pin Functions ....................................................................................................... 244
Port F ................................................................................................................................ 246
8.15.1 Port F Data Direction Register (PFDDR) ............................................................ 246
8.15.2 Port F Output Data Register (PFODR) ................................................................ 246
8.15.3 Port F Input Data Register (PFPIN)..................................................................... 247
8.15.4 Pin Functions ....................................................................................................... 247
Change of Peripheral Function Pins.................................................................................. 248
8.16.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register
(ISSR) .................................................................................................................. 248
8.16.2 Port Control Register 0 (PTCNT0) ...................................................................... 250
Rev. 3.00, 03/04, page xiv of xl
Section 9 8-Bit PWM Timer (PWM).................................................................251
9.1
9.2
9.3
9.4
Features............................................................................................................................. 251
Input/Output Pins .............................................................................................................. 252
Register Descriptions ........................................................................................................ 252
9.3.1 PWM Register Select (PWSL)............................................................................. 253
9.3.2 PWM Data Registers 15 to 0 (PWDR15 to PWDR0).......................................... 255
9.3.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 255
9.3.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 256
9.3.5 Peripheral Clock Select Register (PCSR) ............................................................ 257
Operation .......................................................................................................................... 258
9.4.1 PWM Setting Example ........................................................................................ 260
9.4.2 Diagram of PWM Used as D/A Converter .......................................................... 260
Section 10 14-Bit PWM Timer (PWMX)..........................................................261
10.1 Features............................................................................................................................. 261
10.2 Input/Output Pins .............................................................................................................. 262
10.3 Register Descriptions ........................................................................................................ 262
10.3.1 PWMX (D/A) Counter (DACNT) ....................................................................... 263
10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB)......................... 264
10.3.3 PWMX (D/A) Control Register (DACR) ............................................................ 266
10.3.4 Peripheral Clock Select Register (PCSR) ............................................................ 267
10.4 Bus Master Interface ......................................................................................................... 268
10.5 Operation .......................................................................................................................... 269
Section 11 16-Bit Free-Running Timer (FRT) ..................................................277
11.1 Features............................................................................................................................. 277
11.2 Input/Output Pins .............................................................................................................. 279
11.3 Register Descriptions ........................................................................................................ 279
11.3.1 Free-Running Counter (FRC) .............................................................................. 280
11.3.2 Output Compare Registers A and B (OCRA and OCRB) ................................... 280
11.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 280
11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ......................... 281
11.3.5 Output Compare Register DM (OCRDM)........................................................... 281
11.3.6 Timer Interrupt Enable Register (TIER) .............................................................. 282
11.3.7 Timer Control/Status Register (TCSR)................................................................ 283
11.3.8 Timer Control Register (TCR)............................................................................. 286
11.3.9 Timer Output Compare Control Register (TOCR) .............................................. 287
11.4 Operation .......................................................................................................................... 289
11.4.1 Pulse Output......................................................................................................... 289
11.5 Operation Timing.............................................................................................................. 290
11.5.1 FRC Increment Timing ........................................................................................ 290
11.5.2 Output Compare Output Timing .......................................................................... 291
11.5.3 FRC Clear Timing ............................................................................................... 291
Rev. 3.00, 03/04, page xv of xl
11.5.4 Input Capture Input Timing ................................................................................. 292
11.5.5 Buffered Input Capture Input Timing .................................................................. 293
11.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 294
11.5.7 Timing of Output Compare Flag (OCF) setting................................................... 295
11.5.8 Timing of FRC Overflow Flag (OVF) Setting..................................................... 295
11.5.9 Automatic Addition Timing................................................................................. 296
11.5.10 Mask Signal Generation Timing.......................................................................... 296
11.6 Interrupt Sources............................................................................................................... 298
11.7 Usage Notes ...................................................................................................................... 299
11.7.1 Conflict between FRC Write and Clear ............................................................... 299
11.7.2 Conflict between FRC Write and Increment........................................................ 300
11.7.3 Conflict between OCR Write and Compare-Match ............................................. 301
11.7.4 Switching of Internal Clock and FRC Operation................................................. 302
Section 12 8-Bit Timer (TMR).......................................................................... 305
12.1 Features............................................................................................................................. 305
12.2 Input/Output Pins.............................................................................................................. 308
12.3 Register Descriptions........................................................................................................ 309
12.3.1 Timer Counter (TCNT)........................................................................................ 309
12.3.2 Time Constant Register A (TCORA) .................................................................. 310
12.3.3 Time Constant Register B (TCORB)................................................................... 310
12.3.4 Timer Control Register (TCR)............................................................................. 311
12.3.5 Timer Control/Status Register (TCSR)................................................................ 314
12.3.6 Input Capture Register (TICR) ............................................................................ 319
12.3.7 Time Constant Register C (TCORC)................................................................... 319
12.3.8 Input Capture Registers R and F (TICRR and TICRF)........................................ 319
12.3.9 Timer Input Select Register (TISR)..................................................................... 320
12.3.10 Timer Connection Register I (TCONRI) ............................................................. 320
12.3.11 Timer Connection Register S (TCONRS) ........................................................... 321
12.4 Operation .......................................................................................................................... 322
12.4.1 Pulse Output ........................................................................................................ 322
12.5 Operation Timing.............................................................................................................. 323
12.5.1 TCNT Count Timing ........................................................................................... 323
12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 323
12.5.3 Timing of Timer Output at Compare-Match........................................................ 324
12.5.4 Timing of Counter Clear at Compare-Match....................................................... 324
12.5.5 TCNT External Reset Timing.............................................................................. 325
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 325
12.6 TMR_0 and TMR_1 Cascaded Connection...................................................................... 326
12.6.1 16-Bit Count Mode .............................................................................................. 326
12.6.2 Compare-Match Count Mode .............................................................................. 326
12.7 Input Capture Operation ................................................................................................... 327
12.8 Interrupt Sources............................................................................................................... 329
Rev. 3.00, 03/04, page xvi of xl
12.9 Usage Notes ...................................................................................................................... 330
12.9.1 Conflict between TCNT Write and Counter Clear............................................... 330
12.9.2 Conflict between TCNT Write and Increment..................................................... 331
12.9.3 Conflict between TCOR Write and Compare-Match........................................... 332
12.9.4 Conflict between Compare-Matches A and B ..................................................... 333
12.9.5 Switching of Internal Clocks and TCNT Operation............................................. 333
12.9.6 Mode Setting with Cascaded Connection ............................................................ 335
Section 13 Watchdog Timer (WDT)..................................................................337
13.1 Features............................................................................................................................. 337
13.2 Input/Output Pins .............................................................................................................. 339
13.3 Register Descriptions ........................................................................................................ 340
13.3.1 Timer Counter (TCNT)........................................................................................ 340
13.3.2 Timer Control/Status Register (TCSR)................................................................ 340
13.4 Operation .......................................................................................................................... 344
13.4.1 Watchdog Timer Mode ........................................................................................ 344
13.4.2 Interval Timer Mode............................................................................................ 345
13.4.3 RESO Signal Output Timing ............................................................................... 346
13.5 Interrupt Sources............................................................................................................... 347
13.6 Usage Notes ...................................................................................................................... 348
13.6.1 Notes on Register Access..................................................................................... 348
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 349
13.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 349
13.6.4 Changing Value of PSS Bit.................................................................................. 349
13.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................ 350
13.6.6 System Reset by RESO Signal ............................................................................ 350
Section 14 Serial Communication Interface (SCI, IrDA, and CRC) ................351
14.1 Features............................................................................................................................. 351
14.2 Input/Output Pins .............................................................................................................. 355
14.3 Register Descriptions ........................................................................................................ 356
14.3.1 Receive Shift Register (RSR) .............................................................................. 356
14.3.2 Receive Data Register (RDR) .............................................................................. 356
14.3.3 Transmit Data Register (TDR)............................................................................. 357
14.3.4 Transmit Shift Register (TSR) ............................................................................. 357
14.3.5 Serial Mode Register (SMR) ............................................................................... 357
14.3.6 Serial Control Register (SCR) ............................................................................. 361
14.3.7 Serial Status Register (SSR) ................................................................................ 364
14.3.8 Smart Card Mode Register (SCMR).................................................................... 368
14.3.9 Bit Rate Register (BRR) ...................................................................................... 369
14.3.10 Serial Interface Control Register (SCICR) .......................................................... 375
14.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) .................... 376
14.4 Operation in Asynchronous Mode .................................................................................... 380
Rev. 3.00, 03/04, page xvii of xl
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.4.1 Data Transfer Format........................................................................................... 381
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode ................................................................................................................... 382
14.4.3 Clock.................................................................................................................... 383
14.4.4 Serial Enhanced Mode Clock .............................................................................. 383
14.4.5 SCI Initialization (Asynchronous Mode)............................................................. 386
14.4.6 Serial Data Transmission (Asynchronous Mode) ................................................ 387
14.4.7 Serial Data Reception (Asynchronous Mode) ..................................................... 389
Multiprocessor Communication Function......................................................................... 393
14.5.1 Multiprocessor Serial Data Transmission ............................................................ 395
14.5.2 Multiprocessor Serial Data Reception ................................................................. 396
Operation in Clock Synchronous Mode............................................................................ 399
14.6.1 Clock.................................................................................................................... 399
14.6.2 SCI Initialization (Clock Synchronous Mode)..................................................... 400
14.6.3 Serial Data Transmission (Clock Synchronous Mode)........................................ 401
14.6.4 Serial Data Reception (Clock Synchronous Mode) ............................................. 403
14.6.5 Simultaneous Serial Data Transmission and Reception
(Clock Synchronous Mode) ................................................................................. 405
14.6.6 SCI Selection in Serial Enhanced Mode .............................................................. 405
Smart Card Interface Description ..................................................................................... 407
14.7.1 Sample Connection.............................................................................................. 407
14.7.2 Data Format (Except in Block Transfer Mode) ................................................... 407
14.7.3 Block Transfer Mode ........................................................................................... 409
14.7.4 Receive Data Sampling Timing and Reception Margin ...................................... 409
14.7.5 Initialization......................................................................................................... 410
14.7.6 Serial Data Transmission (Except in Block Transfer Mode) ............................... 411
14.7.7 Serial Data Reception (Except in Block Transfer Mode) .................................... 414
14.7.8 Clock Output Control........................................................................................... 415
IrDA Operation ................................................................................................................. 417
Interrupt Sources............................................................................................................... 420
14.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 420
14.9.2 Interrupts in Smart Card Interface Mode ............................................................. 421
Usage Notes ...................................................................................................................... 422
14.10.1 Module Stop Mode Setting .................................................................................. 422
14.10.2 Break Detection and Processing .......................................................................... 422
14.10.3 Mark State and Break Sending ............................................................................ 422
14.10.4 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ........................................................................ 422
14.10.5 Relation between Writing to TDR and TDRE Flag ............................................. 422
14.10.6 Restrictions on Using DTC.................................................................................. 423
14.10.7 SCI Operations during Mode Transitions ............................................................ 423
14.10.8 Notes on Switching from SCK Pins to Port Pins ................................................. 427
CRC Operation Circuit ..................................................................................................... 428
Rev. 3.00, 03/04, page xviii of xl
14.11.1 Features................................................................................................................ 428
14.11.2 Register Descriptions........................................................................................... 428
14.11.3 CRC Operation Circuit Operation........................................................................ 430
14.11.4 Note on CRC Operation Circuit........................................................................... 433
Section 15 I2C Bus Interface (IIC) .....................................................................435
15.1 Features............................................................................................................................. 435
15.2 Input/Output Pins .............................................................................................................. 438
15.3 Register Descriptions ........................................................................................................ 439
15.3.1 I2C Bus Data Register (ICDR) ............................................................................. 439
15.3.2 Slave Address Register (SAR)............................................................................. 440
15.3.3 Second Slave Address Register (SARX) ............................................................. 441
15.3.4 I2C Bus Mode Register (ICMR)........................................................................... 442
15.3.5 I2C Bus Transfer Rate Select Register (IICX3).................................................... 443
15.3.6 I2C Bus Control Register (ICCR)......................................................................... 446
15.3.7 I2C Bus Status Register (ICSR)............................................................................ 455
15.3.8 I2C Bus Extended Control Register (ICXR)......................................................... 459
15.3.9 I2C SMBus Control Register (ICSMBCR)........................................................... 463
15.4 Operation .......................................................................................................................... 465
15.4.1 I2C Bus Data Format ............................................................................................ 465
15.4.2 Initialization ......................................................................................................... 467
15.4.3 Master Transmit Operation .................................................................................. 467
15.4.4 Master Receive Operation.................................................................................... 471
15.4.5 Slave Receive Operation...................................................................................... 478
15.4.6 Slave Transmit Operation .................................................................................... 485
15.4.7 IRIC Setting Timing and SCL Control ................................................................ 488
15.4.8 Operation Using the DTC .................................................................................... 490
15.4.9 Noise Canceler..................................................................................................... 492
15.4.10 Initialization of Internal State .............................................................................. 492
15.5 Interrupt Source ................................................................................................................ 494
15.6 Usage Notes ...................................................................................................................... 495
Section 16 LPC Interface (LPC) ........................................................................507
16.1 Features............................................................................................................................. 507
16.2 Input/Output Pins .............................................................................................................. 509
16.3 Register Descriptions ........................................................................................................ 510
16.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 512
16.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 518
16.3.3 Host Interface Control Register 4 (HICR4) ......................................................... 521
16.3.4 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................ 522
16.3.5 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L).................... 526
16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 527
16.3.7 Output Data Registers 0 to 3 (ODR1 to ODR3) .................................................. 527
Rev. 3.00, 03/04, page xix of xl
16.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15).................................... 528
16.3.9 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 529
16.3.10 SERIRQ Control Register 0 (SIRQCR0)............................................................. 536
16.3.11 SERIRQ Control Register 1 (SIRQCR1)............................................................. 539
16.3.12 SERIRQ Control Register 2 (SIRQCR2)............................................................. 544
16.3.13 Host Interface Select Register (HISEL)............................................................... 545
16.3.14 SMIC Flag Register (SMICFLG) ........................................................................ 546
16.3.15 SMIC Control Status Register (SMICCSR)......................................................... 548
16.3.16 SMIC Data Register (SMICDTR) ....................................................................... 548
16.3.17 SMIC Interrupt Register 0 (SMICIR0) ................................................................ 548
16.3.18 SMIC Interrupt Register 1 (SMICIR1) ................................................................ 551
16.3.19 BT Status Register 0 (BTSR0)............................................................................. 552
16.3.20 BT Status Register 1 (BTSR1)............................................................................. 554
16.3.21 BT Control Status Register 0 (BTCSR0)............................................................. 557
16.3.22 BT Control Status Register 1 (BTCSR1)............................................................. 558
16.3.23 BT Control Register (BTCR)............................................................................... 560
16.3.24 BT Data Buffer (BTDTR).................................................................................... 563
16.3.25 BT Interrupt Mask Register (BTIMSR)............................................................... 564
16.3.26 BT FIFO Valid Size Register 0 (BTFVSR0) ....................................................... 566
16.3.27 BT FIFO Valid Size Register 1 (BTFVSR1) ....................................................... 566
16.4 Operation .......................................................................................................................... 567
16.4.1 LPC Interface Activation ..................................................................................... 567
16.4.2 LPC I/O Cycles.................................................................................................... 567
16.4.3 SMIC Mode Transfer Flow.................................................................................. 569
16.4.4 BT Mode Transfer Flow ...................................................................................... 572
16.4.5 A20 Gate.............................................................................................................. 574
16.4.6 LPC Interface Shutdown Function (LPCPD)....................................................... 577
16.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ) .................................... 581
16.4.8 LPC Interface Clock Start Request ...................................................................... 583
16.5 Interrupt Sources............................................................................................................... 584
16.5.1 IBFI1, IBFI2, IBFI3, ERRI.................................................................................. 584
16.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 .............................. 584
16.6 Usage Notes ...................................................................................................................... 587
16.6.1 Module Stop Setting ............................................................................................ 587
16.6.2 Usage Note of LPC Interface............................................................................... 587
Section 17 D/A Converter ................................................................................. 589
17.1 Features............................................................................................................................. 589
17.2 Input/Output Pins.............................................................................................................. 590
17.3 Register Descriptions........................................................................................................ 591
17.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 591
17.3.2 D/A Control Register (DACR) ............................................................................ 591
17.4 Operation .......................................................................................................................... 593
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17.5 Usage Note........................................................................................................................ 594
Section 18 A/D Converter..................................................................................595
18.1 Features............................................................................................................................. 595
18.1.1 Block Diagram..................................................................................................... 596
18.2 Input/Output Pins .............................................................................................................. 597
18.3 Register Descriptions ........................................................................................................ 598
18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 598
18.3.2 A/D Control/Status Register (ADCSR) ............................................................... 599
18.3.3 A/D Control Register (ADCR) ............................................................................ 600
18.4 Operation .......................................................................................................................... 601
18.4.1 Single Mode......................................................................................................... 601
18.4.2 Scan Mode ........................................................................................................... 601
18.4.3 Input Sampling and A/D Conversion Time ......................................................... 602
18.4.4 External Trigger Input Timing............................................................................. 603
18.5 Interrupt Source ................................................................................................................ 604
18.6 A/D Conversion Accuracy Definitions ............................................................................. 604
18.7 Usage Notes ...................................................................................................................... 606
18.7.1 Permissible Signal Source Impedance ................................................................. 606
18.7.2 Influences on Absolute Accuracy ........................................................................ 606
18.7.3 Setting Range of Analog Power Supply and Other Pins ...................................... 607
18.7.4 Notes on Board Design ........................................................................................ 607
18.7.5 Notes on Noise Countermeasures ........................................................................ 607
Section 19 RAM ................................................................................................609
Section 20 Flash Memory (0.18-µm F-ZTAT Version) ....................................611
20.1 Features............................................................................................................................. 611
20.1.1 Operating Mode ................................................................................................... 613
20.1.2 Mode Comparison................................................................................................ 614
20.1.3 Flash Memory MAT Configuration..................................................................... 615
20.1.4 Block Division ..................................................................................................... 616
20.1.5 Programming/Erasing Interface ........................................................................... 618
20.2 Input/Output Pins .............................................................................................................. 620
20.3 Register Descriptions ........................................................................................................ 620
20.3.1 Programming/Erasing Interface Register............................................................. 621
20.3.2 Programming/Erasing Interface Parameter .......................................................... 628
20.4 On-Board Programming Mode ......................................................................................... 638
20.4.1 Boot Mode ........................................................................................................... 638
20.4.2 User Program Mode............................................................................................. 642
20.4.3 User Boot Mode................................................................................................... 652
20.4.4 Procedure Program and Storable Area for Programming Data ............................ 655
20.5 Protection .......................................................................................................................... 665
Rev. 3.00, 03/04, page xxi of xl
20.6
20.7
20.8
20.9
20.5.1 Hardware Protection ............................................................................................ 665
20.5.2 Software Protection ............................................................................................. 666
20.5.3 Error Protection ................................................................................................... 666
Switching between User MAT and User Boot MAT........................................................ 668
Programmer Mode ............................................................................................................ 669
Serial Communication Interface Specification for Boot Mode......................................... 670
Usage Notes ...................................................................................................................... 695
Section 21 Boundary Scan (JTAG) ................................................................... 697
21.1 Features............................................................................................................................. 697
21.2 Input/Output Pins.............................................................................................................. 699
21.3 Register Descriptions........................................................................................................ 700
21.3.1 Instruction Register (SDIR) ................................................................................. 701
21.3.2 Bypass Register (SDBPR) ................................................................................... 703
21.3.3 Boundary Scan Register (SDBSR) ...................................................................... 703
21.3.4 ID Code Register (SDIDR).................................................................................. 713
21.4 Operation .......................................................................................................................... 714
21.4.1 TAP Controller State Transitions......................................................................... 714
21.4.2 JTAG Reset.......................................................................................................... 715
21.5 Boundary Scan.................................................................................................................. 715
21.5.1 Supported Instructions ......................................................................................... 715
21.6 Usage Notes ...................................................................................................................... 718
Section 22 Clock Pulse Generator..................................................................... 721
22.1 Oscillator........................................................................................................................... 722
22.1.1 Connecting Crystal Resonator ............................................................................. 722
22.1.2 External Clock Input Method .............................................................................. 723
22.2 PLL Multiplier Circuit ...................................................................................................... 724
22.3 Medium-Speed Clock Divider .......................................................................................... 724
22.4 Bus Master Clock Select Circuit....................................................................................... 724
22.5 Subclock Input Circuit ...................................................................................................... 724
22.6 Subclock Waveform Forming Circuit............................................................................... 724
22.7 Clock Select Circuit .......................................................................................................... 725
22.8 Usage Notes ...................................................................................................................... 725
22.8.1 Note on Resonator ............................................................................................... 725
22.8.2 Notes on Board Design ........................................................................................ 725
22.8.3 Note on Operation Check .................................................................................... 726
Section 23 Power-Down Modes........................................................................ 727
23.1 Register Descriptions........................................................................................................ 728
23.1.1 Standby Control Register (SBYCR) .................................................................... 728
23.1.2 Low-Power Control Register (LPWRCR) ........................................................... 730
Rev. 3.00, 03/04, page xxii of xl
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
23.11
23.12
23.1.3 Module Stop Control Registers H, L, and A
(MSTPCRH, MSTPCRL, MSTPCRA) ............................................................... 732
23.1.4 Sub-Chip Module Stop Control Registers BH, BL
(SUBMSTPBH, SUBMSTPBL) ......................................................................... 734
23.1.5 Sub-Chip Module Stop Control Registers AH, AL
(SUBMSTPAH, SUBMSTPAL) ......................................................................... 734
Mode Transitions and LSI States ...................................................................................... 735
Medium-Speed Mode........................................................................................................ 739
Sleep Mode ....................................................................................................................... 740
Software Standby Mode.................................................................................................... 741
Hardware Standby Mode .................................................................................................. 743
Watch Mode...................................................................................................................... 744
Subsleep Mode.................................................................................................................. 745
Subactive Mode ................................................................................................................ 746
Module Stop Mode ........................................................................................................... 747
Direct Transitions.............................................................................................................. 747
Usage Notes ...................................................................................................................... 748
23.12.1 I/O Port Status...................................................................................................... 748
23.12.2 Current Consumption when Waiting for Oscillation Settling .............................. 748
23.12.3 DTC Module Stop Mode ..................................................................................... 748
23.12.4 Notes on Subclock Usage .................................................................................... 748
Section 24 List of Registers ...............................................................................749
24.1 Register Addresses (Address Order)................................................................................. 749
24.2 Register Bits...................................................................................................................... 762
24.3 Register States in Each Operating Mode .......................................................................... 773
Section 25 Electrical Characteristics .................................................................783
25.1 Absolute Maximum Ratings ............................................................................................. 783
25.2 DC Characteristics ............................................................................................................ 784
25.3 AC Characteristics ............................................................................................................ 788
25.3.1 Clock Timing ....................................................................................................... 788
25.3.2 Control Signal Timing ......................................................................................... 792
25.3.3 Bus Timing .......................................................................................................... 794
25.3.4 Multiplex Bus Timing.......................................................................................... 800
25.3.5 Timing of On-Chip Peripheral Modules .............................................................. 802
25.4 A/D Conversion Characteristics........................................................................................ 811
25.5 D/A Conversion Characteristics........................................................................................ 812
25.6 Flash Memory Characteristics .......................................................................................... 813
25.7 Usage Notes ...................................................................................................................... 816
Rev. 3.00, 03/04, page xxiii of xl
Appendix
A.
B.
C.
......................................................................................................... 817
I/O Port States in Each Pin State....................................................................................... 817
Product Lineup.................................................................................................................. 819
Package Dimensions ......................................................................................................... 820
Main Revisions and Additions in this Edition..................................................... 821
Index
......................................................................................................... 825
Rev. 3.00, 03/04, page xxiv of xl
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement (TFP-144).......................................................................................... 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 19
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 19
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 20
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 21
Figure 2.5 Memory Map............................................................................................................... 22
Figure 2.6 CPU Internal Registers ................................................................................................ 23
Figure 2.7 Usage of General Registers ......................................................................................... 24
Figure 2.8 Stack............................................................................................................................ 25
Figure 2.9 General Register Data Formats (1).............................................................................. 28
Figure 2.9 General Register Data Formats (2).............................................................................. 29
Figure 2.10 Memory Data Formats............................................................................................... 30
Figure 2.11 Instruction Formats (Examples) ................................................................................ 42
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 46
Figure 2.13 State Transitions ........................................................................................................ 50
Section 3
Figure 3.1
Figure 3.2
Figure 3.3
MCU Operating Modes
H8S/2168 Address Map .............................................................................................. 60
H8S/2167 Address Map .............................................................................................. 61
H8S/2166 Address Map .............................................................................................. 62
Section 4
Figure 4.1
Figure 4.2
Figure 4.3
Exception Handling
Reset Sequence............................................................................................................ 67
Stack Status after Exception Handling ........................................................................ 69
Operation when SP Value Is Odd................................................................................ 70
Interrupt Controller
Block Diagram of Interrupt Controller........................................................................ 72
Block Diagram of Interrupts IRQ15 to IRQ0 .............................................................. 82
Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE8
(Example of KIN15 to KIN0) ...................................................................................... 83
Figure 5.4 Block Diagram of Interrupt Control Operation ........................................................... 88
Figure 5.5 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 91
Figure 5.6 State Transition in Interrupt Control Mode 1 .............................................................. 92
Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 94
Figure 5.8 Interrupt Exception Handling ...................................................................................... 95
Figure 5.9 Interrupt Control for DTC ........................................................................................... 97
Figure 5.10 Conflict between Interrupt Generation and Disabling............................................... 99
Section 5
Figure 5.1
Figure 5.2
Figure 5.3
Rev. 3.00, 03/04, page xxv of xl
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 103
Figure 6.2 IOS Signal Output Timing ........................................................................................ 123
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space).............................. 124
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 125
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 127
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 128
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)........................... 129
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................ 130
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 131
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......................... 132
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) .......................... 133
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 134
Figure 6.13 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 135
Figure 6.14 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 135
Figure 6.15 Bus Timing for 8-Bit, 3-State Access Space ........................................................... 136
Figure 6.16 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) ................... 137
Figure 6.17 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) ................... 137
Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) .................... 138
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) .................... 138
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)........................... 139
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)........................... 139
Figure 6.22 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) ................... 140
Figure 6.23 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) .................... 140
Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)........................... 141
Figure 6.25 Example of Wait State Insertion Timing (Pin Wait Mode) ..................................... 142
Figure 6.26 Example of Wait State Insertion Timing................................................................. 144
Figure 6.27 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1).................... 145
Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0).................... 146
Figure 6.29 Examples of Idle Cycle Operation .......................................................................... 147
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC ............................................................................................. 150
Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 161
Figure 7.3 DTC Register Information Location in Address Space............................................. 162
Figure 7.4 DTC Operation Flowchart......................................................................................... 165
Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 166
Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 167
Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 168
Figure 7.8 Chain Transfer Operation.......................................................................................... 169
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 170
Figure 7.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ...................................... 171
Rev. 3.00, 03/04, page xxvi of xl
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 171
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit .............................................................................................. 208
Figure 8.2 Noise Canceler Operation.......................................................................................... 208
Section 9
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
8-Bit PWM Timer (PWM)
Block Diagram of PWM Timer ................................................................................. 251
Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 259
Example of PWM Setting.......................................................................................... 260
Example when PWM is Used as D/A Converter....................................................... 260
Section 10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
14-Bit PWM Timer (PWMX)
PWMX (D/A) Block Diagram................................................................................. 261
PWMX (D/A) Operation ......................................................................................... 269
Output Waveform (OS = 0, DADR corresponds to TL) .......................................... 272
Output Waveform (OS = 1, DADR corresponds to TH) .......................................... 273
D/A Data Register Configuration when CFS = 1 .................................................... 273
Output Waveform when DADR = H'0207 (OS = 1) ............................................... 274
Section 11 16-Bit Free-Running Timer (FRT)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 278
Figure 11.2 Example of Pulse Output......................................................................................... 289
Figure 11.3 Increment Timing with Internal Clock Source ........................................................ 290
Figure 11.4 Increment Timing with External Clock Source ....................................................... 290
Figure 11.5 Timing of Output Compare A Output ..................................................................... 291
Figure 11.6 Clearing of FRC by Compare-Match A Signal ....................................................... 291
Figure 11.7 Input Capture Input Signal Timing (Usual Case) .................................................... 292
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)....................... 292
Figure 11.9 Buffered Input Capture Timing ............................................................................... 293
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ...................................................... 294
Figure 11.11 Timing of Input Capture Flag (ICFA to ICFD) Setting......................................... 294
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................. 295
Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 295
Figure 11.14 OCRA Automatic Addition Timing ...................................................................... 296
Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 296
Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 297
Figure 11.17 Conflict between FRC Write and Clear................................................................. 299
Figure 11.18 Conflict between FRC Write and Increment ......................................................... 300
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)............................................... 301
Figure 11.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)...................................................... 302
Rev. 3.00, 03/04, page xxvii of xl
Section 12 8-Bit Timer (TMR)
Figure 12.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 306
Figure 12.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 307
Figure 12.3 Pulse Output Example ............................................................................................. 322
Figure 12.4 Count Timing for Internal Clock Input ................................................................... 323
Figure 12.5 Count Timing for External Clock Input .................................................................. 323
Figure 12.6 Timing of CMF Setting at Compare-Match ............................................................ 324
Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 324
Figure 12.8 Timing of Counter Clear by Compare-Match ......................................................... 324
Figure 12.9 Timing of Counter Clear by External Reset Input................................................... 325
Figure 12.10 Timing of OVF Flag Setting ................................................................................. 325
Figure 12.11 Timing of Input Capture Operation....................................................................... 327
Figure 12.12 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read) ............................. 328
Figure 12.13 Conflict between TCNT Write and Counter Clear ................................................ 330
Figure 12.14 Conflict between TCNT Write and Increment ...................................................... 331
Figure 12.15 Conflict between TCOR Write and Compare-Match ............................................ 332
Section 13
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Watchdog Timer (WDT)
Block Diagram of WDT .......................................................................................... 338
Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 344
Interval Timer Mode Operation............................................................................... 345
OVF Flag Set Timing .............................................................................................. 345
Output Timing of RESO signal ............................................................................... 346
Writing to TCNT and TCSR (WDT_0)................................................................... 348
Conflict between TCNT Write and Increment ........................................................ 349
Sample Circuit for Resetting the System by the RESO Signal................................ 350
Serial Communication Interface (SCI, IrDA, and CRC)
Block Diagram of SCI_1......................................................................................... 353
Block Diagram of SCI_0 and SCI_2 ....................................................................... 354
Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................... 380
Figure 14.4 Receive Data Sampling Timing in Asynchronous Mode ........................................ 382
Figure 14.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode).............................................................................................. 383
Figure 14.6 Basic Clock Examples When Average Transfer Rate is Selected (1) ..................... 384
Figure 14.7 Basic Clock Examples When Average Transfer Rate is Selected (2) ..................... 385
Figure 14.8 Sample SCI Initialization Flowchart ....................................................................... 386
Figure 14.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................... 387
Figure 14.10 Sample Serial Transmission Flowchart ................................................................. 388
Section 14
Figure 14.1
Figure 14.2
Figure 14.3
Rev. 3.00, 03/04, page xxviii of xl
Figure 14.11 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)................................................... 389
Figure 14.12 Sample Serial Reception Flowchart (1)................................................................. 391
Figure 14.12 Sample Serial Reception Flowchart (2)................................................................. 392
Figure 14.13 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)........................................... 394
Figure 14.14 Sample Multiprocessor Serial Transmission Flowchart ........................................ 395
Figure 14.15 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 396
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 397
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 398
Figure 14.17 Data Format in Synchronous Communication (LSB-First)................................... 399
Figure 14.18 Sample SCI Initialization Flowchart ..................................................................... 400
Figure 14.19 Sample SCI Transmission Operation in Clock Synchronous Mode ...................... 401
Figure 14.20 Sample Serial Transmission Flowchart ................................................................. 402
Figure 14.21 Example of SCI Receive Operation in Clock Synchronous Mode ........................ 403
Figure 14.22 Sample Serial Reception Flowchart ...................................................................... 404
Figure 14.23 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 406
Figure 14.24 Pin Connection for Smart Card Interface .............................................................. 407
Figure 14.25 Data Formats in Normal Smart Card Interface Mode............................................ 408
Figure 14.26 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 408
Figure 14.27 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 408
Figure 14.28 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate) ............................................. 410
Figure 14.29 Data Re-transfer Operation in SCI Transmission Mode........................................ 412
Figure 14.30 TEND Flag Set Timings during Transmission ...................................................... 412
Figure 14.31 Sample Transmission Flowchart ........................................................................... 413
Figure 14.32 Data Re-transfer Operation in SCI Reception Mode ............................................. 414
Figure 14.33 Sample Reception Flowchart................................................................................. 415
Figure 14.34 Clock Output Fixing Timing ................................................................................. 415
Figure 14.35 Clock Stop and Restart Procedure ......................................................................... 416
Figure 14.36 IrDA Block Diagram ............................................................................................. 417
Figure 14.37 IrDA Transmission and Reception ........................................................................ 418
Figure 14.38 Sample Transmission using DTC in Clock Synchronous Mode ........................... 423
Figure 14.39 Sample Flowchart for Mode Transition during Transmission............................... 424
Figure 14.40 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 425
Figure 14.41 Pin States during Transmission in Clock Synchronous Mode
(Internal Clock)...................................................................................................... 425
Figure 14.42 Sample Flowchart for Mode Transition during Reception .................................... 426
Figure 14.43 Switching from SCK Pins to Port Pins.................................................................. 427
Figure 14.44 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 427
Figure 14.45 Block Diagram of CRC Operation Circuit ............................................................ 428
Figure 14.46 LSB-First Data Transmission ................................................................................ 430
Rev. 3.00, 03/04, page xxix of xl
Figure 14.47
Figure 14.48
Figure 14.49
Figure 14.50
MSB-First Data Transmission............................................................................... 430
LSB-First Data Reception ..................................................................................... 431
MSB-First Data Reception .................................................................................... 432
LSB-First and MSB-First Transmit Data .............................................................. 433
I2C Bus Interface (IIC)
Block Diagram of I2C Bus Interface ....................................................................... 436
I2C Bus Interface Connections (Example: This LSI as Master) .............................. 437
I2C Bus Data Formats (I2C Bus Formats)................................................................ 465
I2C Bus Data Formats (Serial Formats)................................................................... 465
I2C Bus Timing........................................................................................................ 466
Sample Flowchart for IIC Initialization .................................................................. 467
Sample Flowchart for Operations in Master Transmit Mode .................................. 468
Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)........... 470
Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0) ................................................................................................. 470
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 471
Figure 15.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................. 473
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1) .................................................................. 474
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) .................................................................... 475
Figure 15.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 477
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 478
Figure 15.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 479
Figure 15.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)....... 481
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 481
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 482
Figure 15.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 484
Figure 15.23 Sample Flowchart for Slave Transmit Mode......................................................... 485
Figure 15.24 Slave Transmit Mode Operation Timing Example (MLS = 0).............................. 487
Figure 15.25 IRIC Setting Timing and SCL Control (1) ............................................................ 488
Figure 15.26 IRIC Setting Timing and SCL Control (2) ............................................................ 489
Figure 15.27 IRIC Setting Timing and SCL Control (3) ............................................................ 490
Figure 15.28 Block Diagram of Noise Canceler......................................................................... 492
Section 15
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
Figure 15.9
Rev. 3.00, 03/04, page xxx of xl
Figure 15.29 Notes on Reading Master Receive Data ................................................................ 500
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................. 501
Figure 15.31 Stop Condition Issuance Timing ........................................................................... 502
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 502
Figure 15.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit
Mode ...................................................................................................................... 503
Figure 15.34 TRS Bit Set Timing in Slave Mode....................................................................... 504
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost ...................................... 506
Section 16 LPC Interface (LPC)
Figure 16.1 Block Diagram of LPC............................................................................................ 508
Figure 16.2 Typical LFRAME Timing....................................................................................... 569
Figure 16.3 Abort Mechanism .................................................................................................... 569
Figure 16.4 SMIC Write Transfer Flow ..................................................................................... 570
Figure 16.5 SMIC Read Transfer Flow ...................................................................................... 571
Figure 16.6 BT Write Transfer Flow .......................................................................................... 572
Figure 16.7 BT Read Transfer Flow........................................................................................... 573
Figure 16.8 GA20 Output ........................................................................................................... 575
Figure 16.9 Power-Down State Termination Timing ................................................................. 580
Figure 16.10 SERIRQ Timing .................................................................................................... 581
Figure 16.11 Clock Start or Speed-Up........................................................................................ 583
Figure 16.12 HIRQ Flowchart (Example of Channel 1)............................................................. 586
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter ........................................................................... 589
Figure 17.2 D/A Converter Operation Example ......................................................................... 593
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Figure 18.6
Figure 18.7
Figure 18.8
A/D Converter
Block Diagram of A/D Converter ........................................................................... 596
A/D Conversion Timing .......................................................................................... 602
External Trigger Input Timing ................................................................................ 603
A/D Conversion Accuracy Definitions.................................................................... 605
A/D Conversion Accuracy Definitions.................................................................... 605
Example of Analog Input Circuit ............................................................................ 606
Example of Analog Input Protection Circuit ........................................................... 608
Analog Input Pin Equivalent Circuit ....................................................................... 608
Section 20
Figure 20.1
Figure 20.2
Figure 20.3
Figure 20.4
Figure 20.5
Figure 20.6
Flash Memory (0.18-µm F-ZTAT Version)
Block Diagram of Flash Memory............................................................................ 612
Mode Transition of Flash Memory.......................................................................... 613
Flash Memory Configuration .................................................................................. 615
Block Division of User MAT .................................................................................. 617
Overview of User Procedure Program..................................................................... 618
System Configuration in Boot Mode....................................................................... 639
Rev. 3.00, 03/04, page xxxi of xl
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 639
Figure 20.8 Overview of Boot Mode State Transition Diagram................................................. 641
Figure 20.9 Programming/Erasing Overview Flow.................................................................... 642
Figure 20.10 RAM Map When Programming/Erasing is Executed ........................................... 643
Figure 20.11 Programming Procedure........................................................................................ 644
Figure 20.12 Erasing Procedure ................................................................................................. 649
Figure 20.13 Repeating Procedure of Erasing and Programming............................................... 651
Figure 20.14 Procedure for Programming User MAT in User Boot Mode ................................ 653
Figure 20.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 654
Figure 20.16 Transitions to Error-Protection State..................................................................... 667
Figure 20.17 Switching between the User MAT and User Boot MAT ...................................... 668
Figure 20.18 Memory Map in Programmer Mode...................................................................... 669
Figure 20.19 Boot Program States.............................................................................................. 671
Figure 20.20 Bit-Rate-Adjustment Sequence ............................................................................. 672
Figure 20.21 Communication Protocol Format .......................................................................... 673
Figure 20.22 New Bit-Rate Selection Sequence......................................................................... 683
Figure 20.23 Programming Sequence......................................................................................... 686
Figure 20.24 Erasure Sequence .................................................................................................. 689
Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Boundary Scan (JTAG)
JTAG Block Diagram.............................................................................................. 698
TAP Controller State Transitions ............................................................................ 714
Reset Signal Circuit Without Reset Signal Interference.......................................... 718
Serial Data Input/Output (1).................................................................................... 719
Serial Data Input/Output (2).................................................................................... 720
Section 22
Figure 22.1
Figure 22.2
Figure 22.3
Figure 22.4
Figure 22.5
Clock Pulse Generator
Block Diagram of Clock Pulse Generator ............................................................... 721
Typical Connection to Crystal Resonator................................................................ 722
Equivalent Circuit of Crystal Resonator.................................................................. 722
Example of External Clock Input ............................................................................ 723
Note on Board Design of Oscillation Circuit Section .............................................. 725
Section 23
Figure 23.1
Figure 23.2
Figure 23.3
Figure 23.4
Power-Down Modes
Mode Transition Diagram ....................................................................................... 736
Medium-Speed Mode Timing ................................................................................. 740
Software Standby Mode Application Example ....................................................... 742
Hardware Standby Mode Timing ............................................................................ 743
Section 25
Figure 25.1
Figure 25.2
Figure 25.3
Figure 25.4
Figure 25.5
Electrical Characteristics
Darlington Transistor Drive Circuit (Example)....................................................... 787
LED Drive Circuit (Example) ................................................................................. 787
Output Load Circuit ................................................................................................ 788
System Clock Timing.............................................................................................. 789
Oscillation Stabilization Timing.............................................................................. 790
Rev. 3.00, 03/04, page xxxii of xl
Figure 25.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 790
Figure 25.7 External Clock Input Timing................................................................................... 790
Figure 25.8 Timing of External Clock Output Stabilization Delay Time ................................... 791
Figure 25.9 Subclock Input Timing ............................................................................................ 791
Figure 25.10 Reset Input Timing................................................................................................ 792
Figure 25.11 Interrupt Input Timing........................................................................................... 793
Figure 25.12 Basic Bus Timing/2-State Access.......................................................................... 795
Figure 25.13 Basic Bus Timing/3-State Access.......................................................................... 796
Figure 25.14 Basic Bus Timing/3-State Access with One Wait State ........................................ 797
Figure 25.15 Burst ROM Access Timing/2-State Access........................................................... 798
Figure 25.16 Burst ROM Access Timing/1-State Access........................................................... 799
Figure 25.17 Multiplex Bus Timing/Data 2-State Access .......................................................... 801
Figure 25.18 Multiplex Bus Timing/Data 3-State Access .......................................................... 801
Figure 25.19 I/O Port Input/Output Timing................................................................................ 804
Figure 25.20 FRT Input/Output Timing ..................................................................................... 804
Figure 25.21 FRT Clock Input Timing ....................................................................................... 804
Figure 25.22 8-Bit Timer Output Timing ................................................................................... 804
Figure 25.23 8-Bit Timer Clock Input Timing ........................................................................... 805
Figure 25.24 8-Bit Timer Reset Input Timing ............................................................................ 805
Figure 25.25 PWM, PWMX Output Timing .............................................................................. 805
Figure 25.26 SCK Clock Input Timing....................................................................................... 805
Figure 25.27 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 806
Figure 25.28 A/D Converter External Trigger Input Timing...................................................... 806
Figure 25.29 WDT Output Timing (RESO) ............................................................................... 806
Figure 25.30 I2C Bus Interface Input/Output Timing ................................................................. 808
Figure 25.31 LPC Interface (LPC) Timing................................................................................. 809
Figure 25.32 JTAG ETCK Timing ............................................................................................. 810
Figure 25.33 Reset Hold Timing ................................................................................................ 810
Figure 25.34 JTAG Input/Output Timing................................................................................... 810
Figure 25.35 Connection of VCL Capacitor............................................................................... 816
Appendix
Figure C.1 Package Dimensions (TFP-144) ............................................................................... 820
Rev. 3.00, 03/04, page xxxiii of xl
Rev. 3.00, 03/04, page xxxiv of xl
Tables
Section 1 Overview
Table 1.1
Pin Arrangement in Each Operating Mode............................................................... 4
Table 1.2
Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1
Instruction Classification ........................................................................................ 31
Table 2.2
Operation Notation ................................................................................................. 32
Table 2.3
Data Transfer Instructions....................................................................................... 33
Table 2.4
Arithmetic Operations Instructions (1) ................................................................... 34
Table 2.4
Arithmetic Operations Instructions (2) ................................................................... 35
Table 2.5
Logic Operations Instructions................................................................................. 36
Table 2.6
Shift Instructions..................................................................................................... 36
Table 2.7
Bit Manipulation Instructions (1)............................................................................ 37
Table 2.7
Bit Manipulation Instructions (2)............................................................................ 38
Table 2.8
Branch Instructions ................................................................................................. 39
Table 2.9
System Control Instructions.................................................................................... 40
Table 2.10
Block Data Transfer Instructions ............................................................................ 41
Table 2.11
Addressing Modes .................................................................................................. 43
Table 2.12
Absolute Address Access Ranges ........................................................................... 45
Table 2.13
Effective Address Calculation (1)........................................................................... 47
Table 2.13
Effective Address Calculation (2)........................................................................... 48
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection ............................................................................ 53
Table 3.2
Pin Functions in Each Mode ................................................................................... 59
Section 4 Exception Handling
Table 4.1
Exception Types and Priority.................................................................................. 63
Table 4.2
Exception Handling Vector Table........................................................................... 64
Table 4.2
Exception Handling Vector Table (cont) ................................................................ 65
Table 4.3
Status of CCR after Trap Instruction Exception Handling ..................................... 68
Section 5 Interrupt Controller
Table 5.1
Pin Configuration.................................................................................................... 73
Table 5.2
Correspondence between Interrupt Source and ICR ............................................... 75
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 85
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) ...................... 86
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) ...................... 87
Table 5.4
Interrupt Control Modes ......................................................................................... 88
Table 5.5
Interrupts Selected in Each Interrupt Control Mode ............................................... 89
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode............ 90
Table 5.7
Interrupt Response Times ....................................................................................... 96
Rev. 3.00, 03/04, page xxxv of xl
Table 5.8
Table 5.9
Number of States in Interrupt Handling Routine Execution Status ........................ 96
Interrupt Source Selection and Clearing Control .................................................... 98
Section 6 Bus Controller (BSC)
Table 6.1
Pin Configuration.................................................................................................. 104
Table 6.2
Address Ranges and External Address Spaces ..................................................... 113
Table 6.3
Bit Settings and Bus Specifications of Basic Bus Interface.................................. 114
Table 6.4
Bus Specifications for Basic Extended Area/Basic Bus Interface ........................ 115
Table 6.5
Bus Specifications for 256-kbyte Extended Area/Basic Bus Interface................. 116
Table 6.6
Bus Specifications for CP Extended Area (Basic Mode)/Basic Bus Interface ..... 117
Table 6.7
Address-Data Multiplex Address Spaces.............................................................. 119
Table 6.8
Bit Settings and Bus Specifications of Basic Bus Interface.................................. 120
Table 6.9
Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Address Cycle) .................................................................................................... 120
Table 6.10
Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 120
Table 6.11
Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Address Cycle).................................................................................................... 121
Table 6.12
Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 121
Table 6.13
Bus Specifications for CP Extended Area/Multiplex Bus Interface
(Address Cycle).................................................................................................... 121
Table 6.14
Bus Specifications for CP Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 122
Table 6.15
Address Range for IOS Signal Output.................................................................. 123
Table 6.16
Data Buses Used and Valid Strobes...................................................................... 126
Table 6.17
Pin States in Idle Cycle......................................................................................... 147
Section 7 Data Transfer Controller (DTC)
Table 7.1
Correspondence between Interrupt Sources and DTCER ..................................... 155
Table 7.2
DTC Event Counter Conditions............................................................................ 159
Table 7.3
Flag Status/Address Code..................................................................................... 160
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 163
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) .... 164
Table 7.5
Register Functions in Normal Mode..................................................................... 166
Table 7.6
Register Functions in Repeat Mode...................................................................... 167
Table 7.7
Register Functions in Block Transfer Mode ......................................................... 168
Table 7.8
DTC Execution Status .......................................................................................... 171
Table 7.9
Number of States Required for Each Execution Status ........................................ 172
Section 8 I/O Ports
Table 8.1
Port Functions....................................................................................................... 177
Table 8.1
Port Functions (cont) ............................................................................................ 178
Table 8.1
Port Functions (cont) ............................................................................................ 179
Rev. 3.00, 03/04, page xxxvi of xl
Table 8.1
Table 8.1
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Port Functions (cont) ............................................................................................ 180
Port Functions (cont) ............................................................................................ 181
Port Functions (cont) ............................................................................................ 182
Port 1 Input Pull-Up MOS States.......................................................................... 186
Port 2 Input Pull-Up MOS States.......................................................................... 190
Port 3 Input Pull-Up MOS States.......................................................................... 195
Port 6 Input Pull-Up MOS States.......................................................................... 213
Port A Input Pull-Up MOS States......................................................................... 231
Port D Input Pull-Up MOS States......................................................................... 242
Section 9 8-Bit PWM Timer (PWM)
Table 9.1
Pin Configuration.................................................................................................. 252
Table 9.2
Internal Clock Selection........................................................................................ 254
Table 9.3
Resolution, PWM Conversion Period, and Carrier Frequency
when φ = 33 MHz ................................................................................................. 255
Table 9.4
Duty Cycle of Basic Pulse .................................................................................... 258
Table 9.5
Position of Pulses Added to Basic Pulses ............................................................. 259
Section 10 14-Bit PWM Timer (PWMX)
Table 10.1
Pin Configuration.................................................................................................. 262
Table 10.2
Clock Select of PWMX_1 and PWMX_0 ............................................................ 267
Table 10.3
Settings and Operation (Examples when φ = 33 MHz)......................................... 270
Table 10.4
Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 275
Section 11 16-Bit Free-Running Timer (FRT)
Table 11.1
Pin Configuration.................................................................................................. 279
Table 11.2
FRT Interrupt Sources .......................................................................................... 298
Table 11.3
Switching of Internal Clock and FRC Operation .................................................. 303
Table 11.3
Switching of Internal Clock and FRC Operation (cont) ....................................... 304
Section 12 8-Bit Timer (TMR)
Table 12.1
Pin Configuration.................................................................................................. 308
Table 12.2
Clock Input to TCNT and Count Condition.......................................................... 312
Table 12.2
Clock Input to TCNT and Count Condition (cont) ............................................... 313
Table 12.3
Registers Accessible by TMR_X/TMR_Y ........................................................... 321
Table 12.4
Input Capture Signal Selection ............................................................................. 328
Table 12.5
Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 329
Table 12.6
Timer Output Priorities ......................................................................................... 333
Table 12.7
Switching of Internal Clocks and TCNT Operation.............................................. 333
Table 12.7
Switching of Internal Clocks and TCNT Operation (cont) ................................... 334
Section 13 Watchdog Timer (WDT)
Table 13.1
Pin Configuration.................................................................................................. 339
Table 13.2
WDT Interrupt Source .......................................................................................... 347
Rev. 3.00, 03/04, page xxxvii of xl
Section 14 Serial Communication Interface (SCI, IrDA, and CRC)
Table 14.1
Pin Configuration.................................................................................................. 355
Table 14.2
Relationships between N Setting in BRR and Bit Rate B..................................... 369
Table 14.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 370
Table 14.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 371
Table 14.4
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 372
Table 14.5
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 372
Table 14.6
BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 373
Table 14.7
Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........ 373
Table 14.8
BRR Settings for Various Bit Rates
(Smart Card Interface Mode, n = 0, s = 372) ........................................................ 374
Table 14.9
Maximum Bit Rate for Each Frequency
(Smart Card Interface Mode, S = 372).................................................................. 374
Table 14.10 Asynchronous Mode Clock Source Select............................................................ 378
Table 14.11
Serial Transfer Formats (Asynchronous Mode)................................................ 381
Table 14.12
SSR Status Flags and Receive Data Handling .................................................. 390
Table 14.13
IrCKS2 to IrCKS0 Bit Settings......................................................................... 419
Table 14.14
SCI Interrupt Sources........................................................................................ 420
Table 14.15
SCI Interrupt Sources........................................................................................ 421
Section 15 I2C Bus Interface (IIC)
Table 15.1
Pin Configuration.................................................................................................. 438
Table 15.2
Transfer Format .................................................................................................... 441
Table 15.3
I2C bus Transfer Rate (1) ...................................................................................... 444
Table 15.3
I2C bus Transfer Rate (2) ...................................................................................... 445
Table 15.4
Flags and Transfer States (Master Mode) ............................................................. 452
Table 15.5
Flags and Transfer States (Slave Mode) ............................................................... 453
Table 15.6
Output Data Hold Time ........................................................................................ 464
Table 15.7
ISCMBCR Setting ................................................................................................ 464
Table 15.8
I2C Bus Data Format Symbols.............................................................................. 466
Table 15.9
Examples of Operation Using the DTC ................................................................ 491
Table 15.10
IIC Interrupt Source .......................................................................................... 494
Table 15.11
I2C Bus Timing (SCL and SDA Outputs)......................................................... 495
Table 15.12
Permissible SCL Rise Time (tsr) Values ........................................................... 496
Table 15.13
I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 498
Section 16 LPC Interface (LPC)
Table 16.1
Pin Configuration.................................................................................................. 509
Table 16.2
LADR1, LADR2 Initial Values ............................................................................ 526
Table 16.3
Host Register Selection......................................................................................... 526
Table 16.4
Slave Selection Internal Registers ........................................................................ 527
Table 16.5
I/O Read and Write Cycles ................................................................................... 568
Table 16.6
GA20 (PD3) Set/Clear Conditions........................................................................ 574
Rev. 3.00, 03/04, page xxxviii of xl
Table 16.7
Table 16.8
Table 16.9
Table 16.10
Table 16.11
Table 16.12
Table 16.13
Fast A20 Gate Output Signals............................................................................... 576
Scope of LPC Interface Pin Shutdown ................................................................. 578
Scope of Initialization in Each LPC Interface Mode ............................................ 579
Serial Interrupt Transfer Cycle Frame Configuration ....................................... 582
Receive Complete Interrupts and Error Interrupt.............................................. 584
HIRQ Setting and Clearing Conditions............................................................. 585
Host Addresses Example .................................................................................. 588
Section 17 D/A Converter
Table 17.1
Pin Configuration.................................................................................................. 590
Table 17.2
D/A Channel Enable ............................................................................................. 592
Section 18 A/D Converter
Table 18.1
Pin Configuration.................................................................................................. 597
Table 18.2
Analog Input Channels and Corresponding ADDR Registers .............................. 598
Table 18.3
A/D Conversion Time (Single Mode)................................................................... 603
Table 18.4
A/D Converter Interrupt Source............................................................................ 604
Section20 Flash Memory (0.18-µm F-ZTAT Version)
Table 20.1
Comparison of Programming Modes.................................................................... 614
Table 20.2
Pin Configuration.................................................................................................. 620
Table 20.3
Register/Parameter and Target Mode ................................................................... 621
Table 20.4
Parameters and Target Modes............................................................................... 629
Table 20.5
Setting On-Board Programming Mode ................................................................. 638
Table 20.6
System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 640
Table 20.7
Executable MAT................................................................................................... 656
Table 20.8 (1)
Useable Area for Programming in User Program Mode............................... 657
Table 20.8 (2)
Useable Area for Erasure in User Program Mode......................................... 659
Table 20.8 (3)
Useable Area for Programming in User Boot Mode..................................... 661
Table 20.8 (4)
Useable Area for Erasure in User Boot Mode............................................... 663
Table 20.9
Hardware Protection ............................................................................................. 665
Table 20.10
Software Protection........................................................................................... 666
Table 20.11
Inquiry and Selection Commands ..................................................................... 674
Table 20.12
Programming/Erasing Command...................................................................... 685
Table 20.13
Status Code ....................................................................................................... 694
Table 20.14
Error Code ........................................................................................................ 694
Section 21 Boundary Scan (JTAG)
Table 21.1
Pin Configuration.................................................................................................. 699
Table 21.2
JTAG Register Serial Transfer.............................................................................. 700
Table 21.3
Correspondence between Pins and Boundary Scan Register ................................ 704
Section 22 Clock Pulse Generator
Table 22.1
Damping Resistance Values ................................................................................. 722
Table 22.2
Crystal Resonator Parameters ............................................................................... 723
Table 22.3
PFSEL and Multipliers ......................................................................................... 724
Rev. 3.00, 03/04, page xxxix of xl
Section 23 Power-Down Modes
Table 23.1
Operating Frequency and Wait Time.................................................................... 730
Table 23.2
LSI Internal States in Each Mode ......................................................................... 737
Section 25 Electrical Characteristics
Table 25.1
Absolute Maximum Ratings ................................................................................. 783
Table 25.2
DC Characteristics (1) .......................................................................................... 784
Table 25.2
DC Characteristics (2) .......................................................................................... 785
Table 25.3
Permissible Output Currents................................................................................. 787
Table 25.4
Clock Timing ........................................................................................................ 788
Table 25.5
External Clock Input Conditions .......................................................................... 789
Table 25.6
Subclock Input Conditions.................................................................................... 789
Table 25.7
Control Signal Timing .......................................................................................... 792
Table 25.8
Bus Timing ........................................................................................................... 794
Table 25.9
Multiplex Bus Timing........................................................................................... 800
Table 25.10
Timing of On-Chip Peripheral Modules ........................................................... 803
Table 25.11
I2C Bus Timing ................................................................................................. 807
Table 25.12
LPC Module Timing......................................................................................... 808
Table 25.13
JTAG Timing.................................................................................................... 809
Table 25.14
A/D Conversion Characteristics
(AN7 to AN0 Input: 134/266-State Conversion).............................................. 811
Table 25.15
D/A Conversion Characteristics ....................................................................... 812
Table 25.16
Flash Memory Characteristics .......................................................................... 813
Rev. 3.00, 03/04, page xl of xl
Section 1 Overview
1.1
Overview
• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
Data transfer controller (DTC)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
CRC operation circuit (CRC)
I2C bus interface (IIC)
LPC interface (LPC)
8-bit D/A converter
10-bit A/D converter
Boundary scan (JTAG)
Clock pulse generator
• On-chip memory
ROM Type
Model
ROM
RAM
Remarks
Flash memory
Version
HD64F2168
256 kbytes
40 kbytes
Flash memory
Version
HD64F2167
384 kbytes
40 kbytes
Flash memory
Version
HD64F2166
512 kbytes
40 kbytes
• General I/O ports
I/O pins: 106
Input-only pins: 9
• Supports various power-down states
• Compact package
Rev. 3.00, 03/04, page 1 of 830
Package
Code
Body Size
Pin Pitch
TQFP-144
TFP-144
16.0 × 16.0 mm
0.4 mm
Internal Block Diagram
Port A
Port 2
P20/A8/AD8/PW8
P21/A9/AD9/PW9
P22/A10/AD10/PW10
P23/A11/AD11/PW11
P24/A12/AD12/PW12
P25/A13/AD13/PW13
P26/A14/AD14/PW14
P27/A15/AD15/PW15
Port 1
P10/A0/AD0/PW0
P11/A1/AD1/PW1
P12/A2/AD2/PW2
P13/A3/AD3/PW3
P14/A4/AD4/PW4
P15/A5/AD5/PW5
P16/A6/AD6/PW6
P17/A7/AD7/PW7
Port 3
P30/D8/WUE8
P31/D9/WUE9
P32/D10/WUE10
P33/D11/WUE11
P34/D12/WUE12
P35/D13/WUE13
P36/D14/WUE14
P37/D15/WUE15
Port 7
DTC
PA0/A16/KIN8/SSE0I/EVENT0
PA1/A17/KIN9/SSE2I/EVENT1
PA2/A18/KIN10/EVENT2
PA3/A19/KIN11/EVENT3
PA4/A20/KIN12/EVENT4
PA5/A21/KIN13/EVENT5
PA6/A22/KIN14/EVENT6
PA7/A23/KIN15/EVENT7
P70/AN0
P71/AN1
P72/ExIRQ2/AN2
P73/ExIRQ3/AN3
P74/ExIRQ4/AN4
P75/ExIRQ5/AN5
P76/ExIRQ6/AN6/DA0
P77/ExIRQ7/AN7/DA1
Port 8
Internal address bus
Clock pulse
generator
Port 9
Interrupt
controller
P80/ExIRQ8/SCL0
P81/ExIRQ9/SDA0
P82/ExIRQ10/SCL1
P83/ExIRQ11/SDA1
P84/ExIRQ12/SCK0/ExTMI0
P85/ExIRQ13/SCK1/ExTMI1
P86/ExIRQ14/SCK2/ExTMIX
P87/ExIRQ15/ADTRG/ExTMIY
Bus controller
ROM
(Flash memory)
Peripheral address bus
Peripheral data bus
RAM
Sub address bus
WDT × 2 channels
Sub data bus
D0/KIN0/FTCI/P60
D1/KIN1/FTOA/P61
D2/KIN2/FTIA/P62
D3/KIN3/FTIB/P63
D4/KIN4/FTIC/P64
D5/KIN5/FTID/P65
D6/KIN6/FTOB/P66
D7/KIN7/P67
H8S/2000 CPU
Port 6
LWR/P90
AH/P91
CPCS1/P92
RD/P93
HWR/P94
IOS/AS/P95
EXCL/φ/P96
CS256/WAIT/P97
VCC
VCL
VSS
XTAL
EXTAL
PFSEL
MD2
MD1
MD0
RES
RESO
STBY
FWE
NMI
ETRST
ETMS
ETDO
ETDI
ETCK
Internal data bus
1.2
8-bit PWM
16-bit FRT
14-bit PWM × 4 channels
LPC interface
8-bit timer × 4 channels
Port 4
TMI0/IRQ0/P40
TMI1/IRQ1/P41
TMO0/IRQ2/P42
TMO1/IRQ3/P43
TMIX/IRQ4/P44
TMIY/IRQ5/P45
TMOX/IRQ6/P46
TMOY/IRQ7/P47
10-bit A/D
SCI × 3 channels
(IrDA × 1 channel)
8-bit D/A
IIC × 6 channels
Port 5
TxD0/IRQ8/P50
RxD0/IRQ9/P51
IrTxD/TxD1/IRQ10/P52
IrRxD/RxD1/IRQ11/P53
TxD2/IRQ12/P54
RxD2/IRQ13/P55
PWX0/IRQ14/P56
PWX1/IRQ15/P57
CRC operation circuit
Port D
EVENT8/PB0
EVENT9/PB1
EVENT10/PB2
EVENT11/PB3
EVENT12/PB4
EVENT13/PB5
EVENT14/PB6
EVENT15/PB7
SCL2/PC0
SDA2/PC1
SCL3/PC2
SDA3/PC3
SCL4/PC4
SDA4/PC5
PWX2/PC6
PWX3/PC7
LSCI/PD0
LSMI/PD1
PME/PD2
GA20/PD3
CLKRUN/PD4
LPCPD/PD5
SCL5/PD6
SDA5/PD7
Port C
Port E
Port F
ExPW0/PF0
ExPW1/PF1
ExPW2/PF2
Port B
LAD0/PE0
LAD1/PE1
LAD2/PE2
LAD3/PE3
LFRAME/PE4
LRESET/PE5
LCLK/PE6
SERIRQ/PE7
AVCC
AVref
AVSS
Figure 1.1 Internal Block Diagram
Rev. 3.00, 03/04, page 2 of 830
P75/ExIRQ5/AN5
P76/ExIRQ6/AN6/DA0
P77/ExIRQ7/AN7/DA1
AVCC
AVref
P60/FTCI/KIN0/D0
P61/FTOA/KIN1/D1
P62/FTIA/KIN2/D2
P63/FTIB/KIN3/D3
P64/FTIC/KIN4/D4
P65/FTID/KIN5/D5
66/FTOB/KIN6/D6
P67/KIN7/D7
VCC
ETMS
ETDO
ETDI
ETCK
ETRST
PF2/ExPW2
PF1/ExPW1
PF0/ExPW0
VSS
P27/A15/PW15/AD15
P26/A14/PW14/AD14
P25/A13/PW13/AD13
P24/A12/PW12/AD12
P23/A11/PW11/AD11
P22/A10/PW10/AD10
P21/A9/PW9/AD9
P20/A8/PW8/AD8
P17/A7/PW7/AD7
P16/A6/PW6/AD6
Pin Arrangement
P15/A5/PW5/AD5
1.3.1
P14/A4/PW4/AD4
Pin Description
P13/A3/PW3/AD3
1.3
108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
AD2/PW2/A2/P12
109
72
P74/ExIRQ4/AN4
AD1/PW1/A1/P11
110
71
P73/ExIRQ3/AN3
VSS
111
70
P72/ExIRQ2/AN2
AD0/PW0/A0/P10
112
69
P71/AN1
EVENT15/PB7
113
68
P70/AN0
EVENT14/PB6
114
67
AVSS
EVENT13/PB5
115
66
PD0/LSCI
EVENT12/PB4
116
65
PD1/LSMI
EVENT11/PB3
117
64
PD2/PME
EVENT10/PB2
118
63
PD3/GA20
EVENT9/PB1
119
62
PD4/CLKRUN
EVENT8/PB0
120
61
PD5/LPCPD
WUE8/D8/P30
121
60
PD6/SCL5
WUE9/D9/P31
122
59
PD7/SDA5
WUE10/D10/P32
123
58
PE0/LAD0
WUE11/D11/P33
124
57
PE1/LAD1
WUE12/D12/P34
125
56
PE2/LAD2
WUE13/D13/P35
126
55
PE3/LAD3
WUE14/D14/P36
127
54
PE4/LFRAME
WUE15/D15/P37
128
53
PE5/LRESET
TMI0/IRQ0/P40
129
52
PE6/LCLK
TMI1/IRQ1/P41
130
51
PE7/SERIRQ
TMO0/IRQ2/P42
131
50
P80/ExIRQ8/SCL0
TMO1/IRQ3/P43
132
49
P81/ExIRQ9/SDA0
IrTxD/TxD1/IRQ10/P52
133
48
P82/ExIRQ10/SCL1
IrRxD/RxD1/IRQ11/P53
134
47
P83/ExIRQ11/SDA1
FWE
135
46
P84/ExIRQ12/SCK0/ExTMI0
TxD2/IRQ12/P54
136
45
P85/ExIRQ13/SCK1/ExTMI1
RxD2/IRQ13/P55
137
44
TMIX/IRQ4/P44
138
43
P87/ExIRQ15/ADTRG/ExTMIY
VSS
139
42
VSS
NC
140
41
PA0/A16/KIN8/SSE0I/EVENT0
PFSEL
141
40
RESO
142
39
PA2/A18/KIN10/EVENT2
XTAL
143
38
PA3/A19/KIN11/EVENT3
EXTAL
144
37
PA4/A20/KIN12/EVENT4
P86/ExIRQ14/SCK2/ExTMIX
PA1/A17/KIN9/SSE2I/EVENT1
VCC
EVENT5/KIN13/A21/PA5
EVENT6/KIN14/A22/PA6
EVENT7/KIN15/A23/PA7
SCL2/PC0
SDA2/PC1
SCL3/PC2
SDA3/PC3
SCL4/PC4
SDA4/PC5
PWX2/PC6
PWX3/PC7
LWR/P90
AH/P91
CPCS1/P92
RD/P93
HWR/P94
IOS/AS/P95
EXCL/φ/P96
CS256/WAIT/P97
TxD0/IRQ8/P50
RxD0/IRQ9/P51
MD2
VCL
STBY
MD1
NMI
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
MD0
8
RES
TMOY/IRQ7/P47
6 7
VSS
VCC
5
PWX1/IRQ15/P57
4
PWX0/IRQ14/P56
2 3
TMIY/IRQ5/P45
1
TMOX/IRQ6/P46
TFP-144
(Top View)
Figure 1.2 Pin Arrangement (TFP-144)
Rev. 3.00, 03/04, page 3 of 830
1.3.2
Pin Arrangement in Each Operating Mode
Table 1.1
Pin
No.
Pin Arrangement in Each Operating Mode
Pin Name
TFP144
Extended Mode
Single-Chip Mode
(EXPE = 1)
(EXPE = 0)
Flash Memory
Programmer Mode
1
VCC
VCC
VCC
2
P45/IRQ5/TMIY
P45/IRQ5/TMIY
NC
3
P46/IRQ6/TMOX
P46/IRQ6/TMOX
NC
4
P47/IRQ7/TMOY
P47/IRQ7/TMOY
NC
5
P56/IRQ14/PWX0
P56/IRQ14/PWX0
NC
6
P57/IRQ15/PWX1
P57/IRQ15/PWX1
NC
7
VSS
VSS
VSS
8
RES
RES
RES
9
MD1
MD1
VSS
10
MD0
MD0
VSS
11
NMI
NMI
FA9
12
STBY
STBY
VCC
13
VCL
VCL
VCL
14
MD2
MD2
VCC
15
P51/IRQ9/RxD0
P51/IRQ9/RxD0
FA17
16
P50/IRQ8/TxD0
P50/IRQ8/TxD0
NC
17
P97/WAIT/CS256
P97
VCC
18
P96/φ/EXCL
P96/φ/EXCL
NC
19
AS/IOS
P95
FA16
20
HWR
P94
FA15
21
RD
P93
WE
22
P92/ CPCS1
P92
VSS
23
P91/AH
P91
VCC
24
P90/ LWR
P90
VCC
25
PC7/PWX3
PC7/PWX3
NC
26
PC6/PWX2
PC6/PWX2
NC
27
PC5/SDA4
PC5/SDA4
NC
Rev. 3.00, 03/04, page 4 of 830
Pin
No.
Pin Name
TFP144
Extended Mode
Single-Chip Mode
(EXPE = 1)
(EXPE = 0)
Flash Memory
Programmer Mode
28
PC4/SCL4
PC4/SCL4
NC
29
PC3/SDA3
PC3/SDA3
NC
30
PC2/SCL3
PC2/SCL3
NC
31
PC1/SDA2
PC1/SDA2
NC
32
PC0/SCL2
PC0/SCL2
NC
33
PA7/A23/KIN15/EVENT7
PA7/KIN15/EVENT7
NC
34
PA6/A22/KIN14/EVENT6
PA6/KIN14/EVENT6
NC
35
PA5/A21/KIN13/EVENT5
PA5/KIN13/EVENT5
NC
36
VCC
VCC
VCC
37
PA4/A20/KIN12/EVENT4
PA4/KIN12/EVENT4
NC
38
PA3/A19/KIN11/EVENT3
PA3/KIN11/EVENT3
NC
39
PA2/A18/KIN10/EVENT2
PA2/KIN10/EVENT2
NC
40
PA1/A17/KIN9/EVENT1/SSE2I
PA1/KIN9/EVENT1/SSE2I
NC
41
PA0/A16/KIN8/EVENT0/SSE0I
PA0/KIN8/EVENT0/SSE0I
NC
42
VSS
VSS
VSS
43
P87/ExIRQ15/ADTRG/ExTMIY
P87/ExIRQ15/ADTRG/ExTMIY
NC
44
P86/ExIRQ14/SCK2/ExTMIX
P86/ExIRQ14/SCK2/ExTMIX
NC
45
P85/ExIRQ13/SCK1/ExTMI1
P85/ExIRQ13/SCK1/ExTMI1
NC
46
P84/ExIRQ12/SCK0/ExTMI0
P84/ExIRQ12/SCK0/ExTMI0
NC
47
P83/ExIRQ11/SDA1
P83/ExIRQ11/SDA1
NC
48
P82/ExIRQ10/SCL1
P82/ExIRQ10/SCL1
NC
49
P81/ExIRQ9/SDA0
P81/ExIRQ9/SDA0
NC
50
P80/ExIRQ8/SCL0
P80/ExIRQ8/SCL0
NC
51
PE7/SERIRQ
PE7/SERIRQ
NC
52
PE6/LCLK
PE6/LCLK
NC
53
PE5/LRESET
PE5/LRESET
NC
54
PE4/LFRAME
PE4/LFRAME
NC
55
PE3/LAD3
PE3/LAD3
NC
56
PE2/LAD2
PE2/LAD2
NC
57
PE1/LAD1
PE1/LAD1
NC
58
PE0/LAD0
PE0/LAD0
NC
Rev. 3.00, 03/04, page 5 of 830
Pin
No.
Pin Name
TFP144
Extended Mode
Single-Chip Mode
(EXPE = 1)
(EXPE = 0)
Flash Memory
Programmer Mode
59
PD7/SDA5
PD7/SDA5
NC
60
PD6/SCL5
PD6/SCL5
NC
61
PD5/LPCPD
PD5/LPCPD
NC
62
PD4/CLKRUN
PD4/CLKRUN
NC
63
PD3/GA20
PD3/GA20
NC
64
PD2/PME
PD2/PME
NC
65
PD1/LSMI
PD1/LSMI
NC
66
PD0/LSCI
PD0/LSCI
NC
67
AVSS
AVSS
VSS
68
P70/AN0
P70/AN0
NC
69
P71/AN1
P71/AN1
NC
70
P72/ExIRQ2/AN2
P72/ExIRQ2/AN2
NC
71
P73/ExIRQ3/AN3
P73/ExIRQ3/AN3
NC
72
P74/ExIRQ4/AN4
P74/ExIRQ4/AN4
NC
73
P75/ExIRQ5/AN5
P75/ExIRQ5/AN5
NC
74
P76/ExIRQ6/AN6/DA0
P76/ExIRQ6/AN6/DA0
NC
75
P77/ExIRQ7/AN7/DA1
P77/ExIRQ7/AN7/DA1
NC
76
AVCC
AVCC
VCC
77
AVref
AVref
VCC
78
P60/FTCI/KIN0/D0
P60/FTCI/KIN0
NC
79
P61/FTOA/KIN1/D1
P61/FTOA/KIN1
NC
80
P62/FTIA/KIN2/D2
P62/FTIA/KIN2
NC
81
P63/FTIB/KIN3/D3
P63/FTIB/KIN3
NC
82
P64/FTIC/KIN4/D4
P64/FTIC/KIN4
NC
83
P65/FTID/KIN5/D5
P65/FTID/KIN5
NC
84
P66/FTOB/KIN6/D6
P66/FTOB/KIN6
NC
85
P67/KIN7/D7
P67/KIN7
VSS
86
VCC
VCC
VCC
87
ETMS
ETMS
NC
88
ETDO
ETDO
NC
89
ETDI
ETDI
NC
Rev. 3.00, 03/04, page 6 of 830
Pin
No.
Pin Name
TFP144
Extended Mode
Single-Chip Mode
(EXPE = 1)
(EXPE = 0)
Flash Memory
Programmer Mode
90
ETCK
ETCK
NC
91
ETRST
ETRST
RES
92
PF2/ExPW2
PF2/ExPW2
NC
93
PF1/ExPW1
PF1/ExPW1
NC
94
PF0/ExPW0
PF0/ExPW0
NC
95
VSS
VSS
VSS
96
P27/A15/AD15
P27/PW15
CE
97
P26/A14/AD14
P26/PW14
FA14
98
P25/A13/AD13
P25/PW13
FA13
99
P24/A12/AD12
P24/PW12
FA12
100
P23/A11/AD11
P23/PW11
FA11
101
P22/A10/AD10
P22/PW10
FA10
102
P21/A9/AD9
P21/PW9
OE
103
P20/A8/AD8
P20/PW8
FA8
104
P17/A7/AD7
P17/PW7
FA7
105
P16/A6/AD6
P16/PW6
FA6
106
P15/A5/AD5
P15/PW5
FA5
107
P14/A4/AD4
P14/PW4
FA4
108
P13/A3/AD3
P13/PW3
FA3
109
P12/A2/AD2
P12/PW2
FA2
110
P11/A1/AD1
P11/PW1
FA1
111
VSS
VSS
VSS
112
P10/A0/AD0
P10/PW0
FA0
113
PB7/EVENT15
PB7/EVENT15
NC
114
PB6/EVENT14
PB6/EVENT14
NC
115
PB5/EVENT13
PB5/EVENT13
NC
116
PB4/EVENT12
PB4/EVENT12
NC
117
PB3/EVENT11
PB3/EVENT11
NC
118
PB2/EVENT10
PB2/EVENT10
NC
119
PB1/EVENT9
PB1/EVENT9
NC
120
PB0/EVENT8
PB0/EVENT8
NC
Rev. 3.00, 03/04, page 7 of 830
Pin
No.
Pin Name
TFP144
Extended Mode
Single-Chip Mode
Flash Memory
Programmer Mode
121
P30/D8/WUE8
P30/WUE8
FO0
122
P31/D9/WUE9
P31/WUE9
FO1
123
P32/D10/WUE10
P32/WUE10
FO2
124
P33/D11/WUE11
P33/WUE11
FO3
125
P34/D12/WUE12
P34/WUE12
FO4
126
P35/D13/WUE13
P35/WUE13
FO5
127
P36/D14/WUE14
P36/WUE14
FO6
128
P37/D15/WUE15
P37/WUE15
FO7
129
P40/IRQ0/TMI0
P40/IRQ0/TMI0
NC
130
P41/IRQ1/TMI1
P41/IRQ1/TMI1
NC
131
P42/IRQ2/TMO0
P42/IRQ2/TMO0
NC
132
P43/IRQ3/TMO1
P43/IRQ3/TMO1
NC
133
P52/IRQ10/TxD1/IrTxD
P52/IRQ10/TxD1/IrTxD
FA18
134
P53/IRQ11/RxD1/IrRxD
P53/IRQ11/RxD1/IrRxD
NC
135
FWE
FWE
FWE
136
P54/IRQ12/TxD2
P54/IRQ12/TxD2
NC
137
P55/IRQ13/RxD2
P55/IRQ13/RxD2
NC
138
P44/IRQ4/TMIX
P44/IRQ4/TMIX
NC
139
VSS
VSS
VSS
140
NC
NC
NC
141
PFSEL
PFSEL
VCC
142
RESO
RESO
NC
143
XTAL
XTAL
XTAL
144
EXTAL
EXTAL
EXTAL
Rev. 3.00, 03/04, page 8 of 830
1.3.3
Pin Functions
Table 1.2
Pin Functions
Type
Symbol
Pin No.
I/O
Name and Function
Power
supply
VCC
1, 36
86
Input
Power supply pins. Connect all these pins to the
system power supply. Connect the bypass
capacitor between VCC and VSS (near VCC).
VCL
13
Input
External capacitance pin for internal step-down
power. Connect this pin to Vss through an
external capacitor (that is located near this pin) to
stabilize internal step-down power.
VSS
7, 42,
95, 111
139
Input
Ground pins. Connect all these pins to the system
power supply (0V).
XTAL
143
Input
EXTAL
144
Input
For connection to a crystal resonator. An external
clock can be supplied from the EXTAL pin. For an
example of crystal resonator connection, see
section 22, Clock Pulse Generator.
φ
18
Output
Supplies the system clock to external devices.
EXCL
18
Input
32.768-kHz external clock for sub clock should be
supplied.
PFSEL
141
Input
Pin for use by PLL. For an example of PLL
connection, see section 22, Clock Pulse
Generator.
Operating
mode
control
MD2
MD1
MD0
14
9
10
Input
These pins set the operating mode. Inputs at
these pins should not be changed during
operation.
System
control
RES
8
Input
Reset pin. When this pin is low, the chip is reset.
RESO
142
Output
Outputs a reset signal to an external device.
STBY
12
Input
When this pin is low, a transition is made to
hardware standby mode.
FWE
135
Input
Pin for use by flash memory.
Output
Address output pins
Clock
Address
bus
Data bus
A23 to A16 33 to 35
37 to 41
A15 to A0
96 to 110
112
D15 to D8
128 to 121 Input/
Output
Upper bidirectional data bus
D7 to D0
85 to 78
Lower bidirectional data bus
Rev. 3.00, 03/04, page 9 of 830
Type
Symbol
Pin No.
I/O
Name and Function
Address/
data
multiplex
bus
AD15 to
AD8
96 to 103
Input/
Output
8-bit, upper 16-bit bus
AD7 to
AD0
104 to 110,
112
Bus control WAIT
Interrupts
Lower 16-bit bus
17
Input
Requests insertion of a wait state in the bus cycle
when accessing an external 3-state address
space.
RD
21
Output
This pin is low when the external address space
is being read.
HWR
20
Output
This pin is low when the external address space
is to be written to, and the upper half of the data
bus is enabled.
LWR
24
Output
This pin is low when the external address space
is to be written to, and the lower half of the data
bus is enabled.
AS/IOS
19
Output
This pin is low when address output on the
address bus is valid.
CS256
17
Output
Indicates that the 256k-byte area from H'F80000
to H'FBFFFF is accessed.
CPCS1
22
Output
Indicates that the CP extended area is accessed.
AH
23
Output
Address latch signal for address/data multiplex
bus.
NMI
11
Input
Nonmaskable interrupt request input pin
IRQ15 to
IRQ0
6, 5, 137, Input
136, 134,
133, 15,
16, 4 to 2,
138, 132 to
129
These pins request a maskable interrupt.
Selectable to which pin of IRQn or ExIRQn to
insert IRQ15 to IRQ2 interrupts.
ExIRQ15 43 to 50
to ExIRQ2 75 to 70
Boundary
scan
ETRST
91
Input
ETMS
87
Input
ETDO
88
Output
ETDI
89
Input
ETCK
90
Input
Rev. 3.00, 03/04, page 10 of 830
Boundary scan interface pins
Type
Symbol
PWM timer PW15 to
(PWM)
PW0
ExPW2 to
ExPW0
Pin No.
I/O
Name and Function
96 to 110
112
Output
PWM timer pulse output pins.
Selectable from which pin of PWn or ExPWn to
output PW2 to PW0.
92 to 94
14-bit PWM PWX0
timer
PWX1
(PWMX)
PWX2
PWX3
5
6
26
25
Output
PWM D/A pulse output pins
16-bit free FTCI
running
FTOA
timer (FRT) FTOB
78
Input
External event input pin
79
84
Output
Output compare output pins
FTIA to
FTID
80 to 83
Input
Input capture input pins
TMO0
TMO1
TMOX
TMOY
131
132
3
4
Output
Waveform output pins with output compare
function
TMI0
TMI1
TMIX
TMIY
ExTMI0
ExTMI1
ExTMIX
ExTMIY
129
130
138
2
46
45
44
43
Input
External event input pins and counter reset input
pins. Selectable to which pin of TMIn or ExTMIn
to insert external event and counter reset.
TxD0 to
TxD2
16, 133
136
Output
Transmit data output pins
RxD0 to
RxD2
15, 134
137
Input
Receive data input pins
SCK0 to
SCK2
46, 45
44
Input/
Output
Clock input/output pins. Output format is NMOS
push-pull output.
8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y)
Serial
communication
Interface
(SCI_0,
SCI_1,
SCI_2)
SCI with
IrDA (SCI)
2
I C bus
interface
(IIC)
SSE0I
41
Input
Input pin to halt SCI_0
SSE2I
40
Input
Input pin to halt SCI_2
IrTxD
133
Output
Encoded data output pin for IrDA
IrRxD
134
Input
Encoded data input pin for IrDA
SCL0 to
SCL5
50, 48, 32, Input/
30, 28, 60 Output
IIC clock input/output pins. These pins can drive a
bus directly with the NMOS open drain output.
SDA0 to
SDA5
49, 47, 31, Input/
29, 27, 59 Output
IIC data input/output pins. These pins can drive a
bus directly with the NMOS open drain output.
Rev. 3.00, 03/04, page 11 of 830
Type
Symbol
Pin No.
I/O
Name and Function
Keyboard
control
KIN15 to
KIN13
33 to 35
Input
KIN12 to
KIN8
37 to 41
Input
KIN7 to
KIN0
85 to 78
Input
Matrix keyboard input pins. All pins have a wakeup function. Normally, KIN15 to KIN0 function as
key scan inputs, and P17 to P10 and P27 to P20
function as key scan outputs. Thus, at a
maximum of 16 outputs x 16 inputs, 256-key
matrix can be configured.
WUE15 to 128 to 121 Input
WUE8
Wake-up event input pins. Same wake up as key
wake up can be performed with various sources.
AN7 to
AN0
75 to 68
Input
Analog input pins
ADTRG
43
Input
External trigger input pin to start A/D conversion
D/A
converter
(DAC)
DA0
DA1
74
75
Output
Analog output pins
A/D
converter
(ADC)
AVCC
76
Input
Analog power supply pins for the A/D converter
and D/A converter. When the A/D converter and
D/A converter are not used, these pins should be
connected to the system power supply (+3.3 V).
AVref
77
Input
Reference voltage input pin for the A/D converter
and D/A converter. When the A/D converter and
D/A converter are not used, this pin should be
connected to the system power supply (+3.3 V).
AVSS
67
Input
Ground pins for the A/D converter and D/A
converter. These pins should be connected to the
system power supply (0 V).
A/D
converter
(ADC)
D/A
converter
(DAC)
Rev. 3.00, 03/04, page 12 of 830
Type
Symbol
Pin No.
I/O
Name and Function
LPC
Interface
(LPC)
LAD3 to
LAD0
55 to 58
Input/
Output
Transfer cycle type/address/data I/O pins
LFRAME
54
Input
Input pin indicating transfer cycle start and forced
termination
LRESET
53
Input
LPC reset pin. When this pin is low, a reset state
is entered.
LCLK
52
Input
PCI clock input pin
SERIRQ
51
Input/
Output
LPC serialized host interrupt request signal
LSCI,
LSMI,
PME
66
65
64
Input/
Output
General input/output ports of LSCI, LSMI, and
PME
GA20
63
Input/
Output
GATE A20 control signal output pin. The monitor
input of an output state is enabled.
CLKRUN
62
Input/
Output
LCLK restart request I/O pin
LPCPD
61
Input
LPC module shutdown control input pin
Event
Counter
EVENT15 113 to 120, Input
to EVENT0 33 to 35,
37 to 41
Event counter input pins.
Rev. 3.00, 03/04, page 13 of 830
Type
Symbol
Pin No.
I/O ports
P17 to P10
104 to 110, Input/
112
Output
Eight input/output pins
P27 to P20
96 to 103
Input/
Output
Eight input/output pins
P37 to P30
128 to 121 Input/
Output
Eight input/output pins
P47 to P40
4 to 2, 138, Input/
132 to 129 Output
Eight input/output pins
P57 to P50
6, 5
137, 136
134, 133
15, 16
Input/
Output
Eight input/output pins
P67 to P60
85 to 78
Input/
Output
Eight input/output pins
P77 to P70
75 to 68
Input
Eight input pins
P87 to P80
43 to 50
Input/
Output
Eight input/output pins
P97 to P90
17 to 24
Input/
Output
Eight input/output pins (P96 input pin)
PA7 to PA0
33 to 35,
37 to 41
Input/
Output
Eight input/output pins
PB7 to PB0
113 to 120 Input/
Output
Eight input/output pins
PC7 to PC0
25 to 32
Input/
Output
Eight input/output pins
PD7 to PD0
59 to 66
Input/
Output
Eight input/output pins
PE7 to PE0
51 to 58
Input/
Output
Eight input/output pins
PF2 to PF0
92 to 94
Input/
Output
Three input/output pins
Rev. 3.00, 03/04, page 14 of 830
I/O
Name and Function
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.
2.1
Features
• Upward-compatibility with H8/300 and H8/300H CPUs
 Can execute H8/300 CPU and H8/300H CPU object programs
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16 Mbytes address space
 Program: 16 Mbytes
 Data: 16 Mbytes
• High-speed operation
 All frequently-used instructions are executed in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
CPUS210A_010020021100
Rev. 3.00, 03/04, page 15 of 830
• Two CPU operating modes
 Normal mode*
 Advanced mode
Note: * Not available in this LSI.
• Power-down state
 Transition to power-down state by SLEEP instruction
 Selectable CPU clock speed
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 3.00, 03/04, page 16 of 830
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
 Eight 16-bit extended registers and one 8-bit control register have been added.
• Extended address space
 Normal mode* supports the same 64 kbytes address space as the H8/300 CPU.
 Advanced mode supports a maximum 16 Mbytes address space.
Note: * Not available in this LSI.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16 Mbytes address
space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 Two-bit shift and two-bit rotate instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions are executed twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
 One 8-bit control register has been added.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Two-bit shift and two-bit rotate instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions are executed twice as fast.
Rev. 3.00, 03/04, page 17 of 830
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a
maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address
space. The mode is selected by the LSI's mode pins.
Note: * Not available in this LSI.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
Linear access to a maximum address space of 64 kbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack structure
In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
Note: Normal mode is not available in this LSI.
Rev. 3.00, 03/04, page 18 of 830
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
(a) Subroutine Branch
SP
CCR
CCR*
PC
(16 bits)
(b) Exception Handling
Note: * Ignored when returning.
Figure 2.2 Stack Structure in Normal Mode
Rev. 3.00, 03/04, page 19 of 830
2.2.2
Advanced Mode
• Address space
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper eight bits are ignored and a branch address is
stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section
4, Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
H'0000000B
H'0000000C
H'00000010
(Reserved for system use)
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 3.00, 03/04, page 20 of 830
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper eight bits of these 32 bits are a reserved area that
is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to
H'000000FF. Note that the top area of this range is also used for the exception vector table.
• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved
PC
(24-bit)
(a) Subroutine Branch
CCR
SP
PC
(24-bit)
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
Rev. 3.00, 03/04, page 21 of 830
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64 kbytes address space in normal mode, and a maximum 16 Mbytes
(architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, see section 3, MCU Operating
Modes.
H'0000
H'00000000
64 kbytes
16 Mbytes
H'FFFF
Program area
H'00FFFFFF
Data area
Not available
in this LSI
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Not: * Not available in this LSI.
Figure 2.5 Memory Map
Rev. 3.00, 03/04, page 22 of 830
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR* T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Note: * Does not affect operation in this LSI.
Figure 2.6 CPU Internal Registers
Rev. 3.00, 03/04, page 23 of 830
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing sixteen 16-bit registers at the maximum. The E registers (E0 to
E7) are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing sixteen 8-bit registers at the maximum.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
Rev. 3.00, 03/04, page 24 of 830
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit
Bit Name
Initial Value R/W
7
T
0
R/W
Description
Trace Bit
Does not affect operation in this LSI.
6 to 3 –
All 1
R
Reserved
These bits are always read as 1.
2 to 0 I2
1
I1
1
I0
1
R/W
Interrupt Mask Bits 2 to 0
Do not affect operation in this LSI.
Rev. 3.00, 03/04, page 25 of 830
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial Value
R/W Description
7
I
1
R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
see section 5, Interrupt Controller.
6
UI
Undefined
R/W User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined
R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
4
U
Undefined
R/W User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined
R/W Negative Flag
Stores the value of the most significant bit of data as a sign
bit.
2
Z
Undefined
R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
1
V
Undefined
R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and cleared to
0 otherwise.
Rev. 3.00, 03/04, page 26 of 830
Bit
Bit Name
Initial Value
R/W Description
0
C
Undefined
R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0 otherwise.
Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
Rev. 3.00, 03/04, page 27 of 830
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data Type
Register Number
Data Image
7
1-bit data
RnH
0
Don't care
7 6 5 4 3 2 1 0
0
7
1-bit data
Don't care
RnL
4 3
7
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
7 6 5 4 3 2 1 0
Upper
0
Lower
Don't care
4 3
7
Don't care
7
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Don't care
MSB
Figure 2.9 General Register Data Formats (1)
Rev. 3.00, 03/04, page 28 of 830
0
Lower
LSB
Data Type
Register Number
Word data
Rn
Data Image
15
0
LSB
MSB
Word data
En
15
0
MSB
LSB
Longword data
ERn
31
16 15
MSB
En
0
Rn
LSB
[Legend]
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL:
General register RL
MSB: Most significant bit
LSB:
Least significant bit
Figure 2.9 General Register Data Formats (2)
Rev. 3.00, 03/04, page 29 of 830
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Address
Data Image
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M + 1
Longword data
1
MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
Figure 2.10 Memory Data Formats
Rev. 3.00, 03/04, page 30 of 830
LSB
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Data transfer
MOV
1
POP* , PUSH*
1
LDM, STM*
MOVFPE* , MOVTPE*
Arithmetic
operations
Types
B/W/L
5
W/L
2
3
Size
L
3
B
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS
B
19
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
BIAND, BOR, BIOR, BXOR, BIXOR
14
Branch
BCC*4, JMP, BSR, JSR, RTS
–
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
–
9
–
1
Block data transfer EEPMOV
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
3. Cannot be used in this LSI.
4. BCC is the general name for conditional branch instructions.
Rev. 3.00, 03/04, page 31 of 830
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 3.00, 03/04, page 32 of 830
Table 2.3
Data Transfer Instructions
Instruction
Size*1
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn → @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM*2
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM*
2
L
Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot
be used as an STM/LDM register.
Rev. 3.00, 03/04, page 33 of 830
Table 2.4
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
SUB
ADDX
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
B
SUBX
INC
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
B/W/L
DEC
ADDS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
B
Rd (decimal adjust) → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAS
MULXU
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)
SUBS
DAA
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8-bit × 8-bit → 16-bit or 16-bit × 16-bit → 32-bit.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8bit × 8-bit → 16-bit or 16-bit × 16-bit → 32-bit.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16-bit
÷ 8-bit → 8-bit quotient and 8-bit remainder or 32-bit ÷ 16-bit → 16-bit
quotient and 16-bit remainder.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
Rev. 3.00, 03/04, page 34 of 830
Table 2.4
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets the CCR bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
Rev. 3.00, 03/04, page 35 of 830
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ Rd → Rd
Takes the one's complement (logical complement) of data in a general
register.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
B/W/L
Rd (shift) → Rd
SHAR
SHLL
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
B/W/L
SHLR
ROTL
Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.
B/W/L
ROTR
ROTXL
ROTXR
Rd (shift) → Rd
Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
B/W/L
Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
Rev. 3.00, 03/04, page 36 of 830
Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR
B
C ∨ (∼ <bit-No.> of <EAd>) → C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
[Legend]
*:
Size refers to the operand size.
B:
Byte
Rev. 3.00, 03/04, page 37 of 830
Table 2.7
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ∼ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
∼ C → (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
[Legend]
*:
Size refers to the operand size.
B:
Byte
Rev. 3.00, 03/04, page 38 of 830
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
–
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
C=0
(high or same)
JMP
–
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
Branches unconditionally to a specified address.
BSR
–
Branches to a subroutine at a specified address
JSR
–
Branches to a subroutine at a specified address
RTS
–
Returns from a subroutine
Rev. 3.00, 03/04, page 39 of 830
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
–
Starts trap-instruction exception handling.
RTE
–
Returns from an exception-handling routine.
SLEEP
–
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper eight bits are
valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper eight
bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
NOP
–
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
PC + 2 → PC
Only increments the program counter.
[Legend]
*:
Size refers to the operand size.
B:
Byte
W:
Word
Rev. 3.00, 03/04, page 40 of 830
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
–
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
EEPMOV.W
–
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3-bit, and data registers by 3-bit
or 4-bit. Some instructions have two register fields, and some have no register field.
• Effective address extension
8-, 16-, or 32-bit specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
Rev. 3.00, 03/04, page 41 of 830
(1) Operation field only
op
NOP, RTS
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16
Figure 2.11 Instruction Formats (Examples)
Rev. 3.00, 03/04, page 42 of 830
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode
Symbol
1
Rn
Register direct
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Rev. 3.00, 03/04, page 43 of 830
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper eight bits are all assumed to be 0 (H'00).
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper eight
bits are all assumed to be 0 (H′00).
Rev. 3.00, 03/04, page 44 of 830
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode*
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
Note:
2.7.6
*
H'000000 to H'FFFFFF
24 bits (@aa:24)
Not available in this LSI.
Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24-bit and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24-bit of this branch
address are valid; the upper eight bits are all assumed to be 0 (H′00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128-byte (–63 to +64 words) or –32766 to +32768-byte (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
Rev. 3.00, 03/04, page 45 of 830
2.7.8
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode).
In normal mode*, the memory operand is a word operand and the branch address is 16 bits long.
In advanced mode, the memory operand is a longword operand, the first byte of which is assumed
to be 0 (H'00).
Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, see section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Note: * Not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
Rev. 3.00, 03/04, page 46 of 830
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode*, the upper eight bits of the effective address are ignored in order to generate a 16-bit
address.
Note * Not available in this LSI.
Table 2.13 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
31
0
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
31
0
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
disp
0
31
31
24 23
0
Don't care
General register contents
r
• Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
1, 2, or 4
31
0
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
Rev. 3.00, 03/04, page 47 of 830
Table 2.13 Effective Address Calculation (2)
Addressing Mode and Instruction Format
No
5
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
@aa:16
31
@aa:24
24 23
16 15
0
31
24 23
0
Don't care
abs
op
0
H'FFFF
Don't care Sign extension
abs
op
8 7
24 23
Don't care
abs
op
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
8 7
31
op
abs
H'000000
31
0
Memory contents
Note:
*
Not available in this LSI.
Rev. 3.00, 03/04, page 48 of 830
0
abs
31
24 23
Don't care
0
2.8
Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset state
In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 4, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
In a product which has a bus master other than the CPU, such as a data transfer controller
(DTC), the bus-released state occurs when the bus has been released in response to a bus
request from a bus master other than the CPU. While the bus is released, the CPU halts
operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
see section 23, Power-Down Modes.
Rev. 3.00, 03/04, page 49 of 830
End of bus request
Bus request
Program execution
state
End of bus
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Bus
request
Bus-released state
End of
exception
handling
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Request for
exception
handling
Sleep mode
Interrupt
request
Exception-handling state
External interrupt
request
Software standby mode
RES = high
Reset state*1
STBY = high, RES = low
Hardware standby mode*2
Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 23, Power-Down Modes.
Figure 2.13 State Transitions
Rev. 3.00, 03/04, page 50 of 830
2.9
Usage Notes
2.9.1
Note on TAS Instruction Usage
The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers.
The TAS instruction can be used as a user-defined intrinsic function.
2.9.2
Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the
data of the target bit, and write data in byte units. Special care is required when using these
instructions in cases where a register containing a write-only bit is used or a bit is directly
manipulated for a port.
In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this
case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not
be read before executing the BCLR instruction.
Rev. 3.00, 03/04, page 51 of 830
2.9.3
EEPMOV Instruction
1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*,
which starts from the address indicated by ER5, to the address indicated by ER6.
ER5
ER6
ER5 + R4*
ER6 + R4*
2. Set R4* and ER6 so that the end address of the destination address (value of ER6 + R4*) does
not exceed H'00FFFFFF (the value of ER6 must not change from H'00FFFFFF to H'01000000
during execution).
ER5
ER6
ER5 + R4*
Invalid
Note: * For byte transfer R4L is used.
Rev. 3.00, 03/04, page 52 of 830
H'FFFFFFF
ER6 + R4*
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
This LSI supports one operating mode (mode 2). The operating mode is determined by the setting
of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection.
Table 3.1
MCU Operating Mode Selection
MCU Operating
CPU Operating
Mode
MD2 MD1 MD0 Mode
Description
2
1
1
0
Advanced
Extended mode with on-chip ROM
Single-chip mode
Mode 2 is single-chip mode after a reset. The CPU can switch to extended mode by setting bit
EXPE in MDCR to 1.
Modes 0, 1, 3, 5, and 7 are not available in this LSI. Modes 4 and 6 are operating mode for a
special purpose. Thus, mode pins should be set to enable mode 2 in normal program execution
state. Mode pins should not be changed during operation.
Rev. 3.00, 03/04, page 53 of 830
3.2
Register Descriptions
The following registers are related to the operating mode. For details on the bus control register
(BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2
(BCR2), see section 6.3.2, Bus Control Register 2 (BCR2).
• Mode control register (MDCR)
• System control register (SYSCR)
• Serial timer control register (STCR)
3.2.1
Mode Control Register (MDCR)
MDCR is used to set an operating mode and to monitor the current operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
EXPE
0
R/W
Extended Mode Enable
Specifies extended mode.
0: Single-chip mode
1: Extended mode
6
to
3
—
All 0
R
Reserved
2
1
0
MDS2
MDS1
MDS0
—*
—*
—*
R
R
R
Mode Select 2 to 0
Note:
*
These bits indicate the input levels at mode pins (MD2,
MD1, and MD0) (the current operating mode). Bits
MDS2, MDS1, and MDS0 correspond to MD2, MD1,
and MD0, respectively. MDS2 to MDS0 are read-only
bits and they cannot be written to. The mode pin (MD2,
MD1, and MD0) input levels are latched into these bits
when MDCR is read. These latches are canceled by a
reset.
The initial values are determined by the settings of the MD2, MD1, and MD0 pins.
Rev. 3.00, 03/04, page 54 of 830
3.2.2
System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, enables or disables register access to the on-chip peripheral
modules, and enables or disables on-chip RAM address space.
Bit
Bit Name
Initial Value
R/W
Description
7
CS256E
0
R/W
Chip Select 256 Enable
Enables or disables P97/WAIT/CS256 pin function in
extended mode.
0: P97/WAIT pin
WAIT pin function is selected by the settings of
WSCR and WSCR2.
1: CS256 pin
Outputs low when a 256-kbyte expansion area of
addresses H'F80000 to H'FBFFFF is accessed.
6
IOSE
0
R/W
IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
Outputs low when an external area is accessed.
1: IOS pin
Outputs low when an IOS expansion area of
addresses H'FFF000 to H'FFF7FF is accessed.
5
4
INTM1
INTM0
0
0
R
R/W
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
3
XRST
1
R
External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
2
NMIEG
0
R/W
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 3.00, 03/04, page 55 of 830
Bit
Bit Name
Initial Value
R/W
Description
1
KINWUE
0
R/W
Keyboard Control Register Access Enable
Enables or disables CPU access for input control
registers (KMIMRA, KMIMR6, WUEMR3) of KINn and
WUEn pins, input pull-up MOS control register
(KMPCR6) of the KINn pin, and registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X,
TCORB_X) of 8-bit timers (TMR_X, TMR_Y),
0: Enables CPU access for registers of TMR_X and
TMR_Y in an area from H'FFFFF0 to H'FFFFF7 and
from H'FFFFFC to H'FFFFFF.
1: Enables CPU access for input control registers of
the KINn and WUEn pins and the input pull-up MOS
control register of the KINn pin in an area from
H'FFFFF0 to H'FFFFF7 and from H'FFFFFC to
H'FFFFFF.
0
RAME
1
R/W
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
3.2.3
Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
IICX2
IICX1
IICX0
0
0
0
R/W
R/W
R/W
IIC Transfer Rate Select 2, 1 and 0
These bits control the IIC operation. These bits
select a transfer rate in master mode together with
2
bits CKS2 to CKS0 in the I C bus mode register
(ICMR). For details on the transfer rate, see table
15.3. The IICXn bit controls IIC_n. (n = 0 to 2)
Rev. 3.00, 03/04, page 56 of 830
Bit
Bit Name
Initial Value
R/W
Description
4
IICE
0
R/W
IIC Master Enable
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
SCI_2 registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
SCI_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
1: IIC_1 registers are accessed in an area from
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
PWMX registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
IIC_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
3
FLSHE
0
R/W
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS,
FTDAR), control registers of power-down states
(SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and
control registers of on-chip peripheral modules
(BCR2, WSCR2, PCSR, SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is reserved.
Control registers of power-down states and onchip peripheral modules are accessed in an area
from H'FFFF80 to H'FFFF87.
1: Control registers of flash memory are accessed in
an area from H'FFFE88 to H'FFFE8F.
Area from H'FFFF80 to H'FFFF87 is reserved.
2
—
0
R/W
Reserved
The initial value should not be changed.
1
0
ICKS1
ICKS0
0
0
R/W
R/W
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, see section 12.3.4, Timer Control
Register (TCR).
Rev. 3.00, 03/04, page 57 of 830
3.3
Operating Mode Descriptions
3.3.1
Mode 2
The CPU can access a 16 Mbytes address space in advanced mode. The on-chip ROM is enabled.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
Normal extended mode:
In extended modes, ports 1 and 2 function as input ports after a reset.
Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction
register (DDR). Port 3 functions as a data bus port, and parts of port 9 carry bus control signals.
Port 6 functions as a data bus port when the ABW bit in WSCR is cleared to 0.
Multiplex extended mode:
When 8-bit bus is specified, port 2 functions as the port for address output and data input/output
regardless of the setting of the data direction register (DDR). Port 1 can be used as a general port.
When 16-bit bus is specified, ports 1 and 2 function as the port for address output and data
input/output regardless of the setting of the data direction register (DDR).
3.3.2
Pin Functions in Each Operating Mode
Pin functions of ports 1 to 3, 6, 9, and A depend on the extended mode. Table 3.2 shows pin
functions in each operating mode.
Rev. 3.00, 03/04, page 58 of 830
Table 3.2
Pin Functions in Each Mode
Mode 2
Port
Normal extension
Multiplex extension
Port 1
I/O port* or Address bus output
I/O port* or Address/Data multiplex
I/O
Port 2
I/O port* or Address bus output
I/O port* or Address/Data multiplex
I/O
Port 3
I/O port* or Data bus I/O
I/O port*
Port 6
I/O port* or Data bus I/O
I/O port*
I/O port97
I/O port* or Control signal output
I/O port* or Control signal output
I/O port96
Input port* or Clock I/O
Input port* or Clock I/O
Port 9
I/O port95 to I/O port* or Control signal output
I/O port93
I/O port* or Control signal output
I/O port92
I/O port* or Control signal output
I/O port* or Control signal output
I/O port91
I/O port* or Control signal output
I/O port* or Control signal output
I/O port90
I/O port* or Control signal output
I/O port* or Control signal output
I/O port* or Address bus output
I/O port*
Port A
[Legend]
*:
After reset
Rev. 3.00, 03/04, page 59 of 830
3.4
Address Map
Figures 3.1 to 3.3 show memory maps in operating mode.
ROM: 256 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 1)
Advanced mode
Extended mode with
on-chip ROM
ROM: 256 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
H'000000
H'000000
On-chip ROM
H'03FFFF
On-chip ROM
H'03FFFF
Reserved area
Reserved area
H'07FFFF
H'080000
H'F7FFFF
H'F80000
H'FBFFFF
H'FC0000
H'FEFFFF
H'FF0000
H'FF07FF
H'FF0800
H'07FFFF
External address
space
256 kbytes
extended area
External address
space
Reserved area
H'FF0000
H'FF07FF
H'FF0800
Reserved area
On-chip RAM *
(36 kbytes)
On-chip RAM
(36 kbytes)
H'FF97FF
H'FF9800
H'FF97FF
H'FF9800
Reserved area*
H'FFBFFF
H'FFC000
H'FFDFFF
H'FFE000
H'FFE07F
H'FFE080
H'FFEFFF
H'FFF000
H'FFF7FF
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Reserved area
H'FFBFFF
CP extended
area
External address
space
On-chip RAM *
(3,968 bytes)
External address
space
(IOS extended area)
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM
*
(128 bytes)
Internal I/O
registers 1
H'FFE080
H'FFEFFF
On-chip RAM
(3,968 bytes)
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM
(128 bytes)
Internal I/O
registers 1
Notes: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.1 H8S/2168 Address Map
Rev. 3.00, 03/04, page 60 of 830
ROM: 384 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 1)
Advanced mode
Extended mode with
on-chip ROM
ROM: 384 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
H'000000
H'000000
On-chip ROM
H'05FFFF
On-chip ROM
H'05FFFF
Reserved area
Reserved area
H'07FFFF
H'080000
H'F7FFFF
H'F80000
H'FBFFFF
H'FC0000
H'FEFFFF
H'FF0000
H'FF07FF
H'FF0800
H'07FFFF
External address
space
256 kbytes
extended area
External address
space
Reserved area
H'FF0000
H'FF07FF
H'FF0800
Reserved area
On-chip RAM *
(36 kbytes)
On-chip RAM
(36 kbytes)
H'FF97FF
H'FF9800
H'FF97FF
H'FF9800
Reserved area *
H'FFBFFF
H'FFC000
H'FFDFFF
H'FFE000
H'FFE07F
H'FFE080
H'FFEFFF
H'FFF000
H'FFF7FF
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Reserved area
H'FFBFFF
CP extended
area
External address
space
On-chip RAM*
(3,968 bytes)
External address
space
(IOS extended area)
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM*
(128 bytes)
Internal I/O
registers 1
H'FFE080
H'FFEFFF
On-chip RAM
(3,968 bytes)
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM
(128 bytes)
Internal I/O
registers 1
Notes: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.2 H8S/2167 Address Map
Rev. 3.00, 03/04, page 61 of 830
ROM: 512 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 1)
Advanced mode
Extended mode with
on-chip ROM
H'000000
ROM: 512 kbytes, RAM: 40 kbytes
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
H'000000
On-chip ROM
H'07FFFF
H'080000
H'F7FFFF
H'F80000
H'FBFFFF
H'FC0000
H'FEFFFF
H'FF0000
H'FF07FF
H'FF0800
On-chip ROM
H'07FFFF
External address
space
256 kbytes
extended area
External address
space
Reserved area
H'FF0000
H'FF07FF
H'FF0800
Reserved area
On-chip RAM*
(36 kbytes)
On-chip RAM
(36 kbytes)
H'FF97FF
H'FF9800
H'FF97FF
H'FF9800
Reserved area*
H'FFBFFF
H'FFC000
H'FFDFFF
H'FFE000
H'FFE07F
H'FFE080
H'FFEFFF
H'FFF000
H'FFF7FF
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Reserved area
H'FFBFFF
CP extended
area
External address
space
On-chip RAM*
(3,968 bytes)
External address
space
(IOS extended area)
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM*
(128 bytes)
Internal I/O
registers 1
H'FFE080
H'FFEFFF
On-chip RAM
(3,968 bytes)
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM
(128 bytes)
Internal I/O
registers 1
Notes: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.3 H8S/2166 Address Map
Rev. 3.00, 03/04, page 62 of 830
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or
trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Direct transition
Starts when a direct transition occurs as the result of
SLEEP instruction execution.
Trap instruction
Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Low
Rev. 3.00, 03/04, page 63 of 830
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.
Table 4.2
Exception Handling Vector Table
Vector Address
Exception Source
Vector Number
Advanced Mode
Reset
0
H'000000 to H'000003
Reserved for system use
1

5
H'000004 to H'000007
|
H'000014 to H'000017
Direct transition
6
H'000018 to H'00001B
External interrupt (NMI)
7
H'00001C to H'00001F
Trap instruction (four sources)
8
H'000020 to H'000023
9
H'000024 to H'000027
10
H'000028 to H'00002B
11
H'00002C to H'00002F
Direct transition (clock switchover)
12
H'000030 to H'000033
Reserved for system use
13

15
H'000034 to H'000037
|
H'00003C to H'00003F
External interrupt IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
16
17
18
19
20
21
22
23
H'000040 to H'000043
H'000044 to H'000047
H'000048 to H'00004B
H'00004C to H'00004F
H'000050 to H'000053
H'000054 to H'000057
H'000058 to H'00005B
H'00005C to H'00005F
Internal interrupt*
24

29
H'000060 to H'000063

H'000074 to H'000077
External interrupt KIN7 to KIN0
KIN15 to KIN8
Reserved
WUE15 to WUE8
30
31
32
33
H'000078 to H'00007B
H'00007C to H'00007F
H'000080 to H'000083
H'000084 to H'000087
Rev. 3.00, 03/04, page 64 of 830
Table 4.2
Exception Handling Vector Table (cont)
Vector Address
Exception Source
Vector Number
Advanced Mode
Internal interrupt*
34

55
H'000088 to H'00008B

H'0000DC to H'0000DF
External interrupt IRQ8
56
H'0000E0 to H'0000E3
IRQ9
57
H'0000E4 to H'0000E7
IRQ10
58
H'0000E8 to H'0000EB
IRQ11
59
H'0000EC to H'0000EF
IRQ12
60
H'0000F0 to H'0000F3
Internal interrupt*
Note:
*
IRQ13
61
H'0000F4 to H'0000F7
IRQ14
62
H'0000F8 to H'0000FB
IRQ15
63
H'0000FC to H'0000FF
64

119
H'000100 to H'000103

H'0001DC to H'0001DF
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Table.
Rev. 3.00, 03/04, page 65 of 830
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip
can also be reset by overflow of the watchdog timer. For details, see section 13, Watchdog Timer
(WDT).
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit in CCR is set to 1.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
Rev. 3.00, 03/04, page 66 of 830
Vector
fetch
Internal
processing
Prefetch of first
program instruction
φ
RES
Internal address bus
(1) U
(1) L
(3)
Internal read signal
High
Internal write signal
Internal data bus
(2) U
(2) L
(4)
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2)U + (2)L)
(4) First program instruction
Figure 4.1 Reset Sequence
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR, MSTPCRA, SUBMSTPB,
and SUBMSTPA) are initialized, and all modules except the DTC operate in module stop mode.
Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read
from and write to these registers, clear module stop mode.
Rev. 3.00, 03/04, page 67 of 830
4.4
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to
WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt
with the highest priority. For details, see section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
4.5
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3
Status of CCR after Trap Instruction Exception Handling
CCR
Interrupt Control Mode
I
UI
0
Set to 1
Retains value prior to
execution
1
Set to 1
Set to 1
Rev. 3.00, 03/04, page 68 of 830
4.6
Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Advanced mode
SP
CCR
PC
(24 bits)
Figure 4.2 Stack Status after Exception Handling
Rev. 3.00, 03/04, page 69 of 830
4.7
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed in words or longwords, and the value of the stack pointer (SP:
ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W
Rn
PUSH.L
ERn
(or MOV.W Rn, @-SP)
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
POP.L
ERn
(or MOV.W @SP+, Rn)
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what
happens when the SP value is odd.
Address
SP
CCR
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
SP
H'FFFEFF
TRAPA instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7 executed
Data saved above SP
Contents of CCR lost
[Legend]
CCR:
PC:
R1L:
SP:
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0.
Figure 4.3 Operation when SP Value Is Odd
Rev. 3.00, 03/04, page 70 of 830
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels
can be set for each module for all interrupts except NMI, KIN, and WUE.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR, and ICR, 3-level interrupt mask
control is performed.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Forty-one external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQ15 to IRQ0. An interrupt is requested at the falling edge for
KIN15 to KIN0 and WUE15 to WUE8.
• DTC control
The DTC can be activated by an interrupt request.
Rev. 3.00, 03/04, page 71 of 830
CPU
INTM1, INTM0
SYSCR
NMIEG
NMI input
NMI input
IRQ input
IRQ input
ISR
ISCR
IER
Interrupt
request
Vector number
Priority level
determination
KMIMR WUEMR
KIN input
WUE input
I, UI
KIN, WUE
input
CCR
Internal interrupt sources
SWDTEND to IBFI3
ICR
Interrupt controller
[Legend]
ICR:
ISCR:
IER:
ISR:
KMIMR:
WUEMR:
SYSCR:
Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register
Keyboard matrix interrupt mask register
Wake-up event interrupt mask register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 3.00, 03/04, page 72 of 830
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Symbol
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ15 to IRQ0
ExIRQ15 to ExIRQ2
Input
Maskable external interrupts
Rising edge, falling edge, or both edges, or level sensing, can
be selected individually for each pin. Pin of IRQn or ExIRQn to
input IRQ15 to IRQ2 interrupts can be selected.
KIN15 to KIN0
Input
Maskable external interrupts
An interrupt is requested at falling edge.
WUE15 to WUE8
Input
Maskable external interrupts
An interrupt is requested at falling edge.
Rev. 3.00, 03/04, page 73 of 830
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense
port select registers (ISSR16, ISSR), see section 8.16.1, IRQ Sense Port Select Register 16
(ISSR16), IRQ Sense Port Select Register (ISSR).
•
•
•
•
•
•
•
•
Interrupt control registers A to D (ICRA to ICRD)
Address break control register (ABRKCR)
Break address registers A to C (BARA to BARC)
IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
IRQ enable registers (IER16, IER)
IRQ status registers (ISR16, ISR)
Keyboard matrix interrupt mask registers (KMIMRA, KMIMR6)
Wake-up event interrupt mask register (WUEMR3)
5.3.1
Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI.
The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2.
Bit
Bit Name
Initial Value
7 to 0
ICRn7 to IRCn0 All 0
R/W
Description
R/W
Interrupt Control Level
0: Corresponding interrupt source is interrupt
control level 0 (no priority)
1: Corresponding interrupt source is interrupt
control level 1 (priority)
[Legend]
n:
A to D
Rev. 3.00, 03/04, page 74 of 830
Table 5.2
Correspondence between Interrupt Source and ICR
Register
Bit
Bit Name
ICRA
ICRB
ICRC
ICRD
7
ICRn7
IRQ0
A/D converter
SCI_0
IRQ8 to IRQ11
6
ICRn6
IRQ1
FRT
SCI_1
IRQ12 to IRQ15
5
ICRn5
IRQ2, IRQ3
—
SCI_2
—
4
ICRn4
IRQ4, IRQ5
TMR_X
IIC_0
—
3
ICRn3
IRQ6, IRQ7
TMR_0
IIC_1
—
2
ICRn2
DTC
TMR_1
IIC_2, IIC_3
—
1
ICRn1
WDT_0
TMR_Y
LPC
—
0
ICRn0
WDT_1
IIC_4, IIC_5
—
—
[Legend]]
n:
A to D
:
Reserved. The write value should always be 0.
5.3.2
Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit
Bit Name
Initial Value
R/W
Description
7
CMF
Undefined
R
Condition Match Flag
Address break source flag. Indicates that an
address specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
6 to 1
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
0
BIE
0
R/W
Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Rev. 3.00, 03/04, page 75 of 830
5.3.3
Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first
byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to
A16 are not compared.
• BARA
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
A23 to A16
All 0
R/W
Addresses 23 to 16
The A23 to A16 bits are compared with A23 to
A16 in the internal address bus.
• BARB
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
A15 to A8
All 0
R/W
Addresses 15 to 8
The A15 to A8 bits are compared with A15 to
A8 in the internal address bus.
• BARC
Bit
Bit Name
Initial Value
R/W
Description
7 to 1
A7 to A1
All 0
R/W
Addresses 7 to 1
The A7 to A1 bits are compared with A7 to A1
in the internal address bus.
0
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 3.00, 03/04, page 76 of 830
5.3.4
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or
pins ExIRQ15 to ExIRQ2.
• ISCR16H
Bit
Bit Name
Initial Value
R/W
Description
7
6
IRQ15SCB
IRQ15SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
5
4
IRQ14SCB
IRQ14SCA
0
0
R/W
R/W
00: Interrupt request generated at low level of
IRQn or ExIRQn input
3
2
IRQ13SCB
IRQ13SCA
0
0
R/W
R/W
01: Interrupt request generated at falling edge
of IRQn or ExIRQn input
1
0
IRQ12SCB
IRQ12SCA
0
0
R/W
R/W
10: Interrupt request generated at rising edge of
IRQn or ExIRQn input
11: Interrupt request generated at both falling
and rising edges of IRQn or ExIRQn input
(n = 15 to 12)
• ISCR16L
Bit
Bit Name
Initial Value
R/W
Description
7
6
IRQ11SCB
IRQ11SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
5
4
IRQ10SCB
IRQ10SCA
0
0
R/W
R/W
00: Interrupt request generated at low level of
IRQn or ExIRQn input
3
2
IRQ9SCB
IRQ9SCA
0
0
R/W
R/W
01: Interrupt request generated at falling edge
of IRQn or ExIRQn input
1
0
IRQ8SCB
IRQ8SCA
0
0
R/W
R/W
10: Interrupt request generated at rising edge of
IRQn or ExIRQn input
11: Interrupt request generated at both falling
and rising edges of IRQn or ExIRQn input
(n = 11 to 8)
Rev. 3.00, 03/04, page 77 of 830
• ISCRH
Bit
Bit Name
Initial Value
R/W
Description
7
6
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
5
4
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
00: Interrupt request generated at low level of
IRQn or ExIRQn input
3
2
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
01: Interrupt request generated at falling edge
of IRQn or ExIRQn input
1
0
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
10: Interrupt request generated at rising edge of
IRQn or ExIRQn input
11: Interrupt request generated at both falling
and rising edges of IRQn or ExIRQn input
(n = 7 to 4)
• ISCRL
Bit
Bit Name
Initial Value
R/W
Description
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
00: Interrupt request generated at low level of
IRQn or ExIRQn* input
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
01: Interrupt request generated at falling edge
of IRQn or ExIRQn* input
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
10: Interrupt request generated at rising edge of
IRQn or ExIRQn* input
11: Interrupt request generated at both falling
and rising edges of IRQn or ExIRQn* input
(n = 3 to 0)
Note:
*
ExIRQn stands for ExIRQ3 or ExIRQ2.
Rev. 3.00, 03/04, page 78 of 830
5.3.5
IRQ Enable Registers (IER16, IER)
The IER registers control the enabling and disabling of interrupt requests IRQ15 to IRQ0.
• IER16
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
IRQ15E to
IRQ8E
All 0
R/W
IRQn Enable (n = 15 to 8)
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
IRQ7E to
IRQ0E
All 0
R/W
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this
bit is 1.
• IER
The IRQn interrupt request is enabled when this
bit is 1.
Rev. 3.00, 03/04, page 79 of 830
5.3.6
IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
• ISR16
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
IRQ15F to
IRQ8F
All 0
R/W
[Setting condition]
•
When the interrupt source selected by the
ISCR16 registers occurs
[Clearing conditions]
•
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn or ExIRQn input is high
•
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 15 to 8)
• ISR
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
IRQ7F to
IRQ0F
All 0
R/W
[Setting condition]
•
When the interrupt source selected by the
ISCR registers occurs
[Clearing conditions]
•
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn or ExIRQn* input is high
•
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 7 to 0)
Note:
*
ExIRQn stands for ExIRQ7 to ExIRQ2.
Rev. 3.00, 03/04, page 80 of 830
5.3.7
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6)
Wake-Up Event Interrupt Mask Register (WUEMR3)
The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to
KIN0), and wake-up event interrupt inputs (WUE15 to WUE8). The KMIMRA, KMIMR6, and
WUEMR3 registers can be accessed when the KINWUE bit in SYSCR is set to 1. See section
3.2.2, System Control Register (SYSCR).
• KMIMRA
Bit
Bit Name
Initial Value
R/W
7 to 0
KMIM15 to
KMIM8
All 1
R/W
Description
Keyboard Matrix Interrupt Mask
These bits enable or disable a key-sensing
input interrupt request (KIN15 to KIN8).
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt
request
• KMIMR6
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
KMIM7 to
KMIM0
All 1
R/W
Keyboard Matrix Interrupt Mask
These bits enable or disable a key-sensing
input interrupt request (KIN7 to KIN0).
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt
request
• WUEMR3
Bit
Bit Name
Initial Value
7 to 0
WUEM15 to All 1
WUEM8
R/W
Description
R/W
Wake-Up Event Interrupt Mask
These bits enable or disable a wake-up event
input interrupt request (WUE15 to WUE8).
0: Enables a wake-up event input interrupt
request
1: Disables a wake-up event input interrupt
request
Rev. 3.00, 03/04, page 81 of 830
5.4
Interrupt Sources
5.4.1
External Interrupts
There are four external interrupts: NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE8.
These interrupts can be used to restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Interrupts IRQ15 to IRQ0 have the following
features:
• The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an
independent vector address.
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, clear the
corresponding port DDR to 0 so that it is not used as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
S
Q
R
IRQn input or
ExIRQn* input
Clear signal
n = 15 to 0
Note: * ExIRQn stands for ExIRQ15 to ExIRQ2.
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
Rev. 3.00, 03/04, page 82 of 830
IRQn interrupt
request
KIN15 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts KIN15 to KIN0 and
WUE15 to WUE8 are requested by an input signal at pins KIN15 to KIN0 and WUE15 to WUE8.
Interrupts KIN15 to KIN0 and WUE15 to WUE8 have the following features:
• Interrupts KIN15 and KIN8, KIN7 to KIN0 and WUE15 to WUE8 each form a group. The
interrupt exception handling for an interrupt request from the same group is started at the same
vector address.
• Enabling or disabling of interrupt requests can be selected with the I bit in CCR.
• An interrupt is generated by a falling edge at pins KIN15 to KIN0 and WUE15 to WUE8.
• Enabling or disabling of interrupt requests KIN15 to KIN0 and WUE15 to WUE8 can be
selected using KMIMRA, KMIMR6, and WUEMR3.
• The status of interrupt requests KIN15 to KIN0 and WUE15 to WUE8 are not indicated.
The detection of KIN15 to KIN0 and WUE15 to WUE8 interrupts does not depend on whether the
relevant pin has been set for input or output. However, when a pin is used as an external interrupt
input pin, clear the corresponding port DDR to 0 so that it is not used as an I/O pin for another
function.
A block diagram of interrupts KIN15 to KIN0 and WUE15 to WUE8 is shown in figure 5.3.
KMIMn
Falling-edge
detection circuit
S
Q
KINn interrupt request
R
KINn input
Clear signal
n = 15 to 0
Figure 5.3 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE8
(Example of KIN15 to KIN0)
Rev. 3.00, 03/04, page 83 of 830
5.4.2
Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
• The control level for each interrupt can be set by ICR.
• The DTC can be activated by an interrupt request from an on-chip peripheral module.
• An interrupt request that activates the DTC is not affected by the interrupt control mode or the
status of the CPU interrupt mask bits.
Rev. 3.00, 03/04, page 84 of 830
5.5
Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are
given priority and processed before interrupt requests from modules that are set to interrupt control
level 0 (no priority).
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Name
Vector Address
Vector
Number Advanced Mode
External pin
NMI
7
H'00001C
—
IRQ0
16
H'000040
ICRA7
IRQ1
17
H'000044
ICRA6
IRQ2
IRQ3
18
19
H'000048
H'00004C
ICRA5
IRQ4
IRQ5
20
21
H'000050
H'000054
ICRA4
IRQ6
IRQ7
22
23
H'000058
H'00005C
ICRA3
DTC
SWDTEND (Software activation
data transfer end)
24
H'000060
ICRA2
WDT_0
WOVI0 (Interval timer)
25
H'000064
ICRA1
WDT_1
WOVI1 (Interval timer)
26
H'000068
ICRA0
—
Address break
27
H'00006C
—
A/D converter
ADI (A/D conversion end)
28
H'000070
ICRB7
EVC
EVENTI
29
H'000074
—
External pin
KIN7 to KIN0
KIN15 and KIN8
WUE15 to WUE8
30
31
33
H'000078
H'00007C
H'000084
—
TMR_X
CMIAX (Compare match A)
CMIBX (Compare match B)
OVIX (Overflow)
ICIX (Input capture)
44
45
46
47
H'0000B0
H'0000B4
H'0000B8
H'0000BC
ICRB4
ICR
Priority
High
Low
Rev. 3.00, 03/04, page 85 of 830
Table 5.3
Origin of
Interrupt
Source
Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont)
Name
Vector Address
Vector
Number Advanced Mode
FRT
ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
48
49
50
51
52
53
54
H'0000C0
H'0000C4
H'0000C8
H'0000CC
H'0000D0
H'0000D4
H'0000D8
ICRB6
External pin
IRQ8
IRQ9
IRQ10
IRQ11
56
57
58
59
H'0000E0
H'0000E4
H'0000E8
H'0000EC
ICRD7
IRQ12
IRQ13
IRQ14
IRQ15
60
61
62
63
H'0000F0
H'0000F4
H'0000F8
H'0000FC
ICRD6
TMR_0
CMIA0 (Compare match A)
CMIB0 (Compare match B)
OVI0 (Overflow)
64
65
66
H'000100
H'000104
H'000108
ICRB3
TMR_1
CMIA1 (Compare match A)
CMIB1 (Compare match B)
OVI1 (Overflow)
68
69
70
H'000110
H'000114
H'000118
ICRB2
TMR_Y
CMIAY (Compare match A)
CMIBY (Compare match B)
OVIY (Overflow)
72
73
74
H'000120
H'000124
H'000128
ICRB1
IIC_2
IICI2
76
H'000130
ICRC2
IIC_3
IICI3
78
H'000138
SCI_0
ERI0 (Reception error 0)
RXI0 (Reception completion 0)
TXI0 (Transmission data empty 0)
TEI0 (Transmission end 0)
80
81
82
83
H'000140
H'000144
H'000148
H'00014C
ICRC7
SCI_1
ERI1 (Reception error 1)
RXI1 (Reception completion 1)
TXI1 (Transmission data empty 1)
TEI1 (Transmission end 1)
84
85
86
87
H'000150
H'000154
H'000158
H'00015C
ICRC6
SCI_2
ERI2 (Reception error 2)
RXI2 (Reception completion 2)
TXI2 (Transmission data empty 2)
TEI2 (Transmission end 2)
88
89
90
91
H'000160
H'000164
H'000168
H'00016C
ICRC5
Rev. 3.00, 03/04, page 86 of 830
ICR
Priority
High
Low
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont)
Origin of
Interrupt
Source
Name
Vector Address
Vector
Number Advanced Mode
IIC_0
IICI0
94
H'000178
ICRC4
IIC_1
IICI1
98
H'000188
ICRC3
IIC_4
IICI4
100
H'000190
ICRB0
IIC_5
IICI5
102
H'000198
LPC
ERR1(transfer error, etc.)
IBFI1 (IDR1 reception completion)
IBFI2 (IDR2 reception completion)
IBFI3 (IDR3 reception completion)
104
105
106
107
H'0001A0
H'0001A4
H'0001A8
H′0001AC
ICR
Priority
High
ICRC1
Low
Rev. 3.00, 03/04, page 87 of 830
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1.
Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address
break interrupts are always accepted except for in reset state or in hardware standby mode. The
interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes.
Table 5.4
Interrupt Control Modes
Interrupt
SYSCR
Control
Mode
INTM1
INTM0
Priority
Setting
Registers
Interrupt
Mask Bits
0
0
ICR
I
Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
1
ICR
I, UI
3-level interrupt mask control is
performed by the I and UI bits. Priority
levels can be set with ICR.
0
1
Description
Figure 5.4 shows a block diagram of the priority decision circuit.
I
UI
ICR
Interrupt
source
Interrupt
acceptance control
and 3-level mask
control
Default priority
determination
Vector
number
Interrupt control modes
0 and 1
Figure 5.4 Block Diagram of Interrupt Control Operation
Rev. 3.00, 03/04, page 88 of 830
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR and ICR (control level).
Table 5.5 shows the interrupts selected in each interrupt control mode.
Table 5.5
Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode I
UI
Selected Interrupts
0
0
*
All interrupts (interrupt control level 1 has
priority)
1
*
NMI and address break interrupts
0
*
All interrupts (interrupt control level 1 has
priority)
1
0
NMI, address break, and interrupt control level 1
interrupts
1
NMI and address break interrupts
1
[Legend]
*:
Don’t care
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
Rev. 3.00, 03/04, page 89 of 830
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control
Setting
Interrupt
Control Mode
INTM1
INTM0
0
0
0
1
1
3-Level Control
Default Priority
I
UI
ICR
Determination
T (Trace)
O
IM
—
PR
O
—
O
IM
IM
PR
O
—
[Legend]
O:
Interrupt operation control performed
IM:
Used as an interrupt mask bit
PR:
Sets priority
—:
Not used
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupts other than NMI are masked by ICR and the I bit of the CCR
in the CPU. Figure 5.5 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller accepts an
interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request
with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt
request with the highest priority is accepted according to the priority order, an interrupt
handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, only NMI and address break interrupt requests are accepted by
the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted. KIN, WUE, and EVENTI interrupts are enabled or disabled
by the I bit.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 3.00, 03/04, page 90 of 830
Program execution state
Interrupt generated?
No
Yes
Yes
NMI
No
No
An interrupt with interrupt
control level 1?
Hold pending
Yes
No
No
IRQ0
IRQ0
Yes
No
Yes
IRQ1
Yes
No
IRQ1
Yes
IBFI3
IBFI3
Yes
Yes
I=0
No
Yes
Save PC and CCR
I
1
Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 3.00, 03/04, page 91 of 830
5.6.2
Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
1. An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
to 0. When the I bit is set to 1, the interrupt request is held pending.
EVENTI, KIN, and WUE interrupts are enabled or disabled by the I bit.
2. An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
For instance, the state when the interrupt enable bit corresponding to each interrupt is set to 1, and
ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are
set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown
below. Figure 5.6 shows a state transition diagram.
1. All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 >
IRQ1 > address break …)
2. Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
0.
3. Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
I
All interrupt requests
are accepted
I
I
0
0
1, UI
Only NMI, address break, and
interrupt control level 1 interrupt
requests are accepted
0
UI
0
Exception handling
execution or UI 1
Exception handling execution
or I 1, UI 1
Only NMI and address break
interrupt requests are accepted
Figure 5.6 State Transition in Interrupt Control Mode 1
Figure 5.7 shows a flowchart of the interrupt acceptance operation.
Rev. 3.00, 03/04, page 92 of 830
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or
when the I bit is set to 1 while the UI bit is cleared to 0.
An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.
When both the I and UI bits are set to 1, only NMI and address break interrupt requests are
accepted, and other interrupts are held pending.
When the I bit is cleared to 0, the UI bit is not affected.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address
break interrupts.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 3.00, 03/04, page 93 of 830
Program execution state
No
Interrupt generated?
Yes
Yes
NMI
No
No
An interrupt with interrupt
control level 1?
Hold pending
Yes
IRQ0
Yes
No
No
IRQ0
No
Yes
IRQ1
No
IRQ1
Yes
Yes
IBFI3
IBFI3
Yes
Yes
I=0
No
I=0
Yes
No
UI = 0
No
Yes
Yes
Save PC and CCR
I
1, UI
1
Read vector address
Branch to interrupt handling routine
Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 1
5.6.3
Interrupt Exception Handling Sequence
Figure 5.8 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 3.00, 03/04, page 94 of 830
Figure 5.8 Interrupt Exception Handling
Rev. 3.00, 03/04, page 95 of 830
(2) (4)
(3)
(5)
(7)
(1)
Internal
data bus
(1)
(2)
(4)
Instruction
prefetch
(3)
Instruction prefetch address (Instruction is not executed.
Address is saved as PC contents, becoming return address.)
Instruction code (not executed)
Instruction prefetch address (Instruction is not executed.)
SP – 2
SP – 4
Internal write
signal
Internal read
signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Internal
processing
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
(7)
(8)
(9)
(10)
Vector fetch
(12)
(11)
Internal
processing
Saved PC and CCR
Vector address
Starting address of interrupt-handling routine (contents of vector address)
Starting address of interrupt-handling routine ((13) = (10) (12))
First instruction in interrupt-handling routine
(6)
Stack access
(14)
(13)
Prefetch of instruction in
interrupt-handling routine
5.6.4
Interrupt Response Times
Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.7 are explained in table 5.8.
Table 5.7
No.
1
Interrupt Response Times
Execution Status
Advanced Mode
Interrupt priority determination*
1
3
2
2
Number of wait states until executing instruction ends*
1 to (19 + 2·SI)
3
PC, CCR stack save
2·SK
4
Vector fetch
2·SI
5
6
Instruction fetch*
3
2·SI
4
Internal processing*
2
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
Table 5.8
12 to 32
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6 + 2m
2
3+m
Branch address read SJ
Stack manipulation SK
[Legend]
m:
Number of wait states in external device access.
Rev. 3.00, 03/04, page 96 of 830
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DTC
• Both of the above
For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer
Controller (DTC). Figure 5.9 shows a block diagram of the DTC and interrupt controller.
Interrupt
request
IRQ
interrupt
On-chip
peripheral
module
Interrupt source
clear signal
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC
Clear signal
DTVECR
SWDTE
clear signal
Interrupt controller
Determination of
priority
CPU interrupt
request vector
number
CPU
I, UI
Figure 5.9 Interrupt Control for DTC
The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt
request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the
DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the
specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number
of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit
is cleared to 0 and an interrupt request is sent to the CPU.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.5, Location of Register
Information and DTC Vector Table, for the respective priorities.
Rev. 3.00, 03/04, page 97 of 830
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to
the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in
the DTC.
Table 5.9
Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Source Selection/Clearing Control
DTCE
DISEL
DTC
CPU
0
*
×
∆
1
0
∆
×
1
∆
[Legend]
∆:
The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
:
The relevant interrupt is used. The interrupt source is not cleared.
×:
The relevant interrupt cannot be used.
*:
Don’t care
Rev. 3.00, 03/04, page 98 of 830
5.7
Usage Notes
5.7.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10
shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
TCR write cycle
by CPU
CMIA exception handling
φ
Internal
address bus
TCR address
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.10 Conflict between Interrupt Generation and Disabling
Rev. 3.00, 03/04, page 99 of 830
5.7.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.7.3
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
5.7.4
EEPMOV.W
MOV.W
R4,R4
BNE
L1
IRQ Status Registers (ISR16, ISR)
Since IRQnF may be set to 1 according to the pin status after a reset, the ISR16 and the ISR
should be read after a reset, and then write 0 in IRQnF (n = 15 to 0).
Rev. 3.00, 03/04, page 100 of 830
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU and data transfer controller (DTC).
6.1
Features
• Extended modes
Two modes for external extension
Normal extended mode: Normal extension (when the ADMXE bit in SYSCR2 is 0)
Address-data multiplex extended mode: Multiplex extension (when the ADMXE bit in
SYSCR2 is 1)
• Extended area division
Possible in normal extended mode
The external address space can be accessed as basic extended areas.
A 256-kbyte extended area can be set and controlled independently of basic extended areas.
A CP extended area can be set and controlled independently of basic extended areas.
• Address pin reduction
In normal extended mode:
A 256-kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address pins
and the CS256 signal.
A CP extended area (8 kbytes, basic mode) from H'FFC000 to H'FFDFFF can be selected
using 13 address pins and the CPCS1 signal.
A 2-kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins
and the IOS signal.
In address-data multiplex extended mode:
The external address space can be accessed as the following three extended areas.
H'F80000 to H'F8FFFF
64 kbytes
256-kbyte extended area
H'FFC000 to H'FFDFFF
8 kbytes
CP extended area
H'FFF000 to H'FFF7FF
2 kbytes
IOS extended area
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data
input/output pins.
• Control address hold signal and aria select signal polarity
The output polarity of IOS, CS256, CPCS1, and AH can be inverted by the PNCCS and
PNCAH bits in LPWRCR
BSCS200A_000220030700
Rev. 3.00, 03/04, page 101 of 830
• Multiplex bus interface
No Wait Inserted
Wait Inserted
Address
Data
Address
Data
2 states *
2 states
2 states *
(3 + wait) states
CP extended area 2 states *
2 states
2 states *
(3 + wait) states
IOS extended area 2 states *
2 states
2 states *
(3 + wait) states
256-kbyte
extended area
Note:
*
A wait cycle is inserted by the setting of the WC22 bit.
• Basic bus interface
2-state access or 3-state access can be selected for each area.
Program wait states can be inserted for each area.
• Burst ROM interface
In normal extended mode
A burst ROM interface can be set for basic extended areas.
1-state access or 2-state access can be selected for burst access.
• Idle cycle insertion
In normal extended mode
An idle cycle can be inserted for external write cycles immediately after external read cycles.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC.
Rev. 3.00, 03/04, page 102 of 830
Bus
controller
External bus control signals
Internal control signals
BCR
BCR2
WSCR
WSCR2
Internal data bus
Bus mode signal
Wait
controller
WAIT
CPU bus request signal
Bus arbiter
DTC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
[Legend]
BCR:
BCR2:
WSCR:
WSCR2:
Bus control register
Bus control register 2
Wait state control register
Wait state control register 2
Figure 6.1 Block Diagram of Bus Controller
Rev. 3.00, 03/04, page 103 of 830
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Symbol
I/O
Function
AS
Output
Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-kbyte
extended area is accessed (the CS256E bit in SYSCR is 1)
or when the CP extended area is accessed (the CPCSE bit
in BCR2 is 1).
IOS
Output
Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
CPCS1
Output
Chip select signal indicating that the CP extended area is
being accessed (when the CPCSE bit in BCR2 is 1).
CS256
Output
Chip select signal indicating that the 256-kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
RD
Output
Strobe signal indicating that the external address space is
being read.
HWR
Output
Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is enabled.
LWR
Output
Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is enabled.
WAIT
Input
Wait request signal when accessing the external space.
AH
Output
Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
AD15 to AD0
Input/Output
Address output and data input/output pins for address-data
multiplex extension.
Rev. 3.00, 03/04, page 104 of 830
6.3
Register Descriptions
The following registers are provided for the bus controller. For the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR). For system control register 2
(SYSCR2), see section 8.6.4, System Control Register 2 (SYSCR2).
•
•
•
•
Bus control register (BCR)
Bus control register 2 (BCR2)
Wait state control register (WSCR)
Wait state control register 2 (WSCR2)
6.3.1
Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space and the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit
Bit Name
Initial
Value
R/W
Description
7

1
R/W
Reserved
The initial value should not be changed.
6
ICIS
1
R/W
Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle cycle
between successive external read and external write cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
5
BRSTRM
0
R/W
Valid only in the normal extended mode.
Burst ROM Enable
Selects the bus interface for the external address space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, burst ROM interface cannot be selected for the
256 -kbyte extended area and CP extended area.
4
BRSTS1
1
R/W
Valid only in the normal extended mode.
Burst Cycle Select 1
Selects the number of states in the burst cycle of the burst
ROM interface.
0: 1 state
1: 2 states
Rev. 3.00, 03/04, page 105 of 830
Bit
Bit Name
Initial
Value
R/W
Description
3
BRSTS0
0
R/W
Valid only in the normal extended mode.
Burst Cycle Select 0
Selects the number of words that can be accessed by burst
access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
2

0
R/W
Reserved
The initial value should not be changed.
1
0
IOS1
IOS0
1
1
R/W
R/W
IOS Select 1 and 0
Select the address range where the IOS signal is output.
See table 6.15.
6.3.2
Bus Control Register 2 (BCR2)
BCR2 is used to specify the access mode for the CP extended area.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0
R/W
Reserved
The initial value should not be changed.
5
ABWCP
1
R/W
CP Extended Area Bus Width Control
Selects the bus width for access to the CP extended area
when the CPCSE bit is set to 1
0: 16-bit bus
1: 8-bit bus
4
ASTCP
1
R/W
CP Extended Area Access State Control
Selects the number of states for access to the CP extended
area when the CPCSE bit is set to 1. This bit also enables or
disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
Rev. 3.00, 03/04, page 106 of 830
Bit
Bit Name
Initial
Value
R/W
Description
3
ADFULLE
0
R/W
Address Output Full Enable
Controls the address output in access to the IOS extended
area, 256-kbyte extended area, or CP extended area. See
section 8, I/O Ports. This is not supported while ADMXE = 1.
2
EXCKS
0
R/W
External Extension Clock Select
Selects the operating clock used in external extended area
access.
0: Medium-speed clock is selected as the operating clock
1: System clock (φ) is selected as the operating clock.
The operating clock is switched in the bus cycle prior to
external extended area access.
1

1
R/W
Reserved
The initial value should not be changed.
0
CPCSE
0
R/W
CP Extended Area Enable
Selects the extended area to be accessed.
0: External address space
1: CP extended area
Rev. 3.00, 03/04, page 107 of 830
6.3.3
Wait State Control Register (WSCR)
WSCR is used to specify the data bus width, the number of access states, the wait mode, and the
number of wait states for access to external address spaces (basic extended area and 256-kbyte
extended area). The bus width and the number of access states for internal memory and internal
I/O registers are fixed regardless of the WSCR settings.
Bit
Bit Name
Initial
Value
R/W
Description
7
ABW256
1
R/W
256-kbyte Extended Area Bus Width Control
Selects the bus width for access to the 256-kbyte extended
area when the CS256E bit in SYSCR is set to 1.
0: 16-bit bus
1: 8-bit bus
6
AST256
1
R/W
256-kbyte Extended Area Access State Control
Selects the number of states for access to the 256-kbyte
extended area when the CS256E bit in SYSCR is set to 1.
This bit also enables or disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
5
ABW
1
R/W
Basic Extended Area Bus Width Control
Selects the bus width for access to the basic extended area.
0: 16-bit bus
1: 8-bit bus
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
Rev. 3.00, 03/04, page 108 of 830
Bit
Bit Name
Initial
Value
R/W
4
AST
1
R/W
Description
Basic Extended Area Access State Control
Selects the number of states for access to the basic extended
area. This bit also enables or disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
3
2
WMS1
WMS0
0
0
R/W
R/W
Basic Extended Area Wait Mode Select 1 and 0
Selects the wait mode for access to the basic extended area
when the AST bit is set to 1.
00: Program wait mode
01: Wait disabled mode
10: Pin wait mode
11: Pin auto-wait mode
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
1
0
WC1
WC0
1
1
R/W
R/W
Basic Extended Area Wait Count 1 and 0
Selects the number of program wait states to be inserted
when the basic extended area is accessed when the AST bit
is set
to 1. The program wait state is only inserted into data cycles.
00: Program wait state is not inserted
01: 1 program wait state is inserted
10: 2 program wait states are inserted
11: 3 program wait states are inserted
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
Rev. 3.00, 03/04, page 109 of 830
6.3.4
Wait State Control Register 2 (WSCR2)
WSCR2 is used to specify the wait mode and number of wait states in access to the 256-kbyte
extended area and CP extended area.
Bit
Bit Name
Initial
Value
R/W
Description
7
WMS10
0
R/W
256-kbyte Extended Area Wait Mode Select 0
Selects the wait mode for access to the 256-kbyte extended
area when the CS256E bit in SYSCR and the AST256 bit in
WSCR are set to 1.
0: Program wait mode
1: Wait disabled mode
6
5
WC11
WC10
1
1
R/W
R/W
256-kbyte Extended Area Wait Count 1 and 0
Selects the number of program wait states to be inserted into
the data cycle for access to the 256-kbyte extended area
when the CS256E bit in SYSCR and the AST256 bit in WSCR
are set to 1.
00: Program wait state is not inserted
01: 1 program wait state is inserted
10: 2 program wait states are inserted
11: 3 program wait states are inserted
4
3
WMS21
WMS20
0
0
R/W
R/W
CP Extended Area Wait Mode Select 1 and 0
Selects the wait mode for access to the CP extended area
when the CPCSE and ASTCP bits in BCR2 are set to 1.
00: Program wait mode
01: Wait disabled mode
10: Pin wait mode
11: Pin auto-wait mode
Rev. 3.00, 03/04, page 110 of 830
• When ADMXE = 0
Bit
Bit Name
Initial
Value
R/W
Description
2
1
0
WC22
WC21
WC20
1
1
1
R/W
R/W
R/W
CP Extended Area Wait Count 2 to 0
Select the number of program wait states to be inserted for
access to the CP extended area when the CPCSE and
ASTCP bits in BCR2 are set to 1.
If the CP extended area is selected, the WC22 bit must be
cleared to 0.
000: Program wait state is not inserted
001: 1 program wait state is inserted
010: 2 program wait states are inserted
011: 3 program wait states are inserted
100: (Setting prohibited)
101: (Setting prohibited)
110: (Setting prohibited)
111: (Setting prohibited)
• When ADMXE = 1
Bit
Bit Name
Initial
Value
R/W
Description
2
WC22
1
R/W
Address-Data Multiplex Extended Area Address Cycle Wait
Count 2
Selects the number of program wait states to be inserted
into the address cycle for access to the address-data
multiplex extended area.
0: Program wait state is not inserted
1: 1 program wait state is inserted in the address cycle
1
0
WC21
WC20
1
1
R/W
R/W
CP Extended Area Data Cycle Wait Count 1 and 0
Selects the number of program wait states to be inserted in
the data cycle for access to the CP extended area when the
CPCSE and ASTCP bits in BCR2 are set to 1.
00: Program wait state is not inserted in the data cycle
01: 1 program wait state is inserted in the data cycle
10: 2 program wait states are inserted in the data cycle
11: 3 program wait states are inserted in the data cycle
Rev. 3.00, 03/04, page 111 of 830
6.4
Bus Control
6.4.1
Bus Specifications
The external address space bus specifications consist of three elements: bus width, the number of
access states, and the wait mode and the number of program wait states. The bus width and the
number of access states for on-chip memory and internal I/O registers are fixed, and are not
affected by the bus controller settings.
(1) In Normal Extended Mode
(a) Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in
WSCR, and the ABWCP bit in BCR2.
(b) Number of Access States: Two or three access states can be selected via the AST and
AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated,
wait-state insertion is disabled.
In the burst ROM interface, the number of access states for the basic extended area is determined
regardless of the AST bit setting.
(c) Wait Mode and Number of Program Wait States: When the basic extended area is specified
as a 3-state access space by the AST bit in WSCR, the wait mode and the number of program wait
states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in
WSCR. From 0 to 3 program wait states can be selected.
When the 256-kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. From 0 to 3 program wait states can
be selected.
When the CP extended area is specified as a 3-state access space by the ASTCP bit in BCR2, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS21, WMS20, WC21, and WC20 bits in WSCR2. From 0 to 3 program wait states can be
selected.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC are to be delayed.
Tables 6.2 to 6.6 show each bit setting and external address space division in the address ranges of
the external address space, and the bus specifications for the basic bus interface of each area.
Rev. 3.00, 03/04, page 112 of 830
Table 6.2
Address Ranges and External Address Spaces
Areas
Address Range
H'080000 to H'F7FFFF
Basic Extended Area
No condition
256-kbyte Extended Area, CP
Extended Area (Basic Mode)

(15 Mbytes)
H'F80000 to H'FBFFFF
(256 kbytes)
∆ When CS256E = 0, used as
basic extended area.
256-kbyte extended area
H'FC0000 to H'FEFFFF
No condition
When WAIT pin function is not
selected while CS256E = 1,
CS256 is output and address
pins A17 to A0 are used.

(192 kbytes)
H'FF0800 to H'FFBFFF
(46 kbytes)
H'FFC000 to H'FFDFFF
(8 kbytes)
∆ When RAME = 0, used as
basic extended area.

∆ When CPCSE = 0, used as
basic extended area.
When CPCSE = 1, CPCS1 is
output in the CP extended area
and address pins A12 to A0 are
used.
CP extended area
H'FFE000 to H'FFE07F
No condition

(128 bytes)
H'FFE080 to H'FFEFFF
(3968 bytes)
H'FFF000 to H'FFF7FF
(2 kbytes)
H'FFFF00 to H'FFFF7F
(128 bytes)
∆ When RAME = 0, used as
basic extended area.

No condition

When IOSE = 1, IOS is
output and address pins A10
to A0 are used.
∆ When RAME = 0, used as
basic extended area.

[Legend]
:
This address range unconditionally accessed as the basic extended area.
∆:
Condition for making this address range accessed as the basic extended area.
:
This address range cannot be used as a 256-kbyte extended area or CP extended area.
Rev. 3.00, 03/04, page 113 of 830
Table 6.3
Bit Settings and Bus Specifications of Basic Bus Interface
Areas
BRSTRM CS256E
CPCSE
0
0
0
1
1
Basic Extended
Area
256-kbyte
Extended Area
CP Extended Area (Basic
Mode)
Basic extended
area
ABW, AST,
WMS1, WMS0,
WC1, WC0
Used as basic
extended area
Used as basic extended
area
0
ABW256, AST256, Same as when CS256E = 0
WMS10, WC11,
WC10
1
1
0
1
0
Burst ROM
interface*
1
ABW, AST,
WMS0, WC1,
WC0, BRSTS1,
BRSTS0
0
1
Note:
*
ABWCP, ASTCP, WMS21,
WMS20, WC21, WC20
Used as burst
ROM interface
Used as burst ROM
interface
ABWCP, ASTCP, WMS21,
WMS20, WC21, WC20
ABW256, AST256, Same as when CS256E = 0
WMS10, WC11,
WC10
In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the
number of full access states (wait can be inserted) is specified by the AST bit in WSCR,
and the number of access cycles in burst access is specified regardless of the AST bit
setting.
Rev. 3.00, 03/04, page 114 of 830
Table 6.4
Bus Specifications for Basic Extended Area/Basic Bus Interface
Bus Specifications
Number of
Program
Wait
States
ABW
AST
WMS1
WMS0
WC1
WC0
Bus Width
Number of
Access
States
0
0
*
*
*
*
16
2
0
1
0
1
*
*
16
3
0
0
0
3
0
Other than
WMS1 = 0 and
WMS0 = 1
1
1
1
1
0
2
1
3
0
*
*
*
*
8
2
0
1
0
1
*
*
8
3
0
0
0
3
0
Other than
WMS1 = 0 and
WMS0 = 1
1
1
1
0
2
1
3
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 115 of 830
Table 6.5
Bus Specifications for 256-kbyte Extended Area/Basic Bus Interface
Bus Specifications
ABW256
AST256
WMS10
WC11
WC10
Bus Width
Number of
Access States
0
0
*
*
*
16
2
16
1
1
*
*
0
0
0
1
1
Number of
Program Wait
States
0
3
0
3
0
1
1
0
2
1
3
0
*
*
*
8
2
0
1
1
*
*
8
3
0
0
0
0
3
0
1
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 116 of 830
1
1
0
2
1
3
Table 6.6
Bus Specifications for CP Extended Area (Basic Mode)/Basic Bus Interface
Bus Specifications
ABWCP ASTCP
WMS21
WMS20 WC21
WC20
Bus Width
Number of
Number of Program
Access
Wait
States
States
0
0
*
*
*
*
16
2
0
1
0
1
*
*
16
3
0
0
0
3
0
Other than
WMS21 = 0 and
WMS20 = 1
1
1
0
1
*
*
0
1
Other than
WMS21 = 0 and
WMS20 = 1
1
1
0
2
1
3
*
8
*
*
8
0
0
*
1
2
0
3
0
3
0
1
1
0
2
1
3
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 117 of 830
(2) In Address-Data Multiplex Extended Mode
(a) Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in
WSCR, and the ABWCP bit in BCR2.
(b) Number of Access States: Two or three states can be selected for data access via the AST and
AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated,
wait-state insertion is disabled.
(c) Wait Mode and Number of Program Wait States:
i)
IOS Extended Area
When the IOS extended area is specified as a 3-state access space by the AST bit in WSCR, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS1, WMS0, WC1, and WC0 bits in WSCR. Zero or one program wait state can be inserted
into address cycle. From zero to three program wait states can be selected for data cycle.
ii)
256-kbyte Extended Area
When the 256-kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. Zero or one program wait state can be
inserted into address cycle. From zero to three program wait states can be selected for data cycle.
iii)
CP Extended Area
When the CP extended area is specified as a 3-state access space by the ASTCP bit in BCR2, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS21, WMS20, WC22, WC21, and WC20 bits in WSCR2. Zero or one program wait state can
be inserted into address cycle. From zero to three program wait states can be selected for data
cycle.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC, are to be delayed.
Tables 6.7 to 6.14 show address-data multiplex address space and the bus specifications for the
basic bus interface of each area.
Rev. 3.00, 03/04, page 118 of 830
Table 6.7
Address-Data Multiplex Address Spaces
Address Range
Address-Data Multiplex Area
H'080000 to H'F7FFFF

No condition
O
When the WAIT pin function is not selected and CS256E
= 1, CS256 is output and address AD15 to AD0 or AD7 to
AD0 are used.

No condition

No condition

No condition

No condition
O
When CPCSE = 1, CPCS1 is output, and address pins
AD15 to AD0 or AD7 to AD0 are used.

No condition
O
When IOSE = 1, IOS is output and address pins AD15 to
AD0 or AD7 to AD0 are used.

No condition
(15 Mbytes)
256-kbyte extended area
H'F80000 to H'F8FFFF
(64 kbytes)
256-kbyte extended area
H'F90000 to H'F9FFFF
(64 kbytes)
256-kbyte extended area
H'FA0000 to H'FAFFFF
(64 kbytes)
256-kbyte extended area
H'FB0000 to H'FBFFFF
(64 kbytes)
H'FC0000 to H'FFBFFF
(240 kbytes)
CP extended area
H'FFC000 to H'FFDFFF
(8 kbytes)
H'FFE000 to H'FFEFFF
(4 kbytes)
IOS extended area
H'FFF000 to H'FFF7FF
(2 kbytes)
H'FFFF00 to H'FFFF7F
(128 bytes)
[Legend]
:
This address range cannot be used as the address-data multiplex address space.
O:
Condition for making this address range accessed as the address-data multiplex address
space.
Rev. 3.00, 03/04, page 119 of 830
Table 6.8
Bit Settings and Bus Specifications of Basic Bus Interface
Area
IOSE
CS256E
CPCSE
1
0
0
IOS Extended
Area
0
1
0
0
CP Extended Area
ABW, AST, WMS1, 
WMS0, WC1, WC0
1
1
256-kbyte
Extended Area

0

ABWCP, ASTCP,
WMS21, WMS20, WC21,
WC20
ABW256, AST256,
WMS10, WC11,
WC10
Same as when CS256E
=0


1
1
ABWCP, ASTCP,
WMS21, WMS20, WC21,
WC20
0
ABW256, AST256,
WMS10, WC11,
WC10
1
Table 6.9
Same as when CS256E
=0
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Address
Cycle)
AST
WMS1
WMS0
WC22
WC1
WC0
Number of
Access
States



0


2
1


Number of
Program
Wait States
0
1
Table 6.10 Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle)
AST
WMS1
WMS0
WC1
WC0
Number of
Access
States
0
—
—
—
—
2
0
0
1
—
1
Number of
Program
Wait States
—
3
0
Other than WMS1 = 0 and 0
WMS0 = 1
0
3
0
1
1
1
0
2
1
3
Rev. 3.00, 03/04, page 120 of 830
Table 6.11 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Address Cycle)
AST256
WMS10
WC22
WC11
WC10
Number of
Access
States


0


2
1


Number of
Program
Wait States
0
1
Table 6.12 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Data Cycle)
WMS1
WC1
WC0
Number of
Number of
Program Wait
Access States States
0
—
—
—
2
0
1
1
—
—
3
0
0
0
0
3
0
AST256
1
1
1
0
2
1
3
Table 6.13 Bus Specifications for CP Extended Area/Multiplex Bus Interface
(Address Cycle)
ASTCP
WMS21
WMS20
WC22
WC21
WC20
Number of
Number of Program
Access
Wait
States
States
—
—
—
0
—
—
2
1
—
—
0
1
Rev. 3.00, 03/04, page 121 of 830
Table 6.14 Bus Specifications for CP Extended Area/Multiplex Bus Interface (Data Cycle)
ASTCP
WMS21
WMS20
WC22
WC21
WC20
Number of
Number of Program
Access
Wait
States
States
0
—
—
—
—
—
2
0
1
0
1
—
—
—
3
0
0
0
3
0
Other than WMS21 = 0 —
and WMS20 = 1
1
6.4.2
1
1
0
2
1
3
Advanced Mode
The external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS
pin as an I/O strobe pin. The 256-kbyte extended area (H'F80000 to H'FBFFFF) and CP extended
area (H'FFC000 to H'FFDFFF) can be accessed by the CS256 pin and CPCS1 pin functions,
respectively.
The external address space is initialized as the basic bus interface and a 3-state access space. In
mode 2, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their
reserved areas is specified as the external address space. The on-chip RAM and its reserved area
are enabled when the RAME bit in SYSCR is set to 1, and disabled when the RAME bit is cleared
to 0. Addresses H'FF0800 to H'FFBFFF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F in
the on-chip RAM area and its reserved area are always specified as the external address space.
Rev. 3.00, 03/04, page 122 of 830
6.4.3
I/O Select Signals
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding
external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Bus cycle
T1
T2
T3
φ
Address bus
External addresses selected by IOS
IOS
Figure 6.2 IOS Signal Output Timing
Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In the extended
mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE
bit to 1. For details, see section 8, I/O Ports.
The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR,
as shown in table 6.15.
Table 6.15 Address Range for IOS Signal Output
IOS1
IOS0
IOS Signal Output Range
0
0
H'FFF000 to H'FFF03F
1
H'FFF000 to H'FFF0FF
0
H'FFF000 to H'FFF3FF
1
H'FFF000 to H'FFF7FF
1
(Initial value)
Rev. 3.00, 03/04, page 123 of 830
6.5
Bus Interface
The normal extended bus interface enables direct connection to ROM and SRAM. For details on
selection of the bus specifications for the basic extended area, 256-kbyte extended area, and CP
extended area, see tables 6.4 to 6.6.
The address-data multiplex extended bus interface enables direct connection to products that
supports this bus interface. For details on selection of the bus specifications for the IOS extended
area, 256-kbyte extended area, and CP extended area, see tables 6.9 to 6.14.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or
lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed,
according to the bus specifications for the area being accessed (8-bit access space or 16-bit access
space) and the data size.
(1) 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space.
With the 8-bit access space, the upper data bus (D15 to D8/AD15 to AD8) is always used for
accesses. The amount of data that can be accessed at one time is one byte: a word access is
performed as two byte accesses, and a longword access, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
Longword
size
7
0
1st bus cycle
15
8
2nd bus cycle
7
0
1st bus cycle
31
24
2nd bus cycle
23
16
3rd bus cycle
15
8
4th bus cycle
7
0
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
Rev. 3.00, 03/04, page 124 of 830
(2) 16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus
(D7 to D0/AD7 to AD0) are used for accesses. The amount of data that can be accessed at one
time is one byte or one word, and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for even addresses, and the lower data bus for odd
addresses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
· Even address
Byte size
· Odd address
8
7
0
15
8 7
0
1st bus cycle
31
24 23
16
2nd bus cycle
15
8 7
0
Word size
Longword
size
15
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
Rev. 3.00, 03/04, page 125 of 830
6.5.2
Valid Strobes
Table 6.16 shows the data buses used and valid strobes for each access space.
In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the
HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.16 Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
Valid
Strobe
Lower Data
Upper Data Bus Bus (D7 to
(D15 to D8/
D0/AD7 to
AD15 to AD8)
AD0)
8-bit access
space
Byte
Read
—
RD
Valid
Write
—
HWR
16-bit access
space
Byte
Read
Even
RD
Write
Even
HWR
Odd
Read
Write
Area
Ports or others
Valid
Invalid
Invalid
Valid
Valid
Undefined
LWR
Undefined
Valid
—
RD
Valid
Valid
—
HWR, LWR
Valid
Valid
Odd
Word
Ports or others
[Legend]
Undefined:
Undefined data is output.
Invalid:
Input state with the input value ignored.
Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the
data bus.
Rev. 3.00, 03/04, page 126 of 830
6.5.3
Basic Operation Timing in Normal Extended Mode
(1) 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access
space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
Rev. 3.00, 03/04, page 127 of 830
(2) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access
space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
Rev. 3.00, 03/04, page 128 of 830
(3) 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be
inserted.
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High level
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
Rev. 3.00, 03/04, page 129 of 830
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)
Rev. 3.00, 03/04, page 130 of 830
Bus cycle
T2
T1
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
Rev. 3.00, 03/04, page 131 of 830
(4) 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state
access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is
used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High level
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
Rev. 3.00, 03/04, page 132 of 830
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)
Rev. 3.00, 03/04, page 133 of 830
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
Rev. 3.00, 03/04, page 134 of 830
6.5.4
Basic Operation Timing in Address-Data Multiplex Extended Mode
(1) 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the
data bus is used. Wait states cannot be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
T1
TAW
Data
T2
T3
T4
φ
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Data
Address
Data
Address
Figure 6.13 Bus Timing for 8-Bit, 2-State Access Space
Read Cycle
Address
T1
T2
Write Cycle
Data
T3
Address
T4
T1
Data
T2
T3
T4
φ
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Address
Data
Address
Data
Figure 6.14 Bus Timing for 8-Bit, 2-State Access Space
Rev. 3.00, 03/04, page 135 of 830
(2) 8-Bit, 3-State Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state
access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used. Wait states can be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
T4
TDSW
Data
Address
T5
T1
TAW
T2
T3
T4
TDSW
T5
φ
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Address
Data
Address
Data
Figure 6.15 Bus Timing for 8-Bit, 3-State Access Space
(3) 16-Bit, 2-State Data Access Space: Figures 6.16 to 6.21 show bus timings for a 16-bit, 2-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
cannot be inserted.
Rev. 3.00, 03/04, page 136 of 830
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
Data
Address
T4
T1
TAW
T2
T3
T4
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Data
Address
Address
Figure 6.16 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)
Write Cycle
Read Cycle
Data
Address
T1
T2
T3
Address
T4
T1
T2
Data
T3
T4
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Address
Data
Address
Figure 6.17 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)
Rev. 3.00, 03/04, page 137 of 830
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
Data
Address
T4
T1
TAW
T2
T3
T4
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Data
Address
Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access)
Write Cycle
Read Cycle
Address
T1
T2
Data
T3
Address
T4
T1
T2
Data
T3
T4
φ
CK2S
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Address
Data
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access)
Rev. 3.00, 03/04, page 138 of 830
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
T1
TAW
Data
T2
T3
T4
φ
CPCS2
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)
Write Cycle
Read Cycle
Data
Address
T1
T2
T3
Address
T4
T1
T2
Data
T3
T4
φ
CPCS1
CP256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)
Rev. 3.00, 03/04, page 139 of 830
(4) 16-Bit, 3-State Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
can be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
T4
TDSW
Data
Address
T5
T1
TAW
T2
T3
T4
TDSW
T5
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Data
Address
Address
Figure 6.22 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
T4
TDSW
Data
Address
T5
T1
TAW
T2
T3
T4
TDSW
T5
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Address
Data
Figure 6.23 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)
Rev. 3.00, 03/04, page 140 of 830
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
T4
TDSW
Data
Address
T5
T1
TAW
T2
T3
T4
TDSW
T5
φ
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
6.5.5
Wait Control
When accessing the external address space, this LSI can extend the bus cycle by inserting one or
more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin
wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin.
(1) In Normal Extended Mode
(a) Program Wait Mode: A specified number of wait states TW are always inserted between the
T2 state and T3 state when accessing the external address space. The number of wait states TW is
specified by the settings of the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in
WSCR2 for the 256-kbyte extended area, and the WC21 and WC20 bits in WSCR2 for the CP
extended area).
(b) Pin Wait Mode: A specified number of wait states TW are always inserted between the T2 state
and T3 state when accessing the external address space. The number of wait states TW is specified
by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP extended area). If
the WAIT pin is low at the falling edge of φ in the last T2 or TW state, another TW state is inserted.
If the WAIT pin is held low, TW states are inserted until it goes high.
Pin wait mode is useful when inserting four or more TW states, or when changing the number of TW
states to be inserted for each external device.
Rev. 3.00, 03/04, page 141 of 830
(c) Pin Auto-Wait Mode: A specified number of wait states TW are inserted between the T2 state
and T3 state when accessing the external address space if the WAIT pin is low at the falling edge
of φ in the last T2 state. The number of wait states TW is specified by the settings of the WC1 and
WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low,
TW states are inserted only up to the specified number of states.
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.25 shows an example of wait state insertion timing in pin wait mode.
The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input
disabled.
By program wait
T1
T2
TW
By WAIT pin
TW
TW
T3
φ
WAIT
Address bus
IOS (IOSE = 1)
CPCS1 (CPCSE = 1)
AS * (IOSE = 0)
RD
Read
Data bus
Read data
WR
Write
Data bus
Write data
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
* For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.25 Example of Wait State Insertion Timing (Pin Wait Mode)
Rev. 3.00, 03/04, page 142 of 830
(2) In Address-Data Multiplex Extended Mode
(a) Program Wait Mode: Program wait mode includes address wait and data wait.
256-kbyte extended area and IOS extended area:
Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states of
data wait TDSW is inserted between T4 and T5 states.
CP extended area:
Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states of
data wait TDSW is inserted between T4 and T5 states.
(b) Pin Wait Mode: When accessing the external address space, a specified number of wait states
TDSW can be inserted between the T4 state and T5 state of data state. The number of wait states TDSW
is specified by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP
extended area). If the WAIT pin is low at the falling edge of φ in the last T4, TDSW, or TDOW state,
another TDOW state is inserted. If the WAIT pin is held low, TDOW states are inserted until it goes
high.
Pin wait mode is useful when inserting four or more TDOW states, or when changing the number of
TDOW states to be inserted for each external device.
(c) Pin Auto-Wait Mode: A specified number of wait states TDOW are inserted between the T4 state
and T5 state when accessing the external address space if the WAIT pin is low at the falling edge
of φ in the last T4 state. The number of wait states TDOW is specified by the settings of the WC1 and
WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low,
TDOW states are inserted only up to the specified number of states.
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.26 shows an example of wait state insertion timing in pin wait mode.
Rev. 3.00, 03/04, page 143 of 830
Write Cycle
Read Cycle
Data
T3
T4
TDSW TDOW TDOW
Data
T5
T3
T4
TDSW TDOW TDOW
φ
CPCS1
CS256
IOS
WAIT
AH
RD
HWR
LWR
AD15 to AD8
Data
Data
AD7 to AD0
Data
Data
Figure 6.26 Example of Wait State Insertion Timing
Rev. 3.00, 03/04, page 144 of 830
T5
6.6
Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM
bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four
or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected
for burst ROM access.
6.6.1
Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.27 and 6.28.
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Only lower address changes
Address bus
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.27 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
Rev. 3.00, 03/04, page 145 of 830
Full access
T1
T2
Burst access
T1
T1
φ
Only lower
address changes
Address bus
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2
Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is
possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.5,
Wait Control. Wait states cannot be inserted in a burst cycle.
Rev. 3.00, 03/04, page 146 of 830
6.7
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle
is inserted at the start of the write cycle.
Figure 6.29 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.29 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.29 (b), an idle cycle is inserted, thus preventing data collision.
Bus cycle A
T2
T1
T3
Bus cycle B
T1
Bus cycle A
T1
T2
φ
φ
Address bus
Address bus
RD
RD
WR
WR
Data bus
Data bus
T2
T3
Bus cycle B
TI
T1
T2
Data collision
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.29 Examples of Idle Cycle Operation
Table 6.17 shows the pin states in an idle cycle.
Table 6.17 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of immediately following bus cycle
D15 to D0
High impedance
AS, IOS, CS256, CPCS1
High
RD
High
HWR, LWR
High
Rev. 3.00, 03/04, page 147 of 830
6.8
Bus Arbitration
6.8.1
Overview
The BSC has a bus arbiter that arbitrates bus master operations. There are two bus masters – the
CPU and DTC – that perform read/write operations while they have bus mastership.
6.8.2
Operation
Each bus master requests the bus mastership by means of a bus mastership request signal. The bus
arbiter detects the bus mastership request signal from the bus masters, and if a bus request occurs,
it sends a bus mastership request acknowledge signal to the bus master that made the request at the
designated timing. If there are bus requests from more than one bus master, the bus mastership
request acknowledge signal is sent to the one with the highest priority. When a bus master receives
the bus mastership request acknowledge signal, it takes the bus mastership until that signal is
canceled. The order of bus master priority is as follows:
(High) DTC > CPU (Low)
6.8.3
Bus Mastership Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus mastership and is currently operating, the bus mastership is not
necessarily transferred immediately. Each bus master can relinquish the bus mastership at the
timings given below.
CPU: The CPU is the lowest-priority bus master, and if a bus mastership request is received from
the DTC, the bus arbiter transfers the bus mastership to the DTC. The timing for transferring the
bus mastership is as follows:
• Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
in discrete operations, as in the case of a long-word size access, the bus is not transferred at a
break between the operations. For details see section 2.7, Bus States During Instruction
Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual.
• If the CPU is in sleep mode, it transfers the bus mastership immediately.
DTC: The DTC sends the bus arbiter a request for the bus mastership when a request for DTC
activation occurs. The DTC releases the bus mastership after a series of processes has completed.
Rev. 3.00, 03/04, page 148 of 830
Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus
connects the DTC to addresses H'FFEC00 to H'FFEFFF in on-chip RAM (1 kbyte), enabling 32bit/1-state reading and writing of the DTC register information.
7.1
•
•
•
•
•
•
•
•
•
Features
Transfer is possible over any number of channels
Three transfer modes
 Normal, repeat, and block transfer modes are available
One activation source can trigger a number of data transfers (chain transfer)
Direct specification of 16 Mbytes address space is possible
Activation by software is possible
Transfer can be set in byte or word units
A CPU interrupt can be requested for the interrupt that activated the DTC
Module stop mode can be set
DTC operates in high-speed mode even when the LSI is in medium-speed mode
DTCH80CA_020020030700
Rev. 3.00, 03/04, page 149 of 830
Internal address bus
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERE:
DTVECR:
Internal data bus
DTC mode register A, B
DTC transfer count register A, B
DTC source address register
DTC destination address register
DTC enable registers A to E
DTC vector register
Figure 7.1 Block Diagram of DTC
Rev. 3.00, 03/04, page 150 of 830
Register information
MRA MRB
CRA
CRB
DAR
SAR
On-chip RAM
Control logic
DTC
DTC activation request
DTVECR
Interrupt
request
DTCERA
to
DTCERE
Interrupt controller
7.2
Register Descriptions
The DTC has the following registers.
•
•
•
•
•
•
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
•
•
•
•
•
DTC enable registers (DTCER)
DTC vector register (DTVECR)
Keyboard comparator control register (KBCOMP)
Event counter control register (ECCR)
Event counter status register (ECS)
Rev. 3.00, 03/04, page 151 of 830
7.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
7
6
SM1
SM0
Initial
Value
R/W
Description
Undefined
—
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0*: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
5
4
DM1
DM0
Undefined
—
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0*: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
3
2
MD1
MD0
Undefined
—
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined
—
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined
—
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
[Legend]
*:
Don't care
Rev. 3.00, 03/04, page 152 of 830
7.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
CHNE
Undefined
—
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.6.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
6
DISEL
Undefined
—
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. When this bit
is cleared to 0, a CPU interrupt request is generated
only when the specified number of data transfer ends.
5 to 0
—
Undefined
—
Reserved
These bits have no effect on DTC operation. The write
value should always be 0.
7.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Rev. 3.00, 03/04, page 153 of 830
7.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
7.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7
DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in
tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit
Bit Name
7 to 0
DTCE7 to
DTCE0
Initial
Value
R/W
Description
All 0
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
as a DTC activation source.
[Clearing conditions]
•
When data transfer has ended with the DISEL bit in
MRB set to 1
•
When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed
Rev. 3.00, 03/04, page 154 of 830
Table 7.1
Correspondence between Interrupt Sources and DTCER
Register
Bit
Bit Name
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
7
DTCEn7
(16)IRQ0
(53)OCIB
(69)CMIB1
(86)TXI1

6
DTCEn6
(17)IRQ1
(76)IICI2
(72)CMIAY
(89)RXI2

5
DTCEn5
(18)IRQ2
(94)IICI0
(73)CMIBY
(90)TXI2

4
DTCEn4
(19)IRQ3

(29)EVENTI
(78)IICI3

3
DTCEn3
(28)ADI

(44)CMIAX
(98)IICI1
(104)ERR1
2
DTCEn2
(48)ICIA
(64)CMIA0
(81)RXI0

(105)IBFI1
1
DTCEn1
(49)ICIB
(65)CMIB0
(82)TXI0

(106)IBFI2
0
DTCEn0
(52)OCIA
(68)CMIA1
(85)RXI1
(45)CMIBX
(107)IBFI3
[Legend]
n:
A to E
( ):
Vector number
:
Reserved. The write value should always be 0.
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
Initial
Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written
to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified number
of transfers have not ended
•
When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number
of transfers has ended.
Rev. 3.00, 03/04, page 155 of 830
Initial
Value
Bit
Bit Name
6 to 0
DTVEC6 to All 0
DTVEC0
R/W
R/W
Description
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to DTVEC0
= H'10, the vector address is H'0420. When the
SWDTE bit is 0, these bits can be written to.
7.2.9
Keyboard Comparator Control Register (KBCOMP)
KBCOMP enables or disables the comparator scan function of event counter.
Bit
Bit Name
Initial
Value
R/W
Description
7
EVENTE
0
R/W
Event Count Enable
0: Disables event count function
1: Enables event count function
6, 5

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
4 to 0

All 0
R/W
Reserved
The initial value should not be changed.
Rev. 3.00, 03/04, page 156 of 830
7.2.10
Event Counter Control Register (ECCR)
ECCR selects the event counter channels for use and the detection edge.
Bit
Bit Name
Initial
Value
R/W
Description
7
EDSB
0
R/W
Event Counter Edge Select
Selects the detection edge for the event counter.
0: Counts the rising edges
1: Counts the falling edges
6 to 4
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3 to 0
ECSB3 to
ECSB0
All 0
R/W
Event Counter Channel Select 3 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
0000: EVENT0 is used
0001: EVENT0 to EVENT1 are used
0010: EVENT0 to EVENT2 are used
0011: EVENT0 to EVENT3 are used
0100: EVENT0 to EVENT4 are used
0101: EVENT0 to EVENT5 are used
0110: EVENT0 to EVENT6 are used
0111: EVENT0 to EVENT7 are used
1000: EVENT0 to EVENT8 are used
1001: EVENT0 to EVENT9 are used
1010: EVENT0 to EVENT10 are used
1011: EVENT0 to EVENT11 are used
1100: EVENT0 to EVENT12 are used
1101: EVENT0 to EVENT13 are used
1110: EVENT0 to EVENT14 are used
1111: EVENT0 to EVENT15 are used
Rev. 3.00, 03/04, page 157 of 830
7.2.11
Event Counter Status Register (ECS)
ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be
incremented according to the state of this register. Reading this register allows the monitoring of
events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
Initial
Value
Bit
Bit Name
15 to 0
E15 to E0 0
R/W
Description
R
Event Monitor 15 to 0
These bits indicate processed/unprocessed states of
the events that are input to EVENT15 to EVENT0.
0: The corresponding event is already processed
1: The corresponding event is not yet processed
Rev. 3.00, 03/04, page 158 of 830
7.3
DTC Event Counter
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below.
Table 7.2
DTC Event Counter Conditions
Register
Bit
Bit Name
MRA
7, 6
SM1, SM0 00: SAR is fixed.
MRB
Description
5, 4
DM1, DM0 00: DAR is fixed.
3, 2
MD1, MD0 01: Repeat mode
1
DTS
0: Destination is repeat area
0
Sz
1: Word size transfer
7
CHNE
0: Chain transfer is disabled
6
DISEL
0: Interrupt request is generated when data is transferred by
the number of specified times
5 to 0

B'000000
SAR
23 to 0

Identical optional RAM address. Its lower five bits are B'00000.
DAR
23 to 0

The start address of 16 words is this address. They are
incremented every time an event is detected in EVENT0 to
EVENT15.
CRAH
7 to 0

H'FF
CRAL
7 to 0

H'FF
CRBH
7 to 0

H'FF
CRBL
7 to 0

H'FF
DTCERC
4
DTCEC4
1: DTC function of the event counter is enabled
KBCOMP
7
EVENTE
1: Event counter enable
RAM


(SAR, DAR) : Result of EVENT0 count
(SAR, DAR) + 2: Result of EVENT 1 count
(SAR, DAR) + 4: Result of EVENT 2 count
↓
(SAR, DAR) + 30: Result of EVENT 15 count
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the
ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag
state, status/address codes are generated.
An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the
same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced
with address code that is generated by the ECS flag status.
Rev. 3.00, 03/04, page 159 of 830
When the DTC transfer is completed, the ECS flag for transfer is cleared.
Table 7.3
Flag Status/Address Code
ECS
15
14
13
12
11
10
9
1
1
7.3.1
8
7
6
5
4
3
2
1
0
Address
Code
1
B'00000
1
0
B'00010
1
0
0
B'00100
1
0
0
0
B'00110
1
0
0
0
0
B'01000
1
0
0
0
0
0
B'01010
1
0
0
0
0
0
0
B'01100
1
0
0
0
0
0
0
0
B'01110
1
0
0
0
0
0
0
0
0
B'10000
0
0
0
0
0
0
0
0
0
B'10010
1
0
0
0
0
0
0
0
0
0
0
B'10100
1
0
0
0
0
0
0
0
0
0
0
0
B'10110
1
0
0
0
0
0
0
0
0
0
0
0
0
B'11000
1
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11010
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11100
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11110
Event Counter Handling Priority
EVENT0 to EVENT15 count handling is operated in the priority shown as below.
High
Low
EVENT0 > EVENT1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ EVENT14 > EVENT15
Rev. 3.00, 03/04, page 160 of 830
7.3.2
Usage Notes
There are following usage notes for this event counter because it uses the DTC. If these usage
notes are not permitted in some applications, use functions such as 8-bit timer event count.
1.
2.
3.
7.4
Continuous events that are input from the same pin and out of DTC handling are ignored
because the count up is operated by means of the DTC.
If some events are generated in short intervals, the priority of event counter handling is not
ordered and events are not handled in order of arrival.
If the counter overflows, this event counter counts from H'0000 without generating an
interrupt.
Activation Sources
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt
request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last
consecutive transfer in the case of chain transfer), the interrupt flag that became the activation
source or the corresponding DTCER bit is cleared. The activation source flag, in the case of
RXI0, for example, is the RDRF flag in SCI_0.
When an interrupt has been designated as a DTC activation source, the existing CPU mask level
and interrupt controller priorities have no effect. If there is more than one activation source at the
same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block
diagram of DTC activation source control. For details on the interrupt controller, see section 5,
Interrupt Controller.
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
peripheral
module
IRQ interrupt
DTVECR
Interrupt
request
Selection circuit
Select
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 7.2 Block Diagram of DTC Activation Source Control
Rev. 3.00, 03/04, page 161 of 830
7.5
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
Register information should be located at an address that is a multiple of four within the range.
The method for locating the register information in address space is shown in figure 7.3. Locate
MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3, and the register information start address should be located at the
vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the
start address of the register information from the vector table set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register
information start address.
Lower address
0
Register
information
start address
Chain
transfer
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
MRA
SAR
MRB
DAR
Register information
for 2nd transfer in
chain transfer
CRB
CRA
4 bytes
Figure 7.3 DTC Register Information Location in Address Space
Rev. 3.00, 03/04, page 162 of 830
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Activation
Source Origin
Activation Source
Vector
Number
DTC Vector
Address
Software
Write to DTVECR
DTVECR
External pins
IRQ0
IRQ1
IRQ2
IRQ3
ADI
EVENTI
CMIAX
CMIBX
ICIA
ICIB
OCIA
OCIB
CMIA0
16
17
18
19
28
29
44
45
48
49
52
53
64
H'0400 + (vector
number x 2)
H'0420
H'0422
H'0424
H'0426
H'0438
H'043A
H'0458
H'045A
H'0460
H'0462
H'0468
H'046A
H'0480
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEC4
DTCEC3
DTCED0
DTCEA2
DTCEA1
DTCEA0
DTCEB7
DTCEB2
CMIB0
CMIA1
CMIB1
CMIAY
CMIBY
IICI2
IICI3
RXI0
TXI0
RXI1
TXI1
RXI2
TXI2
IICI0
65
68
69
72
73
76
78
81
82
85
86
89
90
94
H'0482
H'0488
H'048A
H'0490
H'0492
H'0498
H'049C
H'04A2
H'04A4
H'04AA
H'04AC
H'04B2
H'04B4
H'04BC
DTCEB1
DTCEB0
DTCEC7
DTCEC6
DTCEC5
DTCEB6
DTCED4
DTCEC2
DTCEC1
DTCEC0
DTCED7
DTCED6
DTCED5
DTCEB5
A/D converter
EVC
TMR_X
FRT
TMR_0
TMR_1
TMR_Y
IIC_2
IIC_3
SCI_0
SCI_1
SCI_2
IIC_0
DTCE*
Priority
—
High
Low
Rev. 3.00, 03/04, page 163 of 830
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont)
Activation
Source Origin
IIC_1
LPC
Note:
*
Activation Source
Vector
Number
DTC Vector
Address
DTCE*
Priority
IICI1
98
H'04C4
DTCED3
High
ERRI
104
H'04D0
DTCEE3
IBFI1
105
H'04D2
DTCEE2
IBFI2
106
H'04D4
DTCEE1
IBFI3
107
H'04D6
DTCEE0
Low
DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0.
Rev. 3.00, 03/04, page 164 of 830
7.6
Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register
information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated
register information back to on-chip RAM. The pre-storage of register information in memory
makes it possible to transfer data over any required number of channels. The transfer mode can be
specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it
possible to perform a number of transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1
Yes
No
Transfer counter = 0
or DISEL = 1
Yes
No
Clear an activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 7.4 DTC Operation Flowchart
Rev. 3.00, 03/04, page 165 of 830
7.6.1
Normal Mode
In normal mode, one activation source transfers one byte or one word of data. Table 7.5 lists the
register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified
number of transfers has been completed, a CPU interrupt can be requested.
Table 7.5
Register Functions in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register A
CRA
Transfer counter
DTC transfer count register B
CRB
Not used
DAR
SAR
Transfer
Figure 7.5 Memory Mapping in Normal Mode
Rev. 3.00, 03/04, page 166 of 830
7.6.2
Repeat Mode
In repeat mode, one activation source transfers one byte or one word of data. Table 7.6 lists the
register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified
number of transfers has been completed, the initial states of the transfer counter and the address
register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the
transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when
the DISEL bit in MRB is cleared to 0.
Table 7.6
Register Functions in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Transfer Count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 7.6 Memory Mapping in Repeat Mode
Rev. 3.00, 03/04, page 167 of 830
7.6.3
Block Transfer Mode
In block transfer mode, one activation source transfers one block of data. Either the transfer source
or the transfer destination is designated as a block area. Table 7.7 lists the register functions in
block transfer mode. The block size can be between 1 and 256. When the transfer of one block
ends, the initial state of the block size counter and the address register that is specified as the block
area is restored. The other address register is then incremented, decremented, or left fixed
according to the register information. From 1 to 65,536 transfers can be specified. Once the
specified number of transfers has been completed, a CPU interrupt is requested.
Table 7.7
Register Functions in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Block size counter
DTC transfer count register B
CRB
Transfer counter
1st block
SAR
or
DAR
•
•
•
Block area
Transfer
N th block
Figure 7.7 Memory Mapping in Block Transfer Mode
Rev. 3.00, 03/04, page 168 of 830
DAR
or
SAR
7.6.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the
register information start address stored at the DTC vector address, and then reads the first register
information at that start address. After the data transfer, the CHNE bit will be tested. When it has
been set to 1, DTC reads the next register information located in a consecutive area and performs
the data transfer. These sequences are repeated until the CHNE bit is cleared to 0.
In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated
at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
DTC vector
address
Register information
start address
Destination
Register information
CHNE = 1
Register information
CHNE = 0
Source
Destination
Figure 7.8 Chain Transfer Operation
Rev. 3.00, 03/04, page 169 of 830
7.6.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and priority level control by the interrupt controller.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.6.6
Operation Timing
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write
Transfer information
read
Transfer information
write
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Rev. 3.00, 03/04, page 170 of 830
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write Read Write
Transfer information
read
Transfer information
write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC request
Data transfer
Data transfer
Vector read
Address
Read
Read Write
Transfer information
read
Transfer
information
write
Transfer
information
read
Write
Transfer information
write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
7.6.7
Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number
of states required for each execution status.
Table 7.8
DTC Execution Status
Mode
Register
Information
Vector Read Read/Write
I
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal
1
1
1
3
6
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Rev. 3.00, 03/04, page 171 of 830
Table 7.9
Number of States Required for Each Execution Status
On-Chip RAM
On-Chip RAM (On-chip RAM area
On-
On-Chip
(H'FFEC00 to
other than H'FFEC00 to Chip
Object to be Accessed
H'FFEFFF)
H'FFEFFF)
ROM
Registers
External Devices
Bus width
32
16
16
8
16
8
8
16
16
Access states
1
1
1
2
2
2
3
2
3
—
1
—
—
4
6 + 2m
2
3+m
—
—
—
—
—
—
—
—
Byte data read SK 1
1
1
2
2
2
3+m
2
3+m
Word data read
1
1
1
4
2
4
6 + 2m
2
3+m
Byte data write SL 1
1
1
2
2
2
3+m
2
3+m
Word data write
1
1
1
4
2
4
6 + 2m
2
3+m
Internal operation 1
1
1
1
1
1
1
1
1
Execution Vector read
status
Register
SI —
1
I/O
information
read/write
SJ
SK
SL
SM
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Rev. 3.00, 03/04, page 172 of 830
7.7
Procedures for Using DTC
7.7.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
[5] After one data transfer has been completed, or after the specified number of data transfers have
been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to
continue transferring data, set the DTCE bit to 1.
7.7.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0.
[4] Write 1 to the SWDTE bit and the vector number to DTVECR.
[5] Check the vector number written to DTVECR.
[6] After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not
requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the
SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have
been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
Rev. 3.00, 03/04, page 173 of 830
7.8
Examples of Use of the DTC
7.8.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1
= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI, RDR address in SAR, the start address of the RAM area where the data will be received
in DAR, and 128 (H′0080) in CRA. CRB can be set to any value.
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
[5] Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
[6] When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at
1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine will perform wrap-up processing.
7.8.2
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the transfer destination address is
H'2000. The vector number is H′60, so the vector address is H'04C0.
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000)
in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
Rev. 3.00, 03/04, page 174 of 830
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform wrap-up processing.
Rev. 3.00, 03/04, page 175 of 830
7.9
Usage Notes
7.9.1
Module Stop Mode Setting
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the
initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop
mode is set. Note that when the DTC is being activated, module stop mode can not be specified.
For details, refer to section 23, Power-Down Modes.
7.9.2
On-Chip RAM
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.
7.9.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and
writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
7.9.4
Setting Required on Entering Subactive Mode or Watch Mode
Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm
that is set to 1 before making a transition to subactive mode or watch mode.
7.9.5
DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter
Interrupt sources of the SCI, IIC, or A/D converter which activate the DTC are cleared when DTC
reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit in
MRB.
Rev. 3.00, 03/04, page 176 of 830
Section 8 I/O Ports
Table 8.1 is a summary of the port functions. The pins of each port also function as input/output
pins of peripheral modules and interrupt input pins. Each input/output port includes a data
direction register (DDR) that controls input/output and a data register (DR) that stores output data.
DDR and DR are not provided for an input-only port.
Ports 1 to 3, 6, A, and D0 to D5 have built-in input pull-up MOSs. For port A and D0 to D5, the
on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an
input pull-up MOS control register (PCR), in addition to DDR and DR, to control the on/off status
of the input pull-up MOSs.
Ports 1 to 6, and 8 to F can drive a single TTL load and 30 pF capacitive load. All the I/O ports
can drive a Darlington transistor in output mode. Ports 8, C0 to C5 and D6 to D7 are NMOS pushpull output.
Table 8.1
Port Functions
Port
Description
Port 1
General I/O port also
functioning as PWM
output, address
output, and
address/data
multiplex input/output
Port 2
General I/O port also
functioning as PWM
output, address
output, and
address/data
multiplex input/output
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
P17/A7/AD7
P17/PW7
P16/A6/AD6
P16/PW6
P15/A5/AD5
P15/PW5
P14/A4/AD4
P14/PW4
P13/A3/AD3
P13/PW3
P12/A2/AD2
P12/PW2
P11/A1/AD1
P11/PW1
P10/A0/AD0
P10/PW0
P27/A15/AD15
P27/PW15
P26/A14/AD14
P26/PW14
P25/A13/AD13
P25/PW13
P24/A12/AD12
P24/PW12
P23/A11/AD11
P23/PW11
P22/A10/AD10
P22/PW10
P21/A9/AD9
P21/PW9
P20/A8/AD8
P20/PW8
I/O Status
Built-in input
pull-up MOSs
LED drive
capability
(sink current 5
mA)
Built-in input
pull-up MOSs
LED drive
capability
(sink current 5
mA)
Rev. 3.00, 03/04, page 177 of 830
Table 8.1
Port Functions (cont)
Port
Description
Port 3
General I/O port
also functioning
as bidirectional
data bus, and
wake-up event
input
Port 4
General I/O port
also functioning
as interrupt
input, and
TMR_0,
TMR_1,
TMR_X,
TMR_Y input
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
P37/D15/WVEI5
P37/WUE15
P36/D14/WUEI4
P36/WUE14
P35/D13/WUEI3
P35/WUE13
P34/D12/WUEI2
P34/WUE12
P33/D11/WUEI1
P33/WUE11
P32/D10/WUEI0
P32/WUE10
P31/D9/WUEI9
P31/WUE9
P30/D8/WUEI8
P30/WUE8
P47/IRQ7/TMOY
P46/IRQ6/TMOX
P45/IRQ5/TMIY
P44/IRQ4/TMIX
P43/IRQ3/TMO1
P42/IRQ2/TMO0
P41/IRQ1/TMI1
P40/IRQ0/TMI0
Port 5
General I/O port
also functioning
as interrupt
input, PWMX
output, and
SCI_0, SCI_1,
SCI_2 I/O pins
P57/IRQ15/PWX1
P56/IRQ14/PWX0
P55/IRQ13/RxD2
P54/IRQ12/TxD2
P53/IRQ11/RxD1/IrRxD
P52/IRQ10/TxD1/IrTxD
P51/IRQ9/RxD0
P50/IRQ8/TxD0
Rev. 3.00, 03/04, page 178 of 830
I/O Status
Built-in input
pull-up MOSs
LED drive
capability
(sink current 5
mA)
Table 8.1
Port
Port 6
Port Functions (cont)
Description
General I/O port
also functioning
as bidirectional
data bus, FRT
input/output,
keyboard input
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
1
2
P67//KIN7
2
P66/FTOB/KIN6
2
P65/FTID/KIN5
P64/FTIC/KIN4*
2
D4*
P64/FTIC/KIN4
P63/FTIB/KIN3*1
D3*2
P63/FTIB/KIN3
1
2
P62/FTIA/KIN2
2
P61/FTOA/KIN1
2
P60/FTCI/KIN0
P67/KIN7*
D7*
1
P66/FTOB/KIN6*
1
P65/FTID/KIN5*
D5*
1
P62/FTIA/KIN2*
D2*
1
P61/FTOA/KIN1*
P60/FTCI/KIN0*
Port 7
General I/O port
also functioning
as A/D
converter
analog input,
D/A converter
analog output,
and interrupt
input
D6*
1
D1*
D0*
I/O Status
Built-in
input pullup MOSs
P77/ExIRQ7/AN7/DA1
P76/ExIRQ6/AN6/DA0
P75/ExIRQ5/AN5
P74/ExIRQ4/AN4
P73/ExIRQ3/AN3
P72/ExIRQ2/AN2
P71/AN1
P70/AN0
Rev. 3.00, 03/04, page 179 of 830
Table 8.1
Port Functions (cont)
Port
Description
Port 8
General I/O port also
functioning as A/D
converter external
trigger input pin,
SCI_0, SCI_1, and
SCI_2 clock
inputs/outputs,
TMR_0, TMR_1,
TMR_X, TMR_Y
inputs, and IIC_0
and IIC_1
inputs/outputs
Port 9
General I/O port also
functioning as bus
control input/output,
system clock output,
and external subclock input
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
I/O Status
P87/ExIRQ15/ADTRG/ExTMIY
NMOS pushpull outputs.
P86/ExIRQ14/SCK2/ExTMIX
P85/ExIRQ13/SCK1/ExTMI1
P84/ExIRQ12/SCK0/ExTMI0
P83/ExIRQ11/SDA1
P82/ExIRQ10/SCL1
P81/ExIRQ9/SDA0
P80/ExIRQ8/SCL0
P97/WAIT/CS256
P97
P96/φ/EXCL
AS/IOS3
P95
HWR
P94
RD
P93
P92/CPCS1
P92
P91/AH
P91
P90/LWR
P90
Rev. 3.00, 03/04, page 180 of 830
Table 8.1
Port Functions (cont)
Port
Description
Port A
General I/O port
also functioning
as DTC event
counter input,
address output,
keyboard input,
and SCI_0 and
SCI_2 external
control pins
Port B
Port C
Port D
Extended Mode
(EXPE = 1)
Single-Chip Mode
(EXPE = 0)
PA7/KIN15/
A23/EVENT7
PA7/KIN15/
EVENT7
PA6/KIN14/
A22/EVENT6
PA6/KIN14/
EVENT6
PA5/KIN13/
A21/EVENT5
PA5/KIN13/
EVENT5
PA4/KIN12/
A20/EVENT4
PA4/KIN12/
EVENT4
PA3/KIN11/
A19/EVENT3
PA3/KIN11/
EVENT3
PA2/KIN10/
A18/EVENT2
PA2/KIN10/
EVENT2
PA1/KIN9/
A17/SSE2I/
EVENT1
PA0/KIN8/
A16/SSE0I/
EVENT0
General I/O port PB7/EVENT15
also functioning PB6/EVENT14
as DTC event
PB5/EVENT13
counter input
PB4/EVENT12
PB3/EVENT11
PB2/EVENT10
PB1/EVENT9
PB0/EVENT8
General I/O port PC7/PWX3
also functioning PC6/PWX2
as PWMX output PC5/SDA4
and IIC_2, IIC_3, PC4/SCL4
and IIC_4 I/O
PC3/SDA3
pins
PC2/SCL3
PC1/SDA2
PC0/SCL2
General I/O port PD7/SDA5
also functioning PD6/SCL5
as LPC I/O, and PD5/LPCPD
IIC_5 I/O pins
PD4/CLKRUN
PD3/GA20
PD2/PME
PD1/LSMI
PD0/LSCI
I/O Status
Built-in input
pull-up
MOSs
PA1/KIN9/
SSE2I/
EVENT1
PA0/KIN8/
SSE0I/
EVENT0
NMOS pushpull outputs
(PC0 to
PC5)
Built-in input
pull-up
MOSs
(PD0 to
PD5)
NMOS pushpull outputs
(PD6 to
PD7)
Rev. 3.00, 03/04, page 181 of 830
Table 8.1
Port Functions (cont)
Extended Mode
(EXPE = 1)
Port
Description
Port E
General I/O port also PE7/SERIRQ
functioning as LPC
PE6/LCLK
I/O
PE5/LRESET
PE4/LFRAME
PE3/LAD3
PE2/LAD2
PE1/LAD1
PE0/LAD0
General I/O port also PF2/ExPW2
functioning as PWM PF1/ExPW1
output pin
PF0/ExPW0
Port F
Notes: 1. 8-bit data bus is selected.
2. 16-bit data bus is selected.
Rev. 3.00, 03/04, page 182 of 830
Single-Chip Mode
(EXPE = 0)
I/O Status
8.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus, PWM output pins, and
address/data multiplex bus. Port 1 functions change according to the operating mode. Port 1 has
the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 pull-up MOS control register (P1PCR)
8.1.1
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit
Bit Name
Initial Value
R/W Description
7
P17DDR
0
W
In normal extended mode (ADMXE = 0):
6
P16DDR
0
W
5
P15DDR
0
W
The corresponding port 1 pins are address output
when P1DDR bits are set to 1, and input ports when
cleared to 0.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
In address/data multiplex extended mode (ADMXE =
1):
When the bus width is 16 bits, lower 8 bits of
address/data multiplex bus. When the bus width is 8
bits, this register is used in the same way as in single
chip mode.
In single-chip mode:
The corresponding port 1 pins are output ports or
PWM outputs when the P1DDR bits are set to 1, and
input ports when cleared to 0.
Rev. 3.00, 03/04, page 183 of 830
8.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
8.1.3
P1DR stores output data for the port 1 pins that are
used as the general output port.
If a port 1 read is performed while the P1DDR bits are
set to 1, the P1DR values are read. If a port 1 read is
performed while the P1DDR bits are cleared to 0, the
pin states are read.
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the port 1 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P17PCR
0
R/W
6
P16PCR
0
R/W
When the pins are in input state, the corresponding
input pull-up MOS is turned on when a P1PCR bit is
set to 1.
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
0
P10PCR
0
R/W
Rev. 3.00, 03/04, page 184 of 830
In address-data multiplex extended bus mode is
used, the initial value should not be changed.
8.1.4
Pin Functions
The relationship between register setting values and pin functions are as follows in each operating
mode.
Extended Mode (EXPE = 1):
The function of port 1 pins is switched as shown below according to the P1nDDR bit.
P1nDDR
0
1
ADMXE
0
1
ABW,
ABW256,
ABWCP

Either bit is 0
(8/16 bit bus)
P1n input pin AD7 to AD0
input/output
pin
Pin function
0
1
All 1
(8 bit bus)

Either bit is 0
All 1
(8 bit bus)
P1n input
pin
A7 to A0
output pin
Setting
prohibited
P1n output
pin
[Legend]
n = 7 to 0
Single-Chip Mode (EXPE = 0):
The function of port 1 pins is switched as shown below according to the combination of the OEn
bit and P1nDDR bit in PWOERA of PWM and the PWMS bit in PTCNT0.
P1nDDR
0
1
1
1
PWMS

0
1
0
OEn

0

1
Pin function
P1n input pin
P1n output pin
PWn output pin
[Legend]
n = 7 to 0
Rev. 3.00, 03/04, page 185 of 830
8.1.5
Port 1 Input Pull-Up MOS
Port 1 has a built-in input pull-up MOS that can be controlled by software. This input pull-up
MOS can be used regardless of the operating mode. Table 8.2 summarizes the input pull-up MOS
states.
Table 8.2
Port 1 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
Rev. 3.00, 03/04, page 186 of 830
8.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins also function as an address bus, PWM output pins, and
address-data multiplex bus. Port 2 functions change according to the operating mode. Port 2 has
the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 pull-up MOS control register (P2PCR)
8.2.1
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
In normal extended mode (ADMXE = 0):
6
P26DDR
0
W
5
P25DDR
0
W
The corresponding port 2 pins are address output
ports when the P2DDR bits are set to 1, and input
ports when cleared to 0.
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
Address/data multiplex extended mode (ADMXE =
1):
0
P20DDR
0
W
The upper 8-bit of address/data multiplex bus.
Pins function as the address output port depending
on the setting of bits IOSE and CS256E in SYSCR.
In single-chip mode:
The corresponding port 2 pins are output ports or
PWM outputs when the P2DDR bits are set to 1,
and input ports when cleared to 0.
Rev. 3.00, 03/04, page 187 of 830
8.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
P2DR stores output data for the port 2 pins that are
used as the general output port.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
8.2.3
If a port 2 read is performed while the P2DDR bits
are set to 1, the P2DR values are read. If a port 2
read is performed while the P2DDR bits are
cleared to 0, the pin states are read.
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P27PCR
0
R/W
6
P26PCR
0
R/W
When the pins are in input state, the corresponding
input pull-up MOS is turned on when a P2PCR bit
is set to 1.
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
0
P20PCR
0
R/W
Rev. 3.00, 03/04, page 188 of 830
8.2.4
Pin Functions
The relationship between register setting values and pin functions are as follows in each operating
mode.
Extended Mode (EXPE = 1):
The function of port 2 pins is switched as shown below according to the combination of the
CS256E and IOSE bits in SYSCR, the ADFULLE and CPCSE bits in BCR2 of BSC, and the
P2nDDR bit.
Addresses 13 and 11 in the following table are expressed by the following logical expressions:
Address 13 = 1:ADFULLE • CS256E • (CPCSE  IOSE)
Address 11 = 1:ADFULLE • CS256E • CPCSE • IOSE
P2nDDR
0
1
ADMXE
0
1
0
1
Address 13


0
1

Pin function
P27 to P25
input pins
AD15 to
AD13
input/output
pins
A15 to A13
output pins
P27 to P25
output pins
AD15 to AD13
input/output pins
[Legend]
n = 7 to 5
P24DDR
0
1
ADMXE
0
1
Address 11


0
1

Pin function
P24 input pin
AD12
input/output
pin
A12 output
pin
P24 output
pin
AD12 input/output pin
P23DDR
0
1
0
1
ADMXE
0
1
0
1
Address 11


0
1

Pin function
P23 input pin
AD11
input/output
pin
A11 output
pin
P23 output
pin
AD11 input/output pin
Rev. 3.00, 03/04, page 189 of 830
P2nDDR
0
ADMXE
Pin function
1
0
1
0
1
P2n input pins
AD10 to AD8
input/output pins
A10 to A8 output
pins
AD10 to AD8
input/output pins
[Legend]
n = 7 to 0
Single-Chip Mode (EXPE = 0):
The function of port 2 pins is switched as shown below according to the combination of the OEm
bit in PWOERB of PWR and the P2nDDR bit.
P2nDDR
0
OEm

0
1
P27 to P20 input pins
P27 to P20 output pins
PW15 to PW8 output pins
Pin function
1
[Legend]
n = 7 to 0
m = 15 to 8
8.2.5
Port 2 Input Pull-Up MOS
Port 2 has a built-in input pull-up MOS that can be controlled by software. This input pull-up
MOS can be used regardless of the operating mode. Table 8.3 summarizes the input pull-up MOS
states.
Table 8.3
Port 2 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
Rev. 3.00, 03/04, page 190 of 830
8.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, wake-up event
input pins. Port 3 functions change according to the operating mode. Port 3 has the following
registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 pull-up MOS control register (P3PCR)
8.3.1
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
Bit
Bit Name
Initial Value
R/W Description
7
P37DDR
0
W
In normal extended mode:
6
P36DDR
0
W
Bidirectional data bus
5
P35DDR
0
W
In other mode:
4
P34DDR
0
W
3
P33DDR
0
W
The corresponding port 3 pins are output ports when
the P3DDR bits are set to 1, and input ports when
cleared to 0.
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
8.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P37DR
0
R/W In normal extended mode (ADMXE = 0):
6
P36DR
0
5
P35DR
0
4
P34DR
0
3
P33DR
0
2
P32DR
0
1
P31DR
0
0
P30DR
0
R/W If a port 3 read is performed while the P3DDR bits are
set to 1, the P3DR values are read. When the P3DDR
R/W
bits are cleared to 0, 1 is read.
R/W
In other mode:
R/W
If a port 3 read is performed while the P3DDR bits are
R/W set to 1, the P3DR values are read. If a port 3 read is
R/W performed while the P3DDR bits are cleared to 0, the
pin states are read.
R/W
Rev. 3.00, 03/04, page 191 of 830
8.3.3
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W Description
7
P37PCR
0
R/W In normal extended mode:
6
P36PCR
0
R/W Operation is not affected.
5
P35PCR
0
R/W In other mode:
4
P34PCR
0
3
P33PCR
0
2
P32PCR
0
R/W When the pins are in input state, the corresponding
input pull-up MOS is turned on when a P3PCR bit is set
R/W to 1.
R/W
1
P31PCR
0
R/W
0
P30PCR
0
R/W
8.3.4
Pin Functions
Normal Extended Mode:
Port 3 pins automatically function as the bidirectional data bus.
Address/Data Multiplex Mode:
Same operation as the single-chip mode.
Single-Chip Mode:
• P37/WUE15
The pin function is switched as shown below according to the P37DDR bit.
When the WUEM15 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE15 input pin. To use this pin as the WUE15 input pin, clear the P37DDR bit
to 0.
P37DDR
WUEM15
Pin Function
0
1
0
1

WUEI15 input pin
P37 input pin
P37 output pin
Rev. 3.00, 03/04, page 192 of 830
• P36/WUE14
The pin function is switched as shown below according to the P36DDR bit.
When the WUEM14 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE14 input pin. To use this pin as the WUE14 input pin, clear the P36DDR bit
to 0.
P36DDR
WUEM14
Pin function
0
1
0
1

WUE14 input pin
P36 input pin
P36 output pin
• P35/WUE13
The pin function is switched as shown below according to the P35DDR bit.
When the WUEM13 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE13 input pin. To use this pin as the WUE13 input pin, clear the P35DDR bit
to 0.
P35DDR
WUEM13
Pin function
0
1
0
1

WUE13 input pin
P35 input pin
P35 output pin
• P34/WUE12
The pin function is switched as shown below according to the P34DDR bits.
When the WUEM12 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE12 input pin. To use this pin as the WUE12 input pin, clear the P34DDR bit
to 0.
P34DDR
WUEM12
Pin function
0
1
0
1

WUE12 input pin
P34 input pin
P34 output pin
• P33/WUE11
The pin function is switched as shown below according to the P33DDR bits.
When the WUEM11 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE11 input pin. To use this pin as the WUE11 input pin, clear the P33DDR bit
to 0.
P33DDR
WUEM11
Pin function
0
1
0
1

WUE11 input pin
P33 input pin
P33 output pin
Rev. 3.00, 03/04, page 193 of 830
• P32/WUE10
The pin function is switched as shown below according to the P32DDR bits.
When the WUEM10 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE10 input pin. To use this pin as the WUE10 input pin, clear the P32DDR bit
to 0.
P32DDR
WUEM10
Pin function
0
1
0
1

WUE10 input pin
P32 input pin
P32 output pin
• P31/WUE9
The pin function is switched as shown below according to the P31DDR bits.
When the WUEM9 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE9 input pin. To use this pin as the WUE9 input pin, clear the P31DDR bit to
0.
P31DDR
WUEM9
Pin function
0
1
0
1

WUE9 input pin
P31 input pin
P31 output pin
• P30/WUE8
The pin function is switched as shown below according to the P30DDR bits.
When the WUEM8 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be
used as the WUE8 input pin. To use this pin as the WUE8 input pin, clear the P30DDR bit to
0.
P30DDR
WUEM8
Pin function
0
1
0
1

WUE8 input pin
P30 input pin
P30 output pin
Rev. 3.00, 03/04, page 194 of 830
8.3.5
Port 3 Input Pull-Up MOS
Port 3 has a built-in input pull-up MOS that can be controlled by software. This input pull-up
MOS can be used in single-chip mode. Table 8.4 summarizes the input pull-up MOS states.
Table 8.4
Port 3 Input Pull-Up MOS States
Mode
Reset
Hardware Standby Software
Mode
Standby Mode
In Other Operations
Normal extended
mode (EXPE = 1,
ADMXE = 0)
Off
Off
Off
Off
Single-chip mode
(EXPE = 0)
Off
Off
On/Off
On/Off
Address-data
multiplex extended
mode (EXPE = 1,
ADMXE = 1)
[Legend]
Off
: Always off.
On/Off : On when input state and P3PCR = 1; otherwise off.
Rev. 3.00, 03/04, page 195 of 830
8.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt input, and TMR_0,
TMR_1, TMR_X, and TMR_Y input/output pins. Port 4 has the following registers.
• Port 4 data direction register (P4DDR)
• Port 4 data register (P4DR)
8.4.1
Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the pins of port 4.
Bit
Bit Name
Initial Value
R/W Description
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
3
P43DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
0
P40DDR
0
W
8.4.2
If port 4 pins are specified for use as the general I/O
port, the corresponding port 4 pins are output ports
when the P4DDR bits are set to 1, and input ports when
cleared to 0.
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P47DR
0
6
P46DR
0
R/W P4DR stores output data for the port 4 pins that are
R/W used as the general output port.
5
P45DR
0
R/W
4
P44DR
0
3
P43DR
0
If a port 4 read is performed while the P4DDR bits are
set to 1, the P4DR values are read. If a port 4 read is
R/W performed while the P4DDR bits are cleared to 0, the
R/W pin states are read.
2
P42DR
0
R/W
1
P41DR
0
R/W
0
P40DR
0
R/W
Rev. 3.00, 03/04, page 196 of 830
8.4.3
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P47/IRQ7/TMOY
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR of TMR_Y and the P47DDR bit.
When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller
is set to 1, this pin can be used as the IRQ7 input pin. To use this pin as the IRQ7 input pin,
clear the P47DDR bit to 0.
OS3 to OS0
P47DDR
Pin function
All 0
One bit is set as 1
0
1

P47 input pin
P47 output pin
TMOY output pin
IRQ7 input pin
• P46/IRQ6/TMOX
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR of TMR_X and the P46DDR bit.
When the ISS6 bit in ISSR is cleared to 0 and the IRQ6E bit in IER of the interrupt controller
is set to 1, this pin can be used as the IRQ6 input pin. To use this pin as the IRQ6 input pin,
clear the P46DDR bit to 0.
OS3 to OS0
P46DDR
Pin function
All 0
One bit is set as 1
0
1

P46 input pin
P46 output pin
TMOX output pin
IRQ6 input pin
Rev. 3.00, 03/04, page 197 of 830
• P45/IRQ5/TMIY
The pin function is switched as shown below according to the P45DDR bit.
When the TMIYS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2
to CKS0 bits in TCR of TMR_Y, this bit is used as the TMCIY input pin. When the CCLR1
and CCLR0 bits in TCR of TMR_Y are set to 1, this pin is used as the TMRIY input pin.
When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller
is set to 1, this pin can be used as the IRQ5 input pin. To use this pin as the IRQ5 input pin,
clear the P45DDR bit to 0.
P45DDR
Pin function
0
1
P45 input pin
P45 output pin
TMIY (TMCIY/TMRIY) input pin
IRQ5 input pin
• P44/IRQ4/TMIX
The pin function is switched as shown below according to the P44DDR bits.
When the TMIXS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2
to CKS0 bits in TCR of TMR_X, this bit is used as the TMCIX input pin. When the CCLR1
and CCLR0 bits in TCR of TMR_X are set to 1, this pin is used as the TMRIX input pin.
When the ISS4 bit in ISSR is cleared to 0 and the IRQ4E bit in IER of the interrupt controller
is set to 1, this pin can be used as the IRQ4 input pin. To use this pin as the IRQ4 input pin,
clear the P44DDR bit to 0.
P44DDR
Pin function
0
1
P44 input pin
P44 output pin
TMIY (TMCIY/TMRIY) input pin
IRQ4 input pin
• P43/IRQ3/TMO1
The pin function is switched as shown below according to the OS3 to OS0 bits in TCSR of
TMR_1 and the P43DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in
IER of the interrupt controller is set to 1, this pin can be used as the IRQ3 input pin. To use
this pin as the IRQ3 input pin, clear the P43DDR bit to 0.
OS3 to OS0
P43DDR
Pin function
All 0
One bit is set as 1
0
1

P43 input pin
P43 output pin
TMO1 output pin
IRQ3 input pin
Rev. 3.00, 03/04, page 198 of 830
• P42/IRQ2/TMO0
The pin function is switched as shown below according to the OS3 to OS0 bits in TCSR of
TMR_0 and the P42DDR bit.
When the ISS2 bit in ISSR is cleared to 0 and the IRQ2E bit in IER of the interrupt controller
is set to 1, this pin can be used as the IRQ2 input pin. To use this pin as the IRQ2 input pin,
clear the P42DDR bit to 0.
OS3 to OS0
P42DDR
Pin function
All 0
One bit is set as 1
0
1

P42 input pin
P42 output pin
TMO0 output pin
IRQ2 input pin
• P41/IRQ1/TMI1
The pin function is switched as shown below according to the P41DDR bits.
When the TMI1S bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2
to CKS0 bits in TCR of TMR_1, this bit is used as the TMCI1 input pin. When the CCLR1
and CCLR0 bits in TCR of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. When
the ISS1 bit in ISSR is cleared to 0 and the IRQ1E bit in IER of the interrupt controller is set to
1, this pin can be used as the IRQ1 input pin. To use this pin as the IRQ1 input pin, clear the
P41DDR bit to 0.
P41DDR
Pin function
0
1
P41 input pin
P41 output pin
TMI1(TMCI1/TMRI1) input pin
IRQ1 input pins
• P40/IRQ0/TMI0
The pin function is switched as shown below according to the P40DDR bits.
When the TMI0S bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2
to CKS0 bits in TCR of TMR_0, this bit is used as the TMCI0 input pin. When the CCLR1
and CCLR0 bits in TCR of TMR_0 are set to 1, this pin is used as the TMRI0 input pin. When
the ISS0 bit in ISSR is cleared to 0 and the IRQ0E bit in IER of the interrupt controller is set to
1, this pin can be used as the IRQ0 input pin. To use this pin as the IRQ0 input pin, clear the
P40DDR bit to 0.
P40DDR
Pin function
0
1
P40 input pin
P40 output pin
TMI0(TMCI0/TMRI0) input pin
IRQ0 input pin
Rev. 3.00, 03/04, page 199 of 830
8.5
Port 5
Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin,
SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
8.5.1
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DDR
0
W
6
P56DDR
0
W
5
P55DDR
0
W
If port 5 pins are specified for use as the general I/O
port, the corresponding port 5 pins are output ports
when the P5DDR bits are set to 1, and input ports
when cleared to 0.
4
P54DDR
0
W
3
P53DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
8.5.2
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DR
0
R/W
6
P56DR
0
R/W
P5DR stores output data for the port 5 pins that are
used as the general output port.
5
P55DR
0
R/W
4
P54DR
0
R/W
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
Rev. 3.00, 03/04, page 200 of 830
If a port 5 read is performed while the P5DDR bits are
set to 1, the P5DR values are read. If a port 5 read is
performed while the P5DDR bits are cleared to 0, the
pin states are read.
8.5.3
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P57/IRQ15/PWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR of PWMX and the P57DDR bit.
When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ15 input pin. To use this pin as the IRQ15
input pin, clear the P57DDR bit to 0.
OEB
P57DDR
Pin function
0
1
0
1

P57 input pin
P57 output pin
PWX1 output pin
IRQ15 input pin
• P56/IRQ14/PWX0
The pin function is switched as shown below according to the combination of the OEA bit in
DACR of PWMX and the P56DDR bit.
When the ISS14 bit in ISSR16 is cleared to 0 and the IRQ14E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ14 input pin. To use this pin as the IRQ14
input pin, clear the P56DDR bit to 0.
OEA
P56DDR
Pin function
0
1
0
1

P56 input pin
P56 output pin
PWX0 output pin
IRQ14 input pin
• P55/IRQ13/RxD2
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_2 and the P55DDR bit.
When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ13 input pin. To use this pin as the IRQ13
input pin, clear the P55DDR bit to 0.
RE
P55DDR
Pin function
0
1
0
1

P55 input pin
P55 output pin
RxD2 input pin
IRQ13 input pin
Rev. 3.00, 03/04, page 201 of 830
• P54/IRQ12/TxD2
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_2 and the P54DDR bit.
When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of the interrupt
controller is set to 1 this pin can be used as the IRQ12 input pin. To use this pin as the IRQ12
input pin, clear the P54DDR bit to 0.
TE
P54DDR
Pin function
0
1
0
1

P54 input pin
P54 output pin
TxD2 output pin
IRQ12 input pin
• P53/IRQ11/RxD1/IrRxD
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_1 and the P53DDR bit.
When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ11 input pin. To use this pin as the IRQ11
input pin, clear the P53DDR bit to 0.
RE
P53DDR
Pin function
0
1
0
1

P53 input pin
P53 output pin
RxD1/IrRxD input pin
IRQ11 input pin
• P52/IRQ10/TxD1/IrTxD
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_1 and the P52DDR bit.
When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ10 input pin. To use this pin as the IRQ10
input pin, clear the P52DDR bit to 0.
TE
P52DDR
Pin function
0
1
0
1

P52 input pin
P52 output pin
TxD1/IrTxD output pin
IRQ10 input pin
Rev. 3.00, 03/04, page 202 of 830
• P51/IRQ9/RxD0
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_0 and the P51DDR bit.
When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ9 input pin. To use this pin as the IRQ9
input pin, clear the P51DDR bit to 0.
RE
P51DDR
Pin function
0
1
0
1

P51 input pin
P51 output pin
RxD0 input pin
IRQ9 input pin
• P50/IRQ8/TxD0
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_0 and the P50DDR bit.
When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ8 input pin. To use this pin as the IRQ8
input pin, clear the P50DDR bit to 0.
TE
P50DDR
Pin function
0
1
0
1

P50 input pin
P50 output pin
TxD0 output pin
IRQ8 input pin
Rev. 3.00, 03/04, page 203 of 830
8.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT input/output pin, keyboard input
pin, and noise cancel input pin. Port 6 functions change according to the operating mode. The port
can be used as the extended data bus (lower eight bits). Port 6 has the following registers.
•
•
•
•
•
•
•
Port 6 data direction register (P6DDR)
Port 6 data register (P6DR)
Port 6 pull-up MOS control register (KMPCR6)
System control register 2 (SYSCR2)
Noise canceler enable register (P6NCE)
Noise canceler decision control register (P6NCMC)
Noise cancel cycle setting register (P6NCCS)
8.6.1
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DDR
0
W
Normal extended mode (16-bit data bus):
6
P66DDR
0
W
5
P65DDR
0
W
The port functions as the data bus regardless of the
values in these bits.
4
P64DDR
0
W
3
P63DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
Rev. 3.00, 03/04, page 204 of 830
Other mode:
If port 6 pins are specified for use as the general I/O
port, the corresponding port 6 pins are output ports
when the P6DDR bits are set to 1, and input ports
when cleared to 0.
8.6.2
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DR
0
R/W
Normal extended mode (16-bit data bus):
6
P66DR
0
R/W
5
P65DR
0
R/W
4
P64DR
0
R/W
If a port 6 read is performed while the P6DDR bits are
set to 1, the P6DR values are read. If a port 6 read is
performed while the P6DDR bits are cleared to 0, 1 is
read.
3
P63DR
0
R/W
Other mode:
2
P62DR
0
R/W
1
P61DR
0
R/W
P6DR stores output data for the port 6 pins that are
used as the general output port.
0
P60DR
0
R/W
8.6.3
If a port 6 read is performed while the P6DDR bits are
set to 1, the P6DR values are read. If a port 6 read is
performed while the P6DDR bits are cleared to 0, the
pin states are read.
Port 6 Pull-Up MOS Control Register (KMPCR6)
KMPCR6 controls the port 6 built-in input pull-up MOSs. This register is accessible when SYSCR
KINWUE is 1. See section 3.2.2, System Control Register (SYSCR).
Bit
Bit Name
Initial Value
R/W
Description
7
KM7PCR
0
R/W
Normal extended mode (16-bit data bus):
6
KM6PCR
0
R/W
Operation is not affected.
5
KM5PCR
0
R/W
Other mode:
4
KM4PCR
0
R/W
3
KM3PCR
0
R/W
When the pins are in input state, the corresponding
input pull-up MOS is turned on when a KMPCR6 bit is
set to 1.
2
KM2PCR
0
R/W
1
KM1PCR
0
R/W
0
KM0PCR
0
R/W
Rev. 3.00, 03/04, page 205 of 830
8.6.4
System Control Register 2 (SYSCR2)
SYSCR2 controls the current specifications for the port 6 input pull-up MOSs and address data
multiplex operation.
Bit
Bit Name
Initial Value
R/W
Description
7, 6

All 0
R/W
Reserved
The initial value should not be changed.
5
P6PUE
0
R/W
Port 6 Input Pull-Up Extra
Selects the current specification for the input pull-up
MOS connected by means of KMPCR settings.
0: Standard current specification is selected
1: Current-limit specification is selected
4

0
R/W
Reserved
The initial value should not be changed.
3
ADMXE
0
R/W
Address data multiplex bus interface enable
0: Normal extended bus interface
1: Address data multiplex extended bus interface
2 to 0 
All 0
R/W
Reserved
The initial value should not be changed.
8.6.5
Noise Canceler Enable Register (P6NCE)
P6NCE enables or disables the noise canceler circuit at port 6.
Bit
Bit Name
Initial Value
R/W
Description
7
P67NCE
0
R/W
In 16 bit bus mode in extended mode:
6
P66NCE
0
R/W
Port 6 operates as the data pin (D7 to D0).
5
P65NCE
0
R/W
In other mode:
4
P64NCE
0
R/W
3
P63NCE
0
R/W
Noise canceler circuit is enabled and the pin state is
fetched in the P6DR in the sampling cycle set by the
P6NCCS.
2
P62NCE
0
R/W
1
P61NCE
0
R/W
0
P60NCE
0
R/W
Rev. 3.00, 03/04, page 206 of 830
The operating state changes according to the other
control bits. Check the pin functions.
8.6.6
Noise Canceler Mode Control Register (P6NCMC)
P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units.
Bit
Bit Name
Initial Value
R/W
Description
7
P67NCMC
1
R/W
In 16 bit bus mode in extended mode:
6
P66NCMC
1
R/W
Port 6 operates as the data pin (D7 to D0).
5
P65NCMC
1
R/W
In other mode:
4
P64NCMC
1
R/W
3
P63NCMC
1
R/W
1 expected: 1 is stored in the port data register while 1
is input stably
2
P62NCMC
1
R/W
1
P61NCMC
1
R/W
0
P60NCMC
1
R/W
8.6.7
0 expected: 0 is stored in the port data register while 0
is input stably
Noise Canceler Cycle Setting Register (P6NCCS)
P6NCCS controls the sampling cycles of the noise canceler.
Bit
Bit Name
Initial Value
R/W
Description
7 to 3 
All undefined
R/W
Reserved. The read data is undefined. The initial
value should not be changed.
2
NCCK2
0
R/W
1
NCCK1
0
R/W
These bits set the sampling cycles of the noise
canceler.
0
NCCK0
0
R/W
000:
0.06 µs
φ/2
001:
0.97 µs
φ/32
010:
15.5 µs
φ/512
011:
248.2 µs
φ/8192
100:
993.0 µs
φ/32768
101:
2.0 ms
φ/65536
110:
4.0 ms
φ/131072
111:
7.9 ms
φ/262144
Rev. 3.00, 03/04, page 207 of 830
φ/2, φ/32, φ/512, φ/8192,
φ/32768,
φ/65536,
φ/131072,
φ/2621446
Sampling clock selection
t
Latch
Latch
Latch
t
Sampling clock
Figure 8.1 Noise Canceler Circuit
P6n Input
1 expected
P6nDR
0 expected
P6nDR
Figure 8.2 Noise Canceler Operation
Rev. 3.00, 03/04, page 208 of 830
Matching detection circuit
Pin
input
Port data
register
8.6.8
Pin Functions
Normal Extended Mode: Port 6 automatically become the bidirectional data bus in 16-bit bus
mode. The port 6 pins function the same as in shingle chip mode in 8-bit bus mode.
Address-Data Multiplex Extended Mode: The port 6 pins function the same as in shingle chip
mode.
Single Chip Mode: The relationship between the register setting values and pin functions are as
follows.
Port 6 pins also function as the FRT input/output pin, keyboard input pin, noise cancel input pin,
or I/O port.
• P67/ KIN7
The function of port 6 pins is switched as shown below according to the P67DDR bit.
When the KMIM7 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN7 input pin. To use this pin as the KIN7 input pin, clear the P67DDR bit to 0.
Mode
Port
P67DDR
0
0
1
P67NCE
0
1

P67 input pin
P67 input pin
(noise canceling)
P67 output pin
Pin function
KIN7 input pin
• P66/FTOB/KIN6
The function of port 6 pins is switched as shown below according to the combination of the
OEB bit in TOCR of FRT and the P66DDR bit.
When the KMIM6 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN6 input pin. To use this pin as the KIN6 input pin, clear the P66DDR bit to 0.
Mode
Port
FRT
OEB
0
0
0
1
P66DDR
0
0
1

P66NCE
0
1


P66 input pin
P66 input pin
(noise
canceling)
P66 output pin
FTOB output pin
Pin function
KIN6 input pin
Rev. 3.00, 03/04, page 209 of 830
• P65/FTID/KIN5
The function of port 6 pins is switched as shown below according to the P65DDR bit.
When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin.
When the KMIM5 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN5 input pin. To use this pin as the KIN5 input pin, clear the P65DDR bit to 0.
Mode
P65DDR
P65NCE
Pin function
Port
0
0
FRT
1
0
0
1

0
P65 input pin
P65 input pin
(noise
canceling)
P65 output pin
FTID input pin
KIN5 input pin
• P64/FTIC/KIN4
The function of port 6 pins is switched as shown below according to the P64DDR bit.
When the ICICE bit in TIER of FRT is set to 1, this pin can be used as the FTIC input pin.
When the KMIM4 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN4 input pin. To use this pin as the KIN4 input pin, clear the P64DDR bit to 0.
Mode
Port
FRT
P64DDR
0
0
1
0
P64NCE
0
1

0
P64 input pin
P64 input pin
(noise
canceling)
P64 output pin
FTIC input pin
Pin function
KIN4 input pin
Rev. 3.00, 03/04, page 210 of 830
• P63/FTIB/KIN3
The function of port 6 pins is switched as shown below according to the P63DDR bit.
When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin.
When the KMIM3 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN3 input pin. To use this pin as the KIN3 input pin, clear the P63DDR bit to 0.
Mode
Port
FRT
P63DDR
0
0
1
0
P63NCE
0
1

0
P63 input pin
P63 input pin
(noise
canceling)
P63 output pin
FTIB input pin
Pin function
KIN3 input pin
• P62/FTIA/KIN2
The function of port 6 pins is switched as shown below according to the P62DDR bit.
When the ICIAE bit in TIER of FRT is set to 1, this pin can be used as the FTIA input pin.
When the KMIM2 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN2 input pin. To use this pin as the KIN2 input pin, clear the P62DDR bit to 0.
Mode
Port
FRT
P62DDR
0
0
1
0
P62NCE
0
1

0
P62 input pin
P62 input pin
(noise
canceling)
P62 output pin
FTIA input pin
Pin function
KIN2 input pin
Rev. 3.00, 03/04, page 211 of 830
• P61/FTOA/KIN1
The function of port 6 pins is switched as shown below according to the combination of the
OEA bit in TOCR of FRT, and the P61DDR bit.
When the KMIM1 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be
used as the KIN1 input pin. To use this pin as the KIN1 input pin, clear the P61DDR bit to 0.
Mode
OEA
Port
0
0
FRT
0
1
P61DDR
0
0
1

P61NCE
0
1


P61 input pin
P61 input pin
(noise
canceling)
P61 output pin
FTOA output pin
Pin function
KIN1 input pin
• P60/FTCI/KIN0
The function of port 6 pins is switched as shown below according to the P60DDR bit.
When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the
FTCI input pin. When the KMIM0 bit in KMIMR6 of the interrupt controller is cleared to 0,
this pin can be used as the KIN0 input pin. To use this pin as the KIN0 input pin, clear the
P60DDR bit to 0.
Mode
Port
FRT
P60DDR
0
0
1
0
P60NCE
0
1

0
P60 input pin
P60 input pin
(noise
canceling)
P60 output pin
FTCI input pin
Pin function
KIN0 input pin
Rev. 3.00, 03/04, page 212 of 830
8.6.9
Port 6 Input Pull-Up MOS
Port 6 has a built-in input pull-up MOS that can be controlled by software. This input pull-up
MOS can be used regardless of the operating mode. Table 8.5 summarizes the input pull-up MOS
states.
Table 8.5
Port 6 Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off
: Always off.
On/Off : On when input state and KMPCR = 1; otherwise off.
8.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins, D/A
converter analog output pins, and interrupt input pins. Port 7 has the following register.
• Port 7 input data register (P7PIN)
8.7.1
Port 7 Input Data Register (P7PIN)
P7PIN indicates the pin states.
Bit
Bit Name
Initial Value
R/W
Description
7
P77PIN
Undefined*
R
6
P76PIN
Undefined*
R
5
P75PIN
Undefined*
R
4
P74PIN
Undefined*
R
When a P7PIN read is performed, the pin states are
always read. This register is assigned to the same
address as that of PBDDR. When the register is
programmed, data is programmed in the PBDDR and
the setting of port B is changed.
3
P73PIN
Undefined*
R
2
P72PIN
Undefined*
R
1
P71PIN
Undefined*
R
0
P70PIN
Undefined*
R
Note: The initial value is determined in accordance with the pin states of P77 to P70.
Rev. 3.00, 03/04, page 213 of 830
8.7.2
Pin Functions
Each pin of port 7 can also be used as the interrupt input pins (ExIRQ2 to ExIRQ7), analog input
pin of the A/D converter (AN0 to AN7), and analog output pin (DA0, DA1) of the D/A converter.
By setting the ISS bit of the ISSR to 1, the pins can also be used as the interrupt input pin
(ExIRQ2 to ExIRQ7).
When the interrupt input pin is set, do not use the pins for the A/D or D/A converter.
• P77/ExIRQ7/AN7/DA1
The port 7 function changes as shown in the following table, depending on the combination of
the CH2 to CH0 bits of ADCSR of the A/D converter, the DAOE1 bit of DACR of the D/A
converter, and the ISS7 bit of ISSR of the interrupt controller. Do not set these bits to other
values than those shown in the following table.
CH2 to CH0
B'111
DAOE1
0
ISS7
Pin function
Other than B'111
0
1
0
0
1
0
AN7 input pin
P77 input pin
ExIRQ7 input pin
DA1 output pin
• P76/ExIRQ6/AN6/DA0
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter, the DAOE0 bit of
DACR of the D/A converter, and the ISS6 bit of ISSR of the interrupt controller. Do not set
these bits to other values than those shown in the following table.
SCAN
CH2 to CH0
0
B'110
DAOE0
0
ISS6
0
Pin function
AN6
input
pin
1
Other than B'110
0
0
1
P76
ExIRQ6
input pin input pin
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 214 of 830
B'11*
1
0
0
0
DA0
output
pin
Other than B'11*
0
0
1
1
AN6
P76
ExIRQ6
input pin input pin input pin
0
DA0
output
pin
• P75/ExIRQ5/AN5
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS5 bit of
ISSR of the interrupt controller. Do not set these bits to other values than those shown in the
following table.
SCAN
CH2 to CH0
ISS5
Pin function
0
B'101
1
Other than B'101
B'101, B'11*
Other than B'101 and
B'11*
0
0
1
0
0
1
AN5
input pin
P75
input pin
ExIRQ5
input pin
AN5
input pin
P75
input pin
ExIRQ5
input pin
[Legend]
*:
Don’t care
• P74/ExIRQ4/AN4
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS4 bit of
ISSR of the interrupt controller. Do not set these bits to other values than those shown in the
following table.
SCAN
CH2 to CH0
ISS4
Pin function
0
B'100
1
Other than B'100
B'1**
Other than B'1**
0
0
1
0
0
1
AN4
input pin
P74
input pin
ExIRQ4
input pin
AN4
input pin
P74
input pin
ExIRQ4
input pin
[Legend]
*:
Don’t care
• P73/ExIRQ3/AN3
The port 7 function changes as shown in the following table, depending on the combination of
the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS3 bit of ISSR of the interrupt
controller. Do not set these bits to other values than those shown in the following table.
CH2 to CH0
ISS3
Pin function
B'011
Other than B'011
0
0
1
AN3
input pin
P73
input pin
ExIRQ3
input pin
Rev. 3.00, 03/04, page 215 of 830
• P72/ExIRQ2/AN2
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS2 bit of
ISSR of the interrupt controller. Do not set these bits to other values than those shown in the
following table.
SCAN
CH2 to CH0
ISS2
Pin function
0
B'010
1
Other than B'010
B'01*
Other than B'01*
0
0
1
0
0
1
AN2
input pin
P72
input pin
ExIRQ2
input pin
AN2
input pin
P72
input pin
ExIRQ2
input pin
[Legend]
*:
Don’t care
• P71/AN1
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter. Do not set these bits
to other values than those shown in the following table.
SCAN
0
1
CH2 to CH0
B'001
Other than
B'001
B'001, B'01*
Other than B'001
and B'01*
Pin function
AN1
input pin
P71 input pin
AN1
input pin
P71 input pin
[Legend]
*:
Don’t care
• P70/AN0
The port 7 function changes as shown in the following table, depending on the combination of
the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter. Do not set these bits
to other values than those shown in the following table.
SCAN
0
1
CH2 to CH0
B'000
Other than
B'000
B'0**
Other than B'0**
Pin function
AN0
input pin
P70 input pin
AN0
input pin
P70 input pin
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 216 of 830
8.8
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins also function as the A/D converter external trigger input pin,
SCI_0, SCI_1, and SCI_2 clock input/output pins, IIC_0 and IIC_1 input/output pins, TMR_0,
TMR_1, TMR_X, and TMR_Y input pins, and interrupt input pins. Port 8 is an NMOS push-pull
output. Port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
8.8.1
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DDR
0
W
6
P86DDR
0
W
This register is assigned to the same address as that
of PBPIN. When this register is read, the port B states
are read.
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
8.8.2
If port 8 pins are specified for use as the general I/O
port, the corresponding port 8 pins are output ports
when the P8DDR bits are set to 1, and input ports
when cleared to 0.
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DR
0
R/W
6
P86DR
0
R/W
P8DR stores output data for the port 8 pins that are
used as the general output port.
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
If a port 8 read is performed while the P8DDR bits are
set to 1, the P8DR values are read. If a port 8 read is
performed while the P8DDR bits are cleared to 0, the
pin states are read.
Rev. 3.00, 03/04, page 217 of 830
8.8.3
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P87/ExIRQ15/ADTRG/ExTMIY
The pin function is switched as shown below according to the P87DDR bit.
When the TRGS1 and TRGS0 bits in ADCR of the A/D converter are both set to 1, this pin
can be used as the ADTRG input pin.
When the ISS15 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ15 input pin. When the TMIYS bit in PTCNT0 is set to 1, this pin can be used as the
TMIY (TMCIX/TMRIY) input pin. To use this pin as the ExIRQ15 input pin, clear the
P87DDR bit to 0.
When this pin is used as the P87 output pin, the output format is NMOS push-pull output.
P87DDR
Pin function
0
1
P87 input pin
P87 output pin
ExIRQ15 input pin
/ADTRG input pin
/ExTMIY input pin
• P86/ExIRQ14/SCK2/ExTMIX
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_2, the CKE1 and CKE0 bits in SCR, and the P86DDR bit.
When the ISS14 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ14 input pin. When the TMIXS bit in PTCNT0 is set to 1, this pin can be used as the
TMIX (TMCIX/TMRIX) input pin. To use this pin as the ExIRQ14 input pin, clear the
P86DDR bit to 0.
When this pin is used as the P86 output pin, the output format is NMOS push-pull output.
CKE1
0
C/A
0
Pin function
1

1


0
1



P86 input pin
P86 output
pin
SCK2 output
pin
CKE0
P86DDR
1
0
ExIRQ14 input pin
/ExTMIX input pin
Rev. 3.00, 03/04, page 218 of 830
SCK2 output SCK2 input pin
pin
• P85/ExIRQ13/SCK1/ExTMI1
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit.
When the ISS13 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ13 input pin. When the TMI1S bit in PTCNT0 is set to 1, this pin can be used as the
TMI1 (TMI1/TMRI1) input pin. To use this pin as the ExIRQ13 input pin, clear the P85DDR
bit to 0.
When this pin is used as the P85 output pin, the output format is NMOS push-pull output.
CKE1
0
C/A
Pin function
1

1


0
CKE0
P85DDR
1
0
0
1



P85 input pin
P85 output
pin
SCK1 output
pin
SCK1 output
pin
SCK1 input
pin
ExIRQ13 input pin
/ExTMI1 input pin
• P84/ExIRQ12/SCK0/ExTMI0
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_0, the CKE1 and CKE0 bits in SCR, and the P84DDR bit.
When the ISS12 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ12 input pin. When the TMI0S bit in PTCNT0 is set to 1, this pin can be used as the
TMI0 (TMI0/TMRI0) input pin. To use this pin as the ExIRQ12 input pin, clear the P84DDR
bit to 0.
When this pin is used as the P84 output pin, the output format is NMOS push-pull output.
CKE1
0
C/A
Pin function
1

1


0
CKE0
P84DDR
1
0
0
1



P84 input pin
P84 output
pin
SCK0 output
pin
SCK0 output
pin
SCK0 input
pin
ExIRQ12 input pin
/ExTMI0 input pin
Rev. 3.00, 03/04, page 219 of 830
• P83/ExIRQ11/SDA1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P83DDR bit.
When the ISS11 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ11 input pin. To use this pin as the ExIRQ11 input pin, clear the P83DDR bit to 0.
When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The
output format for SDA1 is NMOS open-drain output, and direct bus drive is possible.
ICE
P83DDR
Pin function
0
1
0
1

P83 input pin
P83 output pin
SDA1 input/output pin
ExIRQ11 input pin
• P82/ExIRQ10/SCL1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P82DDR bit.
When the ISS10 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ10 input pin. To use this pin as the ExIRQ10 input pin, clear the P82DDR bit to 0.
When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The
output format for SCL1 is NMOS open-drain output, and direct bus drive is possible.
ICE
P82DDR
Pin function
0
1
0
1

P82 input pin
P82 output pin
SCL1 input/output pin
ExIRQ10 input pin
• P81/ExIRQ9/SDA0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P81DDR bit.
When the ISS9 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ9 input pin. To use this pin as the ExIRQ9 input pin, clear the P81DDR bit to 0.
When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The
output format for SDA0 is NMOS open-drain output, and direct bus drive is possible.
ICE
P81DDR
Pin function
0
1
0
1

P81 input pin
P81 output pin
SDA0 input/output pin
ExIRQ9 input pin
Rev. 3.00, 03/04, page 220 of 830
• P80/ExIRQ8/SCL0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P80DDR bit.
When the ISS8 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the
ExIRQ8 input pin. To use this pin as the ExIRQ8 input pin, clear the P80DDR bit to 0.
When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The
output format for SCL0 is NMOS open-drain output, and direct bus drive is possible.
ICE
P80DDR
Pin function
0
1
0
1

P80 input pin
P80 output pin
SCL0 input/output pin
ExIRQ8 input pin
Rev. 3.00, 03/04, page 221 of 830
8.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins also function as the bus control I/O pins or the system clock
output pin. Pin functions are switched depending on the operating mode. Port 9 has the following
registers.
• Port 9 data direction register (P9DDR)
• Port 9 data register (P9DR)
8.9.1
Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the pins of port 9.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DDR
0
W
If port 9 pins are specified for use as the general I/O
port, the corresponding port 9 pins are output ports
when the P9DDR bits are set to 1, and input ports
when cleared to 0.
6
P96DDR
0
W
When this bit is set to 1, the corresponding port 96 pin
is the system clock output pin (φ), and as a general
input port when cleared to 0.
5
P95DDR
0
W
4
P94DDR
0
W
3
P93DDR
0
W
If port 9 pins are specified for use as the general I/O
port, the corresponding port 9 pins are output ports
when the P9DDR bits are set to 1, and input ports
when cleared to 0.
2
P92DDR
0
W
1
P91DDR
0
W
0
P90DDR
0
W
Rev. 3.00, 03/04, page 222 of 830
8.9.2
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DR
0
R/W
6
P96DR
Undefined*
R
P9DR stores output data for the port 9 pins that are
used as the general output port except for bit 6.
5
P95DR
0
R/W
4
P94DR
0
R/W
3
P93DR
0
R/W
2
P92DR
0
R/W
1
P91DR
0
R/W
0
P90DR
0
R/W
If a port 9 read is performed while the P9DDR bits are
set to 1, the P9DR values are read. If a port 9 read is
performed while the P9DDR bits are cleared to 0, the
pin states are read.
Note: The initial value of bit 6 is determined in accordance with the P96 pin state.
8.9.3
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as
follows.
• P97/WAIT/CS256
The pin function is switched as shown below according to the combination of the operating
mode, the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and
the P97DDR bit.
Operating
Mode
Extended Mode
WMS1,
WMS21
All 0
CS256E
P97DDR
Pin function
0
0
1
1
P97 input P97 output
pin
pin
Single-Chip Mode
One bit is set as
1





0
1
CS256 output
pin
WAIT input pin
P97 input
pin
P97output
pin
Rev. 3.00, 03/04, page 223 of 830
• P96/φ/EXCL
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P96DDR bit.
P96DDR
0
0
1

P96 input pin
EXCL input pin
φ output pin
EXCLE
Pin function
1
• P95/AS/IOS
The pin function is switched as shown below according to the combination of the operating
mode, the IOSE bit in SYSCR, and the P95DDR bit.
Operating
Mode
Extended Mode
P95DDR

IOSE
Pin function
Single-Chip Mode
0
1

0
1
AS output pin
IOS output pin
P95 input pin
P95 output pin
• P94/HWR
The pin function is switched as shown below according to the combination of the operating
mode and the P94DDR bit.
Operating
Mode
P94DDR
Pin function
Extended Mode
Single-Chip Mode

0
1
HWR output pin
P94 input pin
P94 output pin
• P93/RD
The pin function is switched as shown below according to the combination of the operating
mode and the P93DDR bit.
Operating
Mode
P93DDR
Pin function
Extended Mode
Single-Chip Mode

0
1
RD output pin
P93 input pin
P93 output pin
Rev. 3.00, 03/04, page 224 of 830
• P92/CPCS1
The pin function is switched as shown below according to the combination of the operating
mode, the CPCSE bit in BCR2 of BSC, and the P92DDR bit.
Operating
Mode
Extended Mode
CPCSE
P92DDR
Pin function
0
Single-Chip Mode

1
0
1
P92 input pin
P92 output pin

0
1
CPCS1 output pin P92 input pin P92 output pin
• P91/AH
The pin function is switched as shown below according to the combination of the operating
mode, the ADMXE bit of SYSCR2, and the P91DDR bit.
Operating
Mode
Extended Mode
ADMXE
P91DDR
Pin function
0
Single-Chip Mode

1
0
1

0
1
P91 input pin
P91 output pin
AH output pin
P91 input pin
P91 output pin
• P90/LWR
The pin function is switched as shown below according to the combination of the operating
mode, the ABW and ABW256 bits in WSCR, the ABWCP bit in BCR2, and the P90DDR bit.
Operating
Mode
Extended Mode
ABW,
ABW256,
ABWCP
P90DDR
Pin function
All 1
Single-Chip Mode

One bit is set as
0
0
1

0
1
P90 input pin
P90 output pin
LWR output pin
P90 input pin
P90 output pin
Rev. 3.00, 03/04, page 225 of 830
8.10
Port A
Port A is an 8-bit I/O port. Port A pins also function as the address output, event counter input,
keyboard input, and SCI_0 and SCI_2 external control pins. Pin functions are switched depending
on the operating mode. Port A has the following registers. PADDR and PAPIN have the same
address.
• Port A data direction register (PADDR)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
8.10.1
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
In normal extended mode:
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
The corresponding port A pins are address output
ports when the PADDR bits are set to 1, and input
ports when cleared to 0. Pins function as the address
output port depending on the setting of bits IOSE,
CS256E, CPCSE, ADFULLE in bus controller.
2
PA2DDR
0
W
In other mode:
1
PA1DDR
0
W
0
PA0DDR
0
W
The corresponding port A pins are output ports when
the PADDR bits are set to 1, and input ports when
cleared to 0.
Rev. 3.00, 03/04, page 226 of 830
8.10.2
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
PAODR stores output data for the port A pins that are
used as the general output port.
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
8.10.3
Port A Input Data Register (PAPIN)
PAPIN indicates the pin states.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PIN
Undefined*
R
6
PA6PIN
Undefined*
R
When a PAPIN read is performed, the pin states are
always read.
5
PA5PIN
Undefined*
R
4
PA4PIN
Undefined*
R
3
PA3PIN
Undefined*
R
2
PA2PIN
Undefined*
R
1
PA1PIN
Undefined*
R
0
PA0PIN
Undefined*
R
Note: The initial values are determined in accordance with the pin states of PA7 to PA0.
Rev. 3.00, 03/04, page 227 of 830
8.10.4
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as
follows.
Normal Extended Mode: Port A functions as address output, keyboard input, external control
input of SCI_0 and SCI_2, and also as an I/O port, and input or output can be specified in bit units.
Address 18 and 13 in the following table are expressed by the following logical expressions:
Address 18 = 1:ADFULLE
Address 13 = 1:ADFULLE • CS256E • (CPCSE  IOSE)
• PA7/KIN15/EVENT7/A23, PA6/KIN14/EVENT6/A22, PA5/KIN13/EVENT5/A21,
PA4/KIN12/EVENT4/A20, PA3/KIN11/EVENT3/A19, PA2/KIN10/EVENT2/A18
The function of port A pins is switched according to the combination of address 18 setting and
the PAnDDR bit. When the KMIM bit in KMIMRA of the interrupt controller is cleared to 0,
this pin can be used as the KIN input pin. To use this pin as the KIN input pin, clear the
PAnDDR bit to 0. When this pin is used as EVENT input pin according to bits ECSB3 to
ECSB0 in ECCR of the data transfer controller settings, clear the PAnDDR bit to 0. Though
this pin has been set to the EVENT input pin, to use as the PAn or A1 output pin, set the
PAnDDR bit to 1.
PAnDDR
0
1
1
Address 18
1
1
0
Pin function
PAn input pins
PAn output pin
Al output pin
KINm input pin
EVENTn input pin
[Legend]
n = 7 to 2
m = 15 to 10
l = 23 to 18
• PA1/KIN9/EVENT1/A17/SSE2I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, address 13 setting, and
the PA1DDR bit.
When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
When this pin is used as EVENT1 input pin according to bits ECSB3 to ECSB0 in ECCR of
the data transfer controller settings, clear the PA1DDR bit to 0. Though this pin has been set to
the EVENT1 input pin, to use as the PA1 or A17 output pin, set the PA1DDR bit to 1.
Rev. 3.00, 03/04, page 228 of 830
SSE
0
1
C/A

1
CEK1

1
PA1DDR
0
Address 13
Pin function
1
0

PA1 output pin
A17 output pin
SSE2I input pin
1
PA1 input pin

1
KIN9 input pin
/EVENT1 input pin
• PA0 /KIN8/EVENT0/A16/SSE0I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, address 13 setting, and
the PA0DDR bit.
When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0.
When this pin is used as EVENT0 input pin according to bits ECSB3 to ECSB0 in ECCR of
the data transfer controller settings, clear the PA0DDR bit to 0. Though this pin has been set to
the EVENT0 input pin, to use as the PA0 or A16 output pin, set the PA0DDR bit to 1.
SSE
0
1
C/A

1
CKE1

1
PA0DDR
0
Address 13
Pin function
1
1
PA0 input pin
PA0 output pin
1

0

A16 output pin
SSE0I input pin
KIN8 input pin
/EVENT0 input pin
Single-Chip Mode and Address-Data Multiplex Extended Mode: Port A functions as keyboard
input, external control input of SCI_0 and SCI_2, and also as an I/O port, and input or output can
be specified in bit units.
• PA7/KIN15/EVENT7, PA6/KIN14/EVENT6, PA5/KIN13/EVENT5, PA4/KIN12/EVENT4,
PA3/KIN11/EVENT3, PA2/KIN10/EVENT2
When the KMIM bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN input pin. To use this pin as the KIN input pin, clear the PAnDDR bit to 0.
When this pin is used as the EVENT input pin according to bits ECSB3 to ECSB0 in ECCR of
the data transfer controller settings, clear the PAnDDR bit to 0. Though this pin has been set to
the EVENT input pin, to use as the PAn output pins, set the PAnDDR bit to 1.
Rev. 3.00, 03/04, page 229 of 830
PAnDDR
Pin function
0
1
PAn input pins
PAn output pins
KINm input pin/EVENTn input pins
[Legend]
n = 7 to 2
m = 15 to 10
• PA1/KIN9/EVENT1/SSE2I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, and the PA1DDR bit.
When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
When this pin is used as the EVENT1 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA1DDR bit to 0. Though this pin has been set
to the EVENT1 input pin, to use as the PA1 output pin, set the PA1DDR bit to1.
SSE
0
1
C/A

1

CKE1
PA1DDR
Pin function
1
0
1

PA1 input pin
PA1 output pin
SSE2I input pin
KIN9 input pin
/EVENT1 input pin
• PA0/KIN8/EVENT0/SSE0I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, and the PA0DDR bit.
When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0.
When this pin is used as the EVENT0 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA0DDR bit to 0. Though this pin has been set
to the EVENT0 input pin, to use as the PA0 output pin, set the PA0DDR bit to1.
Rev. 3.00, 03/04, page 230 of 830
SSE
0
1
C/A

1
CKE1

1
PA0DDR
Pin function
0
1

PA0 input pin
PA0 output pin
SSE0I
KIN8 input pin
/EVENT0 input pin
8.10.5
Input Pull-Up MOS
Port A has a built-in input pull-up MOS that can be controlled by software. This input pull-up
MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PAnDDR
0
PAnODR
PAn pull-up MOS
1
1
0

ON
OFF
OFF
[Legend]
n = 7 to 0
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.6 summarizes the input pull-up MOS states.
Table 8.6
Port A Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
Rev. 3.00, 03/04, page 231 of 830
8.11
Port B
Port B is an 8-bit multi-function input/output port that can also be used event counter input pin.
Port B has the following registers.
• Port B data direction register (PBDDR)
• Port B output data register (PBODR)
• Port B input data register (PBPIN)
8.11.1
Port B Data Direction Register (PBDDR)
PBDDR is used to specify the input/output attribute of each pin of port B.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DDR
0
W
6
PB6DDR
0
W
The corresponding port B pins are output ports when
the PBDDR bits are set to 1, and input ports when
cleared to 0.
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
8.11.2
Port B Output Data Register (PBODR)
PBODR stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7ODR
0
R/W
6
PB6ODR
0
R/W
The PBODR register stores the output data for the
pins that are used a general output port.
5
PB5ODR
0
R/W
4
PB4ODR
0
R/W
3
PB3ODR
0
R/W
2
PB2ODR
0
R/W
1
PB1ODR
0
R/W
0
PB0ODR
0
R/W
Rev. 3.00, 03/04, page 232 of 830
8.11.3
Port B Input Data Register (PBPIN)
PBPIN indicates the pin states.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PIN
Undefined*
R
6
PB6PIN
Undefined*
R
Pin states can be read by performing a read cycle on
this register.
5
PB5PIN
Undefined*
R
4
PB4PIN
Undefined*
R
3
PB3PIN
Undefined*
R
2
PB2PIN
Undefined*
R
1
PB1PIN
Undefined*
R
0
PB0PIN
Undefined*
R
This register is assigned to the same address as that
of P8DDR. When this register is written to, data is
written to P8DDR and the port 8 setting is then
changed.
Note: The initial value of these pins is determined in accordance with the state of pins PB7 to
PB0.
8.11.4
Pin Functions
Port B is a multi-function port that can function as an event counter input pin. The relationship
between the operating mode setup and pin functions is described below.
When this pin is used as the EVENT input pin according to bits ECSB3 to ECSB0 in ECCR of the
data transfer controller settings, clear the PBnDDR bit to 0.
(n = 7 to 0 )
• PB7/EVENT15
PB7DDR
0
*1
Event counter
Pin function
1
Disable
Enable

PB7 input pin
EVENT15 input pin
PB7 output pin
• PB6/EVENT14
PB6DDR
0
*1
Event counter
Pin function
1
Disable
Enable

PB6 input pin
EVENT14 input pin
PB6 output pin
Rev. 3.00, 03/04, page 233 of 830
• PB5/ EVENT13
PB5DDR
0
1
Event counter*
Pin function
1
Disable
Enable

PB5 input pin
EVENT13 input pin
PB5 output pin
• PB4/EVENT12
PB4DDR
0
1
Event counter*
Pin function
1
Disable
Enable

PB4 input pin
EVENT12 input pin
PB4 output pin
• PB3/EVENT11
PB3DDR
0
1
Event counter*
Pin function
1
Disable
Enable

PB3 input pin
EVENT11 input pin
PB3 output pin
Disable
Enable

PB2 input pin
EVENT10 input pin
PB2 output pin
• PB2/EVENT10
PB2DDR
0
Event counter*1
Pin function
1
• PB1/EVENT9
PB1DDR
0
1
Event counter*
Pin function
1
Disable
Enable

PB1 input pin
EVENT9 input pin
PB1 output pin
• PB0/EVENT8
PB0DDR
0
1
Event counter*
Pin function
1
Disable
Enable

PB0 input pin
EVENT8 input pin
PB0 output pin
Note: For event counter setting, refer to section 7, Data Transfer Controller (DTC).
Rev. 3.00, 03/04, page 234 of 830
8.12
Port C
Port C is an 8-bit multi-function I/O port that functions as PWMX output pins or input/output pins
of IIC_2, 3, 4. The output format of ports C0 to C5 is NMOS push-pull output.
Port C has the following registers.
• Port C data direction register (PCDDR)
• Port C output data register (PCODR)
• Port C input data register (PCPIN)
8.12.1
Port C Data Direction Register (PCDDR)
PCDDR is used to specify the input/output attribute of each pin of port C.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
6
PC6DDR
0
W
When a given bit is set to 1, the corresponding pin will
function as an output port, and when cleared to 0, it
functions as an input port.
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
8.12.2
This register is assigned to the same address as that
of PCPIN. When this address is read, the port C
states are returned.
Port C Output Data Register (PCODR)
PCODR stores output data for port C.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
The PCODR register stores the output data for the
pins that are used as a general output port.
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
Rev. 3.00, 03/04, page 235 of 830
8.12.3
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states of port C.
Bit
7
6
5
Bit Name
PC7PIN
PC6 PIN
PC5 PIN
Initial Value
R/W
Description
1
R
When this register is read, the pin state is read.
1
R
1
R
1
This register is assigned to the same address as that
of PCDDR. When this register is written to, data is
written to PCDDR and the port C setting is then
changed.
Undefined*
Undefined*
Undefined*
4
PC4 PIN
Undefined*
R
3
PC3 PIN
Undefined*1
R
PC2 PIN
1
R
1
R
1
R
2
1
0
PC1 PIN
PC0 PIN
Undefined*
Undefined*
Undefined*
Note: The initial values are determined in accordance with the states of PC7 to PC0 pins.
8.12.4
Pin Functions
Port C is capable of functioning as the input and output of IIC_2, IIC_3, and IIC_4, and the
PWMX output. The relationship between the register settings and pin function is described below.
• PC7/PWX3
The pin function is switched as shown below according to the combination of the OEB bit of
the 14-bit PWMX DACR and the PC7DDR.
OEB
PC7DDR
Pin Function
0
1
0
1

PC7 input pin
PC7 output pin
PWX3 output pin
• PC6/PWX2
The pin function is switched as shown below according to the combination of the OEA bit of
the 14-bit PWMX DACR and the PC6DDR.
OEA
PC6DDR
Pin Function
0
1
0
1

PC6 input pin
PC6 output pin
PWX2 output pin
Rev. 3.00, 03/04, page 236 of 830
• PC5/SDA4
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_4 ICCR and the PC5DDR.
ICE
PC5DDR
Pin Function
0
1
0
1

PC5 input pin
PC5 output pin
SDA4 input/output pin
• PC4/SCL4
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_4 ICCR and the PC4DDR.
ICE
PC4DDR
Pin Function
0
1
0
1

PC4 input pin
PC4 output pin
SCL4 input/output pin
• PC3/SDA3
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_3 ICCR and the PC3DDR.
ICE
PC3DDR
Pin Function
0
1
0
1

PC3 input pin
PC3 output pin
SDA3 input/output pin
• PC2/SCL3
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_3 ICCR and the PC2DDR.
ICE
PC2DDR
Pin Function
0
1
0
1

PC2 input pin
PC2 output pin
SCL3 input/output pin
• PC1/SDA2
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_2 ICCR and the PC1DDR.
ICE
PC1DDR
Pin Function
0
1
0
1

PC1 input pin
PC1 output pin
SDA2 input/output pin
Rev. 3.00, 03/04, page 237 of 830
• PC0/SCL2
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_2 ICCR and the PC0DDR.
ICE
0
0
1

PC0 input pin
PC0 output pin
SCL2 input/output pin
PC0DDR
Pin Function
8.13
1
Port D
Port D is an 8-bit multi-function I/O port that supports the following register set. Port D functions
as both the IIC_5 I/O pin, and the LPC I/O pin. Ports D7 and D6 are NMOS push-pull outputs.
• Port D data direction register (PDDDR)
• Port D output data register (PDODR)
• Port D input data register (PDPIN)
8.13.1
Port D Data Direction Register (PDDDR)
PDDDR is used to specify the input/output attribute of each pin of port D.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
When the general input/output port function is
selected, and the given bit is set to 1, the
corresponding pin will function as an output port, and
when the bit is cleared to 0, the pin will function as an
input port.
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Rev. 3.00, 03/04, page 238 of 830
This register is assigned to the same address as that
of PDPIN. When this address is read, the port D
states are returned.
8.13.2
Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7ODR
0
R/W
6
PD6ODR
0
R/W
The PDODR register stores the output data for the
pins that are used a general output port.
5
PD5ODR
0
R/W
4
PD4ODR
0
R/W
3
PD3ODR
0
R/W
2
PD2ODR
0
R/W
1
PD1ODR
0
R/W
0
PD0ODR
0
R/W
8.13.3
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7PIN
Undefined*
R
6
PD6PIN
Undefined*
R
Pin states can be read by performing a read cycle on
this register.
5
PD5PIN
Undefined*
R
4
PD4PIN
Undefined*
R
3
PD3PIN
Undefined*
R
2
PD2PIN
Undefined*
R
1
PD1PIN
Undefined*
R
0
PD0PIN
Undefined*
R
This register is assigned to the same address as that
of PDDDR. When this register is written to, data is
written to PDDDR and the port D setting is then
changed.
Note: The initial value of these pins is determined in accordance with the state of pins PD7 to
PD0.
Rev. 3.00, 03/04, page 239 of 830
8.13.4
Pin Functions
Port D is a multi-function port that functions as an LPC input/output and IIC_5 input/output. The
relationship between the register settings and pin functions is described below.
The LPC module is disabled when the LPC1E, LPC2E, and LPC3E bits in HICR0 of LPC are all
cleared to a 0.
• PD7/SDA5
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_5 ICCR and the PD7DDR.
ICE
PD7DDR
Pin Function
0
1
0
1

PD7 input pin
PD7 output pin
SDA5 input/output pin
• PD6/SCL5
The pin function is switched as shown below according to the combination of the ICE bit of
the IIC_5 ICCR and the PD6DDR.
ICE
PD6DDR
Pin Function
0
1
0
1

PD6 input pin
PD6 output pin
SCL5 input/output pin
• PD5/LPCPD
The pin function is switched as shown below according to the combination of LPC
enabled/disabled and the PD5DDR.
LPC
PD5DDR
Pin Function
Disabled
Enabled
0
1
0
PD5 input pin
PD5 output pin
LPCPD input pin
• PD4/CLKRUN
The pin function is switched as shown below according to the combination of LPC
enabled/disabled and the PD4DDR.
LPC
PD4DDR
Pin Function
Disabled
Enabled
0
1
0
PD4 input pin
PD4 output pin
CLKRUN input/output pin
Rev. 3.00, 03/04, page 240 of 830
• PD3/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
of LPC HICR0 and the PD3DDR.
FGA20E
PD3DDR
Pin Function
0
1
0
1
0
PD3 input pin
PD3 output pin
GA20 output pin
• PD2/PME
The pin function is switched as shown below according to the combination of the PMEE bit of
LPC HICR0 and the PD2DDR.
PMEE
PD2DDR
Pin Function
0
1
0
1
0
PD2 input pin
PD2 output pin
PME output pin
• PD1/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit of
LPC HICR0 and the PD1DDR.
LSMIE
PD1DDR
Pin Function
0
1
0
1
0
PD1 input pin
PD1 output pin
LSMI output pin
• PD0/LSCI
The pin function is switched as shown below according to the combination of the LSCIE bit of
LPC HICR0 and the PD0DDR.
LSCIE
PD0DDR
Pin Function
0
1
0
1
0
PD0 input pin
PD0 output pin
LSCI output pin
Rev. 3.00, 03/04, page 241 of 830
8.13.5
Input Pull-Up MOS
Ports D5 to D0 have a built-in input pull-up MOS that can be controlled by software. This input
pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit
basis.
PDnDDR
0
1
0

ON
OFF
OFF
PDnODR
PDn pull-up
MOS
1
[Legend]
n = 5 to 0
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.7 summarizes the input pull-up MOS states.
Table 8.7
Port D Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PDDDR = 0 and PDODR = 1; otherwise off.
Rev. 3.00, 03/04, page 242 of 830
8.14
Port E
Port E functions as an 8-bit input/output port and also as an LPC input/output. Port E provides the
following register set.
• Port E data direction register (PEDDR)
• Port E output data register (PEODR)
• Port E input data register (PEPIN)
8.14.1
Port E Data Direction Register (PEDDR)
PEDDR is used to specify the input/output attribute of each pin of port E.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
6
PE6DDR
0
W
When a given bit of PEDDR is set to 1, the
corresponding pin will function as an output port, and
when cleared to 0, it will function as an input port.
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
8.14.2
This register is assigned to the same address as that
of PEPIN. When this address is read, the port E
states are returned.
Port E Output Data Register (PEODR)
PEODR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7ODR
0
R/W
6
PE6ODR
0
R/W
The PEODR register stores the output data for the
pins that are used a general output port.
5
PE5ODR
0
R/W
4
PE4ODR
0
R/W
3
PE3ODR
0
R/W
2
PE2ODR
0
R/W
1
PE1ODR
0
R/W
0
PE0ODR
0
R/W
Rev. 3.00, 03/04, page 243 of 830
8.14.3
Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7PIN
Undefined*
R
6
PE6PIN
Undefined*
R
Pin states can be read by performing a read cycle on
this register.
5
Pe5PIN
Undefined*
R
4
PE4PIN
Undefined*
R
3
PE3PIN
Undefined*
R
2
PE2PIN
Undefined*
R
1
PE1PIN
Undefined*
R
0
PE0PIN
Undefined*
R
This register is assigned to the same address as that
of PEDDR. When this register is written to, data is
written to PEDDR and the port E setting is then
changed.
Note: The initial value of these pins is determined in accordance with the state of pins PE7 to
PE0.
8.14.4
Pin Functions
Port E also functions as an LPC input/output. The pin function is switched with LPC enabled or
disabled. The LPC module is disabled when the LPC1E, LPC2E, and LPC3E bits in HICR0 of
LPC are all 0.
• PE7/SERIRQ
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE7DDR.
LPC
PE7DDR
Pin Function
Disabled
Enabled
0
1

PE7 input pin
PE7 output pin
SERIRQ input/output pin
• PE6/LCLK
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE6DDR.
LPC
PE6DDR
Pin Function
Disabled
Enabled
0
1

PE6 input pin
PE6 output pin
LCLK input pin
Rev. 3.00, 03/04, page 244 of 830
• PE5/LRESET
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE5DDR.
LPC
PE5DDR
Pin Function
Disabled
Enabled
0
1

PE5 input pin
PE5 output pin
LRESET input pin
• PE4/LFRAME
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE4DDR.
LPC
PE4DDR
Pin Function
Disabled
Enabled
0
1

PE4 input pin
PE4 output pin
LFRAME input pin
• PE3/LAD3
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE3DDR.
LPC
PE3DDR
Pin Function
Disabled
Enabled
0
1

PE3 input pin
PE3 output pin
LAD3 input/output pin
• PE2/LAD2
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE2DDR.
LPC
PE2DDR
Pin Function
Disabled
Enabled
0
1

PE2 input pin
PE2 output pin
LAD2 input/output pin
• PE1/LAD1
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE1DDR.
LPC
PE1DDR
Pin Function
Disabled
Enabled
0
1

PE1 input pin
PE1 output pin
LAD1 input/output pin
Rev. 3.00, 03/04, page 245 of 830
• PE0/LAD0
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE0DDR.
LPC
Disabled
0
1

PE0 input pin
PE0 output pin
LAD0 input/output pin
PE0DDR
Pin Function
8.15
Enabled
Port F
Port F is a 3-bit multi-function input/output port supporting the following register set.
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
8.15.1
Port F Data Direction Register (PFDDR)
PFDDR is used to specify the input/output attribute of each pin of port F.
Bit
Bit Name
Initial Value
R/W
Description
7 to 3



Reserved
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
When the given bit of PFDDR is set to 1, the
corresponding pin of port F will function as an output
port, and when the bit is cleared to 0, the port pin will
function as an input port.
This register is assigned to the same address as that
of PFPIN. When this address is read, the port F states
are returned.
8.15.2
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins.
Bit
Bit Name
Initial Value
R/W
Description
7 to 3



Reserved. When this bit is read, an undefined value is
returned.
2
PF2ODR
0
R/W
1
PF1ODR
0
R/W
The PFODR register stores the output data for the
pins that are used a general output port.
0
PF0ODR
0
R/W
Rev. 3.00, 03/04, page 246 of 830
8.15.3
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit
Bit Name Initial Value
R/W
Description
7 to 3



Reserved. When this bit is read, an undefined value is
returned.
2
PF2PIN
Undefined*
R
When PFPIN is read, the pin states are returned.
1
PF1PIN
Undefined*
R
0
PF0PIN
Undefined*
R
This register is assigned to the same address as that
of PFDDR. When this register is written to, data is
written to PFDDR and the port F setting is then
changed.
Note: The initial value of these pins is determined in accordance with the state of pins PF2 to
PF0.
8.15.4
Pin Functions
Port F is a 3-bit input/output port that functions as a PWM output. The relationship between the
register settings and pin functions is depicted below.
• PF2/ExPW2, PF1/ExPW1, PF0/ExPW0
The pin function is switched as shown below according to the combination of the OEn bit in
PWOERA of PWM, the PWMS bit in PTCNT0, and PFnDDR bit.
PFnDDR
0

1
PWMS
0
1
0
1
1
OEn

0

0
1
Pin Function
PFn input pin
PFn output pin
PWn output pin
[Legend]
n = 2 to 0
Rev. 3.00, 03/04, page 247 of 830
8.16
Change of Peripheral Function Pins
I/O ports that also function as peripheral modules, such as the external interrupts, 8-bit timer input,
and 8-bit PWM timer output, can be changed.
I/O ports that also function as the external interrupt pins are changed according to the setting of
ISSR16 and ISSR. I/O ports that also function as the 8-bit timer input pins and the 8-bit PWM
timer output pins are changed according to the setting of PTCNT0. The pin name of the peripheral
function is indicated by adding ‘Ex’ at the head of the original pin name. In each peripheral
function description, the original pin name is used.
8.16.1
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
ISSR16 and ISSR select ports that also function as IRQ15 to IRQ0 input pins.
• ISSR16
Bit
Bit Name
Initial Value
R/W
Description
15
ISS15
0
R/W
0: P57/IRQ15 is selected
1: P87/ExIRQ15 is selected
14
ISS14
0
R/W
0: P56/IRQ14 is selected
1: P86/ExIRQ14 is selected
13
ISS13
0
R/W
0: P55/IRQ13 is selected
1: P85/ExIRQ13 is selected
12
ISS12
0
R/W
0: P54/IRQ12 is selected
1: P84/ExIRQ12 is selected
11
ISS11
0
R/W
0: P53/IRQ11 is selected
1: P83/ExIRQ11 is selected
10
ISS10
0
R/W
0: P52/IRQ10 is selected
9
ISS9
0
R/W
0: P51/IRQ9 is selected
1: P82/ExIRQ10 is selected
1: P81/ExIRQ9 is selected
8
ISS8
0
R/W
0: P50/IRQ8 is selected
1: P80/ExIRQ8 is selected
Rev. 3.00, 03/04, page 248 of 830
• ISSR
Bit
Bit Name
Initial Value
R/W
Description
7
ISS7
0
R/W
0: P47/IRQ7 is selected
1: P77/ExIRQ7 is selected
6
ISS6
0
R/W
0: P46/IRQ6 is selected
1: P76/ExIRQ6 is selected
5
ISS5
0
R/W
0: P45/IRQ5 is selected
1: P75/ExIRQ5 is selected
4
ISS4
0
R/W
0: P44/IRQ4 is selected
1: P74/ExIRQ4 is selected
3
ISS3
0
R/W
0: P43/IRQ3 is selected
1: P73/ExIRQ3 is selected
2
ISS2
0
R/W
0: P42/IRQ2 is selected
1
ISS1
0
R/W
P41/IRQ1 is always selected
0
ISS0
0
R/W
P40/IRQ0 is always selected
1: P72/ExIRQ2 is selected
Rev. 3.00, 03/04, page 249 of 830
8.16.2
Port Control Register 0 (PTCNT0)
PTCNT0 selects ports that also function as 8-bit timer input pins, and 8-bit PWM timer output
pins.
Bit
Bit Name
Initial Value
R/W
7
TMI0S
0
R/W
Description
0: P40/TMI0 is selected
1: P84/ExTMI0 is selected
6
TMI1S
0
R/W
0: P41/TMI1 is selected
1: P85/ExTMI1 is selected
5
TMIXS
0
R/W
0: P44/TMIX is selected
1: P86/ExTMIX is selected
4
TMIYS
0
R/W
0: P45/TMIY is selected
1: P87/ExTMIY is selected
3

0
R/W
Reserved
The initial values should not be changed.
2
PWMS
0
R/W
0: P10/PW0, P11/PW1, P12/PW2 are selected
1: PF0/ExPW0, PF1/ExPW1, and PF2/ExPW2 are
selected
1, 0

All 0
R/W
Reserved
The initial values should not be changed.
Rev. 3.00, 03/04, page 250 of 830
Section 9 8-Bit PWM Timer (PWM)
This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output
waveforms are generated from a common time base, enabling PWM output with a high carrier
frequency to be produced using pulse division.
9.1
Features
• Operable at a maximum carrier frequency of 2.06 kHz using pulse division (at 33 MHz
operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output, and PWM output enable/disable control
Figure 9.1 shows a block diagram of the PWM timer.
PWDR0
Comparator 1
PWDR1
P12/PW2
Comparator 2
PWDR2
P13/PW3
Comparator 3
PWDR3
P14/PW4
Comparator 4
PWDR4
Comparator 5
PWDR5
Comparator 6
PWDR6
Comparator 7
PWDR7
Comparator 8
PWDR8
Comparator 9
PWDR9
Comparator 10
PWDR10
P23/PW11
Comparator 11
PWDR11
P24/PW12
Comparator 12
PWDR12
P25/PW13
Comparator 13
PWDR13
P26/PW14
Comparator 14
PWDR14
P27/PW15
Comparator 15
PWDR15
P15/PW5
P16/PW6
P17/PW7
P20/PW8
P21/PW9
P22/PW10
PWDPRB
PWDPRA
PWOERB
PWOERA
P2DDR
P1DDR
P2DR
P1DR
Clock
counter
φ
PWM register select
PWM data register
PWM data polarity register A
PWM data polarity register B
PWM output enable register A
PWM output enable register B
PCSR:
P1DDR:
P2DDR:
P1DR:
P2DR:
PTCNT0:
φ/2
φ/4
φ/8
Internal
data bus
PWSL
Select
clock
PTCNT0
[Legend]
PWSL:
PWDR:
PWDPRA:
PWDPRB:
PWOERA:
PWOERB:
Module
data bus
Bus interface
Comparator 0
P11/PW1
Port/PWM output control
P10/PW0
PCSR
φ/16
Internal clock
Peripheral clock select register
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
Port control register 0
Figure 9.1 Block Diagram of PWM Timer
PWM0802A_000020021100
Rev. 3.00, 03/04, page 251 of 830
9.2
Input/Output Pins
Table 9.1 shows the PWM output pins.
Table 9.1
Pin Configuration
Name
Abbreviation
I/O
Function
PWM output 15 to 0
PW15 to PW0
Output
PWM timer pulse output 15 to 0
9.3
Register Descriptions
The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control
register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see
section 3.2.3, Serial Timer Control Register (STCR).
•
•
•
•
•
•
•
PWM register select (PWSL)
PWM data registers 15 to 0 (PWDR15 to PWDR0)
PWM data polarity register A (PWDPRA)
PWM data polarity register B (PWDPRB)
PWM output enable register A (PWOERA)
PWM output enable register B (PWOERB)
Peripheral clock select register (PCSR)
Rev. 3.00, 03/04, page 252 of 830
9.3.1
PWM Register Select (PWSL)
PWSL is used to select the input clock and the PWM data register.
Bit
Initial
Bit Name Value
7
6
PWCKE
PWCKS
0
0
R/W Description
R/W PWM Clock Enable
PWM Clock Select
These bits, together with bits PWCKB and PWCKA in PCSR,
select the internal clock input to TCNT in the PWM. For
details, see table 9.2.
The resolution, PWM conversion period, and carrier frequency
depend on the selected internal clock, and can be obtained
from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
With a 33 MHz system clock (φ), the resolution, PWM
conversion period, and carrier frequency are as shown in table
9.3.
5
—
1
R
4
—
0
R
Reserved
This bit is always read as 1 and cannot be modified.
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 3.00, 03/04, page 253 of 830
Bit
Bit Name
Initial
Value
3 to 0 RS3 to RS0 All 0
R/W Description
R/W Register Select
These bits select the PWM data register.
0000: PWDR0 selected
0001: PWDR1 selected
0010: PWDR2 selected
0011: PWDR3 selected
0100: PWDR4 selected
0101: PWDR5 selected
0110: PWDR6 selected
0111: PWDR7 selected
1000: PWDR8 selected
1001: PWDR9 selected
1010: PWDR10 selected
1011: PWDR11 selected
1100: PWDR12 selected
1101: PWDR13 selected
1110: PWDR14 selected
1111: PWDR15 selected
Table 9.2
Internal Clock Selection
PWSL
PCSR
PWCKE
PWCKS
PWCKB
PWCKA
Description
0
—
—
—
Clock input is disabled
1
0
—
—
φ (system clock) is selected
1
0
0
φ/2 is selected
1
φ/4 is selected
0
φ/8 is selected
1
φ/16 is selected
1
Rev. 3.00, 03/04, page 254 of 830
(Initial value)
Table 9.3
Resolution, PWM Conversion Period, and Carrier Frequency when φ = 33 MHz
Internal Clock
Frequency
Resolution
PWM Conversion
Period
Carrier Frequency
φ
30 ns
7.76 µs
2063 kHz
φ/2
61 ns
15.52 µs
1031 kHz
φ/4
121 ns
31.03 µs
515.6 kHz
φ/8
242 ns
62.06 µs
257.8 kHz
φ/16
485 ns
124.12 µs
128.9 kHz
9.3.2
PWM Data Registers 15 to 0 (PWDR15 to PWDR0)
PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
9.3.3
PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
Each PWDPR selects the PWM output phase.
• PWDPRA
Bit
Bit Name
Initial
Value
7 to 0 OS7 to OS0 All 0
R/W Description
R/W Output Select 7 to 0
These bits select the PWM output phase. Bits OS7 to OS0
correspond to outputs PW7 to PW0.
0: PWM direct output (PWDR value corresponds to high width
of output)
1: PWM inverted output (PWDR value corresponds to low
width of output)
Rev. 3.00, 03/04, page 255 of 830
• PWDPRB
Bit
Bit Name
Initial
Value R/W Description
7 to 0 OS15 to OS8 All 0
R/W Output Select 15 to 8
These bits select the PWM output phase. Bits OS15 to OS8
correspond to outputs PW15 to PW8.
0: PWM direct output (PWDR value corresponds to high width
of output)
1: PWM inverted output (PWDR value corresponds to low
width of output)
9.3.4
PWM Output Enable Registers A and B (PWOERA and PWOERB)
Each PWOER switches between PWM output and port output.
• PWOERA
Bit
Bit Name
7 to 0 OE7 to OE0
Initial
Value R/W Description
All 0
R/W Output Enable 7 to 0
These bits, together with P1DDR, specify the P1n/PWn pin
state. Bits OE7 to OE0 correspond to outputs PW7 to PW0.
P1nDDR OEn: Pin state
0*: Port input
10: Port output or PWM 256/256 output
11: PWM output (0 to 255/256 output)
[Legend]
n = 0 to 7
*:
Don't care
Rev. 3.00, 03/04, page 256 of 830
• PWOERB
Bit
Initial
Value R/W Description
Bit Name
7 to 0 OE15 to OE8 All 0
R/W Output Enable 15 to 8
These bits, together with P2DDR, specify the P2n/PWm pin
state. Bits OE15 to OE8 correspond to outputs PW15 to PW8.
P2nDDR OEm: Pin state
0*: Port input
10: Port output or PWM 256/256 output
11: PWM output (0 to 255/256 output)
[Legend]
n = 0 to 7
m = 8 to 15
*:
Don't care
To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set
to port output. The corresponding pin can be set as port output in single-chip mode or when IOSE
= 1 and CS256E = 0 in SYSCR in extended mode with on-chip ROM. Otherwise, it should be
noted that an address bus is output to the corresponding pin.
DR data is output when the corresponding pin is used as port output. A value corresponding to
PWM 256/256 output is determined by the OS bit, so the value should have been set to DR
beforehand.
9.3.5
Peripheral Clock Select Register (PCSR)
PCSR selects the PWM input clock.
Bit Bit Name
Initial Value R/W Description
7
6
PWCKX1B
PWCKX1A
0
0
R/W See section 10.3.4, Peripheral Clock Select Register
R/W (PCSR).
5
4
PWCKX0B
PWCKX0A
0
0
R/W
R/W
3
PWCKX1C
0
R/W
2
1
PWCKB
PWCKA
0
0
R/W PWM Clock Select B and A
R/W Together with bits PWCKE and PWCKS in PWSL, these
bits select the internal clock input to TCNT in the PWM. For
details, see table 9.2.
0
PWCKX0C
0
R/W See section 10.3.4, Peripheral Clock Select Register
(PCSR).
Rev. 3.00, 03/04, page 257 of 830
9.4
Operation
The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse.
Table 9.4
Duty Cycle of Basic Pulse
Upper 4 Bits
Basic Pulse Waveform (Internal)
B'0000
H: 0 1 2 3 4 5 6 7 8 9 A B C D E F 0
L:
B'0001
B'0010
B'0011
B'0100
B'0101
B'0110
B'0111
B'1000
B'1001
B'1010
B'1011
B'1100
B'1101
B'1110
B'1111
Rev. 3.00, 03/04, page 258 of 830
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An
additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the
rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge
of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of
the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional
pulse timing.
Table 9.5
Position of Pulses Added to Basic Pulses
Basic Pulse No.
Lower 4 Bits 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B'0000
B'0001
Yes
B'0010
Yes
Yes
B'0011
Yes
Yes
Yes
Yes
Yes
Yes
B'0100
Yes
B'0101
Yes
Yes
Yes
Yes
Yes
B'0110
Yes
Yes
Yes
Yes
Yes
Yes
B'0111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
B'1000
Yes
Yes
Yes
Yes
Yes
Yes
Yes
B'1001
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes
B'1010
Yes
Yes
Yes Yes Yes
Yes
Yes
Yes Yes Yes
B'1011
Yes
Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
B'1100
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
B'1101
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
B'1110
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
B'1111
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No additional pulse
Resolution width
With additional pulse
Additional pulse
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
Rev. 3.00, 03/04, page 259 of 830
9.4.1
PWM Setting Example
1-conversion cycle
Duty cycle
Basic
waveform
Additiona
pulse
7F
127/256
112 pulse
15 pulse
80
128/256
128 pulse
0 pulse
81
129/256
128 pulse
1 pulse
82
130/256
128 pulse
2 pulse
PWDR
setting example
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
: Pulse added
Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of duty cycle as low ripple waveform.
Figure 9.3 Example of PWM Setting
9.4.2
Diagram of PWM Used as D/A Converter
Figure 9.4 shows the diagram example when using the PWM pulse as the D/A converter. Analog
signal with low ripple can be generated by connecting the low pass filter.
Resistor : 120 kΩ
Capacitor : 0.1 µF
This LSI
Low pass filter
Reference value
Figure 9.4 Example when PWM is Used as D/A Converter
Rev. 3.00, 03/04, page 260 of 830
Section 10 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with four output channels. It
can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
10.1
Features
• Division of pulse into multiple base cycles to reduce ripple
• Eight resolution settings
The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
• Two base cycle settings
The base cycle can be set equal to T × 64 or T × 256, where T is the resolution.
• Sixteen operation clocks (by combination of eight resolution settings and two base cycle
settings)
Figure 10.1 shows a block diagram of the PWM (D/A) module.
Internal clock
Select clock
φ
φ/2, φ/64, φ/128, φ/256,
φ/1024, φ/4096, φ/16384
Clock
Internal data bus
Bus interface
Base cycle compare match A
PWX0
Fine–adjustment pulse addition A
PWX1
Base cycle compare match B
Fine–adjustment pulse addition B
Comparator A
DADRA
Comparator B
DADRB
Control
logic
Base cycle overflow
DACNT
DACR
[Legend]
DACR:
DADRA:
DADRB:
DACNT:
Module data bus
PWMX D/A control register (6 bits)
PWMX D/A data register A (15 bits)
PWMX D/A data register B (15 bits)
PWMX D/A counter (14 bits)
Figure 10.1 PWMX (D/A) Block Diagram
PWM1420A_010020021100
Rev. 3.00, 03/04, page 261 of 830
10.2
Input/Output Pins
Table 10.1 lists the PWMX (D/A) module input and output pins.
Table 10.1 Pin Configuration
Name
Abbreviation I/O
Function
PWMX output pin 0
PWX0
Output
PWM timer pulse output of PWMX_0 channel A
PWMX output pin 1
PWX1
Output
PWM timer pulse output of PWMX_0 channel B
PWMX output pin 2
PWX2
Output
PWM timer pulse output of PWMX_1 channel A
PWMX output pin 3
PWX3
Output
PWM timer pulse output of PWMX_1 channel B
10.3
Register Descriptions
The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to
the same addresses with other registers. The registers are selected by the IICE bit in the serial
timer control register (STCR). For details on the module stop control register, see section 23.1.3,
Module Stop Control Register H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA).
• PWMX (D/A) counter (DACNT)
• PWMX (D/A) data register A (DADRA)
• PWMX (D/A) data register B (DADRB)
• PWMX (D/A) control register (DACR)
• Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.
Rev. 3.00, 03/04, page 262 of 830
10.3.1
PWMX (D/A) Counter (DACNT)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit
(CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed
in 8-bit units. DACNT should always be accessed in 16-bit units. For details, see section 10.4, Bus
Master Interface.
• DACNT
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
UC7 to UC0
All 0
R/W
Lower Up-Counter
7 to 2
UC8 to UC13 All 0
R/W
Upper Up-Counter
1

R
Reserved
1
This bit is always read as 1 and cannot be modified.
0
REGS
1
R/W
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 3.00, 03/04, page 263 of 830
10.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The
DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed
in 16-bit units. For details, see section 10.4, Bus Master Interface.
• DADRA
Bit
Bit Name
15 to 2 DA13 to DA0
Initial
Value
R/W
Description
All 1
R/W
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with UC12 and UC13 of DACNT.
1
CFS
1
R/W
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
The range of DA13 to DA0: H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
The range of DA13 to DA0: H'0040 to H'3FFF
0

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 3.00, 03/04, page 264 of 830
• DADRB
Bit
Bit Name
Initial
Value
15 to 2 DA13 to DA0 All 1
R/W
Description
R/W
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with UC12 and UC13 of DACNT.
1
CFS
1
R/W
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
DA13 to DA0 range = H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
DA13 to DA0 range = H'0040 to H'3FFF
0
REGS
1
R/W
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 3.00, 03/04, page 265 of 830
10.3.3
PWMX (D/A) Control Register (DACR)
DACR enables the PWM outputs, and selects the output phase and operating speed.
Bit
Bit Name
Initial Value
R/W
Description
7

0
R/W
Reserved
The initial value should not be changed.
6
PWME
0
R/W
PWMX Enable
Starts or stops the PWM D/A counter (DACNT).
0: DACNT operates as a 14-bit up-counter
1: DACNT halts at H'0003
5, 4 
All 1
R
Reserved
These bits are always read as 1 and cannot be
modified.
3
OEB
0
R/W
Output Enable B
Enables or disables output on PWMX (D/A) channel B.
0: PWMX (D/A) channel B output (at the PWX1, PWX3
pins) is disabled
1: PWMX (D/A) channel B output (at the PWX1, PWX3
pins) is enabled
2
OEA
0
R/W
Output Enable A
Enables or disables output on PWMX (D/A) channel A.
0: PWMX (D/A) channel A output (at the PWX0, PWX2
pin) is disabled
1: PWMX (D/A) channel A output (at the PWX0, PWX2
pins) is enabled
1
OS
0
R/W
Output Select
Selects the phase of the PWMX (D/A) output.
0: Direct PWMX (D/A) output
1: Inverted PWMX (D/A) output
0
CKS
0
R/W
Clock Select
Selects the PWMX (D/A) resolution. Eight kinds of
resolution can be selected.
0: Operates at resolution (T) = system clock cycle time
(tcyc)
1: Operates at resolution (T) = system clock cycle time
(tcyc) × 2, × 64, × 128, × 256, × 1024, × 4096, and ×
16384.
Rev. 3.00, 03/04, page 266 of 830
10.3.4
Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit
Bit Name
Initial Value
R/W
Description
7
6
PWCKX1B
PWCKX1A
0
0
R/W
R/W
PWMX_1 Clock Select
These bits select a clock cycle with the CKS bit of
DACR of PWMX_1 being 1.
See table 10.2.
5
4
PWCKX0B
PWCKX0A
0
0
R/W
R/W
PWMX_0 Clock Select
These bits select a clock cycle with the CKS bit of
DACR of PWMX_0 being 1.
See table 10.2.
3
PWCKX1C
0
R/W
PWMX_1 Clock Select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_1 being 1.
See table 10.2.
2
1
PWCKB
PWCKA
0
0
R/W
R/W
PWM Clock Select B and A
0
PWCKX0C
0
R/W
PWMX_0 Clock Select
See section 9.3.5, Peripheral Clock Select Register
(PCSR).
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_0 being 1.
See table 10.2.
Table 10.2 Clock Select of PWMX_1 and PWMX_0
PWCKX0C
PWCKX1C
PWCKX0B
PWCKX1B
PWCKX0A
PWCKX1A
Resolution (T)
0
0
0
Operates on the system clock cycle (tcyc) x 2
0
0
1
Operates on the system clock cycle (tcyc) x 64
0
1
0
Operates on the system clock cycle (tcyc) x 128
0
1
1
Operates on the system clock cycle (tcyc) x 256
1
0
0
Operates on the system clock cycle (tcyc) x 1024
1
0
1
Operates on the system clock cycle (tcyc) x 4096
1
1
0
Operates on the system clock cycle (tcyc) x 16384
1
1
1
Setting prohibited
Rev. 3.00, 03/04, page 267 of 830
10.4
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written to and read from as follows.
• Write
When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written to, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read from, the upper-byte value is transferred to the CPU and the
lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper
byte should always be accessed before the lower byte. Correct data will not be transferred if only
the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction
cannot be used to access these registers.
Example 1: Write to DACNT
MOV.W R0, @DACNT
; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
; Copy contents of DADRA to R0
Rev. 3.00, 03/04, page 268 of 830
10.5
Operation
A PWM waveform like the one shown in figure 10.2 is output from the PWX pin. DA13 to DA0
in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle
(256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly
output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value
corresponds to the total width (TH) of the high (1) output pulses. Figures 10.3 and 10.4 show the
types of waveform output available.
1 conversion cycle
(T × 214 (= 16384))
tf
Base cycle
(T × 64 or T × 256)
tL
T: Resolution
m
TL = Σ tLn (OS = 0)
n=1
(When CFS = 0, m = 256
When CFS = 1, m = 64)
Figure 10.2 PWMX (D/A) Operation
Table 10.3 summarizes the relationships between the CKS and CFS bit settings and the resolution,
base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR
contain at least a certain minimum value. The relationship between the OS bit and the output
waveform is shown in figures 10.3 and 10.4.
Rev. 3.00, 03/04, page 269 of 830
Table 10.3 Settings and Operation (Examples when φ = 33 MHz)
PCSR
Fixed DADR Bits
ResoConversion
TL/TH
Accuracy
B
A
CKS (µs)
CFS Cycle
Cycle
(OS = 0/OS = 1)
(Bits)
 

0
0
496.48
Always low/high output
14
C
0.03
1.94
(µs)
(µs)
/515.6kHz
1
(φ)
0
0
0
1
0.06
7.76
496.48
(µs)
(µs)
/128.9kHz
0
3.88
(µs)
0.99
(ms)
/257.8kHz
1
15.52
(µs)
(φ/2)
0
0
1
1
1.94
0.99
(ms)
/64.5kHz
0
124.12
(µs)
31.78
(ms)
/8.1kHz
1
496.48
(µs)
(φ/64)
0
1
0
1
3.88
31.78
(ms)
/2.0kHz
0
248.24
(µs)
63.55
(ms)
/4.0kHz
1
992.97
(µs)
(φ/128)
63.55
(ms)
/1.0kHz
Rev. 3.00, 03/04, page 270 of 830
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
10
Always low/high output
14
(Data value) × T
10
Always low/high output
14
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
Always low/high output
14
(Data value) × T
10
Always low/high output
14
(Data value) × T
10
Always low/high output
14
DA13 to 0 = H'0000 to H'003F
(Data value) × T
10
Always low/high output
14
(Data value) × T
10
Always low/high output
14
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
0
0
0
0.12
0
0
0.03
0
0
0.12
0
0
0.03
0
0
0.25
0
0
0.06
0.99
0
0
0
0
0.25
0
0
0.06
31.78
0
0
0
0
7.94
0
0
1.99
31.78
0
0
0
0
7.94
0
0
1.99
63.55
0
0
0
0
15.89
0
0
3.97
63.55
12
10
0
0.99
12
DA13 to 0 = H'0100 to H'3FFF
DA13 to 0 = H'0000 to H'003F
0
12
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
0
12
DA13 to 0 = H'0100 to H'3FFF
Cycle (ms)*
0.50
12
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
0
12
10
DA13 to 0 = H'0000 to H'003F
0
12
DA13 to 0 = H'0040 to H'3FFF
Conversion
0.50
12
DA13 to 0 = H'0100 to H'3FFF
DA13 to 0 = H'0000 to H'003F
Bit Data
DA0
Base
DA1
T
DA2
lution
PWCKX1
DA3
PWCKX0
0
0
0
0
15.89
0
0
3.97
PCSR
Fixed DADR Bits
ResoConversion
TL/TH
Accuracy
C
B
A
CKS (µs)
CFS Cycle
Cycle
(OS = 0/OS = 1)
(Bits)
0
1
1
1
0
127.10
Always low/high output
14
7.76
496.48
(µs)
(ms)
/2.0kHz
1
1985.94
(µs)
(φ/256)
1
0
0
1
31.03
127.10
(ms)
/0.5kHz
0
1.99
(ms)
508.40
(ms)
/503.5Hz
1
(φ/1024)
1
0
1
1
124.12
7.94
508.40
(ms)
(ms)
7.94
(ms)
2.03
(s)
/125.9Hz
1
31.78
(ms)
(φ/4096)
1
1
0
1
496.48
2.03
(s)
/31.5Hz
0
31.78
(ms)
8.13
(s)
/31.5Hz
1
127.10
(ms)
(φ/16384)
1
1
1
1
Setting
8.13
(s)
/7.9Hz


(Data value) × T
10
Always low/high output
14
DA13 to 0 = H'0000 to H'003F
(Data value) × T
10
Always low/high output
14
DA13 to 0 = H'0000 to H'00FF
(Data value) × T

Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
10
14
DA13 to 0 = H'0100 to H'3FFF
Always low/high output
14
10
Always low/high output
14
(Data value) × T
10
Always low/high output
14
(Data value) × T
31.78
0
0
7.94
0
0
31.78
0
0
7.94
508.40
0
0
0
0
127.10
0
0
31.78
0
0
127.10
0
0
31.78
508.40
0
0
2033.60
0
0
0
0
508.40
0
0
127.10
2033.60
0
0
0
0
508.40
0
0
127.10
8134.41
12
DA13 to 0 = H'0100 to H'3FFF
DA13 to 0 = H'0000 to H'003F
0
12
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
0
12
10
(Data value) × T
0
14
Always low/high output
DA13 to 0 = H'0000 to H'003F
0
127.10
12
10
(Data value) × T
0
12
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
0
12
DA13 to 0 = H'0040 to H'3FFF
Cycle (ms)*
127.10
12
DA13 to 0 = H'0100 to H'3FFF
DA13 to 0 = H'0100 to H'3FFF
/125.9Hz
0
DA13 to 0 = H'0000 to H'00FF
Conversion
Bit Data
DA0
Base
DA1
T
DA2
lution
PWCKX1
DA3
PWCKX0
0
0
0
0
2033.60
0
0
508.40
8134.41
12
0
0
2033.60
DA13 to 0 = H'0040 to H'3FFF
10
0
0
0
0
508.40







prohibited
Note:
*
Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.
Rev. 3.00, 03/04, page 271 of 830
1 conversion cycle
tf1
tL1
tf2
tf255
tL2
tL3
tL255
tf256
tL256
tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64
tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tL1
tf2
tL2
tf63
tL3
tL63
tf64
tL64
tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256
tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 10.3 Output Waveform (OS = 0, DADR corresponds to TL)
Rev. 3.00, 03/04, page 272 of 830
1 conversion cycle
tf1
tH1
tf2
tf255
tH2
tH3
tf256
tH255
tH256
tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64
tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tH1
tf2
tf63
tH2
tH3
tf64
tH63
tH64
tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256
tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 10.4 Output Waveform (OS = 1, DADR corresponds to TH)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 10.5.
Table 10.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
DA8
Duty cycle of base pulse
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Location of additional pulses
CFS
1
1
Figure 10.5 D/A Data Register Configuration when CFS = 1
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 10.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 10.4. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
Rev. 3.00, 03/04, page 273 of 830
1 conversion cycle
Base cycle
No. 0
Base cycle
Base cycle
No. 1
No. 63
Base pulse
High width: 2/256 × (T)
Additional pulse output location
Base pulse
2/256 × (T)
Additional pulse
1/256 × (T)
Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1)
However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is
determined by the upper six bits and the locations of the additional pulses by the subsequent eight
bits with a method similar to as above.
Rev. 3.00, 03/04, page 274 of 830
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Lower 6 bits
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
Base pulse No.
1 2 3 4 5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Table 10.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
Rev. 3.00, 03/04, page 275 of 830
Rev. 3.00, 03/04, page 276 of 830
Section 11 16-Bit Free-Running Timer (FRT)
This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input
pulse width and external clock periods.
11.1
Features
• Selection of four clock sources
 One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be
selected (enabling use as an external event counter).
• Two independent comparators
 Two independent waveforms can be output.
• Four independent input capture channels
 The rising or falling edge can be selected.
 Buffer modes can be specified.
• Counter clearing
 The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
 Two compare-match interrupts, four input capture interrupts, and one overflow interrupt
can be requested independently.
• Special functions provided by automatic addition function
 The contents of OCRAR and OCRAF can be added to the contents of OCRA
automatically, enabling a periodic waveform to be generated without software intervention.
The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling
input capture operations in this interval to be restricted.
Figure 11.1 shows a block diagram of the FRT.
TIM8FR1A_000120020900
Rev. 3.00, 03/04, page 277 of 830
Internal clock
OCRAR/F
φ/2
φ/8
φ/32
Clock
Clock selector
OCRA
Compare-match A
Comparator A
FTOA
Overflow
FTOB
FRC
Clear
FTIA
FTIB
Control logic
Compare-match B
Comparator B
FTIC
Bus interface
FTCI
Module data bus
External clock
Internal data bus
OCRB
FTID
Input capture
ICRA
ICRB
ICRC
ICRD
Comparator M
×1
×2
Compare-match M
OCRDM
TCSR
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Interrupt signal
[Legend]
OCRA, OCRB:
OCRAR,OCRAF:
OCRDM:
FRC:
ICRA to D:
TCSR:
TIER:
TCR:
TOCR:
Output compare register A, B (16-bit)
Output compare register AR, AF (16-bit)
Output compare register DM (16-bit)
Free-running counter (16-bit)
Input capture registers A to D (16-bit)
Timer control/status register (8-bit)
Timer interrupt enable register (8-bit)
Timer control register (8-bit)
Timer output compare control register (8-bit)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
Rev. 3.00, 03/04, page 278 of 830
11.2
Input/Output Pins
Table 11.1 lists the FRT input and output pins.
Table 11.1 Pin Configuration
Name
Abbreviation
I/O
Function
Counter clock input pin
FTCI
Input
FRC counter clock input
Output compare A output pin
FTOA
Output
Output compare A output
Output compare B output pin
FTOB
Output
Output compare B output
Input capture A input pin
FTIA
Input
Input capture A input
Input capture B input pin
FTIB
Input
Input capture B input
Input capture C input pin
FTIC
Input
Input capture C input
Input capture D input pin
FTID
Input
Input capture D input
11.3
Register Descriptions
The FRT has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Free-running counter (FRC)
Output compare register A (OCRA)
Output compare register B (OCRB)
Input capture register A (ICRA)
Input capture register B (ICRB)
Input capture register C (ICRC)
Input capture register D (ICRD)
Output compare register AR (OCRAR)
Output compare register AF (OCRAF)
Output compare register DM (OCRDM)
Timer interrupt enable register (TIER)
Timer control/status register (TCSR)
Timer control register (TCR)
Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS
bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF,
and OCRDM. Register selection is controlled by the ICRS bit in TOCR.
Rev. 3.00, 03/04, page 279 of 830
11.3.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit
units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.
11.3.2
Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is
set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values
match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output
compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0
until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed
in 8-bit units. OCR is initialized to H'FFFF.
11.3.3
Input Capture Registers A to D (ICRA to ICRD)
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only
register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID)
is detected, the current FRC value is transferred to the corresponding input capture register (ICRA
to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set
to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture
edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer
enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when
ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then
transferred to the buffer register ICRC. When IEDGA and IEDGC bits in TCR are set to different
values, both rising and falling edges can be specified as the change of the external input signal.
To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (φ) for
a single edge. When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clocks (φ).
ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is
initialized to H'0000.
Rev. 3.00, 03/04, page 280 of 830
11.3.4
Output Compare Registers AR and AF (OCRAR and OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is
set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The
contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is
written to OCRA. The write operation is performed on the occurrence of compare-match A. In the
1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to
compare-match A varies according to whether the compare-match follows addition of OCRAR or
OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A
following addition of OCRAF, while 0 is output on a compare-match A following addition of
OCRAR.
When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC
input clock together with a set value of H'0001 or less for OCRAR (or OCRAF).
OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units.
OCRAR and OCRAF are initialized to H'FFFF.
11.3.5
Output Compare Register DM (OCRDM)
OCRDM is a 16-bit readable/writable register in which the upper eight bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval. A mask interval is not generated when the contents of OCRDM are
H'0000 while the ICRDMS bit is set to 1.
OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is
initialized to H'0000.
Rev. 3.00, 03/04, page 281 of 830
11.3.6
Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit
Bit Name
Initial Value
R/W
Description
7
ICIAE
0
R/W
Input Capture Interrupt A Enable
Selects whether to enable input capture interrupt A
request (ICIA) when input capture flag A (ICFA) in
TCSR is set to 1.
0: ICIA requested by ICFA is disabled
1: ICIA requested by ICFA is enabled
6
ICIBE
0
R/W
Input Capture Interrupt B Enable
Selects whether to enable input capture interrupt B
request (ICIB) when input capture flag B (ICFB) in
TCSR is set to 1.
0: ICIB requested by ICFB is disabled
1: ICIB requested by ICFB is enabled
5
ICICE
0
R/W
Input Capture Interrupt C Enable
Selects whether to enable input capture interrupt C
request (ICIC) when input capture flag C (ICFC) in
TCSR is set to 1.
0: ICIC requested by ICFC is disabled
1: ICIC requested by ICFC is enabled
4
ICIDE
0
R/W
Input Capture Interrupt D Enable
Selects whether to enable input capture interrupt D
request (ICID) when input capture flag D (ICFD) in
TCSR is set to 1.
0: ICID requested by ICFD is disabled
1: ICID requested by ICFD is enabled
3
OCIAE
0
R/W
Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled
Rev. 3.00, 03/04, page 282 of 830
Bit
Bit Name
Initial Value
R/W
Description
2
OCIBE
0
R/W
Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
1
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
0

0
R
Reserved
This bit is always read as 1 and cannot be modified.
11.3.7
Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit
Bit Name
Initial Value
R/W
Description
7
ICFA
0
R/(W)* Input Capture Flag A
This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture
signal. When BUFEA = 1, ICFA indicates that the old
ICRA value has been moved into ICRC and the new
FRC value has been transferred to ICRA.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRA
[Clearing condition]
Read ICFA when ICFA = 1, then write 0 to ICFA
Rev. 3.00, 03/04, page 283 of 830
Bit
Bit Name
Initial Value
R/W
Description
6
ICFB
0
R/(W)* Input Capture Flag B
This status flag indicates that the FRC value has been
transferred to ICRB by means of an input capture
signal. When BUFEB = 1, ICFB indicates that the old
ICRB value has been moved into ICRD and the new
FRC value has been transferred to ICRB.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRB
[Clearing condition]
Read ICFB when ICFB = 1, then write 0 to ICFB
5
ICFC
0
R/(W)* Input Capture Flag C
This status flag indicates that the FRC value has been
transferred to ICRC by means of an input capture
signal. When BUFEA = 1, on occurrence of an input
capture signal specified by the IEDGC bit at the FTIC
input pin, ICFC is set but data is not transferred to
ICRC. In buffer operation, ICFC can be used as an
external interrupt signal by setting the ICICE bit to 1.
[Setting condition]
When an input capture signal is received
[Clearing condition]
Read ICFC when ICFC = 1, then write 0 to ICFC
4
ICFD
0
R/(W)* Input Capture Flag D
This status flag indicates that the FRC value has been
transferred to ICRD by means of an input capture
signal. When BUFEB = 1, on occurrence of an input
capture signal specified by the IEDGD bit at the FTID
input pin, ICFD is set but data is not transferred to
ICRD. In buffer operation, ICFD can be used as an
external interrupt signal by setting the ICIDE bit to 1.
[Setting condition]
When an input capture signal is received
[Clearing condition]
Read ICFD when ICFD = 1, then write 0 to ICFD
Rev. 3.00, 03/04, page 284 of 830
Bit
Bit Name
Initial Value
R/W
Description
3
OCFA
0
R/(W)* Output Compare Flag A
This status flag indicates that the FRC value matches
the OCRA value.
[Setting condition]
When FRC = OCRA
[Clearing condition]
Read OCFA when OCFA = 1, then write 0 to OCFA
2
OCFB
0
R/(W)* Output Compare Flag B
This status flag indicates that the FRC value matches
the OCRB value.
[Setting condition]
When FRC = OCRB
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 to OCFB
1
OVF
0
R/(W)* Overflow Flag
This status flag indicates that the FRC has overflowed.
[Setting condition]
When FRC overflows (changes from H'FFFF to
H'0000)
[Clearing condition]
Read OVF when OVF = 1, then write 0 to OVF
0
CCLRA
0
R/W
Counter Clear A
This bit selects whether the FRC is to be cleared at
compare-match A (when the FRC and OCRA values
match).
0: FRC clearing is disabled
1: FRC is cleared at compare-match A
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 285 of 830
11.3.8
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit
Bit Name
Initial Value
R/W
7
IEDGA
0
R/W
Description
Input Edge Select A
Selects the rising or falling edge of the input capture A
signal (FTIA).
0: Capture on the falling edge of FTIA
1: Capture on the rising edge of FTIA
6
IEDGB
0
R/W
Input Edge Select B
Selects the rising or falling edge of the input capture B
signal (FTIB).
0: Capture on the falling edge of FTIB
1: Capture on the rising edge of FTIB
5
IEDGC
0
R/W
Input Edge Select C
Selects the rising or falling edge of the input capture C
signal (FTIC).
0: Capture on the falling edge of FTIC
1: Capture on the rising edge of FTIC
4
IEDGD
0
R/W
Input Edge Select D
Selects the rising or falling edge of the input capture D
signal (FTID).
0: Capture on the falling edge of FTID
1: Capture on the rising edge of FTID
3
BUFEA
0
R/W
Buffer Enable A
Selects whether ICRC is to be used as a buffer register
for ICRA.
0: ICRC is not used as a buffer register for ICRA
1: ICRC is used as a buffer register for ICRA
2
BUFEB
0
R/W
Buffer Enable B
Selects whether ICRD is to be used as a buffer register
for ICRB.
0: ICRD is not used as a buffer register for ICRB
1: ICRD is used as a buffer register for ICRB
Rev. 3.00, 03/04, page 286 of 830
Bit
Bit Name
Initial Value
R/W
Description
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1 and 0
Select clock source for FRC.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: External clock source (counting at FTCI rising edge)
11.3.9
Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access
between output compare registers A and B, controls the ICRD and OCRA operating modes, and
switches access to input capture registers A, B, and C.
Bit
Bit Name
Initial Value
R/W
Description
7
ICRDMS
0
R/W
Input Capture D Mode Select
Specifies whether ICRD is used in the normal operating
mode or in the operating mode using OCRDM.
0: The normal operating mode is specified for ICRD
1: The operating mode using OCRDM is specified for
ICRD
6
OCRAMS
0
R/W
Output Compare A Mode Select
Specifies whether OCRA is used in the normal
operating mode or in the operating mode using OCRAR
and OCRAF.
0: The normal operating mode is specified for OCRA
1: The operating mode using OCRAR and OCRAF is
specified for OCRA
5
ICRS
0
R/W
Input Capture Register Select
The same addresses are shared by ICRA and OCRAR,
by ICRB and OCRAF, and by ICRC and OCRDM. The
ICRS bit determines which registers are selected when
the shared addresses are read from or written to. The
operation of ICRA, ICRB, and ICRC is not affected.
0: ICRA, ICRB, and ICRC are selected
1: OCRAR, OCRAF, and OCRDM are selected
Rev. 3.00, 03/04, page 287 of 830
Bit
Bit Name
Initial Value
R/W
Description
4
OCRS
0
R/W
Output Compare Register Select
OCRA and OCRB share the same address. When this
address is accessed, the OCRS bit selects which
register is accessed. The operation of OCRA or OCRB
is not affected.
0: OCRA is selected
1: OCRB is selected
3
OEA
0
R/W
Output Enable A
Enables or disables output of the output compare A
output pin (FTOA).
0: Output compare A output is disabled
1: Output compare A output is enabled
2
OEB
0
R/W
Output Enable B
Enables or disables output of the output compare B
output pin (FTOB).
0: Output compare B output is disabled
1: Output compare B output is enabled
1
OLVLA
0
R/W
Output Level A
Selects the level to be output at the output compare A
output pin (FTOA) in response to compare-match A
(signal indicating a match between the FRC and OCRA
values). When the OCRAMS bit is 1, this bit is ignored.
0: 0 is output at compare-match A
1: 1 is output at compare-match A
0
OLVLB
0
R/W
Output Level B
Selects the level to be output at the output compare B
output pin (FTOB) in response to compare-match B
(signal indicating a match between the FRC and OCRB
values).
0: 0 is output at compare-match B
1: 1 is output at compare-match B
Rev. 3.00, 03/04, page 288 of 830
11.4
Operation
11.4.1
Pulse Output
Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference.
When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and
OLVLB bits are inverted by software.
FRC
H'FFFF
Counter clear
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 11.2 Example of Pulse Output
Rev. 3.00, 03/04, page 289 of 830
11.5
Operation Timing
11.5.1
FRC Increment Timing
Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the
increment timing with an external clock source. The pulse width of the external clock signal must
be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is
shorter than 1.5 system clocks (φ).
φ
Internal clock
FRC input
clock
FRC
N–1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
φ
External clock
input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
Rev. 3.00, 03/04, page 290 of 830
11.5.2
Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
11.5 shows the timing of this operation for compare-match A.
φ
FRC
N
OCRA
N
N+1
N
N+1
N
Compare-match
A signal
Clear*
OLVLA
Output compare A
output pin FTOA
Note : * Indicates instruction execution by software.
Figure 11.5 Timing of Output Compare A Output
11.5.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
Compare-match
A signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A Signal
Rev. 3.00, 03/04, page 291 of 830
11.5.4
Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (φ). Figure 11.8 shows the timing for this case.
Read cycle of ICRA to ICRD
T1
T2
φ
Input capture
input pin
Input capture signal
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)
Rev. 3.00, 03/04, page 292 of 830
11.5.5
Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
φ
FTIA
Input capture
signal
FRC
n
n+1
N
N+1
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 11.9 Buffered Input Capture Timing
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock (φ). Figure 11.10 shows the
timing when BUFEA = 1.
Rev. 3.00, 03/04, page 293 of 830
CPU read cycle of ICRA or ICRC
T1
T2
φ
FTIA
Input capture
signal
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
11.5.6
Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is
simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure
11.11 shows the timing of setting the ICFA to ICFD flag.
φ
Input capture
signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 11.11 Timing of Input Capture Flag (ICFA to ICFD) Setting
Rev. 3.00, 03/04, page 294 of 830
11.5.7
Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag.
φ
FRC
N
OCRA, OCRB
N+1
N
Compare-match
signal
OCFA, OCFB
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
11.5.8
Timing of FRC Overflow Flag (OVF) Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of setting the OVF flag.
φ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Timing of Overflow Flag (OVF) Setting
Rev. 3.00, 03/04, page 295 of 830
11.5.9
Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. Figure 11.14 shows the OCRA write timing.
φ
FRC
N
N +1
OCRA
N
N+A
OCRAR, OCRAF
A
Compare-match
signal
Figure 11.14 OCRA Automatic Addition Timing
11.5.10 Mask Signal Generation Timing
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture signal is generated. The mask signal is set by the input
capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the
OCRDM contents, and an FRC compare-match. Figure 11.15 shows the timing of setting the mask
signal. Figure 11.16 shows the timing of clearing the mask signal.
φ
Input capture
signal
Input capture
mask signal
Figure 11.15 Timing of Input Capture Mask Signal Setting
Rev. 3.00, 03/04, page 296 of 830
φ
FRC
N
ICRD + OCRDM × 2
N+1
N
Compare-match
signal
Input capture
mask signal
Figure 11.16 Timing of Input Capture Mask Signal Clearing
Rev. 3.00, 03/04, page 297 of 830
11.6
Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts.
The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources.
Table 11.2 FRT Interrupt Sources
Interrupt
Interrupt Source
Interrupt Flag
DTC Activation
Priority
ICIA
Input capture of ICRA
ICFA
Possible
High
ICIB
Input capture of ICRB
ICFB
Possible
ICIC
Input capture of ICRC
ICFC
Not possible
ICID
Input capture of ICRD
ICFD
Not possible
OCIA
Compare match of OCRA
OCFA
Possible
OCIB
Compare match of OCRB
OCFB
Possible
FOVI
Overflow of FRC
OVF
Not possible
Rev. 3.00, 03/04, page 298 of 830
Low
11.7
Usage Notes
11.7.1
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of
conflict.
Write cycle of FRC
T1
T2
φ
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 11.17 Conflict between FRC Write and Clear
Rev. 3.00, 03/04, page 299 of 830
11.7.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.
Write cycle of FRC
T1
T2
φ
Address
FRC address
Internal write
signal
FRC input
clock
FRC
N
M
Write data
Figure 11.18 Conflict between FRC Write and Increment
Rev. 3.00, 03/04, page 300 of 830
11.7.3
Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of
conflict.
Write cycle of OCR
T1
T2
φ
Address
OCR address
Internal write
signal
FRC
N
OCR
N
N+1
M
Write data
Compare-match
signal
Disabled
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)
Rev. 3.00, 03/04, page 301 of 830
φ
Address
OCRAR (OCRAF)
address
Internal write signal
OCRAR (OCRAF)
Compare-match signal
Old data
New data
Disabled
FRC
N
OCR
N
N+1
Automatic addition is not performed
because compare-match signals are disabled.
Figure 11.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)
11.7.4
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may source FRC to increment. This depends
on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table
11.3.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also source FRC to increment.
Rev. 3.00, 03/04, page 302 of 830
Table 11.3 Switching of Internal Clock and FRC Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
low to low
FRC Operation
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
CKS bit rewrite
2
Switching from
low to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
3
Switching from
high to low
Clock before
switchover
Clock after
switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Rev. 3.00, 03/04, page 303 of 830
Table 11.3 Switching of Internal Clock and FRC Operation (cont)
No.
4
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
high to high
FRC Operation
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated on the assumption that the switchover is a falling edge; FRC is incremented.
Rev. 3.00, 03/04, page 304 of 830
Section 12 8-Bit Timer (TMR)
This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on
the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a
variety of applications, such as generation of counter reset, interrupt requests, and pulse output
with an arbitrary duty cycle using a compare-match signal with two registers.
This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels.
12.1
Features
• Selection of clock sources
 TMR_0, TMR_1: The counter input clock can be selected from six internal clocks and an
external clock
 TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks and
an external clock
• Selection of three ways to clear the counters
 The counters can be cleared on compare-match A, compare-match B, or by an external
reset signal.
• Timer output controlled by two compare-match signals
 The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle.
• Cascading of TMR_0 and TMR_1
(Cascading of TMR_Y and TMR_X is not allowed)
 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1
as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare
match occurrences (compare-match count mode).
• Multiple interrupt sources for each channel
 TMR_0, TMR_1,
and TMR_Y:
Three types of interrupts: Compare-match A,
compare-match B, and overflow
 TMR_X:
Four types of interrupts: Compare-match A, comparematch B, overflow, and input capture
Figures 12.1 and 12.2 show block diagrams of 8-bit timers.
An input capture function is added to TMR_X.
TIMH261A_000120020900
Rev. 3.00, 03/04, page 305 of 830
External clock
TMCI0
TMCI1
Internal clock
TMR_0
φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024
TMR_1
φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048
Clock 1
Clock 0
Compare match A1
Compare match A0
Overflow 1
Overflow 0
TMO0
TMRI0
TCORA_0
TCORA_1
Comparator A_0
Comparator A_1
TCNT_0
TCNT_1
Clear 0
Clear 1
Control logic
TMO1
TMRI1
Compare match B1
Compare match B0
Comparator B_0
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
[Legend]
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 12.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)
Rev. 3.00, 03/04, page 306 of 830
Internal bus
Select clock
External clock
TMCIY
Internal clock
TMR_X
φ, φ/2, φ/4
TMCIX
TMR_Y
φ/4, φ/256, φ/2048
Clock X
Clock Y
Select clock
Compare match AX
Compare match AY
Overflow X
Overflow Y
TCORA_Y
TCORA1_X
Comparator A_Y
Comparator A_X
TCNT_Y
TCNT_X
Clear Y
Compare match BX
Compare match BY
TMOY
TMRIY
Control logic
TMOX
TMRIX
Comparator B_Y
Comparator B_X
TCORB_Y
TCORB_X
Input capture
Internal bus
Clear X
TICRR
TICRF
TICR
Compare match C
Comparator C
TCORC
TCOR_Y
TCSR_X
TCR_Y
TCR_X
TISR
Interrupt signals
CMIAX
CMIBX
OVIX
CMIAY
CMIBY
OVIY
ICIX
[Legend]
TCORA_Y:
TCORB_Y:
TCNT_Y:
TCSR_Y:
TCR_Y:
TISR:
Time constant register A_Y
Time constant register B_Y
Timer counter_Y
Timer control / status register_Y
Timer control register_Y
Timer input select register
TCORA_X:
TCORB_X:
TCNT_X:
TCSR_X:
TCR_X:
TICR:
TCORC:
TICRR:
TICRF:
Time constant register A_X
Time constant register B_X
Timer counter_X
Timer control / status register_X
Timer control register_X
Input capture register
Tme constant registerC
Input capture register R
Input capture register F
Figure 12.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
Rev. 3.00, 03/04, page 307 of 830
12.2
Input/Output Pins
Table 12.1 summarizes the input and output pins of the TMR.
Table 12.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
TMR_0
Timer output
TMO0
Output
Output controlled by compare-match
Timer clock/reset
input
TMI0/ExTMI0
Input
External clock input (TMCI0)/external
reset input (TMRI0) for the counter
Timer output
TMO1
Output
Output controlled by compare-match
Timer clock/reset
input
TMI1/ExTMI1
Input
External clock input (TMCI1)/external
reset input (TMRI1) for the counter
Timer output
TMOY
Output
Output controlled by compare-match
Timer clock/reset
input
TMIY/ExTMIY
Input
External clock input (TMCIY)/external
reset input (TMRIY) for the counter
Timer output
TMOX
Output
Output controlled by compare-match
Timer clock/reset
input
TMIX/ExTMIX
Input
External clock input (TMCIX)/external
reset input (TMRIX) for the counter
TMR_1
TMR_Y
TMR_X
Rev. 3.00, 03/04, page 308 of 830
12.3
Register Descriptions
The TMR has the following registers for each channel. For details on the serial timer control
register, see section 3.2.3, Serial Timer Control Register (STCR).
• Timer counter (TCNT)
• Time constant register A (TCORA)
• Time constant register B (TCORB)
• Timer control register (TCR)
• Timer control/status register (TCSR)
• Input capture register (TICR)*1
• Time constant register C (TCORC)*1
• Input capture register R (TICRR)*1
• Input capture register F (TICRF)*1
• Timer input select register (TISR)*2
• Timer connection register I (TCONRI)*1
• Timer connection register S (TCONRS)*1
Notes:
Some of the registers of TMR_X and TMR_Y use the same address. The registers can
be switched by the TMRX/Y bit in TCONRS.
1. Only for the TMR_X
2. Only for the TMR_Y
12.3.1
Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the
CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1
and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in
TCSR is set to 1. TCNT is initialized to H'00.
TCNT_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 1. TCNT_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y
bit in TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11,
Timer Connection Register S (TCONRS).
Rev. 3.00, 03/04, page 309 of 830
12.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register, so they can be accessed together by word access. TCORA is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA)
in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA
write cycle. The timer output from the TMO pin can be freely controlled by these compare-match
A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to
H'FF.
TCORA_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 1. TCORA_X can be accessed when the KINWUE bit in SYSCR is 0 and the
TMRX/Y bit in TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section
12.3.11, Timer Connection Register S (TCONRS).
12.3.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_ comprise a single 16-bit
register, so they can be accessed together by word access. TCORB is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB)
in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB
write cycle. The timer output from the TMO pin can be freely controlled by these compare-match
B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to
H'FF.
TCORB_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 1. TCORB_X can be accessed when the KINWUE bit in SYSCR is 0 and the
TMRX/Y bit in TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section
12.3.11, Timer Connection Register S (TCONRS).
Rev. 3.00, 03/04, page 310 of 830
12.3.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS
is 1. TCR_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11, Timer
Connection Register S (TCONRS).
Bit
Bit Name Initial Value R/W Description
7
CMIEB
0
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
6
CMIEA
0
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
5
OVIE
0
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
4
3
CCLR1
CCLR0
0
0
R/W Counter Clear 1 and 0
R/W These bits select the method by which the timer
counter is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
2 to 0
CKS2 to
CKS0
All 0
R/W Clock Select 2 to 0
These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
STCR. For details, see table 12.2.
Rev. 3.00, 03/04, page 311 of 830
Table 12.2 Clock Input to TCNT and Count Condition
TCR
STCR
Channel
CKS2
CKS1
CKS0
ICKS1
ICKS0
Description
TMR_0
0
0
0


Disables clock input
0
0
1

0
Increments at falling edge of internal
clock φ/8
0
0
1

1
Increments at falling edge of internal
clock φ/2
0
1
0

0
Increments at falling edge of internal
clock φ/64
0
1
0

1
Increments at falling edge of internal
clock φ/32
0
1
1

0
Increments at falling edge of internal
clock φ/1024
0
1
1

1
Increments at falling edge of internal
clock φ/256
1
0
0


Increments at overflow signal from
TCNT_1*
0
0
0


Disables clock input
0
0
1
0

Increments at falling edge of internal
clock φ/8
0
0
1
1

Increments at falling edge of internal
clock φ/2
0
1
0
0

Increments at falling edge of internal
clock φ/64
0
1
0
1

Increments at falling edge of internal
clock φ/128
0
1
1
0

Increments at falling edge of internal
clock φ/1024
0
1
1
1

Increments at falling edge of internal
clock φ/2048
1
0
0


Increments at compare-match A from
TCNT_0*
0
0
0


Disables clock input
0
0
1


Increments at falling edge of internal
clock φ/4
0
1
0


Increments at falling edge of internal
clock φ/256
TMR_1
TMR_Y
Rev. 3.00, 03/04, page 312 of 830
Table 12.2 Clock Input to TCNT and Count Condition (cont)
TCR
STCR
Channel
CKS2
CKS1
CKS0
ICKS1
ICKS0
Description
TMR_Y
0
1
1


Increments at falling edge of internal
clock φ/2048
1
0
0


Setting prohibited
0
0
0


Disables clock input
0
0
1


Increments at falling edge of internal
clock φ
0
1
0


Increments at falling edge of internal
clock φ/2
0
1
1


Increments at falling edge of internal
clock φ/4
TMR_X
Common
Note:
*
1
0
0


Setting prohibited
1
0
1


Increments at rising edge of external
clock
1
1
0


Increments at falling edge of external
clock
1
1
1


Increments at both rising and falling
edges of external clock.
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should therefore be
avoided.
Rev. 3.00, 03/04, page 313 of 830
12.3.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. About the TCSR_Y and
TCSR_X accesses see section 3.2.2, System Control Register (SYSCR).
• TCSR_0
Bit
Bit Name Initial Value R/W
7
CMFB
0
Description
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H′FF to H′00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ADTE
0
R/W
A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A
are disabled
1: A/D converter start requests by compare-match A
are enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits specify how the TMO0 pin output level is
to be changed by compare-match B of TCORB_0
and TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Rev. 3.00, 03/04, page 314 of 830
Bit
Bit Name Initial Value R/W
Description
1
0
OS1
OS0
Output Select 1 and 0
0
0
R/W
R/W
These bits specify how the TMO0 pin output level is
to be changed by compare-match A of TCORA_0
and TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
• TCSR_1
Bit
Bit Name Initial Value R/W
7
CMFB
0
Description
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_1 and TCORB_1 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_1 and TCORA_1 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_1 overflows from H′FF to H′00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 3.00, 03/04, page 315 of 830
Bit
Bit Name Initial Value R/W
Description
3
2
OS3
OS2
Output Select 3 and 2
0
0
R/W
R/W
These bits specify how the TMO1 pin output level is
to be changed by compare-match B of TCORB_1
and TCNT_1.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits specify how the TMO1 pin output level is
to be changed by compare-match A of TCORA_1
and TCNT_1.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
• TCSR_Y
This register can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 1.
Bit
Bit Name Initial Value R/W
7
CMFB
0
Description
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_Y and TCORB_Y match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_Y and TCORA_Y match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
Rev. 3.00, 03/04, page 316 of 830
Bit
Bit Name Initial Value R/W
5
OVF
0
Description
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_Y overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ICIE
0
R/W
Input Capture Interrupt Enable
[Setting condition]
Enables or disables the ICF interrupt request (ICIX)
when the ICF bit in TCSR_X is set to 1.
0: ICF interrupt request (ICIX) is disabled
1: ICF interrupt request (ICIX) is enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits specify how the TMOY pin output level is
to be changed by compare-match B of TCORB_Y
and TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits specify how the TMOY pin output level is
to be changed by compare-match A of TCORA_Y
and TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Table: *
Only 0 can be written, for flag clearing.
Rev. 3.00, 03/04, page 317 of 830
• TCSR_X
This register can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0.
Bit
Bit Name Initial Value R/W
7
CMFB
0
Description
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_X and TCORB_X match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_X and TCORA_X match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_X overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ICF
0
R/(W)* Input Capture Flag
[Setting condition]
When a rising edge and falling edge is detected in
the external reset signal in that order.
[Clearing condition]
Read ICF when ICF = 1, then write 0 in ICF
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits specify how the TMOX pin output level is
to be changed by compare-match B of TCORB_X
and TCNT_X.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Rev. 3.00, 03/04, page 318 of 830
Bit
Bit Name Initial Value R/W
Description
1
0
OS1
OS0
Output Select 1 and 0
0
0
R/W
R/W
These bits specify how the TMOX pin output level is
to be changed by compare-match A of TCORA_X
and TCNT_X.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note:
12.3.6
*
Only 0 can be written, for flag clearing.
Input Capture Register (TICR)
TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the
external reset input. TICR cannot be directly accessed by the CPU.
12.3.7
Time Constant Register C (TCORC)
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always
compared with TCNT. When a match is detected, a compare-match C signal is generated.
However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of
TICR is disabled. TCORC is initialized to H'FF.
12.3.8
Input Capture Registers R and F (TICRR and TICRF)
TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the
contents of TCNT are transferred at the rising edge and falling edge of the external reset input in
that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are
initialized to H'00.
TICRR and TICRF can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0. See section 3.2.2, System Control Register (SYSCR).
Rev. 3.00, 03/04, page 319 of 830
12.3.9
Timer Input Select Register (TISR)
TISR selects a signal source of external clock/reset input for the counter.
Bit
Bit Name Initial Value R/W
Description
7 to 1

Reserved
All 1
R/W
The initial values should not be modified.
0
IS
0
R/W
Input Select
Selects TMIY or ExTMIY as the signal source of
external clock/reset input for the TMR_Y counter.
When external reset input is selected for the CCLR0
and CCLR1 in TCR_Y or external clock is selected
for the CKS2 to CKS0 in TCR_Y, set this bit to1.
0: TMIY or ExTMIY (TMCIY/TMRIY) is not selected
1: TMIY or ExTMIY (TMCIY/TMRIY) is selected
12.3.10 Timer Connection Register I (TCONRI)
TCONRI controls TMR_X input capture.
Bit
Bit Name
Initial Value
R/W
Description
7 to 5

All 0
R/W
Reserved
The initial values should not be modified.
4
ICST
0
R/W
Input Capture Start Bit
TMR_X has input capture registers (TICR,
TICRR, and TICRF). TICRR and TICRF can
measure the width of a pulse by means of a
single capture operation under the control of the
ICST bit. When a rising edge followed by a falling
edge is detected on TMRIX after the ICST bit is
set to 1, the contents of TCNT at those points are
captured into TICRR and TICRF, respectively,
and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
3 to 0

All 0
R/W
Reserved
The initial values should not be modified.
Rev. 3.00, 03/04, page 320 of 830
12.3.11 Timer Connection Register S (TCONRS)
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit
Bit Name
Initial Value
R/W
Description
7
TMRX/Y
0
R/W
TMR_X/TMR_Y Access Select
For details, see table 12.3.
0: The TMR_X registers are accessed at
addresses H'FFFFF0 to H'FFFFF5
1: The TMR_Y registers are accessed at
addresses H'FFFFF0 to H'FFFFF5
6 to 0
All 0
R/W
Reserved
The initial values should not be modified.
Table 12.3 Registers Accessible by TMR_X/TMR_Y
TMRX/Y
H'FFFFF0 H'FFFFF1 H'FFFFF2 H'FFFFF3 H'FFFFF4 H'FFFFF5 H'FFFFF6 H'FFFFF7
0
TMR_X
1
TMR_X
TMR_X
TMR_X
TMR_X
TMR_X
TMR_X
TCORA_X TCORB_X
TCR_X
TCSR_X
TICRR
TICRF
TCNT_X
TCORC
TMR_Y
TMR_Y
TMR_Y
TMR_Y
TMR_Y
TMR_Y
TCR_Y
TCSR_Y
TCORA_Y TCORB_Y TCNT_Y
TMR_X
TISR
Rev. 3.00, 03/04, page 321 of 830
12.4
Operation
12.4.1
Pulse Output
Figure 12.3 shows an example for outputting an arbitrary duty pulse.
1. Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1in TCR so that TCNT is cleared according
to the compare match of TCORA.
2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match
of TCORA and 0 is output according to the compare match of TCORB.
According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width
can be output without the intervention of software.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.3 Pulse Output Example
Rev. 3.00, 03/04, page 322 of 830
12.5
Operation Timing
12.5.1
TCNT Count Timing
Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the
TCNT count timing with an external clock source. The pulse width of the external clock signal
must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both
edges. The counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.4 Count Timing for Internal Clock Input
φ
External clock
input pin
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.5 Count Timing for External Clock Input
12.5.2
Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 12.6
shows the timing of CMF flag setting.
Rev. 3.00, 03/04, page 323 of 830
φ
TCNT
N
TCOR
N
N+1
Compare-match
signal
CMF
Figure 12.6 Timing of CMF Setting at Compare-Match
12.5.3
Timing of Timer Output at Compare-Match
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 12.7 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
φ
Compare-match A
signal
Timer output pin
Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal
12.5.4
Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
N
TCNT
H'00
Figure 12.8 Timing of Counter Clear by Compare-Match
Rev. 3.00, 03/04, page 324 of 830
12.5.5
TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.9 shows the timing of clearing the counter by an external reset input.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.9 Timing of Counter Clear by External Reset Input
12.5.6
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
12.10 shows the timing of OVF flag setting.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.10 Timing of OVF Flag Setting
Rev. 3.00, 03/04, page 325 of 830
12.6
TMR_0 and TMR_1 Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected.
12.6.1
16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits.
• Setting of compare-match flags
 The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
• Counter clear specification
 If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when
counter clear by the TMI0 pin has been set.
 The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
be cleared independently.
• Pin output
 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with
the 16-bit compare-match conditions.
 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with
the lower 8-bit compare-match conditions.
12.6.2
Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B′100, TCNT_1 counts the occurrence of compare-match
A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the
CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for each channel.
Rev. 3.00, 03/04, page 326 of 830
12.7
Input Capture Operation
TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be
measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X
input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X
at that time is transferred to both TICRR and TICRF.
Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture
operation.
φ
TMRIX
Input capture
signal
TCNT_X
n
TICRR
M
TICRF
m
n+1
n
N
N+1
n
m
N
Figure 12.11 Timing of Input Capture Operation
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock (φ) cycle. Figure 12.12 shows the timing of this operation.
Rev. 3.00, 03/04, page 327 of 830
TICRR, TICRF read cycle
T1
T2
φ
TMRIX
Input capture
signal
Figure 12.12 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read)
Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is
switched according to the setting of the ICST bits in TCONR1. Input capture signal selections are
shown in table 12.4.
Table 12.4 Input Capture Signal Selection
TCONRI
Bit 4
ICST
Description
0
Input capture function not used
1
TMIX pin input selection
Rev. 3.00, 03/04, page 328 of 830
12.8
Interrupt Sources
TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI.
TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX.
Table 12.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or
disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to
the interrupt controller for each interrupt.
The CMIA and CMIB interrupts can be used as DTC activation interrupt sources.
Table 12.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
Interrupt
Priority
TMR_X
CMIAX
TCORA_X compare-match
CMFA
Possible
High
TMR_0
TMR_1
TMR_Y
CMIBX
TCORB_X compare-match
CMFB
Possible
OVIX
TCNT_X overflow
OVF
Not possible
ICIX
Input capture
ICF
Not possible
CMIA0
TCORA_0 compare-match
CMFA
Possible
CMIB0
TCORB_0 compare-match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
CMIA1
TCORA_1 compare-match
CMFA
Possible
CMIB1
TCORB_1 compare-match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
CMIAY
TCORA_Y compare-match
CMFA
Possible
CMIBY
TCORB_Y compare-match
CMFB
Possible
OVIY
TCNT_Y overflow
OVF
Not possible
Low
Rev. 3.00, 03/04, page 329 of 830
12.9
Usage Notes
12.9.1
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in
figure 12.13, the counter clear takes priority and the write is not performed.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.13 Conflict between TCNT Write and Counter Clear
Rev. 3.00, 03/04, page 330 of 830
12.9.2
Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure
12.14, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.14 Conflict between TCNT Write and Increment
Rev. 3.00, 03/04, page 331 of 830
12.9.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.15, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input
capture conflicts with a compare-match in the same way as with a write to TCORC. In this case
also, the input capture takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare-match signal
Disabled
Figure 12.15 Conflict between TCOR Write and Compare-Match
Rev. 3.00, 03/04, page 332 of 830
12.9.4
Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 12.6.
Table 12.6 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
12.9.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.7 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 12.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.
Table 12.7 Switching of Internal Clocks and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Clock switching from low
1
to low level*
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
CKS bit rewrite
Rev. 3.00, 03/04, page 333 of 830
Table 12.7 Switching of Internal Clocks and TCNT Operation (cont)
No.
2
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Clock switching from low
2
to high level∗
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
3
Clock switching from high
to low level∗3
Clock before
switchover
Clock after
switchover
*4
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
4
Clock switching from high
to high level
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
Notes: 1.
2.
3.
4.
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Rev. 3.00, 03/04, page 334 of 830
12.9.6
Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating.
Simultaneous setting of these two modes should therefore be avoided.
Rev. 3.00, 03/04, page 335 of 830
Rev. 3.00, 03/04, page 336 of 830
Section 13 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing
to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset
signal or an internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 are shown in figure 13.1.
13.1
Features
• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
• If the counter overflows, an internal reset or an internal NMI interrupt is generated.
• When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
Internal Timer Mode:
•
If the counter overflows, an internal timer interrupt (WOVI) is generated.
WDT0102A_000120020900
Rev. 3.00, 03/04, page 337 of 830
Internal NMI
(Interrupt request signal*2)
Interrupt
control
Overflow
Clock
Clock
selection
Reset
control
RESO signal*1
Internal reset signal*1
TCNT_0
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
Internal bus
WOVI0
(Interrupt request signal)
TCSR_0
Bus
interface
Module bus
WDT_0
Internal NMI
(Interrupt request signal*2)
RESO signal*1
Interrupt
control
Overflow
Clock
Clock
selection
Reset
control
Internal reset signal*1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
TCNT_1
TCSR_1
Module bus
Bus
interface
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Internal bus
WOVI1
(Interrupt request signal)
WDT_1
[Legend]
TCSR_0:
TCNT_0:
TCSR_1:
TCNT_1:
Timer control/status register_0
Timer counter_0
Timer control/status register_1
Timer counter_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is
generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal
first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Figure 13.1 Block Diagram of WDT
Rev. 3.00, 03/04, page 338 of 830
13.2
Input/Output Pins
The WDT has the pins listed in table 13.1.
Table 13.1 Pin Configuration
Name
Symbol
I/O
Function
Reset output pin
RESO
Output
Outputs the counter overflow signal in
watchdog timer mode
Input
Inputs the clock pulses to the WDT_1
prescaler counter
External sub-clock input EXCL
pin
Rev. 3.00, 03/04, page 339 of 830
13.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 13.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
13.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared
to 0.
13.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Bit
Bit Name Initial Value R/W
7
OVF
0
Description
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
[Clearing conditions]
6
WT/IT
0
R/W
•
When TCSR is read when OVF = 1, then 0 is written
to OVF
•
When 0 is written to TME
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
Rev. 3.00, 03/04, page 340 of 830
Bit
Bit Name Initial Value R/W
Description
5
TME
Timer Enable
0
R/W
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4

0
R/W
Reserved
The initial value should not be changed.
3
RST/NMI 0
R/W
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
2 to 0 CKS2 to
CKS0
All 0
R/W
Clock Select 2 to 0
Select the clock source to be input to TCNT. The
overflow frequency for φ = 33 MHz is enclosed in
parentheses.
000: φ/2 (frequency: 15.5 µs)
001: φ/64 (frequency: 496.5 µs)
010: φ/128 (frequency: 993.0 µs)
011: φ/512 (frequency: 4.0 ms)
100: φ/2048 (frequency: 15.9 ms)
101: φ/8192 (frequency: 63.6 ms)
110: φ/32768 (frequency: 254.2 ms)
111: φ/131072 (frequency: 1.02 s)
Note:
*
Only 0 can be written, to clear the flag.
Rev. 3.00, 03/04, page 341 of 830
• TCSR_1
Bit
7
Bit Name Initial Value R/W
OVF
0
Description
1
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
[Clearing conditions]
6
WT/IT
0
R/W
•
When TCSR is read when OVF = 1* , then 0 is
written to OVF
•
When 0 is written to TME
2
Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4
PSS
0
R/W
Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
3
RST/NMI 0
R/W
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 3.00, 03/04, page 342 of 830
Bit
Bit Name Initial Value R/W
2 to 0 CKS2 to
CKS0
All 0
R/W
Description
Clock Select 2 to 0
Select the clock source to be input to TCNT. The
overflow cycle for φ = 33 MHz and φSUB = 32.768 kHz
is enclosed in parentheses.
When PSS = 0:
000: φ/2 (frequency: 15.5 µs)
001: φ/64 (frequency: 496.5 µs)
010: φ/128 (frequency: 993.0 µs)
011: φ/512 (frequency: 4.0 ms)
100: φ/2048 (frequency: 15.9 ms)
101: φ/8192 (frequency: 63.6 ms)
110: φ/32768 (frequency: 254.2 ms)
111: φ/131072 (frequency: 1.02 s)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Rev. 3.00, 03/04, page 343 of 830
13.4
Operation
13.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
RESO pin for 132 states, as shown in figure 13.2. If the RST/NMI bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin
remains high.
An internal reset request from the watchdog timer and a reset input from the RES pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
Write H'00 to
TCNT
OVF = 1*
WT/IT = 1 Write H'00 to
TME = 1 TCNT
Internal reset signal
518 system clocks
WT/IT:
TME:
OVF:
Timer mode select bit
Timer enable bit
Overflow flag
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
Figure 13.2 Watchdog Timer Mode (RST/NMI = 1) Operation
Rev. 3.00, 03/04, page 344 of 830
13.4.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows, as shown in figure 13.3. Therefore, an interrupt can be generated at
intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is
requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 13.4.
TCNT value
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WOVI
WOVI
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI : Interval timer interrupt request occurrence
Figure 13.3 Interval Timer Mode Operation
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
Figure 13.4 OVF Flag Set Timing
Rev. 3.00, 03/04, page 345 of 830
RESO Signal Output Timing
13.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 13.5.
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
RESO signal
132 states
518 states
Internal reset
signal
Figure 13.5 Output Timing of RESO signal
Rev. 3.00, 03/04, page 346 of 830
13.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow
Table 13.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Not possible
Rev. 3.00, 03/04, page 347 of 830
13.6
Usage Notes
13.6.1
Notes on Register Access
The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more
difficult to write to. The procedures for writing to and reading from these registers are given
below.
Writing to TCNT and TCSR (Example of WDT_0):
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 13.6 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain
the value H'5A and the lower bytes must contain the write data. To write to TCSR, the higher
bytes must contain the value H'A5 and the lower bytes must contain the write data.
<TCNT write>
15
8 7
H'5A
Address : H'FFA8
0
Write data
<TCSR write>
15
Address : H'FFA8
8 7
H'A5
0
Write data
Figure 13.6 Writing to TCNT and TCSR (WDT_0)
Reading from TCNT and TCSR (Example of WDT_0):
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR
and H'FFA9 for TCNT.
Rev. 3.00, 03/04, page 348 of 830
13.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 13.7 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.7 Conflict between TCNT Write and Increment
13.6.3
Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of CKS2 to CKS0 bits.
13.6.4
Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the
operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of
PSS bit.
Rev. 3.00, 03/04, page 349 of 830
13.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is
operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
13.6.6
System Reset by RESO Signal
Inputting the RESO output signal to the RES pin of this LSI prevents the LSI from being
initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI.
To reset the entire system by the RESO signal, use the circuit as shown in figure 13.8.
This LSI
Reset input
Reset signal for entire system
RES
RESO
Figure 13.8 Sample Circuit for Resetting the System by the RESO Signal
Rev. 3.00, 03/04, page 350 of 830
Section 14 Serial Communication Interface
(SCI, IrDA, and CRC)
This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clock synchronous serial communication. Asynchronous serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function). The SCI also supports the smart card (IC
card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous
communication function.
SCI_1 can handle communication using the waveform based on the Infrared Data Association
(IrDA) standard version 1.0. SCI_0 and SCI_2 provide high-speed communication at an average
transfer rate of a specific system clock frequency. Reliable fast data transfers are secured using the
internal cyclic redundancy check (CRC) operation circuit. Since the CRC operation circuit is not
connected to the SCI, data is transferred to the circuit using the MOV instruction to be operated
there.
14.1
Features
• Choice of asynchronous or clock synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
The external clock can be selected as a transfer clock source (except for the smart card
interface).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources  transmit-end, transmit-data-empty, receive-data-full, and receive
error  that can issue requests.
The transmit-data-empty and receive-data-full interrupt sources can activate DTC.
• Module stop mode availability
SCI0022A_000120020900
Rev. 3.00, 03/04, page 351 of 830
Asynchronous Mode:
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
• Average transfer rate generator (SCI_0 and SCI_2): 460.606 kbps or 115.152 kbps selectable
at 10.667-MHz operation; 720 kbps, 460.784 kbps, 230.392 kbps, or 115.196 kbps selectable
at 16- or 24-MHz operation; 230.392 kbps or 115.196 kbps selectable at 20-MHz operation;
and 720 kbps selectable at 32-MHz operation
Clock Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
• SCI channel selectable (SCI_0 and SCI_2): When SSE0I = 1, TxD0 = high-impedance state
and SCK0 = fixed to high input; when SSE2I = 1, TxD2 = high-impedance state and SCK2 =
fixed to high input
Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception
• Data can be automatically re-transmitted on detection of a error signal during transmission
• Both direct convention and inverse convention are supported
Figure 14.1 shows a block diagram of SCI_1, and figure 14.2 shows a block diagram of SCI_0 and
SCI_2.
Rev. 3.00, 03/04, page 352 of 830
RDR
TDR
BRR
SCMR
SSR
φ
SCR
RxD1
RSR
TSR
Baud rate
generator
SMR
φ/4
φ/16
Transmission/
reception control
TxD1
Parity generation
Internal data bus
Bus interface
Module data bus
φ/64
Clock
Parity check
External clock
SCK1
[Legend]
RSR:
Receive shift register
RDR: Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
TEI
TXI
RXI
ERI
SCR:
SSR:
SCMR:
BRR:
Serial control register
Serial status register
Smart card mode register
Bit rate register
Figure 14.1 Block Diagram of SCI_1
Rev. 3.00, 03/04, page 353 of 830
RDR
TDR
SCMR
Internal data bus
Bus interface
Module data bus
BRR
SSR
φ
SCR
RxD0/
RxD2
RSR
TSR
Baud rate
generator
SMR
SEMR
TxD0/
TxD2
φ/4
φ/16
φ/64
Transmission/
reception control
Parity generation
Parity check
SSE0I/
SSE2I
Clock
TEI
TXI
RXI
ERI
C/A
CKE1
Average transfer
rate generator
SSE
External clock
SCK0/
SCK2
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
SCR:
SSR:
SCMR:
BRR:
SEMR:
Serial control register
Serial status register
Smart card mode register
Bit rate register
Serial enhanced mode register
Figure 14.2 Block Diagram of SCI_0 and SCI_2
Rev. 3.00, 03/04, page 354 of 830
14.2
Input/Output Pins
Table 14.1 shows the input/output pins for each SCI channel.
Table 14.1 Pin Configuration
Channel
Symbol*
Input/Output
Function
0
SCK0
Input/Output
Channel 0 clock input/output
1
2
Note:
*
RxD0
Input
Channel 0 receive data input
TxD0
Output
Channel 0 transmit data output
SSE0I
Input
Channel 0 stop input
SCK1
Input/Output
Channel 1 clock input/output
RxD1/IrRxD
Input
Channel 1 receive data input (normal/IrDA)
TxD1/IrTxD
Output
Channel 1 transmit data output (normal/IrDA)
SCK2
Input/Output
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
SSE2I
Input
Channel 2 stop input
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Rev. 3.00, 03/04, page 355 of 830
14.3
Register Descriptions
The SCI has the following registers for each channel. Some bits in the serial mode register (SMR),
serial status register (SSR), and serial control register (SCR) have different functions in different
modesnormal serial communication interface mode and smart card interface mode; therefore,
the bits are described separately for each mode in the corresponding register sections. . The SCI
registers are allocated to the same address. Selecting register is carried out by means of the IICE
bit in the serial timer control register (STCR).
•
•
•
•
•
•
•
•
•
•
•
Receive shift register (RSR)
Receive data register (RDR)
Transmit data register (TDR)
Transmit shift register (TSR)
Serial mode register (SMR)
Serial control register (SCR)
Serial status register (SSR)
Smart card mode register (SCMR)
Bit rate register (BRR)
Serial interface control register (SCICR)*1
Serial enhanced mode register (SEMR)*2
Notes: 1. SCICR is not available in SCI_0 or SCI_2.
2. SEMR is not available in SCI_1.
14.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one
frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly
accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can
receive the next data. Since RSR and RDR function as a double buffer in this way, continuous
receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR
for only once. RDR cannot be written to by the CPU.
Rev. 3.00, 03/04, page 356 of 830
14.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after
confirming that the TDRE bit in SSR is set to 1.
14.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
Rev. 3.00, 03/04, page 357 of 830
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial Value
R/W Description
7
C/A
0
R/W Communication Mode
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
and the MSB of TDR is not transmitted in
transmission.
In clock synchronous mode, a fixed data length of 8
bits is used.
5
PE
0
R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
4
O/E
0
R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit frame.
2
MP
0
R/W Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
Rev. 3.00, 03/04, page 358 of 830
Bit
Bit Name
Initial Value
R/W Description
1
0
CKS1
CKS0
0
0
R/W Clock Select 1 and 0
R/W These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 14.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 14.3.9, Bit Rate Register
(BRR)).
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
Bit Name
Initial Value
R/W Description
7
GM
0
R/W GSM Mode
Setting this bit to 1 allows GSM mode operation. In
GSM mode, the TEND set timing is put forward to
11.0 etu* from the start and the clock output control
function is appended. For details, see section 14.7.8,
Clock Output Control.
6
BLK
0
R/W Setting this bit to 1 allows block transfer mode
operation. For details, see section 14.7.3, Block
Transfer Mode.
5
PE
0
R/W Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
4
O/E
0
R/W Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card
interface mode, see section 14.7.2, Data Format
(Except in Block Transfer Mode).
Rev. 3.00, 03/04, page 359 of 830
Bit
Bit Name
Initial Value
R/W Description
3
2
BCP1
BCP0
0
0
R/W Basic Clock Pulse 1 and 0
R/W These bits select the number of basic clock cycles in
a 1-bit data transfer time in smart card interface
mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 14.7.4, Receive Data
Sampling Timing and Reception Margin. S is
described in section 14.3.9, Bit Rate Register (BRR).
1
0
CKS1
CKS0
0
0
R/W Clock Select 1 and 0
R/W These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 14.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 14.3.9, Bit Rate Register
(BRR)).
Note:
*
etu: Element Time Unit (time taken to transfer one bit)
Rev. 3.00, 03/04, page 360 of 830
14.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, see section
14.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card
interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial Value
R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, see
section 14.5, Multiprocessor Communication
Function.
2
TEIE
0
R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Rev. 3.00, 03/04, page 361 of 830
Bit
Bit Name
Initial Value
R/W Description
1
0
CKE1
CKE0
0
0
R/W Clock Enable 1 and 0
R/W These bits select the clock source and SCK pin
function.
Asynchronous mode:
00: Internal clock
(SCK pin functions as I/O port.)
01: Internal clock
(Outputs a clock of the same frequency as the bit
rate from the SCK pin.)
1*: External clock
(Inputs a clock with a frequency 16 times the bit
rate from the SCK pin.)
Clock synchronous mode:
0*: Internal clock (SCK pin functions as clock output.)
1*: External clock (SCK pin functions as clock input.)
[Legend]
*:
Don’t care
Rev. 3.00, 03/04, page 362 of 830
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
Bit Name
Initial Value
R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1,a TXI interrupt request is
enabled.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
2
TEIE
0
R/W Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
1
0
CKE1
CKE0
0
0
R/W Clock Enable 1 and 0
R/W These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 14.7.8, Clock Output Control.
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1*: Reserved
When GM in SMR = 1
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output
[Legend]
*:
Don’t care.
Rev. 3.00, 03/04, page 363 of 830
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and
TDR is ready for data write
[Clearing conditions]
6
RDRF
0
•
When 0 is written to TDRE after reading TDRE =
1
•
When a TXI interrupt request is issued allowing
DTC to write data to TDR
R/(W)* Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF
=1
•
When an RXI interrupt request is issued allowing
DTC to read data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared to
0.
Rev. 3.00, 03/04, page 364 of 830
Bit
Bit Name
Initial Value
R/W
Description
5
ORER
0
R/(W)* Overrun Error
[Setting condition]
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4
FER
0
R/(W)* Framing Error
[Setting condition]
When the stop bit is 0
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading TDRE =
1
•
When a TXI interrupt request is issued allowing
DTC to write data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
frame. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit frame.
Note:
*
Only 0 can be written, to clear the flag.
Rev. 3.00, 03/04, page 365 of 830
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR, and
TDR can be written to.
[Clearing conditions]
6
RDRF
0
•
When 0 is written to TDRE after reading TDRE =
1
•
When a TXI interrupt request is issued allowing
DTC to write data to TDR
R/(W)*1 Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF
=1
•
When an RXI interrupt request is issued
allowing DTC to read data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0.
5
ORER
0
R/(W)*1 Overrun Error
[Setting condition]
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4
ERS
0
1
R/(W)* Error Signal Status
[Setting condition]
When a low error signal is sampled
[Clearing condition]
When 0 is written to ERS after reading ERS = 1
Rev. 3.00, 03/04, page 366 of 830
Bit
3
Bit Name
PER
Initial Value
0
R/W
Description
1
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
TEND is set to 1 when the receiving end
acknowledges no error signal and the next transmit
data is ready to be transferred to TDR.
[Setting conditions]
•
When both TE in SCR and ERS are 0
•
When ERS = 0 and TDRE = 1 after a specified
time passed after the start of 1-byte data
transfer. The set timing depends on the register
setting as follows.
2
When GM = 0 and BLK = 0, 2.5 etu* after
transmission start
When GM = 0 and BLK = 1, 1.5 etu*2 after
transmission start
2
When GM = 1 and BLK = 0, 1.0 etu* after
transmission start
2
When GM = 1 and BLK = 1, 1.0 etu* after
transmission start
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading
TDRE = 1
•
When a TXI interrupt request is issued allowing
DTC to write the next data to TDR
Multiprocessor Bit
Not used in smart card interface mode.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Notes: 1. Only 0 can be written, to clear the flag.
2. etu: Element Time Unit (time taken to transfer one bit)
Rev. 3.00, 03/04, page 367 of 830
14.3.8
Smart Card Mode Register (SCMR)
SCMR selects smart card interface mode and its format.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4

All 1
R
Reserved
These bits are always read as 1 and cannot be
modified.
3
SDIR
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: TDR contents are transmitted with LSB-first.
Stores receive data as LSB first in RDR.
1: TDR contents are transmitted with MSB-first.
Stores receive data as MSB first in RDR.
The SDIR bit is valid only when the 8-bit data format
is used for transmission/reception; when the 7-bit
data format is used, data is always
transmitted/received with LSB-first.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit.
When the parity bit is inverted, invert the O/E bit in
SMR.
0: TDR contents are transmitted as they are.
Receive data is stored as it is in RDR.
1: TDR contents are inverted before being
transmitted. Receive data is stored in inverted
form in RDR.
1

1
R
Reserved
This bit is always read as 1 and cannot be modified.
0
SMIF
0
R/W
Smart Card Interface Mode Select
When this bit is set to 1, smart card interface mode
is selected.
0: Normal asynchronous or clock synchronous
mode
1: Smart card interface mode
Rev. 3.00, 03/04, page 368 of 830
14.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clock synchronous mode, and smart card interface mode. The initial value of BRR is H′FF, and it
can be read from or written to by the CPU at all times.
Table 14.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Bit Rate
Error
Asynchronous mode
φ × 106
B=
64 × 2
Clock synchronous mode
8×2
– 1 } × 100
2n – 1
× (N + 1)

2n – 1
Smart card interface mode
× (N + 1)
φ × 106
B=
S×2
[Legend]
B:
N:
φ:
n and S:
B × 64 × 2
× (N + 1)
φ × 106
B=
φ × 106
Error (%) = {
2n – 1
2n + 1
φ × 106
Error (%) = {
B×S×2
× (N + 1)
2n + 1
–1 } × 100
× (N + 1)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate settable for each frequency. Table 14.6 and 14.8 show sample N settings in
BRR in clock synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin. Tables 14.5
and 14.7 show the maximum bit rates with external clock input.
Rev. 3.00, 03/04, page 369 of 830
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
5
6
6.144
Bit Rate
(bit/s) n
N
Error
(%)
n
N
Error
(%)
n
N
110
2
88
–0.25
2
106 –0.44
2
150
2
64
0.16
2
77
0.16
300
1
129 0.16
1
600
1
64
0.16
1200
0
129 0.16
2400
0
64
4800
0
9600
7.3728
Error
(%)
8
n
N
Error
(%)
n
N
108 0.08
2
130 –0.07
2
141 0.03
2
79
0.00
2
95
0.00
2
103 0.16
155 0.16
1
159 0.00
1
191 0.00
1
207 0.16
1
77
0.16
1
79
0.00
1
95
0.00
1
103 0.16
0
155 0.16
0
159 0.00
0
191 0.00
0
207 0.16
0.16
0
77
0.16
0
79
0.00
0
95
0.00
0
103 0.16
32
–1.36
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
0
15
1.73
0
19
–2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
7
1.73
0
9
–2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
4
0.00
0
5
0.00
0
5
2.40
 

0
7
0.00
38400
0
3
1.73
0
4
–2.34
0
4
0.00
0
0.00
 
5
Error
(%)

Operating Frequency φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bit/s) n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
[Legend]
:
Can be set, but there will be a degree of error.
Note: * Make the settings so that the error does not exceed 1%.
Rev. 3.00, 03/04, page 370 of 830
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
14
14.7456
16
17.2032
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
248
–0.17
3
64
0.70
3
70
0.03
3
75
0.48
150
2
181
0.16
2
191
0.00
2
207
0.16
2
223
0.00
300
2
90
0.16
2
95
0.00
2
103
0.16
2
111
0.00
600
1
181
0.16
1
191
0.00
1
207
0.16
1
223
0.00
1200
1
90
0.16
1
95
0.00
1
103
0.16
1
111
0.00
2400
0
181
0.16
0
191
0.00
0
207
0.16
0
223
0.00
4800
0
90
0.16
0
95
0.00
0
103
0.16
0
111
0.00
9600
0
45
–0.93
0
47
0.00
0
51
0.16
0
55
0.00
19200
0
22
–0.93
0
23
0.00
0
25
0.16
0
27
0.00
31250
0
13
0.00
0
14
–1.70
0
15
0.00
0
16
1.20
38400



0
11
0.00
0
12
0.16
0
16
0.00
Operating Frequency φ (MHz)
18
19.6608
20
25
33
Bit Rate
(bit/s)
n
N
Error
(%)
n N
Error
(%)
n N
Error
(%)
n N
Error
(%)
110
3
79
–0.12
3
86
0.31
3
88
–0.25
3
110 –0.02
3
145 0.33
150
2
233 0.16
2
255 0.00
3
64
0.16
3
80
3
106 0.39
300
2
116 0.16
2
127 0.00
2
129 0.16
2
162 0.15
2
214 –0.07
600
1
233 0.16
1
255 0.00
2
64
0.16
2
80
2
106 0.39
1200
1
116 0.16
1
127 0.00
1
129 0.16
1
162 0.15
1
214 –0.07
2400
0
233 0.16
0
255 0.00
1
64
0.16
1
80
1
106 0.39
4800
0
116 0.16
0
127 0.00
0
129 0.16
0
162 0.15
0
214 –0.07
9600
0
58
–0.69
0
63
0.00
0
64
0.16
0
80
–0.47
0
106 0.39
19200
0
28
1.02
0
31
0.00
0
32
–1.36
0
40
–0.76
0
53
–0.54
31250
0
17
0.00
0
19
–1.70
0
19
0.00
0
24
0.00
0
32
0.00
38400
0
14
–2.34
0
15
0.00
0
15
1.73
0
19
1.73
0
26
–0.54
–0.47
–0.47
–0.47
n N
Error
(%)
[Legend]
:
Can be set, but there will be a degree of error.
Note: * Make the settings so that the error does not exceed 1%.
Rev. 3.00, 03/04, page 371 of 830
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum
Bit Rate
(bit/s)
n
N
5
156250
0
0
φ (MHz)
Maximum
Bit Rate
(bit/s)
n
N
14
437500
0
0
6
187500
0
0
14.7456
460800
0
0
6.144
192000
0
0
16
500000
0
0
7.3728
230400
0
0
17.2032
537600
0
0
8
250000
0
0
18
562500
0
0
9.8304
307200
0
0
19.6608
614400
0
0
10
312500
0
0
20
625000
0
0
12
375000
0
0
25
781250
0
0
12.288
384000
0
0
33
1031250
0
0
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input Maximum Bit
Clock (MHz) Rate (bit/s)
5
1.2500
78125
14
3.5000
218750
6
15.000
93750
14.7456
3.6864
230400
6.144
1.5360
96000
16
4.0000
250000
7.3728
1.8432
115200
17.2032
4.3008
268800
8
2.0000
125000
18
4.5000
281250
9.8304
2.4576
153600
19.6608
4.9152
307200
10
2.5000
156250
20
5.0000
312500
12
3.0000
187500
25
6.2500
390625
12.288
3.0720
192000
33
8.2500
515625
Rev. 3.00, 03/04, page 372 of 830
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency φ (MHz)
Bit
Rate
(bit/s)
8
10
16
n
N
n
N
n
N
250
3
124


3
249
500
2
249


3
1k
2
124


2.5k
1
199
1
5k
1
99
10k
0
25k
50k
20
24
32
n
N
n
N
n
N
124




3
249
2
249




3
124
249
2
99
2
124
2
149
2
199
1
124
1
199
1
249
2
74
2
99
199
0
249
1
99
1
124
1
149
1
199
0
79
0
99
0
159
0
199
0
239
0
179
0
39
0
49
0
79
0
99
0
119
0
159
100k
0
19
0
24
0
39
0
49
0
59
0
79
250k
0
7
0
9
0
15
0
19
0
23
0
31
500k
0
3
0
4
0
7
0
9
0
11
0
15
1M
0
1
0
3
0
4
0
5
0
7
0
1
0
0*
110
2.5M
0
0*
5M
[Legend]
: Setting prohibited.
:
Can be set, but there will be a degree of error.
*:
Continuous transfer or reception is not possible.
Table 14.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
6
1.0000
1000000.0
16
2.6667
2666666.7
8
1.3333
1333333.3
18
3.0000
3000000.0
10
1.6667
1666666.7
20
3.3333
3333333.3
12
2.0000
2000000.0
25
4.1667
4166666.7
14
2.3333
2333333.3
33
5.5000
5500000.0
Rev. 3.00, 03/04, page 373 of 830
Table 14.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372)
Operating Frequency φ (MHz)
Bit Rate
7.1424
10.00
13.00
14.2848
16.00
(bit/s)
n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
9600
0
0
0.00
0
1
30
0
1
-8.99
0
1
0.00
0
1
12.01
Operating Frequency φ (MHz)
Bit Rate
18.00
20.00
21.4272
25
33
(bit/s)
n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
9600
0
2
-15.99
0
2
-6.65
0
2
0.00
0
3
-12.49
0
4
-7.59
Table 14.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372)
φ (MHz)
Maximum Bit
Rate
(bit/s)
φ (MHz)
Maximum Bit
Rate
(bit/s)
n
n
N
N
7.1424
9600
0
0
18.00
24194
0
0
10.00
13441
0
0
20.00
26882
0
0
13.00
17473
0
0
21.4272
28800
0
0
14.2848
19200
0
0
25.00
33602
0
0
16.00
21505
0
0
33.00
44355
0
0
Rev. 3.00, 03/04, page 374 of 830
14.3.10 Serial Interface Control Register (SCICR)
SCICR controls IrDA operation of SCI_1.
Bit
Bit Name
Initial Value
R/W Description
7
IrE
0
R/W IrDA Enable
Specifies SCI_1 I/O pins for either normal SCI or IrDA.
0: TxD1/IrTxD and RxD1/IrRxD pins function as TxD1
and RxD1 pins, respectively
1: TxD1/IrTxD and RxD1/IrRxD pins function as IrTxD
and IrRxD pins, respectively
6
5
4
IrCKS2
IrCKS1
IrCKS0
0
0
0
R/W IrDA Clock Select 2 to 0
R/W These bits specify the high-level width of the clock
R/W pulse during IrTxD output pulse encoding when the
IrDA function is enabled.
000: B x 3/16 (three sixteenths of the bit rate)
001: φ/2
010: φ/4
011: φ/8
100: φ/16
101: φ/32
110: φ/64
111: φ/128
3, 2

All 0
R/W Reserved
The initial value should no be changed.
1, 0

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 3.00, 03/04, page 375 of 830
14.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2)
SEMR_0 and SEMR_2 select the SCI_0 and SCI_2 functions, respectively, and the clock source
in asynchronous mode. The basic clock is automatically specified when the average transfer rate
operation is selected.
Bit
Bit Name
Initial Value
R/W Description
7
SSE
0
R/W SCI Select Enable
Enables/disables the external pins to select the SCI
functions when the external clock is supplied in clock
synchronous mode.
0: Disables the external pins to select the SCI functions
(normal)
1: Enables the external pins to select the SCI functions
•
SCI_0
SSE0I pin input = 0 (selected state): SCI_0 operates
normally
SSE0I pin input = 1 (non-selected state): SCI_0 halts
operation
(TxD0 = high-impedance state, SCK0 = fixed to high)
•
SCI_2
SSE2I pin input = 0 (selected state): SCI_2 operates
normally
SSE2I pin input = 1 (non-selected state): SCI_2 halts
operation
(TxD2 = high-impedance state, SCK2 = fixed to high)
6, 5

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3
ABCS
0
R/W Asynchronous Mode Basic Clock Select
Specifies the basic clock for a 1-bit cycle in
asynchronous mode.
This bit is valid only in asynchronous mode (C/A bit in
SMR is 0).
0: The basic clock has a frequency 16 times the transfer
clock frequency (normal operation)
1: The basic clock has a frequency 8 times the transfer
clock frequency (double-speed operation)
Rev. 3.00, 03/04, page 376 of 830
Bit
Bit Name
Initial Value
R/W Description
4
2
1
0
ACS4
ACS2
ACS1
ACS0
0
0
0
0
R/W
R/W
R/W
R/W
Asynchronous Mode Clock Source Select
Specify the clock source and the average transfer rate
in asynchronous mode. These bits are valid only when
external clock is supplied in asynchronous mode.
0000: Normal operation with external clock input and
average transfer rate operation not used
(operated using the basic clock with a frequency
16 or 8 times the transfer clock frequency)
0001: Average transfer rate operation at 115.152 kbps
when the system clock frequency is 10.667 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
0010: Average transfer rate operation at 460.606 kbps
when the system clock frequency is 10.667 MHz
(operated using the basic clock with a frequency
8 times the transfer clock frequency)
0011: Average transfer rate operation at 720 kbps when
the system clock frequency is 32 MHz (operated
using the basic clock with a frequency 16 times
the transfer clock frequency)
0100: Reserved
0101: Average transfer rate operation at 115.196 kbps
when the system clock frequency is 16 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
0110: Average transfer rate operation at 460.784 kbps
when the system clock frequency is 16 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
0111: Average transfer rate operation at 720 kbps when
the system clock frequency is 16 MHz (operated
using the basic clock with a frequency 8 times the
transfer clock frequency)
1000: Average transfer rate operation at 115.196 kbps
when the system clock frequency is 16 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
1001: Average transfer rate operation at 230.392 kbps
when the system clock frequency is 16 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
Rev. 3.00, 03/04, page 377 of 830
Bit
Bit Name
Initial Value
R/W Description
4
2
1
0
ACS4
ACS2
ACS1
ACS0
0
0
0
0
R/W 1010: Average transfer rate operation at 115.196 kbps
R/W
when the system clock frequency is 20 MHz
R/W
(operated using the basic clock with a frequency
R/W
16 times the transfer clock frequency)
1011: Average transfer rate operation at 230.392 kbps
when the system clock frequency is 20 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
1100: Average transfer rate operation at 115.196 kbps
when the system clock frequency is 24 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
1101: Average transfer rate operation at 230.392 kbps
when the system clock frequency is 24 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
1110: Average transfer rate operation at 460.784 kbps
when the system clock frequency is 24 MHz
(operated using the basic clock with a frequency
16 times the transfer clock frequency)
1111: Average transfer rate operation at 720 kbps when
the system clock frequency is 24 MHz (operated
using the basic clock with a frequency 8 times the
transfer clock frequency)
Table 14.10 Asynchronous Mode Clock Source Select
ACS 4 ACS 2
ACS 1
ACS 0
Average
Transfer Rate
0
0
0
0
0
0
0
0
0
1
0
0
0
System Clock (φ)
Operating Clock
None
External clock input,
normal operation
Transfer rate × 16 or
Transfer rate × 8
1
115.152 kbps
10.667 MHz
Transfer rate × 16
0
460.606 kbps
10.667 MHz
Transfer rate × 8
1
1
Reserved
Reserved
Reserved
1
0
0
Reserved
Reserved
Reserved
0
1
0
1
115.196 kbps
16 MHz
Transfer rate × 16
0
1
1
0
460.784 kbps
16 MHz
Transfer rate × 16
0
1
1
1
720 kbps
16 MHz
Transfer rate × 8
1
0
0
0
115.196 kbps
16 MHz
Transfer rate × 16
1
0
0
1
230.392 kbps
16 MHz
Transfer rate × 16
1
0
1
0
115.196 kbps
20 MHz
Transfer rate × 16
Rev. 3.00, 03/04, page 378 of 830
ACS 4 ACS 2
ACS 1
ACS 0
Average
Transfer Rate
System Clock (φ)
Operating Clock
1
0
1
1
230.392 kbps
20 MHz
Transfer rate × 16
1
1
0
0
115.196 kbps
24 MHz
Transfer rate × 16
1
1
0
1
230.392 kbps
24 MHz
Transfer rate × 16
1
1
1
0
460.784 kbps
24 MHz
Transfer rate × 16
1
1
1
1
720 kbps
24 MHz
Transfer rate × 8
Rev. 3.00, 03/04, page 379 of 830
14.4
Operation in Asynchronous Mode
Figure 14.3 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the transmission line is usually held in the mark
state (high level). The SCI monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer and reception.
Idle state
(mark state)
1
Serial
data
LSB
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity
bit
Stop bit
1 bit or
none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 14.3 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 3.00, 03/04, page 380 of 830
14.4.1
Data Transfer Format
Table 14.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, see section 14.5, Multiprocessor Communication Function.
Table 14.11 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transmit/Receive Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB:
Multiprocessor bit
Rev. 3.00, 03/04, page 381 of 830
14.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse
of the basic clock, data is latched at the middle of each bit, as shown in figure 14.4. Thus the
reception margin in asynchronous mode is determined by formula (1) below.
M = } (0.5 –
1
2N
)–
D – 0.5
(1+F) – (L – 0.5) F } × 100
N
[%]
... Formula (1)
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16) } × 100
[%] = 46.875 %
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
Synchronization
sampling timing
Data sampling
timing
Figure 14.4 Receive Data Sampling Timing in Asynchronous Mode
Rev. 3.00, 03/04, page 382 of 830
D1
14.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.5.
SCK
TxD
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 14.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)
14.4.4
Serial Enhanced Mode Clock
SCI_0 and SCI_2 can be operated not only based on the clocks described in section 14.4.3, Clock,
but based on the following clocks, which are specified by the serial enhanced mode registers,
SEMR_0 and SEMR_2.
Double-Speed Operation: Operations that are usually achieved using the clock with frequency 16
times the normal bit rate can be achieved using the clock with frequency 8 times the bit rate in this
mode. That is, double transfer rate can be achieved using a single basic clock.
Double-speed operation can be specified by the ABCS bit in SEMR and is available for both clock
sources of an internal clock generated by the on-chip baud rate generator and an external clock
input at the SCK pin. However, double-speed operation cannot be specified when the average
transfer rate operation is selected.
Average Transfer Rate Operation: The SCI can be operated based on the clock with an average
transfer rate generated from the system clock instead of the external clock input at the SCK pin. In
this case, the SCK pin is fixed to input.
Average transfer rate operation can be specified by the ACS4 and ACS2 to ACS0 bits in SEMR.
Double-speed operation may be selected by clearing the ACS4 and ACS2 to ACS0 bits to 0.
Figures 14.6 and 14.7 show some examples of internal basic clock operations when average
transfer rate operation is selected.
Rev. 3.00, 03/04, page 383 of 830
Figure 14.6 Basic Clock Examples When Average Transfer Rate is Selected (1)
Rev. 3.00, 03/04, page 384 of 830
1
1
2
2
4
5
1
1
2
2
8
7
3
3
9
10 11 12
13 14
4
5
7
8
15 16
7
Average error rate = –0.043%
Average transfer rate = 3.6848 MHz/8= 460.606 kbps
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1
1 bit = Basic clock × 8*
3.6848 MHz
4 5
6
5.333 MHz
6
Average error rate = –0.043%
Average transfer rate = 1.8424 MHz/16 = 115.152 kbps
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1
1 bit = Basic clock × 16*
1.8424 MHz
4 5
6
7
Note: * 1-bit length depends on the changes in basic clock synchronization.
3.6848 MHz (average)
5.333 MHz × (38/55) =
10.667 MHz/2 = 5.333 MHz
Basic clock
6
2.667 MHz
3
3
Average transfer rate at basic clock = 460.606 kbps
1.8424 MHz (average)
2.667 MHz × (38/55) =
10.6677 MHz/4 = 2.667 MHz
Basic clock
Average transfer rate at basic clock = 115.152 kbps
When ø = 10.667 MHz
2
2
3 4
3 4
Figure 14.7 Basic Clock Examples When Average Transfer Rate is Selected (2)
Rev. 3.00, 03/04, page 385 of 830
1
1
2
2
3
3
4
5
1
1
2
2
3
3
1
1
2
2
4
5
13 14 15 16
7
8
9 10 11 12
4
5
7
5.76 MHz
4 5
6
6
8
13 14 15 16
7
Average error rate = –0%
Average transfer rate = 5.76 MHz/8 = 720 kbps
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1
Average error rate = –0.004%
8 MHz
2
3 4
5
6
7 8
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1 bit = Basic clock × 16*
7.3725 MHz
5 6 7 8
6
Average transfer rate = 7.3725 MHz/16 = 460.784 kbps
4
8 MHz
1 bit = Basic clock × 8*
3
3
1 bit = Basic clock × 16*
9 10 11 12
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1
Note: * 1-bit length depends on the changes in basic clock synchronization.
5.76 MHz (average)
8 MHz × (18/25) =
16 MHz/2 = 8 MHz
Basic clock
8
Average error rate = –0.004%
Average transfer rate at basic clock = 720 kbps
7.3725 MHz (average)
8 MHz × (47/51) =
16 MHz/2 = 8 MHz
Basic clock
7
1.8431 MHz
5 6 7 8
6
Average transfer rate = 1.8431 MHz/16 = 115.196 kbps
4
2 MHz
Average transfer rate at basic clock = 460.784 kbps
1.8431 MHz (average)
2 MHz × (47/51) =
16 MHz/8 = 2 MHz
Basic clock
Average transfer rate at basic clock = 115.196 kbps
When ø = 16 MHz
14.4.5
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 14.8. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR,
or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completion>
Figure 14.8 Sample SCI Initialization Flowchart
Rev. 3.00, 03/04, page 386 of 830
14.4.6
Serial Data Transmission (Asynchronous Mode)
Figure 14.9 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 14.10 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt service routine
TEI interrupt
request generated
1 frame
Figure 14.9 Example of Operation in Transmission in Asynchronous Mode (Example with
8-Bit Data, Parity, One Stop Bit)
Rev. 3.00, 03/04, page 387 of 830
[1]
Initialization
Start transmission
[2]
Read TDRE flag in SSR
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
[3] Serial transmission continuation
procedure:
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and clear
the TDRE flag to 0. However, the
TDRE flag is checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 14.10 Sample Serial Transmission Flowchart
Rev. 3.00, 03/04, page 388 of 830
14.4.7
Serial Data Reception (Asynchronous Mode)
Figure 14.11 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
ERI interrupt request
generated by framing
error
1 frame
Figure 14.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
One Stop Bit)
Rev. 3.00, 03/04, page 389 of 830
Table 14.12 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.12 shows a sample
flowchart for serial data reception.
Table 14.12 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
Rev. 3.00, 03/04, page 390 of 830
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing and break
detection:
[2]
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
Yes
appropriate error processing, ensure
PER ∨ FER ∨ ORER = 1
that the ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot be
No
Error processing
resumed if any of these flags are set to
1. In the case of a framing error, a
(Continued on next page)
break can be detected by reading the
value of the input port corresponding to
[4]
Read RDRF flag in SSR
the RxD pin.
Read ORER, PER, and
FER flags in SSR
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
However, the RDRF flag is cleared
automatically when the DTC is initiated
by an RXI interrupt and reads data from
RDR.
Legend
∨ : Logical add (OR)
Figure 14.12 Sample Serial Reception Flowchart (1)
Rev. 3.00, 03/04, page 391 of 830
[3]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
No
PER = 1
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 14.12 Sample Serial Reception Flowchart (2)
Rev. 3.00, 03/04, page 392 of 830
14.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle for
the specified receiving station. The multiprocessor bit is used to differentiate between the ID
transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID
transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure
14.13 shows an example of inter-processor communication using the multiprocessor format. The
transmitting station first sends the ID code of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving
station compares that data with its own ID. The station whose ID matches then receives the data
sent next. Stations whose ID does not match continue to skip data until data with a 1
multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the RDRF, FER, and
ORER status flags in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 3.00, 03/04, page 393 of 830
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
Legend
MPB: Multiprocessor bit
Figure 14.13 Example of Communication Using Multiprocessor Format (Transmission of
Data H'AA to Receiving Station A)
Rev. 3.00, 03/04, page 394 of 830
14.5.1
Multiprocessor Serial Data Transmission
Figure 14.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 14.14 Sample Multiprocessor Serial Transmission Flowchart
Rev. 3.00, 03/04, page 395 of 830
14.5.2
Multiprocessor Serial Data Reception
Figure 14.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
14.15 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data 1)
D0
D1
Stop
MPB bit
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
D0
D1
Stop
MPB bit
D7
1
1
Start
bit
0
Data (Data 2)
D0
D1
D7
Stop
MPB bit
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
ID2
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
Data 2
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 14.15 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Rev. 3.00, 03/04, page 396 of 830
Initialization
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[1]
Start reception
Set MPIE bit in SCR to 1
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[2]
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
Yes
Read receive data in RDR
No
This station’s ID?
Yes
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
[4]
value.
No
Legend
∨ : Logical add (OR)
RDRF = 1
Yes
Read receive data in RDR
No
All data received?
[5]
Error processing
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 3.00, 03/04, page 397 of 830
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 3.00, 03/04, page 398 of 830
14.6
Operation in Clock Synchronous Mode
Figure 14.17 shows the general format for clock synchronous communication. In clock
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one
falling edge of the synchronization clock to the next. In data reception, the SCI receives data in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit
is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that the next transmit data can be written during transmission or the
previous receive data can be read during reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Synchronization
clock
MSB
LSB
Bit 0
Serial data
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 14.17 Data Format in Synchronous Communication (LSB-First)
14.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1
and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock
is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one
character, and when no transfer is performed the clock is fixed high.
Rev. 3.00, 03/04, page 399 of 830
14.6.2
SCI Initialization (Clock Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 14.18. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is
set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER
flags in SSR, or RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR and
SCMR.
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. This step is not necessary
if an external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 14.18 Sample SCI Initialization Flowchart
Rev. 3.00, 03/04, page 400 of 830
14.6.3
Serial Data Transmission (Clock Synchronous Mode)
Figure 14.19 shows an example of SCI operation for transmission in clock synchronous mode. In
serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 14.20 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Transfer direction
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
TXI interrupt
request generated
TEI interrupt request
generated
1 frame
Figure 14.19 Sample SCI Transmission Operation in Clock Synchronous Mode
Rev. 3.00, 03/04, page 401 of 830
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DTC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR.
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 14.20 Sample Serial Transmission Flowchart
Rev. 3.00, 03/04, page 402 of 830
14.6.4
Serial Data Reception (Clock Synchronous Mode)
Figure 14.21 shows an example of SCI operation for reception in clock synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the receive data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RXI interrupt
request generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 14.21 Example of SCI Receive Operation in Clock Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.22 shows a sample flowchart
for serial data reception.
Rev. 3.00, 03/04, page 403 of 830
[1]
Initialization
Start reception
[2]
Read ORER flag in SSR
Yes
ORER = 1
[3]
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
However, the RDRF flag is cleared
automatically when the DTC is
initiated by a receive data full interrupt
(RXI) and reads data from RDR.
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 14.22 Sample Serial Reception Flowchart
Rev. 3.00, 03/04, page 404 of 830
14.6.5
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 14.23 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits
to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive
mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking
that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0,
simultaneously set the TE and RE bits to 1 with a single instruction.
14.6.6
SCI Selection in Serial Enhanced Mode
SCI_0 and SCI_2 provide the following capability according to the serial enhanced mode registers
(SEMR_0 and SEMR_2) settings.
If the SCI is used in clock synchronous mode with clock input, the SCI channel can be
enabled/disabled using the input at the external pins. The external pins include PA0/SSE0I
(SCI_0) and PA1/SSE2I (SCI_2); therefore, this capability is not available in modes where the
PA0 and PA1 pins are automatically set for address output.
When the SCI operation is disabled (not selected) by input at the external pins, TxD output is
fixed to the high-impedance state and SCK input is internally fixed to high. One-to-multipoint
communication is possible if the master device, which outputs SCK, controls these external pins
for chip selection. SCI selection capability is selected using the SSE bits in SEMR.
Rev. 3.00, 03/04, page 405 of 830
Initialization
[1]
[1]
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2]
SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Start transmission/reception
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3]
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
Yes
[3]
Error processing
[4]
[4]
SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
Read receive data in RDR, and
reception, before the MSB (bit 7) of
clear RDRF flag in SSR to 0
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0. Also,
No
before the MSB (bit 7) of the current
All data received?
[5]
frame is transmitted, read 1 from the
TDRE flag to confirm that writing is
Yes
possible. Then write data to TDR and
clear the TDRE flag to 0.
However, the TDRE flag is checked
Clear TE and RE bits in SCR to 0
and cleared automatically when the
DTC is initiated by a transmit data
empty interrupt (TXI) request and
<End>
writes data to TDR. Similarly, the
RDRF flag is cleared automatically
when the DTC is initiated by a receive
Note: When switching from transmit or receive operation to simultaneous
data full interrupt (RXI) and reads
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.
data from RDR.
Yes
Figure 14.23 Sample Flowchart of Simultaneous Serial Transmission and Reception
Rev. 3.00, 03/04, page 406 of 830
14.7
Smart Card Interface Description
The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification
Card) standard as an enhanced serial communication interface function. Smart card interface mode
can be selected using the appropriate register.
14.7.1
Sample Connection
Figure 14.24 shows a sample connection between the smart card and this LSI. As in the figure,
since this LSI communicates with the IC card using a single transmission line, interconnect the
TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE
and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception
allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input
the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output
port of this LSI.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Main unit of the device
to be connected
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Figure 14.24 Pin Connection for Smart Card Interface
14.7.2
Data Format (Except in Block Transfer Mode)
Figure 14.25 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
is secured as a guard time after the end of the parity bit before the start of the next frame.
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
has passed from the start bit.
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
after two or more etu.
Rev. 3.00, 03/04, page 407 of 830
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D7
Dp
Output from the transmitting station
When a parity error is generated
Ds
D0
D1
D2
D3
D4
D5
D6
DE
Output from the transmitting station
Output from
the receiving station
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 14.25 Data Formats in Normal Smart Card Interface Mode
For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z) state
Figure 14.26 Direct Convention (SDIR = SINV = O/E = 0)
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 14.26. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z) state
Figure 14.27 Inverse Convention (SDIR = SINV = O/E = 1)
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 14.27. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
Rev. 3.00, 03/04, page 408 of 830
which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
14.7.3
Block Transfer Mode
Block transfer mode is different from normal smart card interface mode in the following respects.
• If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR
is set by error detection, clear the bit before receiving the parity bit of the next frame.
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
before the start of the next frame.
• Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5
etu after transmission start.
• Although the ERS flag in block transfer mode displays the error signal status as in normal
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
14.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a basic
clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0
settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 14.28. The reception margin here is determined by the following formula.
M =  (0.5 –
1
) – (L – 0.5) F –
2N
 D – 0.5  (1 + F)  × 100 [%]
N
... Formula (1)
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1/2 x 372) x 100 [%] = 49.866%
Rev. 3.00, 03/04, page 409 of 830
372 clock cycles
186 clock
cycles
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock
Frequency is 372 Times the Bit Rate)
14.7.5
Initialization
Before starting transmitting and receiving data, initialize the SCI using the following procedure.
Initialization is also necessary before switching from transmission to reception and vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ORER, ERS, and PER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set
the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the
TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high
impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and
TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output
clock pulses.
7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval.
Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.
To switch from reception to transmission, first verify that reception has completed, and initialize
the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception
completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from
transmission to reception, first verify that transmission has completed, and initialize the SCI. At
Rev. 3.00, 03/04, page 410 of 830
the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission
completion can be verified by reading the TEND flag.
14.7.6
Serial Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data is
re-transmitted. Figure 14.29 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
re-transferred from TDR to TSR allowing automatic data retransmission.
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this
case, one frame of data is determined to have been transmitted including re-transfer, and the
TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is
set to 1. Writing transmit data to TDR starts transmission of the next data.
Figure 14.31 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DTC. In transmission, the
TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request
when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of
transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand.
The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error
occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains
as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the
specified number of bytes, including re-transmission in the case of error occurrence. However, the
ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE
bit to 1 to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable it prior to making SCI
settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
Rev. 3.00, 03/04, page 411 of 830
(n + 1) th
transfer frame
Retransfer frame
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
Transfer from TDR to TSR
Transfer from TDR to TSR
TEND
[2]
[3]
FER/ERS
[1]
[3]
Figure 14.29 Data Re-transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 14.30.
Ds
I/O data
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard time
TXI
(TEND interrupt)
12.5 etu
GM = 0
11.0 etu
GM = 1
[Legend]
Ds:
Start bit
D0 to D7:Data bits
Dp:
Parity bit
DE:
Error signal
etu:
Element Time Unit (time taken to transfer one bit)
Figure 14.30 TEND Flag Set Timings during Transmission
Rev. 3.00, 03/04, page 412 of 830
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR and clear
TDRE flag in SSR to 0
No
All data transmitted?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
End
Figure 14.31 Sample Transmission Flowchart
Rev. 3.00, 03/04, page 413 of 830
14.7.7
Serial Data Reception (Except in Block Transfer Mode)
Data reception in smart card interface mode is identical to that in normal serial communication
interface mode. Figure 14.32 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined
to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt
request is generated if the RIE bit in SCR is set.
Figure 14.33 shows a sample flowchart for reception. All the processing steps are automatically
performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1
allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates
DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is
specified as a source of DTC activate beforehand. The RDRF flag is automatically cleared to 0 at
data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set
to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be
cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number
of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is
set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read.
Note: For operations in block transfer mode, see section 14.4, Operation in Asynchronous Mode.
(n + 1) th
transfer frame
Retransfer frame
n th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[3]
[1]
[3]
PER
Figure 14.32 Data Re-transfer Operation in SCI Reception Mode
Rev. 3.00, 03/04, page 414 of 830
Start
Initialization
Start reception
ORER = 0
and PER = 0?
No
Yes
Error processing
No
RDRF = 1?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 14.33 Sample Reception Flowchart
14.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 14.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 14.34 Clock Output Fixing Timing
Rev. 3.00, 03/04, page 415 of 830
At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty ratio.
At Power-On:
To secure the appropriate clock duty ratio simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
4. Set the CKE0 bit in SCR to 1 to start clock output.
At Transition from Smart Card Interface Mode to Software Standby Mode:
1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK
pins to the values for the output fixed state in software standby mode.
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the
CKE1 bit to the value for the output fixed state in software standby mode.
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
specified level with the duty ratio retained.
5. Make the transition to software standby mode.
At Transition from Software Standby Mode to Smart Card Interface Mode:
1. Cancel software standby mode.
2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty
ratio is then generated.
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[1]
[2]
Figure 14.35 Clock Stop and Restart Procedure
Rev. 3.00, 03/04, page 416 of 830
14.8
IrDA Operation
IrDA operation can be used with SCI_1. Figure 14.36 shows an IrDA block diagram.
If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 signals for SCI_1
are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function
as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves
infrared data communication based on the system defined by the IrDA standard version 1.0.
In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate
of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not
incorporate the capability of automatic modification of the transfer rate; the transfer rate must be
modified through programming.
SCI_1
IrDA
TxD1/IrTxD
Pulse encoder
RxD1/IrRxD
Pulse decoder
TxD1
RxD1
SCICR
Figure 14.36 IrDA Block Diagram
Transmission: During transmission, the output signals from the SCI (UART frames) are
converted to IR frames using the IrDA interface (see figure 14.37).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
SCICR.
The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20
MHz, a high-level pulse width of at least 1.41 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Rev. 3.00, 03/04, page 417 of 830
UART frame
Data
Start
bit
0
1
0
1
0
0
Stop
bit
1
Transmission
1
0
1
Reception
IR frame
Data
Start
bit
0
1
Bit
cycle
0
1
0
0
Stop
bit
1
1
0
1
Pulse width is 1.6 µs to
3/16 bit cycle
Figure 14.37 IrDA Transmission and Reception
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_1.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the
minimum width allowed, the pulse is recognized as level 0.
High-Level Pulse Width Selection: Table 14.13 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the
pulse width shorter than 3/16 times the bit rate in transmission.
Rev. 3.00, 03/04, page 418 of 830
Table 14.13 IrCKS2 to IrCKS0 Bit Settings
Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row)
Operating
Frequency
2400
9600
19200
38400
57600
115200
φ (MHz)
78.13
19.53
9.77
4.88
3.26
1.63
5
011
011
011
011
011
011
6
100
100
100
100
100
100
6.144
100
100
100
100
100
100
7.3728
100
100
100
100
100
100
8
100
100
100
100
100
100
9.8304
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
25
110
110
110
110
110
110
33
110
110
110
110
110
110
Rev. 3.00, 03/04, page 419 of 830
14.9
Interrupt Sources
14.9.1
Interrupts in Normal Serial Communication Interface Mode
Table 14.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data
transfer by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 14.14 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
0
ERI0
Receive error
ORER, FER, PER
Not possible
High
RXI0
Receive data full
RDRF
Possible
TXI0
Transmit data empty
TDRE
Possible
TEI0
Transmit end
TEND
Not possible
ERI1
Receive error
ORER, FER, PER
Not possible
1
2
RXI1
Receive data full
RDRF
Possible
TXI1
Transmit data empty
TDRE
Possible
TEI1
Transmit end
TEND
Not possible
ERI2
Receive error
ORER, FER, PER
Not possible
RXI2
Receive data full
RDRF
Possible
TXI2
Transmit data empty
TDRE
Possible
TEI2
Transmit end
TEND
Not possible
Rev. 3.00, 03/04, page 420 of 830
Low
14.9.2
Interrupts in Smart Card Interface Mode
Table 14.15 shows the interrupt sources in smart card interface mode. A TEI interrupt request
cannot be used in this mode.
Table 14.15 SCI Interrupt Sources
Channel Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
0
Receive error, error
signal detection
ORER, PER, ERS
Not possible
High
1
2
ERI0
RXI0
Receive data full
RDRF
Possible
TXI0
Transmit data empty
TEND
Possible
ERI1
Receive error, error
signal detection
ORER, PER, ERS
Not possible
RXI1
Receive data full
RDRF
Possible
TXI1
Transmit data empty
TEND
Possible
ERI2
Receive error, error
signal detection
ORER, PER, ERS
Not possible
RXI2
Receive data full
RDRF
Possible
TXI2
Transmit data empty
TEND
Possible
Low
Data transmission/reception using the DTC is also possible in smart card interface mode, similar
to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously
set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request
thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC
activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer
by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and
DTC automatically transmit the specified number of bytes, including re-transmission in the case of
error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not
automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1
to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to
making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI
interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is
automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set
but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued
to the CPU instead; the error flag must be cleared.
Rev. 3.00, 03/04, page 421 of 830
14.10
Usage Notes
14.10.1
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 23, Power-Down Modes.
14.10.2
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
14.10.3 Mark State and Break Sending
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark
state (high level) or send a break during serial data transmission. To maintain the communication
line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at
this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break
during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the
TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the
TxD pin becomes an I/O port, and 0 is output from the TxD pin.
14.10.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
14.10.5 Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data
is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
Rev. 3.00, 03/04, page 422 of 830
14.10.6 Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
14.38).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 14.38 Sample Transmission using DTC in Clock Synchronous Mode
14.10.7 SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop, software standby, or sub-sleep mode,
stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of
the output pins during each mode depend on the port settings, and the pins output a high-level
signal after mode cancellation. If the transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 14.39 shows a sample flowchart for mode transition during transmission. Figures 14.40 and
14.41 show the pin states during transmission.
Before making the transition from the transmission mode using DTC transfer to module stop,
software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting
TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission
using the DTC.
Rev. 3.00, 03/04, page 423 of 830
Reception: Before making the transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 14.42 shows a sample flowchart for mode transition during reception.
Transmission
No
All data transmitted?
[1]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
TE = 0
[2]
[2] Also clear TIE and TEIE to 0
when they are 1.
[3]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
[1] Data being transmitted is lost
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation; however, if the DTC
has been initiated, the data
remaining in DTC RAM will be
transmitted when TE and TIE are
set to 1.
[3] Module stop, watch, sub-active,
and sub-sleep modes are
included.
No
Yes
Initialization
TE = 1
Start transmission
Figure 14.39 Sample Flowchart for Mode Transition during Transmission
Rev. 3.00, 03/04, page 424 of 830
Transmission start
Transition to
Software standby
Transmission end software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
High output
Start
Stop
Port input/output
SCI TxD output
Port
Port
High output
SCI
TxD output
Figure 14.40 Pin States during Transmission in Asynchronous Mode (Internal Clock)
Transmission start
Transmission end
Transition to
Software standby
software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
Marking output
Port
Last TxD bit retained
SCI TxD output
Port input/output
Port
High output*
SCI
TxD output
Note: Initialized in software standby mode
Figure 14.41 Pin States during Transmission in Clock Synchronous Mode
(Internal Clock)
Rev. 3.00, 03/04, page 425 of 830
Reception
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Data being received will be invalid.
Yes
Read receive data in RDR
[2] Module stop, watch, sub-active, and subsleep modes are included.
RE = 0
[2]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
No
Yes
Initialization
RE = 1
Start reception
Figure 14.42 Sample Flowchart for Mode Transition during Reception
Rev. 3.00, 03/04, page 426 of 830
14.10.8 Notes on Switching from SCK Pins to Port Pins
When SCK pins are switched to port pins after transmission has completed, pins are enabled for
port output after outputting a low pulse of half a cycle as shown in figure 14.43.
Low pulse of half a cycle
SCK/Port
4. Low pulse output
1. Transmission end
Data
Bit 6
Bit 7
2. TE = 0
TE
3. C/A = 0
C/A
CKE1
CKE0
Figure 14.43 Switching from SCK Pins to Port Pins
To prevent the low pulse output that is generated when switching the SCK pins to the port pins,
specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure
below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1.
1.
2.
3.
4.
5.
End serial data transmission
TE bit = 0
CKE1 bit = 1
C/A bit = 0 (switch to port output)
CKE1 bit = 0
High output
SCK/Port
1. Transmission end
Data
TE
Bit 6
Bit 7
2. TE = 0
4. C/A = 0
C/A
3. CKE1 = 1
CKE1
5. CKE1 = 0
CKE0
Figure 14.44 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
Rev. 3.00, 03/04, page 427 of 830
14.11
CRC Operation Circuit
The cyclic redundancy check (CRC) operation circuit detects errors in data blocks.
14.11.1 Features
The features of the CRC operation circuit are listed below.
•
•
•
•
CRC code generated for any desired data length in an 8-bit unit
CRC operation executed on eight bits in parallel
One of three generating polynomials selectable
CRC code generation for LSB-first or MSB-first communication selectable
Figure 14.45 shows a block diagram of the CRC operation circuit.
Internal bus
CRCCR
Control
signal
CRCDIR
CRC code
generation
circuit
CRCDOR
[Legend]
CRCCR: CRC control register
CRCDIR: CRC data input register
CRCDOR: CRC data output register
Figure 14.45 Block Diagram of CRC Operation Circuit
14.11.2 Register Descriptions
The CRC operation circuit has the following registers.
• CRC control register (CRCCR)
• CRC data input register (CRCDIR)
• CRC data output register (CRCDOR)
Rev. 3.00, 03/04, page 428 of 830
CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the
operation mode, and selects the generating polynomial.
Bit
Bit Name
Initial Value
R/W Description
7
DORCLR
0
W
CRCDOR Clear
Setting this bit to 1 clears CRCDOR to H′0000.
6 to 3 
All 0
R
Reserved
The initial value should not be changed.
2
LMS
0
R/W CRC Operation Switch
Selects CRC code generation for LSB-first or MSBfirst communication.
0: Performs CRC operation for LSB-first
communication. The lower byte (bits 7 to 0) is first
transmitted when CRCDOR contents (CRC code)
are divided into two bytes to be transmitted in two
parts.
1: Performs CRC operation for MSB-first
communication. The upper byte (bits 15 to 8) is
first transmitted when CRCDOR contents (CRC
code) are divided into two bytes to be transmitted
in two parts.
1
0
G1
G0
0
0
R/W CRC Generating Polynomial Select
R/W These bits select the polynomial.
00: Reserved
8
2
01: X + X + X + 1
16
15
2
10: X + X + X + 1
16
12
5
11: X + X + X + 1
CRC Data Input Register (CRCDIR): CRCDIR is an 8-bit readable/writable register, to which
the bytes to be CRC-operated are written. The result is obtained in CRCDOR.
CRC Data Output Register (CRCDOR): CRCDOR is a 16-bit readable/writable register that
contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR
after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to
which CRC operation is to be performed, the CRC operation result will be H'0000 if the data
contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1,
respectively, the lower byte of this register contains the result.
Rev. 3.00, 03/04, page 429 of 830
14.11.3 CRC Operation Circuit Operation
The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An
example in which a CRC code for hexadecimal data H'F0 is generated using the X16 + X12 + X5 + 1
polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
1. Write H'83 to CRCCR
2. Write H'F0 to CRCDIR
7
CRCCR
7
0
0
1
0
0
0
0
CRCDIR
1 1
0
1
1
1
1
0
CRCDOR clearing
0 0
CRC code generation
0
7
0
0
7
CRCDORH
0
0
0
0
0
0
0 0
CRCDORH
1
1
1
1
0
1
1 1
CRCDORL
0
0
0
0
0
0
0 0
CRCDORL
1
0
0
0
1
1
1 1
3. Read from CRCDOR
CRC code = H'F78F
4. Serial transmission (LSB first)
Data
CRC code
7
1
1
1
1
0
1
1
F
0
7
1
1
0
7
0
0
1
1
8
1
0
7
1
1
0
1
F
1
1
0
0
F
0
0
Output
0
Figure 14.46 LSB-First Data Transmission
1. Write H'87 to CRCCR
2. Write H'F0 to CRCDIR
7
CRCCR
7
0
0
1
0
0
0
1
CRCDIR
1 1
CRCDOR clearing
0
7
0
1
1
1
1
0
0
0
0
CRC code generation
0
7
CRCDORH
0
0
0
0
0
0
0 0
CRCDORH
1
1
1
0
1
1
1
1
CRCDORL
0
0
0
0
0
0
0 0
CRCDORL
0
0
0
1
1
1
1
1
3. Read from CRCDOR
CRC code = H'EF1F
4. Serial transmission (MSB first)
CRC code
Data
7
Output
1
1
1
1
0
0
0
F
0
0
7
0
1
1
1
E
0
1
1
1
0
7
1
0
F
Figure 14.47 MSB-First Data Transmission
Rev. 3.00, 03/04, page 430 of 830
0
0
0
1
1
1
1
1
F
1
1. Serial reception (LSB first)
Data
CRC code
7
1
1
1
1
0
1
1
F
0
7
1
1
0
7
0
0
8
2. Write H'83 to CRCCR
1
1
1
7
1
1
F
1
1
0
0
F
0
0
0
0
0
0
0
0
1
1
CRCDIR
1
0
1
1
1
0
0
CRC code generation
CRCDOR clearing
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
1
1
1
1
0
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
1
0
0
0
1
1
1
1
1
0
1
1
1
4. Write H'8F to CRCDIR
5. Write H'F7 to CRCDIR
7
CRCDIR
1
7
0
0
Input
0
7
0
0
0
1
3. Write H'F0 to CRCDIR
7
CRCCR
1
0
0
0
1
1
1
1
CRCDIR
1
0
1
1
CRC code generation
CRC code generation
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
0
0
0
0
0
0
0
0
CRCDORL
1
1
1
1
0
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
6. Read from CRCDOR
CRC code = H'0000 → No error
Figure 14.48 LSB-First Data Reception
Rev. 3.00, 03/04, page 431 of 830
1. Serial reception (MSB first)
Data
CRC code
7
Input
1
1
1
1
0
0
0
F
0
7
0
1
0
2. Write H'87 to CRCCR
1
1
0
1
1
E
0
7
1
0
0
0
F
0
1
1
1
0
0
0
1
1
1
CRCDIR
1
0
1
1
1
0
0
0
0
CRC code generation
CRCDOR clearing
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
1
1
1
0
1
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
1
1
1
1
1
1
1
1
1
1
4. Write H'EF to CRCDIR
5. Write H'1F to CRCDIR
7
CRCDIR
1
7
0
1
1
1
F
7
0
0
1
3. Write H'F0 to CRCDIR
7
CRCCR
1
1
0
1
1
1
1
CRCDIR
0
0
0
0
CRC code generation
CRC code generation
0
7
0
7
CRCDORH
0
0
0
1
1
1
1
1
CRCDORH
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
0
0
0
0
0
6. Read from CRCDOR
CRC code = H'0000 → No error
Figure 14.49 MSB-First Data Reception
Rev. 3.00, 03/04, page 432 of 830
1
14.11.4 Note on CRC Operation Circuit
Note that the sequence to transmit the CRC code differs between LSB-first transmission and
MSB-first transmission.
1. CRC code generation
After specifying the operation method, write data to CRCDIR in the sequence of (1) → (2) → (3) → (4).
7
0
(1) → (2) → (3) → (4)
CRCDIR
CRC code generation
0
7
CRCDORH
(5)
CRCDORL
(6)
2. Transmission data
(i) LSB-first transmission
CRC code
7
07
07
(6)
(5)
07
(4)
07
07
(3)
(2)
0
Output
(1)
(ii) MSB-first transmission
CRC code
7
Output
07
(1)
07
(2)
07
(3)
0 7
(4)
07
(5)
0
(6)
Figure 14.50 LSB-First and MSB-First Transmit Data
Rev. 3.00, 03/04, page 433 of 830
Rev. 3.00, 03/04, page 434 of 830
Section 15 I2C Bus Interface (IIC)
This LSI has a six-channel I2C bus interface (IIC). The I2C bus interface conforms to and provides
a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that
controls the I2C bus differs partly from the Philips configuration, however.
15.1
Features
• Selection of addressing format or non-addressing format
 I2C bus format: addressing format with acknowledge bit, for master/slave operation
 Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master operation only
• Conforms to Philips I2C bus interface (I2C bus format)
• Two ways of setting slave address (I2C bus format)
• Start and stop conditions generated automatically in master mode (I2C bus format)
• Selection of acknowledge output levels when receiving (I2C bus format)
• Automatic loading of acknowledge bit when transmitting (I2C bus format)
• Wait function in master mode (I2C bus format)
 A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
 The wait can be cleared by clearing the interrupt flag.
• Wait function (I2C bus format)
 A wait request can be generated by driving the SCL pin low after data transfer.
 The wait request is cleared when the next transfer becomes possible.
• Interrupt sources
 Data transfer end (including when a transition to transmit mode with I2C bus format occurs,
when ICDR data is transferred, or during a wait state)
 Address match: when any slave address matches or the general call address is received in
slave receive mode with I2C bus format (including address reception after loss of master
arbitration)
 Arbitration loss
 Start condition detection (in master mode)
 Stop condition detection (in slave mode)
• Selection of 32 internal clocks (in master mode)
• Direct bus drive
 PinsSCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function
as NMOS open-drain outputs when the bus drive function is selected.
IFIIC50C_000020030700
Rev. 3.00, 03/04, page 435 of 830
Figure 15.1 shows a block diagram of the I2C bus interface. Figure 15.2 shows an example of I/O
pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 25, Electrical Characteristics.
ICXR
PS
SCL
Noise
canceler
ICCR
Clock
control
ICMR
Bus state
decision
circuit
SDA
ICSR
Arbitration
decision
circuit
ICDRT
Output data
control
circuit
ICDRS
Internal data bus
φ
ICDRR
Noise
canceler
Address comparator
SAR, SARX
Interrupt
generator
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
ICXR:
SAR:
SARX:
PS:
I2C
bus control register
I2C bus mode register
I2C bus status register
I2C bus data register
I2C bus extended control register
Slave address register
Slave address register X
Prescaler
Figure 15.1 Block Diagram of I2C Bus Interface
Rev. 3.00, 03/04, page 436 of 830
Interrupt
generator
VCC
VDD
VCC
SCL
SCL
SDA
SDA
SCL in
SDA out
(Master)
SCL in
This LSI
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
SCL
SDA
SDA in
SCL
SDA
SCL out
SCL in
(Slave 2)
Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master)
Rev. 3.00, 03/04, page 437 of 830
15.2
Input/Output Pins
Table 15.1 summarizes the input/output pins used by the I2C bus interface.
Table 15.1 Pin Configuration
Channel
Symbol*
Input/Output
Function
0
SCL0
Input/Output
Clock input/output pin of channel IIC_0
SDA0
Input/Output
Data input/output pin of channel IIC_0
SCL1
Input/Output
Clock input/output pin of channel IIC_1
SDA1
Input/Output
Data input/output pin of channel IIC_1
SCL2
Input/Output
Clock input/output pin of channel IIC_2
SDA2
Input/Output
Data input/output pin of channel IIC_2
SCL3
Input/Output
Clock input/output pin of channel IIC_3
SDA3
Input/Output
Data input/output pin of channel IIC_3
SCL4
Input/Output
Clock input/output pin of channel IIC_4
SDA4
Input/Output
Data input/output pin of channel IIC_4
SCL5
Input/Output
Clock input/output pin of channel IIC_5
SDA5
Input/Output
Data input/output pin of channel IIC_5
1
2
3
4
5
Note:
*
In the text, the channel subscript is omitted, and only SCL and SDA are used.
Rev. 3.00, 03/04, page 438 of 830
15.3
Register Descriptions
The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. The IIC registers are allocated to the same address.
Selecting register is carried out by means of the IICE bit in the serial timer control register
(STCR).
•
•
•
•
•
•
•
•
•
I2C bus data register (ICDR)
Slave address register (SAR)
Second slave address register (SARX)
I2C bus mode register (ICMR)
I2C bus transfer rate select register (IICX3)
I2C bus control register (ICCR)
I2C bus status register (ICSR)
I2C bus extended control register (ICXR)
I2C SMbus control register (ICSMBCR)
15.3.1
I2C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in accordance with changes in the bus state, and they
affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I2C bus format, writing transmit data to ICDR should be
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If IIC is in transmit mode (TRS=1) and the next data is in ICDRT (the ICDRE flag is 0), data is
transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If IIC is in receive mode
(TRS=0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
Rev. 3.00, 03/04, page 439 of 830
If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
15.3.2
Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. When the LSI is in slave mode
with the I2C bus format selected, if the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Initial
Value
R/W
Description
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
All 0
R/W
Slave Address
FS
0
Bit
Bit Name
7
6
5
4
3
2
1
0
Set a slave address.
R/W
Format Select
Selects the communication format together with the FSX
bit in SARX. Refer to table 15.2.
This bit should be set to 0 when general call address
recognition is performed.
Rev. 3.00, 03/04, page 440 of 830
15.3.3
Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. When the LSI is in slave mode with the I2C bus format selected, if the FSX
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Initial
Value
R/W Description
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
All 0
R/W Second Slave Address
FSX
1
Bit
Bit Name
7
6
5
4
3
2
1
0
Set the second slave address.
R/W Format Select X
Selects the communication format together with the FS bit
in SAR. Refer to table 15.2.
Table 15.2 Transfer Format
SAR
SARX
FS
FSX
Operating Mode
0
0
I C bus format
1
1
0
1
2
•
SAR and SARX slave addresses recognized
•
General call address recognized
I2C bus format
•
SAR slave address recognized
•
SARX slave address ignored
•
General call address recognized
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
•
General call address ignored
Clocked synchronous serial format
•
SAR and SARX slave addresses ignored
•
General call address ignored
Rev. 3.00, 03/04, page 441 of 830
• I2C bus format: addressing format with acknowledge bit
• Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master mode only
15.3.4
I2C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit
Bit Name
Initial
Value
R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
2
Set this bit to 0 when the I C bus format is used.
6
WAIT
0
R/W Wait Insertion Bit
2
This bit is valid only in master mode with the I C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th clock),
the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is
cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
For details, refer to section 15.4.7, IRC Setting Timing and
SCL Control.
5
4
3
CKS2
CKS1
CKS0
All 0
R/W Transfer Clock Select
Rev. 3.00, 03/04, page 442 of 830
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX5 (channel 5), IICX4 (channel 4), and IICX3
(channel 3) bits in IICX3, and the IICX2 (channel 2), IICX1
(channel 1), and IICX0 (channel 0) bits in STCR. Refer to
table 15.3.
Bit
Bit Name
2
1
0
BC2
BC1
BC0
Initial
Value
R/W
All 0
R/W
Description
Bit Counter
These bits specify the number of bits to be transferred
next. Bit BC2 to BC0 settings should be made during an
interval between transfer frames. If bits BC2 to BC0 are
set to a value other than B'000, the setting should be
made while the SCL line is low.
The bit counter is initialized to B'000 when a start condition
is detected. The value returns to B'000 at the end of a data
transfer.
2
I C Bus Format
Clocked Synchronous Serial Mode
B'000: 9 bits
B'000: 8 bits
B'001: 2 bits
B'001: 1 bits
B'010: 3 bits
B'010: 2 bits
B'011: 4 bits
B'011: 3 bits
B'100: 5 bits
B'100: 4 bits
B'101: 6 bits
B'101: 5 bits
B'110: 7 bits
B'110: 6 bits
B'111: 8 bits
B'111: 7 bits
I2C Bus Transfer Rate Select Register (IICX3)
15.3.5
IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channels 3 to 5.
Bit
Bit Name
7 to 4 
Initial
Value
R/W
Description


Reserved
These bits cannot be modified.
3
TCSS
0
R/W
Transfer Rate Clock Source Select
2
This bit selects a clock rate to be applied to the I C bus
transfer rate.
0: φ/2
1: φ/4
2
1
0
IICX5
IICX4
IICX3
All 0
R/W
IIC Transfer Rate Select
These bits are used to control IIC operation.
These bits select the transfer rate in master mode,
together with the CKS2 to CKS0 bits in ICMR. For the
transfer rate, see table 15.3. IICX5, IICX4, and IICX3
control IIC_5, IIC_4, and IIC_3, respectively
Rev. 3.00, 03/04, page 443 of 830
Table 15.3 I2C bus Transfer Rate (1)
• TCSS = 0
STCR/
ICMR
Bit 5
IICXn
CKS2 CKS1 CKS0 Clock
0
0
Bit 4
Transfer Rate (MHz)
IICX3
0
1
1
0
1
1
0
0
1
1
0
1
Bit 3
φ=5
φ=8
φ = 10
φ = 16
φ = 20
φ = 25
MHz
MHz
MHz
MHz
MHz
MHz
1
φ = 33
MHz
1
892.9*
1
625.0*
0
φ/28
178.6
285.7
357.1
571.4*
714.3*
1
φ/40
125.0
200.0
250.0
400.0
500.0*
1
1
1178.6*
1
1
825.0*
1
1
1
0
φ/48
104.2
166.7
208.3
333.3
416.7*
520.8*
687.5*
1
φ/64
78.1
125.0
156.3
250.0
312.5
390.6
515.6*
0
φ/80
62.5
100.0
125.0
200.0
250.0
312.5
412.5*
1
φ/100
50.0
80.0
100.0
160.0
200.0
250.0
330.0*
0
φ/112
44.6
71.4
89.3
142.9
178.6
223.2
294.6*
1
φ/128
39.1
62.5
78.1
125.0
156.3
195.3
257.8*
0
φ/56
89.3
142.9
178.6
285.7
357.1
446.4*
589.3*
1
φ/80
62.5
100.0
125.0
200.0
250.0
312.5
412.5*
0
φ/96
52.1
83.3
104.2
166.7
208.3
260.4
343.8
1
φ/128
39.1
62.5
78.1
125.0
156.3
195.3
257.8
0
φ/160
31.3
50.0
62.5
100.0
125.0
156.3
206.3
1
φ/200
25.0
40.0
50.0
80.0
100.0
125.0
165.0
0
φ/224
22.3
35.7
44.6
71.4
89.3
111.6
147.3
1
φ/256
19.5
31.3
39.1
62.5
78.1
97.7
128.9
1
1
2
2
2
1
2
1
1
Notes: 1. The correct operation cannot be guaranteed since the value is outside the I C bus
interface specifications (high-speed mode: max. 400 kHz)
2. When operate IIC in this setting, see 5 in section 15.6, Usage Notes.
(n = 0 to 5)
Rev. 3.00, 03/04, page 444 of 830
Table 15.3 I2C bus Transfer Rate (2)
• TCSS = 1
STCR/
ICMR
Transfer Rate (MHz)
IICX3
Bit 5
Bit 4
Bit 3
φ=5
φ=8
φ = 10
φ = 16
φ = 20
φ = 25
φ = 33
IICXn
CKS2
CKS1
CKS0
Clock MHz
MHz
MHz
MHz
MHz
MHz
MHz
0
0
0
0
φ/56
89.3
142.9
178.6
285.7
357.1
446.4*
589.3*
1
φ/80
62.5
100.0
125.0
200.0
250.0
312.5
412.5*
1
0
φ/96
52.1
83.3
104.2
166.7
208.3
260.4
343.8
1
φ/128
39.1
62.5
78.1
125.0
156.3
195.3
257.8
0
φ/160
31.3
50.0
62.5
100.0
125.0
156.3
206.3
1
φ/200
25.0
40.0
50.0
80.0
100.0
125.0
165.0
0
φ/224
22.3
35.7
44.6
71.4
89.3
111.6
147.3
1
φ/256
19.5
31.3
39.1
62.5
78.1
97.7
128.9
0
0
φ/112
44.6
71.4
89.3
142.9
178.6
223.2
294.6
1
φ/160
31.3
50.0
62.5
100.0
125.0
156.3
206.3
1
0
φ/190
26.0
41.7
52.1
83.3
104.2
130.2
171.9
1
φ/256
19.5
31.3
39.1
62.5
78.1
97.7
128.9
0
φ/320
15.6
25.0
31.3
50.0
62.5
78.1
103.1
1
φ/400
12.5
20.0
25.0
40.0
50.0
62.5
82.5
0
φ/448
11.2
17.9
22.3
35.7
44.6
55.8
73.7
1
φ/512
9.8
15.6
19.5
31.3
39.1
48.8
64.5
1
0
1
1
0
1
0
1
Note:
*
2
The correct operation cannot be guaranteed since the value is outside the I C bus
interface specifications (high-speed mode: max. 400 kHz)
(n = 0 to 5)
Rev. 3.00, 03/04, page 445 of 830
15.3.6
I2C Bus Control Register (ICCR)
ICCR controls the I2C bus interface and performs interrupt flag confirmation.
Bit
Bit Name
Initial
Value
R/W
Description
7
ICE
0
R/W
I2C Bus Interface Enable
2
2
0: I C bus interface modules are stopped and I C bus
interface module internal state is initialized. SAR and
SARX can be accessed.
2
1: I C bus interface modules can perform transfer and
reception, they are connected to the SCL and SDA pins,
2
and the I C bus can be driven. ICMR and ICDR can be
accessed.
6
IEIC
0
R/W
I2C Bus Interface Interrupt Enable
2
0: Disables interrupts from the I C bus interface to the CPU
2
1: Enables interrupts from the I C bus interface to the CPU.
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
2
in a bus contention in master mode of the I C bus format.
2
In slave receive mode with I C bus format, the R/W bit in
the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
Rev. 3.00, 03/04, page 446 of 830
Bit
Bit Name
Initial
Value
R/W
Description
5
4
MST
TRS
0
0
R/W
R/W
[MST clearing conditions]
(1) When 0 is written by software
(2) When lost in bus contention in I2C bus format master
mode
[MST setting conditions]
(1) When 1 is written by software (for MST clearing
condition 1)
(2) When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
(1) When 0 is written by software (except for TRS setting
condition 3)
(2) When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
(3) When lost in bus contention in I2C bus format master
mode
[TRS setting conditions]
(1) When 1 is written by software (except for TRS clearing
condition 3)
(2) When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
(3) When 1 is received as the R/W bit after the first frame
2
address matching in I C bus format slave mode
3
ACKE
0
R/W
Acknowledge Bit Decision Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the acknowledge bit is 1, continuous transfer is
halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
Rev. 3.00, 03/04, page 447 of 830
Bit
2
0
Bit Name
BBSY
SCP
Initial
Value
0
1
R/W
Description
3
R/W* Bus Busy
W
Start Condition/Stop Condition Prohibit
In master mode
•
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
•
Writing 1 in BBSY and 0 in SCP: A start condition and
a restart condition are issued
In slave mode
•
Writing to the BBSY flag is disabled.
[BBSY setting condition]
•
When the SDA level changes from high to low under
the condition of SCL = high, assuming that the start
condition has been issued.
[BBSY clearing conditions]
•
When the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued.
To issue a start/stop condition, use the MOV instruction.
2
The I C bus interface must be set in master transmit mode
before the issue of a start condition. Set MST to 1 and
TRS to 1 before writing 1 in BBSY and 0 in SCP.
2
The BBSY flag can be read to check whether the I C bus
(SCL, SDA) is busy or free.
Rev. 3.00, 03/04, page 448 of 830
Bit
1
Bit Name
IRIC
Initial
Value
0
R/W
Description
1
R/(W)* I2C Bus Interface Interrupt Request Flag
2
Indicates that the I C bus interface has issued an interrupt
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR and the WAIT bit in ICMR. See section 15.4.7, IRIC
Setting Timing and SCL Control. The conditions under
which IRIC is set also differ depending on the setting of the
ACKE bit in ICCR.
[Setting conditions]
2
I C bus format master mode:
•
When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
•
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
•
At the end of data transfer (rise of the 9th
transmit/receive clock)
•
When a slave address is received after bus mastership
is lost
•
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
•
When the AL flag is set to 1 after bus mastership is lost
while the ALIE bit is 1
2
I C bus format slave mode:
•
When the slave address (SVA or SVAX) matches (when
the AAS or AASX flag in ICSR is set to 1) and at the
end of data transfer up to the subsequent
retransmission start condition or stop condition detection
(rise of the 9th clock)
•
When the general call address is detected (when the 0
is received for R/W bit, and ADZ flag in ICSR is set to 1)
and at the end of data reception up to the subsequent
retransmission start condition or stop condition detection
(rise of the 9th receive clock)
•
When 1 is received as an acknowledge bit while the
ACKE bit is 1 (when the ACKB bit is set to 1)
•
When a stop condition is detected while the STOPIM bit
is 0 (when the STOP or ESTP flag in ICSR is set to 1)
Rev. 3.00, 03/04, page 449 of 830
Bit Bit Name
1
IRIC
Initial
Value
0
R/W
Description
1
R/(W)* At the end of data transfer in clock synchronous serial
format (rise of the 8th transmit/receive clock)
When a start condition is detected with serial format
selected
When a condition occurs in which the ICDRE or ICDRF
flag is set to 1.
•
When a start condition is detected in transmit mode
(when a start condition is detected and the ICDRE flag
is set to 1)
•
When transmitting the data in the ICDR register buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or data
is transferred from ICDRS to ICDRR in receive mode
and the ICDRF flag is set to 1.)
[Clearing conditions]
•
When 0 is written in IRIC after reading IRIC = 1
•
When ICDR is accessed by DTC *2 (This may not be a
clearing condition. For details, see the description of
the DTC operation on the next page.
Notes: 1. Only 0 can be written to clear the flag to 0.
2. The DTC does not support IIC_4 and IIC_5.
3. If the BBSY bit is written to, the value of the flag is not changed.
Rev. 3.00, 03/04, page 450 of 830
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention. The DTC does not support IIC_4 and IIC_5.
When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the
DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission
start condition or stop condition after a slave address (SVA) or general call address match in I2C
bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The
IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous
transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified
number of ICDR reads or writes have been completed.
Tables 15.4 and 15.5 show the relationship between the flags and the transfer states.
Rev. 3.00, 03/04, page 451 of 830
Table 15.4 Flags and Transfer States (Master Mode)
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
1
1
0
0
0
0
0↓
0
0↓
0↓
0

0
Idle state (flag
clearing
required)
1
1
1↑
0
0
1↑
0
0
0
0
0

1↑
Start condition
detected
1

1
0
0

0
0
0
0



Wait state
1
1
1
0
0

0
0
0
0
1↑


Transmission
end (ACKE=1
and ACKB=1)
1
1
1
0
0
1↑
0
0
0
0
0

1↑
Transmission
end with
ICDRE=0
1
1
1
0
0

0
0
0
0
0

0↓
ICDR write with
the above state
1
1
1
0
0

0
0
0
0
0

1
Transmission
end with
ICDRE=1
1
1
1
0
0

0
0
0
0
0

0↓
ICDR write with
the above state
or after start
condition
detected
1
1
1
0
0
1↑
0
0
0
0
0

1↑
Automatic data
transfer from
ICDRT to ICDRS
with the above
state
1
0
1
0
0
1↑
0
0
0
0

1↑

Reception end
with ICDRF=0
1
0
1
0
0

0
0
0
0

0↓

ICDR read with
the above state
1
0
1
0
0

0
0
0
0

1

Reception end
with ICDRF=1
1
0
1
0
0

0
0
0
0

0↓

ICDR read with
the above state
1
0
1
0
0
1↑
0
0
0
0

1↑

Automatic data
transfer from
ICDRS to
ICDRR with the
above state
0↓
0↓
1
0
0

0
1↑
0
0



Arbitration lost
1

0↓
0
0

0
0
0
0


0↓
Stop condition
detected
[Legend]
0: 0-state retained
0↓: Cleared to 0
1: 1-state retained
1↑: Set to 1
Rev. 3.00, 03/04, page 452 of 830
: Previous state retained
Table 15.5 Flags and Transfer States (Slave Mode)
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
0
0
0
0
0
0
0
0
0
0
0

0
Idle state (flag
clearing
required)
0
0
1↑
0
0
0
0↓
0
0
0
0

1↑
Start condition
detected
0
1↑/0
*1
1
0
0
0
0

1↑
0
0
1↑
1
SAR match in
first frame
(SARX≠SAR)
0
0
1
0
0
0
0

1↑
1↑
0
1↑
1
General call
address
match in first
frame
(SARX≠H'00)
0
1↑/0
*1
1
0
0
1↑
1↑

0
0
0
1↑
1
SAR match in
first frame
(SAR≠SARX)
0
1
1
0
0




0
1↑


Transmission
end (ACKE=1
and ACKB=1)
0
1
1
0
0
1↑/0
*1



0
0

1↑
Transmission
end with
ICDRE=0
0
1
1
0
0


0↓
0↓
0
0

0↓
ICDR write
with the above
state
0
1
1
0
0




0
0

1
Transmission
end with
ICDRE=1
0
1
1
0
0


0↓
0↓
0
0

0↓
ICDR write
with the above
state
0
1
1
0
0
1↑/0
*2

0
0
0
0

1↑
Automatic
data transfer
from ICDRT to
ICDRS with
the above
state
0
0
1
0
0
1↑/0
*2





1↑

Reception end
with ICDRF=0
0
0
1
0
0


0↓
0↓
0↓

0↓

ICDR read
with the above
state
Rev. 3.00, 03/04, page 453 of 830
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
0
0
1
0
0






1

Reception
end with
ICDRF=1
0
0
1
0
0


0↓
0↓
0↓

0↓

ICDR read
with the
above state
0
0
1
0
0
1↑/0
*2

0
0
0

1↑

Automatic
data transfer
from ICDRS
to ICDRR
with the
above state
0

0↓
1↑/0
*3
0/1↑
*3







0↓
Stop
condition
detected
[Legend]
0: 0-state retained 1: 1-state retained : Previous state retained
1↑: Set to 1
0↓: Cleared to 0
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
Rev. 3.00, 03/04, page 454 of 830
15.3.7
I2C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 15.4 and 15.5.
Bit
Bit Name
Initial
Value
R/W
7
ESTP
0
R/(W)* Error Stop Condition Detection Flag
Description
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
6
STOP
0
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag in ICCR is cleared to 0
R/(W)* Normal Stop Condition Detection Flag
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer is
completed.
[Clearing conditions]
5
IRTR
0
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag is cleared to 0
2
R/(W)* I C Bus Interface Continuous Transfer Interrupt Request
Flag
2
Indicates that the I C bus interface has issued an interrupt
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is
possible. When the IRTR flag is set to 1, the IRIC flag is
also set to 1 at the same time.
[Setting conditions]
2
I C bus format slave mode:
•
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
2
I C bus format master mode or clocked synchronous serial
format mode:
•
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
•
When 0 is written after reading IRTR = 1
•
When the IRIC flag is cleared to 0 while ICE is 1
Rev. 3.00, 03/04, page 455 of 830
Bit
Bit Name
Initial
Value
R/W
4
AASX
0
R/(W)* Second Slave Address Recognition Flag
Description
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition matches bits
SVAX6 to SVAX0 in SARX.
[Setting condition]
When the second slave address is detected in slave receive
mode and FSX = 0 in SARX
[Clearing conditions]
3
AL
0
•
When 0 is written in AASX after reading AASX = 1
•
When a start condition is detected
•
In master mode
R/(W)* Arbitration Lost Flag
Indicates that arbitration was lost in master mode.
[Setting conditions]
When ALSL=0
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
If the internal SCL line is high at the fall of SCL in
master mode
When ALSL=1
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
If the SDA pin is driven low by another device before the
2
I C bus interface drives the SDA pin low, after the start
condition instruction was executed in master transmit
mode
[Clearing conditions]
Rev. 3.00, 03/04, page 456 of 830
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in AL after reading AL = 1
Bit
Bit Name
Initial
Value
R/W
2
AAS
0
R/(W)* Slave Address Recognition Flag
Description
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address (H'00)
is detected.
[Setting condition]
When the slave address or general call address (one
frame including a R/W bit is H'00) is detected in slave
receive mode and FS = 0 in SAR
[Clearing conditions]
1
ADZ
0
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in AAS after reading AAS = 1
•
In master mode
R/(W)* General Call Address Recognition Flag
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition is the general call
address (H'00).
[Setting condition]
When the general call address (one frame including a R/W
bit is H'00) is detected in slave receive mode and FS = 0
or FSX = 0
[Clearing conditions]
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in ADZ after reading ADZ = 1
•
In master mode
If a general call address is detected while FS=1 and
FSX=0, the ADZ flag is set to 1; however, the general call
address is not recognized (AAS flag is not set to 1).
Rev. 3.00, 03/04, page 457 of 830
Bit
Bit Name
Initial
Value
R/W
Description
0
ACKB
0
R/W
Acknowledge Bit
Stores acknowledge data.
Transmit mode:
[Setting condition]
When 1 is received as the acknowledge bit when ACKE=1
in transmit mode
[Clearing conditions]
•
When 0 is received as the acknowledge bit when
ACKE=1 in transmit mode
•
When 0 is written to the ACKE bit
Receive mode:
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus line
(returned by the receiving device) is read in transmission
(when TRS = 1). In reception (when TRS = 0), the value
set by internal software is read.
When this bit is written, acknowledge data that is returned
after receiving is rewritten regardless of the TRS value. If
the ICSR register bit is written using bit-manipulation
instructions, the acknowledge data should be re-set since
the acknowledge data setting is rewritten by the ACKB bit
reading value.
Write the ACKE bit to 0 to clear the ACKB flag to 0, before
transmission is ended and a stop condition is issued in
master mode, or before transmission is ended and SDA is
released to issue a stop condition by a master device.
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 458 of 830
15.3.8
I2C Bus Extended Control Register (ICXR)
ICXR enables or disables the I2C bus interface interrupt generation and continuous receive
operation, and indicates the status of receive/transmit operations.
Bit
Bit Name
Initial
Value
R/W
Description
7
STOPIM
0
R/W
Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the stop
condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation when
the stop condition is detected (STOP = 1 or ESTP = 1)
in slave mode.
1: Disables IRIC flag setting and interrupt generation when
the stop condition is detected.
6
HNDS
0
R/W
Handshake Receive Operation Select
Enables or disables continuous receive operation in
receive mode.
0: Enables continuous receive operation
1: Disables continuous receive operation
When the HNDS bit is cleared to 0, receive operation is
performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level after data has been received successfully while
ICDRF flag is 0; thus disabling the next data to be
transferred. The bus line is released and next receive
operation is enabled by reading the receive data in ICDR.
Rev. 3.00, 03/04, page 459 of 830
Bit
Bit Name
Initial
Value
R/W
Description
5
ICDRF
0
R
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) status in receive mode.
0: Indicates that the data has been already read from
ICDR (ICDRR) or ICDR is initialized.
1: Indicates that data has been received successfully and
transferred from ICDRS to ICDRR, and the data is ready
to be read out.
[Setting conditions]
•
When data is received successfully and transferred
from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF = 0
(at the rise of the 9th clock pulse).
(2) When ICDR is read successfully in receive mode after
data was received while ICDRF = 1.
[Clearing conditions]
•
When ICDR (ICDRR) is read.
•
When 0 is written to the ICE bit.
When ICDRF is set due to the condition (2) above, ICDRF
is temporarily cleared to 0 when ICDR (ICDRR) is read;
however, since data is transferred from ICDRS to ICDRR
immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Be sure to read data from ICDR in
receive mode (TRS = 0).
Rev. 3.00, 03/04, page 460 of 830
Bit
Bit Name
Initial
Value
R/W
4
ICDRE
0
R
Description
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to ICDR
(ICDRT) or ICDR is initialized.
1: Indicates that data has been transferred from ICDRT to
ICDRS and is being transmitted, or the start condition
has been detected or transmission has been complete,
thus allowing the next data to be written to.
[Setting conditions]
•
When the start condition is detected from the bus line
2
state in I C bus format or serial format.
•
When data is transferred from ICDRT to ICDRS.
1. When data is transmitted completely while ICDRE
= 0 (at the rise of the 9th clock pulse).
2. When data is written to ICDR completely in transmit
mode after data was transmitted while ICDRE = 1.
[Clearing conditions]
•
When data is written to ICDR (ICDRT).
•
When the stop condition is detected in I2C bus format
or serial format.
•
When 0 is written to the ICE bit.
2
Note that if the ACKE bit is set to 1 in I C bus format thus
enabling acknowledge bit decision, ICDRE is not set when
data is transmitted completely while the acknowledge bit is
1.
When ICDRE is set due to the condition (2) above, ICDRE
is temporarily cleared to 0 when data is written to ICDR
(ICDRT); however, since data is transferred from ICDRT to
ICDRS immediately, ICDRF is set to 1 again. Do not write
data to ICDR when TRS = 0 because the ICDRE flag
value is invalid during the time.
Rev. 3.00, 03/04, page 461 of 830
Bit
Bit Name
Initial
Value
R/W
Description
3
ALIE
0
R/W
Arbitration Lost Interrupt Enable
Enables or disables IRIC flag setting and interrupt request
when arbitration is lost.
0: Disables interrupt request when arbitration is lost.
1: Enables interrupt request when arbitration is lost.
2
ALSL
0
R/W
Arbitration Lost Condition Select
Selects the condition under which arbitration is lost.
2
0: If the SDA pin state disagrees with the data that I C bus
interface outputs at the rise of SCL and the SCL pin is
driven low by another device.
2
1: If the SDA pin state disagrees with the data that I C bus
interface outputs at the rise of SCL and the SDA line is
driven low by another device in idle state or after the
start condition instruction was executed.
1
0
FNC1
FNC0
0
0
R/W
R/W
Function Bit
These bits cancel some restrictions on usage. For details,
refer to section 15.6, Usage Notes.
00: Restrictions on operation remaining in effect
01: Setting prohibited
10: Setting prohibited
11: Restrictions on operation canceled
Rev. 3.00, 03/04, page 462 of 830
15.3.9
I2C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 15.6 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Bit
Bit Name
7
6
5
4
3
2
SMB5E
SMB4E
SMB3E
SMB2E
SMB1E
SMB0E
Initial
Value
R/W
Description
All 0
R/W
SMBus Enable
These bits enable/disable to support the SMBus,
combining with bits FSEL1 and FSEL0. The SMB5E bit
controls IIC_5, the SMB4E bit controls IIC_4, the SMB3E
bit controls IIC_3, the SMB2E bit controls IIC_2, the
SMB1E bit controls IIC_1, the SMB0E bit controls IIC_0.
0: Disables to support the SMBus
1: Enables to support the SMBus
1
0
FSEL1
FSEL0
0
0
R/W
R/W
Frequency Selection
These bits must be specified to match the system clock
frequency in order to support the SMBus. For details of the
setting, see table 15.7.
Rev. 3.00, 03/04, page 463 of 830
Table 15.6 Output Data Hold Time
Output Data Hold Time (ns)
φ=5
MHz
φ = 6.6 φ = 8
MHz
MHz
φ = 10
MHz
φ = 13.3 φ = 16 φ = 20 φ = 25
MHz
MHz
MHz MHz
φ = 33
MHz
Min.
400
303
250*
200*
150*
125*
100*
80*
61*
Max.
600
455
375
300
226*
188*
150*
120*
91*
Min.
600
455
375
300
226*
188*
150*
120*
91*
Min./
SMBnE FSEL1 FSEL0 Max.
0
1


0
0
1
1
0
1
Notes:
*
Max.
1000*
758
625
500
376
313
250*
200*
152*
Min.
800
606
500
400
301
250*
200*
160*
121*
Max.
1400*
1061*
875
700
526
438
350
280*
212*
Min.
1200*
909
750
600
451
375
300
240*
182*
Max.
2200*
1667*
1375*
1100*
827
688
550
440
333
Min.
2000*
1515*
1250*
1000*
752
625
500
400
303
Max.
3800*
2879*
2375*
1900*
1429*
1188* 950
760
576
n = 0 to 5
Since the value is outside the SMBus specification, it should not be set.
Table 15.7 ISCMBCR Setting
System Clock
SMBnE
FSEL1
FSEL0
5 to 6.6 MHz
0
0
0
6.6 to 10 MHz
1
0
0
10 to 13.3 MHz
1
0
1
13.3 to 20 MHz
1
1
0
20 to 33 MHz
1
1
1
n = 0 to 5
Rev. 3.00, 03/04, page 464 of 830
15.4
Operation
15.4.1
I2C Bus Data Format
The I2C bus interface has an I2C bus format and a serial format.
The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures
15.3 (a) and (b). The first frame following a start condition always consists of 9 bits.
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
15.4.
Figure 15.5 shows the I2C bus timing.
The symbols used in figures 15.3 to 15.5 are explained in table 15.8.
(a) FS = 0 or FSX = 0
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = from 1)
m
(b) Start condition retransmission FS = 0 or FSX = 0
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
1
7
1
1
n1
1
1
7
1
1
n2
1
m1
1
A/A
P
1
1
m2
Upper row: Transfer bit count (n1, n2 = 1 to 8)
Lower row: Transfer frame count (m1, m2 = from 1)
Figure 15.3 I2C Bus Data Formats (I2C Bus Formats)
FS=1 and FSX=1
S
DATA
DATA
P
1
8
n
1
1
m
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = from 1)
Figure 15.4 I2C Bus Data Formats (Serial Formats)
Rev. 3.00, 03/04, page 465 of 830
SDA
SCL
S
1–7
8
9
SLA
R/W
A
1–7
DATA
8
9
A
1–7
DATA
8
9
A/A
P
Figure 15.5 I2C Bus Timing
Table 15.8 I2C Bus Data Format Symbols
Symbol
Description
S
Start condition. The master device drives SDA from high to low while SCL is high
SLA
Slave address. The master device selects the slave device.
R/W
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
DATA
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
P
Stop condition. The master device drives SDA from low to high while SCL is high
Rev. 3.00, 03/04, page 466 of 830
15.4.2
Initialization
Initialize the IIC by the procedure shown in figure 15.6 before starting transmission/reception of
data.
Start initialization
Set MSTP4 = 0 (IIC_0)
MSTP3 = 0 (IIC_1)
MSTP2 = 0 (IIC_2, IIC_3)
MSTP0 = 0 (IIC_4, IIC_5)
(MSTPCRL)
Cancel module stop mode
Set IICE = 1 in STCR
Enable the CPU accessing to the IIC control register and data register
Set ICE = 0 in ICCR
Enable SAR and SARX to be accessed
Set SAR and SARX
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Set ICE = 1 in ICCR
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set ICSR
Set STCR and IICX3
Set ICMR
Set ICXR
Set ICCR
Set acknowledge bit (ACKB)
Set transfer rate (IICX and TCSS)
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
<< Start transmit/receive operation >>
Figure 15.6 Sample Flowchart for IIC Initialization
Note: Be sure to modify the ICMR register after transmit/receive operation has been completed.
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to
BC0 will be modified erroneously, thus causing incorrect operation.
15.4.3
Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Rev. 3.00, 03/04, page 467 of 830
Figure 15.7 shows the sample flowchart for the operations in master transmit mode.
Start
Initialize IIC
[1] Initialization
Read BBSY in ICCR
[2] Test the status of the SCL and SDA lines.
No
BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
[3] Select master transmit mode.
Set BBSY =1 and
SCP = 0 in ICCR
[4] Start condition issuance
Read IRIC in ICCR
[5] Wait for a start condition generation
No
IRIC = 1?
Yes
Write transmit data in ICDR
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing to ICDR, clear IRIC
continuously.)
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
No
ACKB = 0?
[8] Test the acknowledge bit
transferred from the slave device.
Yes
Transmit mode?
No
Master receive mode
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
[9] Set transmit data for the second and
subsequent bytes.
(After writing to ICDR, clear IRIC
immediately.)
Read IRIC in ICCR
[10] Wait for 1 byte to be transmitted.
No
IRIC = 1?
Yes
Read ACKB in ICSR
[11] Determine end of transfer
No
End of transmission?
(ACKB = 1?)
Yes
Clear IRIC in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
[12] Stop condition issuance
End
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR (ICDRT) write operations, are described below.
Rev. 3.00, 03/04, page 468 of 830
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
Initialize the IIC as described in section 15.4.2, Initialization.
Read the BBSY flag in ICCR to confirm that the bus is free.
Set bits MST and TRS to 1 in ICCR to select master transmit mode.
Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU.
Write the data (slave address + R/W) to ICDR.
With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first
frame data following the start condition indicates the 7-bit slave address and transmit/receive
direction (R/W).
To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR,
clear IRIC continuously so no other interrupt handling routine is executed. If the time for
transmission of one frame of data has passed before the IRIC clearing, the end of
transmission cannot be determined. The master device sequentially sends the transmission
clock and the data written to ICDR. The selected slave device (i.e. the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device
has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the
transmit operation.
Write the transmit data to ICDR.
As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write
and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is
performed in synchronization with the internal clock.
When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
Read the ACKB bit in ICSR.
Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still
data to be transmitted, go to step [9] to continue the next transmission operation. When the
slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end
transmission.
Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP
in ICCR. This changes SDA from low to high when SCL is high, and generates the stop
condition.
Rev. 3.00, 03/04, page 469 of 830
Start condition generation
SCL
(master output)
1
2
3
4
5
6
7
SDA
(master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
9
Bit 0
R/W
Slave address
SDA
(slave output)
8
1
2
Bit 7
Bit 6
Data 1
[7]
A
[5]
ICDRE
IRIC
Interrupt
request
Interrupt
request
IRTR
ICDRT
Data 1
Address + R/W
ICDRS
Address + R/W
Data 1
Note: Do not set ICDR
during this period.
User processing
[4] BBSY set to 1 and
[6] ICDR write
SCP cleared to 0
(start condition issuance)
[9] ICDR write
[6] IRIC clear
[9] IRIC clear
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
Stop condition issuance
SCL
(master output)
8
9
SDA
Bit 0
(master output)
Data 1
SDA
(slave output)
[7]
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
9
[10]
Data 2
A
A
ICDRE
IRIC
IRTR
ICDR
User processing
Data 2
Data 1
[9] ICDR write
[9] IRIC clear
[12] BBSY set to 1 and
SCP cleared to 0
(Stop condition issuance)
[12] IRIC clear
[11] ACKB read
Figure 15.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)
Rev. 3.00, 03/04, page 470 of 830
15.4.4
Master Receive Operation
In I2C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 15.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
[1] Select receive mode.
Set HNDS = 1 in ICXR
Clear IRIC in ICCR
Last receive?
Yes
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
No
Read ICDR
Read IRIC in ICCR
No
[3] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock for the receive frame)
IRIC = 1?
Yes
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICCR
No
[4] Clear IRIC.
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
Dummy read to start receiving if the first frame is
the last receive data.
[8] Wait for 1 byte to be received.
IRIC = 1?
Yes
Clear IRIC in ICCR
Set TRS = 1 in ICCR
[9] Clear IRIC.
[10] Read the receive data.
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
[11] Set stop condition issuance.
Generate stop condition.
End
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
Rev. 3.00, 03/04, page 471 of 830
The reception procedure and operations by which the data reception process is provided in 1-byte
units with SCL fixed low at each data reception are described below.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Set the HNDS bit in ICXR to 1.
Clear the IRIC flag to 0 to determine the end of reception.
Go to step [6] to halt reception operation if the first frame is the last receive data.
When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. (Data from the SDA pin is
sequentially transferred to ICDRS in synchronization with the rise of the receive clock
pulses.)
The master device drives SDA low to return the acknowledge data at the 9th receive clock
pulse. The receive data is transferred to ICDRR from ICDRS at the rise of the 9th clock
pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR
data reading.
Clear the IRIC flag to determine the next interrupt.
Go to step [6] to halt reception operation if the next frame is the last receive data.
Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock continuously to receive the next data.
Data can be received continuously by repeating steps [3] to [5].
Set the ACKB bit to 1 so as to return the acknowledge data for the last reception.
Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock to receive data.
When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at
the rise of the 9th receive clock pulse.
Clear the IRIC flag to 0.
Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0.
Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when
SCL is high, and generates the stop condition.
Rev. 3.00, 03/04, page 472 of 830
Master receive mode
Master transmit mode
SCL is fixed low until ICDR is read
SCL
(master output)
SDA
(slave output)
9
1
2
Bit 6
Bit 7
A
3
Bit 5
SCL is fixed low until ICDR is read
4
Bit 4
5
6
Bit 3
Bit 2
7
8
Bit 1
Bit 0
1
2
Bit 7
Bit 6
9
[3]
Data 1
SDA
(master output)
Data 2
A
IRIC
IRTR
ICDRF
ICDRR
Data 1
Undefined value
User processing
[1] TRS cleared to 0
[6] ICDR read
(Data 1)
[4] IRIC clear
[2] ICDR read
(Dummy read)
[1] IRIC clear
Figure 15.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)
SCL is fixed low until ICDR is read
SCL
(master output)
SDA
(slave output)
7
Bit 1
8
9
Bit 0
Data 2
SDA
(master output)
1
Bit 7
2
3
Bit 6
Bit 5
[3]
4
Bit 4
Data 3
A
SCL is fixed low until ICDR is read
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
Stop condition generation
9
[8]
A
IRIC
IRTR
ICDRF
ICDRR
User processing
Data 1
Data 2
[4] IRIC clear
[7] ICDR read
(Data 2)
[6] ACKB set to 1
Data 3
[10] ICDR read
(Data 3)
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
[9] IRIC clear
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
Rev. 3.00, 03/04, page 473 of 830
Receive Operation Using the Wait Function:
Figures 15.13 and 15.14 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Master receive mode
Set TRS = 0 in ICCR
[1] Select receive mode.
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC in ICCR
Set WAIT = 1 in ICMR
[2] Start receiving. The first read
is a dummy read.
Read ICDR
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
Yes
No
[4] Determine end of reception
IRTR = 1?
Yes
Last receive?
Yes
No
Read ICDR
[5] Read the receive data.
[6] Clear IRIC.
(to end the wait insertion)
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Wait for one clock pulse
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
Set TRS = 1 in ICCR
[10] Read the receive data.
Read ICDR
No
[7] Set acknowledge data for the last reception.
Clear IRIC in ICCR
[11] Clear IRIC.
Read IRIC in ICCR
[12] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
IRIC=1?
Yes
IRTR=1?
Yes
[13] Determine end of reception
No
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Read ICDR
Set BBSY= 0 and SCP= 0
in ICCR
[14] Clear IRIC.
(to end the wait insertion)
[15] Clear wait mode.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data.
[17] Generate stop condition
End
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)
Rev. 3.00, 03/04, page 474 of 830
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
[1] Select receive mode.
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Read ICDR
[2] Start receiving. The first read
is a dummy read.
Read IRIC in ICCR
No
IRIC = 1?
[3] Wait for a receive wait
(Set IRIC at the fall of the 8 th clock)
Yes
No
Set ACKB = 1 in ICSR
[7] Set acknowledge data for
the last reception.
Set TRS = 1 in ICCR
[9] Set TRS for stop condition issuance
Clear IRIC in ICCR
[14] Clear IRIC.
(to end the wait insertion)
Read IRIC in ICCR
[12] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock)
IRIC = 1?
Yes
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
[15] Clear wait mode.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data
[17] Generate stop condition
End
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1)
The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
15.14
Rev. 3.00, 03/04, page 475 of 830
[1]
[2]
[3]
[4]
[5]
[6]
Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 to set the acknowledge data.
Clear the HNDS bit in ICXR to 0 to cancel the handshake function.
Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1.
When ICDR is read (dummy data is read), reception is started, and the receive clock is
output, and data received, in synchronization with the internal clock.
The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been
set to 1, an interrupt request is sent to the CPU.
(1) At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag clearing.
(2) At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next
data.
Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt
reception.
If IRTR flag is 1, read ICDR receive data.
Clear the IRIC flag. When the flag is set as (1) in step [3], the master device outputs the 9th
clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal.
Data can be received continuously by repeating steps [3] to [6].
[7]
[8]
[9]
[10]
[11]
[12]
Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first
clock pulse for the next receive data.
Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit
value becomes valid when the rising edge of the next 9th clock pulse is input.
Read the ICDR receive data.
Clear the IRIC flag to 0.
The IRIC flag is set to 1 in either of the following cases.
(1) At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
(2) At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received.
Rev. 3.00, 03/04, page 476 of 830
[13]
[14]
[15]
[16]
[17]
Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Execute step [12] to read the IRIC flag to detect the end of reception.
Clear the WAIT bit in ICMR to cancel the wait mode.
Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0
after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition may not be issued correctly.)
Read the last ICDR receive data.
Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when
SCL is high, and generates the stop condition.
Master transmit mode
SCL
(master output)
SDA
(slave output)
Master receive mode
9
1
2
A
Bit 7
Bit 6
3
Bit 5
4
5
6
7
8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 1
SDA
(master output)
9
1
Bit 7
[3]
2
Bit 6
3
4
5
Bit 5
Bit 4
Bit 3
Data 2
[3]
A
IRIC
[4]IRTR=0
IRTR
ICDR
[4] IRTR=1
Data 1
User processing [1] TRS cleared to 0
IRIC clear to 0
[2] ICDR read
(dummy read)
[6] IRIC clear
[5] ICDR read [6] IRIC clear
(to end wait insertion)
(Data 1)
Figure 15.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)
Rev. 3.00, 03/04, page 477 of 830
[8] Wait for one clock pulse
Stop condition generation
SCL
(master output)
8
9
SDA
Bit 0
(slave output)
Data 2
[3]
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 3
[3]
A
9
[12]
[12]
A
IRIC
IRTR
[4] IRTR=0
ICDR
Data 1
User processing
[13] IRTR=0
[4] IRTR=1
[13] IRTR=1
Data 2
[6] IRIC clear
(to end wait
insertion)
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
Data 3
[15] WAIT cleared to 0,
IRIC clear
[14] IRIC clear
(to end wait
insertion)
[17] Stop condition issuance
[16] ICDR read
(Data 3)
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
15.4.5
Slave Receive Operation
In I2C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Rev. 3.00, 03/04, page 478 of 830
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 15.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
Slave receive mode
Initialize IIC
Set MST = 0
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
and HNDS = 1 in ICXR
Clear IRIC in ICCR
ICDRF = 1?
No
[1] Initialization. Select slave receive mode.
[2] Read the receive data remaining unread.
Yes
ReadICDR, clear IRIC
[3] to [7] Wait for one byte to be received (slave address + R/W)
Read IRIC in ICCR
No
IRIC = 1?
Yes
[8] Clear IRIC
Clear IRIC in ICCR
Read AASX, AAS and ADZ in ICSR
Yes
AAS = 1
and ADZ = 1?
General call address processing
No
* Description omitted
Read TRS in ICCR
Yes
TRS = 1?
Slave transmit mode
No
Last reception?
No
Yes
Read ICDR
[10] Read the receive data. The first read is a dummy read.
[5] to [7] Wait for the reception to end.
Read IRIC in ICCR
No
IRIC = 1?
Yes
[8] Clear IRIC
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Read ICDR
[5] to [7] Wait for the reception to end.
or
[11] Detect stop condition
Read IRIC in ICCR
No
[9] Set acknowledge data for the last reception.
[10] Read the receive data.
IRIC = 1?
Yes
ESTP = 1 or
STOP = 1?
[12] Check STOP
Yes
No
Clear IRIC in ICCR
[8] Clear IRIC
Clear IRIC in ICCR
[12] Clear IRIC
End
Figure 15.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
Rev. 3.00, 03/04, page 479 of 830
The reception procedure and operations using the HNDS bit function by which data reception
process is provided in 1-byte unit with SCL being fixed low at every data reception, are described
below.
[1] Initialize the IIC as described in section 15.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and
the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
[2] Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
[3] When the start condition output by the master device is detected, the BBSY flag in ICCR is
set to 1. The master device then outputs the 7-bit slave address, and transmit/receive
direction (R/W), in synchronization with the transmit clock pulses.
[4] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
[5] At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as the acknowledge data.
[6] At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, IRTR flag is also set to 1.
[7] At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive
clock pulse until data is read from ICDR.
[8] Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0.
[9] If the next frame is the last receive frame, set the ACKB bit to 1.
[10] If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the
master device to transfer the next data.
Receive operations can be performed continuously by repeating steps [5] to [10].
[11] When the stop condition is detected (SDA is changed from low to high when SCL is high),
the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1.
[12] Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
Rev. 3.00, 03/04, page 480 of 830
Start condition generation
SCL
(Pin waveform)
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
[7] SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
9
1
2
1
2
3
4
5
6
7
8
9
1
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave address
Bit 7
R/W
Bit 6
Data 1
[6]
A
Interrupt
request
occurrence
IRIC
ICDRF
Address+R/W
ICDRS
ICDRR
Address+R/W
Undefined value
User processing
[2] ICDR read
[8] IRIC clear
[10] ICDR read (dummy read)
Figure 15.18 Slave Receive Mode Operation Timing Example (1)
(MLS = 0, HNDS= 1)
[7] SCL is fixed low until ICDR is read
SCL
(master output)
8
9
1
2
[7] SCL is fixed low until ICDR is read
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Stop condition generation
9
SCL
(slave output)
SDA
(master output)
Bit 0
Bit 7
[6]
Data (n-1)
SDA
(slave output)
Bit 6
[6]
Data (n)
A
[11]
A
IRIC
ICDRF
ICDRS
ICDRR
User processing
Data (n-1)
Data (n-2)
Data (n)
Data (n)
Data (n-1)
[8] IRIC clear [10] ICDR read (Data (n-1))
[9] Set ACKB=1
[8] IRIC clear
[10] ICDR read
(Data (n))
[12] IRIC clear
Figure 15.19 Slave Receive Mode Operation Timing Example (2)
(MLS = 0, HNDS= 1)
Rev. 3.00, 03/04, page 481 of 830
Continuous Receive Operation:
Figure 15.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Slave receive mode
Set MST = 0
and TRS = 0 in ICCR
[1] Select slave receive mode.
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC in ICCR
ICDRF = 1?
No
[2] Read the receive data remaining unread.
Yes
Read ICDR
Clear IRIC in ICCR
[3] to [7] Wait for one byte to be received (slave address + R/W)
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
[8] Clear IRIC
Read AASX, AAS and ADZ in ICSR
AAS = 1
and ADZ = 1?
Yes
General call address processing
* Description omitted
No
Read TRS in ICCR
TRS = 1?
Yes
Slave transmit mode
No
(n-2)th-byte
reception?
No
[9] Wait for ACKB setting and set acknowledge data
for the last reception
(after the rise of the 9th clock of (n-1)th byte data)
Wait for one frame
Set ACKB = 1 in ICSR
ICDRF = 1?
* n: Address + total number of bytes received
No
[10] Read the receive data. The first read is a dummy read.
Yes
Read ICDR
[11] Wait for one byte to be received
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
ESTP = 1 or
STOP = 1?
Yes
[12] Detect stop condition
No
Clear IRIC in ICCR
ICDRF = 1?
[13] Clear IRIC
No
[14] Read the last receive data
Yes
Read ICDR
Clear IRIC in ICCR
[15] Clear IRIC
End
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
Rev. 3.00, 03/04, page 482 of 830
The reception procedure and operations in slave receive are described below.
[1] Initialize the IIC as described in section 15.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB
bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
[2] Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
[3] When the start condition output by the master device is detected, the BBSY flag in ICCR is
set to 1. The master device then outputs the 7-bit slave address, and transmit/receive
direction (R/W) in synchronization with the transmit clock pulses.
[4] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
[5] At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as the acknowledge data.
[6] At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, the IRTR flag is also set to 1.
[7] At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1.
[8] Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0.
[9] If the next read data is the third last receive frame, wait for at least one frame time to set the
ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive
frame.
[10] Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0.
[11] At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to
ICDRR due to ICDR read operation, The IRIC and ICDRF flags are set to 1.
[12] When the stop condition is detected (SDA is changed from low to high when SCL is high),
the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has
been cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last
receive data.
[13] Clear the IRIC flag to 0.
Receive operations can be performed continuously by repeating steps [9] to [13].
[14] Confirm that the ICDRF flag is set to 1, and read ICDR.
[15] Clear the IRIC flag.
Rev. 3.00, 03/04, page 483 of 830
Start condition issuance
SCL
(master output)
SDA
(master output)
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Slave address
8
9
1
Bit 7
Bit 0
R/W
SDA
(slave output)
[6]
2
3
4
Bit 6
Bit 5
Bit 4
Data 1
A
IRIC
ICDRF
ICDRS
Address+R/W
Data 1
[7]
ICDRR
Address+R/W
User processing
[8] IRIC clear
[10] ICDR read
Figure 15.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)
Stop condition detection
SCL
(master output)
8
9
SDA
(master output) Bit 0
Data (n-2)
SDA
(slave output)
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data (n-1)
A
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data (n)
A
[11]
[12]
A
IRIC
ICDRF
ICDRS
Data (n-2)
ICDRR
Data (n-1)
Data (n-2)
[9] Wait for one frame
User processing
[13] IRIC clear
Data (n)
Data (n-1)
[13] IRIC clear [10] ICDR read
[10] ICDR read
(Data (n-1))
(Data (n-2))
[9] Set ACKB = 1
Data (n)
[13] IRIC clear
[14] ICDR read
(Data (n))
[15] IRIC clear
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)
Rev. 3.00, 03/04, page 484 of 830
15.4.6
Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 15.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode
Clear IRIC in ICCR
[1], [2] If the slave address matches to the address in the first frame
following the start condition detection and the R/W bit is 1
in slave receive mode, the mode changes to slave transmit mode.
[3], [5] Set transmit data for the second and subsequent bytes.
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
[3], [4] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
[4] Determine end of transfer.
End
of transmission
(ACKB = 1)?
No
Yes
Clear IRIC in ICCR
Clear ACKE to 0 in ICCR
(ACKB=0 clear)
Set TRS = 0 in ICCR
Read ICDR
Read IRIC in ICCR
No
[6] Clear IRIC in ICCR
[7] Clear acknowledge bit data
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
IRIC = 1?
Yes
Clear IRIC in ICCR
End
Figure 15.23 Sample Flowchart for Slave Transmit Mode
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
Rev. 3.00, 03/04, page 485 of 830
[1] Initialize slave receive mode and wait for slave address reception.
[2] When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
ICDRE flag is set to 1. The slave device drives SCL low from the fall of the 9th transmit
clock until ICDR data is written, to disable the master device to output the next transfer
clock.
[3] After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared
to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1
again. The slave device sequentially sends the data written into ICDRS in accordance with
the clock output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
register writing to the IRIC flag clearing should be performed continuously. Prevent any
other interrupt processing from being inserted.
[4] The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to
determine whether the transfer operation was performed successfully. When one frame of
data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit
clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS
and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this
slave device drives SCL low from the fall of the 9th transmit clock until data is written to
ICDR.
[5] To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is
cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from
the ICDR register writing to the IRIC flag clearing should be performed continuously.
Prevent any other interrupt processing from being inserted.
Transmit operations can be performed continuously by repeating steps [4] and [5].
[6] Clear the IRIC flag to 0.
[7] To end transmission, clear the ACKE bit in the ICCR register to 0, to clear the acknowledge
bit stored in the ACKB bit to 0.
[8] Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
[9] Dummy-read ICDR to release SCL on the slave side.
[10] When the stop condition is detected, that is, when SDA is changed from low to high when
SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1.
When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it
is cleared to 0.
Rev. 3.00, 03/04, page 486 of 830
Slave transmit mode
Slave receive mode
SCL
(master output)
8
SDA
(slave output)
9
1
2
A
Bit 7
Bit 6
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 1
[2]
SDA
(master output) R/W
9
1
2
Bit 7
Bit 6
[4]
Data 2
A
IRIC
ICDRE
ICDR
User processing
Data 2
Data 1
[3] IRIC clear
[3] ICDR write
[3] IRIC clear
[5] IRIC clear
[5] ICDR write
Figure 15.24 Slave Transmit Mode Operation Timing Example
(MLS = 0)
Rev. 3.00, 03/04, page 487 of 830
15.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figures 15.25 to 15.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
SDA
7
8
9
7
8
A
1
1
2
2
3
3
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
7
8
9
1
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 15.25 IRIC Setting Timing and SCL Control (1)
Rev. 3.00, 03/04, page 488 of 830
Clear IRIC
When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
SDA
8
9
1
2
3
8
A
1
2
3
IRIC
User processing
Clear IRIC
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
8
9
1
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 15.26 IRIC Setting Timing and SCL Control (2)
Rev. 3.00, 03/04, page 489 of 830
When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
SDA
7
8
7
8
1
1
2
2
3
3
4
4
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
7
8
1
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 15.27 IRIC Setting Timing and SCL Control (3)
15.4.8
Operation Using the DTC
This LSI provides the DTC to allow continuous data transfer. IIC_4 and IIC_5 cannot use the
DTC. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags
(IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of
data transmission regardless of the acknowledge bit value. When the ACKE bit is 1, the ICDRE,
IRIC, and IRTR flags are set if data transmission is completed with the acknowledge bit value of
0, and when the ACKE bit is 1, only the IRIC flag is set if data transmission is completed with the
acknowledge bit value of 1.
When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags
to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is
not initiated, thus allowing an interrupt to be generated if enabled.
Rev. 3.00, 03/04, page 490 of 830
The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,
indicating no specific events.
The I2C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 15.9 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 15.9 Examples of Operation Using the DTC
Item
Master Transmit
Mode
Slave address + Transmission by
R/W bit
DTC (ICDR write)
transmission/
reception
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read

Processing by
CPU (ICDR read)


Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write


Processing by
DTC (ICDR write)

Last frame
processing
Not necessary
Reception by
CPU (ICDR read)
Not necessary
Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
Not necessary
Automatic clearing Not necessary
on detection of
stop condition
during
transmission of
dummy data (H'FF)
Setting of
number of DTC
transfer data
frames
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
2nd time: Stop
condition issuance
by CPU
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Rev. 3.00, 03/04, page 491 of 830
15.4.9
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.28 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or
SDA input
signal
D
C
Q
Latch
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
System clock
cycle
Sampling
clock
Figure 15.28 Block Diagram of Noise Canceler
15.4.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with clearing ICE bit.
Scope of Initialization: The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR(other than ICDRE and
ICDRF))
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, and ICSR registers
Rev. 3.00, 03/04, page 492 of 830
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the ICE bit clearing.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the ICE bit clearing.
4. Initialize (re-set) the IIC registers.
Rev. 3.00, 03/04, page 493 of 830
15.5
Interrupt Source
The IIC interrupt source is IICI. The IIC interrupt sources and their priority order are shown in
table 15.10. Each interrupt source is enabled or disabled by the ICCR interrupt enable bit and
transferred to the interrupt controller independently.
The IICI0 to IICI3 interrupts can be used as sources of activating the on-chip DTC.
Table 15.10 IIC Interrupt Source
Channel
Bit
Name
Enable
Bit
Interrupt Source
2
Interrupt
Flag
DTC Activation Priority
2
IICI2
IEIC
I C bus interface interrupt
request
IRIC
Possible
3
IICI3
IEIC
I2C bus interface interrupt
request
IRIC
Possible
0
IICI0
IEIC
I2C bus interface interrupt
request
IRIC
Possible
1
IICI1
IEIC
I2C bus interface interrupt
request
IRIC
Possible
4
IICI4
IEIC
I2C bus interface interrupt
request
IRIC
Not possible
5
IICI5
IEIC
I2C bus interface interrupt
request
IRIC
Not possible
Rev. 3.00, 03/04, page 494 of 830
High
Low
15.6
Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions*, after issuing the instruction that generates the start
condition, read the relevant DR registers of I2C bus output pins, check that SCL and SDA are
both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then
issue the instruction that generates the stop condition. Note that SCL may not yet have gone
low when BBSY is cleared to 0.
Note: * An illegal procedure in the I2C bus specification.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 15.11 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 15.11 I2C Bus Timing (SCL and SDA Outputs)
Item
Symbol Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28tcyc to 512tcyc
ns
See figure
SCL output high pulse width
tSCLHO
0.5tSCLO
ns
SCL output low pulse width
tSCLLO
0.5tSCLO
ns
25.30
(reference)
SDA output bus free time
tBUFO
0.5tSCLO – 1tcyc
ns
Start condition output hold time
tSTAHO
0.5tSCLO – 1tcyc
ns
Retransmission start condition output
setup time
tSTASO
1tSCLO
ns
Stop condition output setup time
tSTOSO
0.5tSCLO + 2tcyc
ns
Data output setup time (master)
tSDASO
1tSCLLO – 3tcyc
ns
Data output setup time (slave)
Data output hold time
Note:
*
1tSCLLO – (6tcyc or 12tcyc*)
tSDAHO
3tcyc
ns
6tcyc when IICXn is 0, 12tcyc when IICXn is 1 (n = 0 to 5).
Rev. 3.00, 03/04, page 495 of 830
4. SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in section 25, Electrical
Characteristics. Note that the I2C bus interface AC timing specification will not be met with a
system clock frequency of less than 5 MHz.
5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 15.12.
Table 15.12 Permissible SCL Rise Time (tsr) Values
Time Indication [ns]
2
TCSS IICXn
tcyc
Indication
0
7.5 tcyc
0
I C Bus
Specification
φ=5
(Max.) MHz
φ=8
MHz
φ = 10
MHz
φ = 16
MHz
φ = 20
MHz
φ = 25
MHz
φ = 33
MHz
Standard 1000
mode
1000
937
750
468
375
300
227
Highspeed
mode
300
300
300
300
300
300
227
1000
1000
1000
1000
875
700
530
300
300
300
300
300
300
300
1000
1000
1000
1000
1000
1000
1000
300
300
300
300
300
300
300
300
1
17.5 tcyc Standard 1000
mode
1
0
Highspeed
mode
1
1
37.5 tcyc Standard 1000
mode
Highspeed
mode
300
300
Note: n = 0 to 5
6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
table 15.11. However, because of the rise and fall times, the I2C bus interface specifications
may not be satisfied at the maximum transfer rate. Table 15.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
Rev. 3.00, 03/04, page 496 of 830
tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I2C bus.
Rev. 3.00, 03/04, page 497 of 830
Table 15.13 I2C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
I2C Bus
tcyc
tSr/tSf
Specifi-
φ=
φ=
φ=
φ=
φ=
φ=
φ=
Indi-
Influence
cation
5 MHz
8 MHz
10
16
20
25
33
Item
cation
(Max.)
(Min.)
MHz
MHz
MHz
MHz
MHz
tSCLHO
0.5 tSCLO
Standard
–1000
4000
4000
4000
4000
4000
4000
4000
4000*1
(–tSr)
mode
–300
600
2500
1450
1100
950
950
950
950
–250
4700
4750
4750
4750
4750
4750
4750
4750*1
–250
1300
2550
1500
1150*1
1000*1
1000*1
1000*1
1000*1
–1000
4700
3800*1
3875*1
3900*1
3938*1
3950*1
3960*1
3970*1
–300
1300
2300
1325
1000*1
888*1
900*1
910*1
920*1
–250
4000
4550
4625
4650
4688
4700
4710
4720*1
–250
600
2350
1375
1050
938
950
960
970
–1000
4700
9000
9000
9000
9000
9000
9000
9000
–300
600
5300
3200
2500
2200
2200
2200
2200
–1000
4000
4400
4250
4200
4125
4100
4080
4061*1
–300
600
2900
1700
1300
1075
1050
1030
1011
–1000
250
3150
3375
3450
3563
3600
3630
3659
–300
100
1650
825
550
513
550
580
609
–1000
250
1300
2200
2500
2950
3100
3220
3336
–300
100
–1400*1 –500*1
–200*1
250
400
520
636
High-speed
mode
tSCLLO
0.5 tSCLO
Standard
(–tSf )
mode
High-speed
mode
tBUFO
0.5 tSCLO
Standard
–1 tcyc
mode
( –tSr )
High-speed
mode
tSTAHO
0.5 tSCLO
Standard
–1 tcyc
mode
(–tSf )
High-speed
mode
tSTASO
1 tSCLO
Standard
(–tSr )
mode
High-speed
mode
tSTOSO
0.5 tSCLO
Standard
+ 2 tcyc
mode
(–tSr )
High-speed
mode
tSDASO
1 tSCLLO*3
Standard
(master)
–3 tcyc
mode
(–tSr )
High-speed
mode
tSDASO
(slave)
1 tSCLL*3
Standard
2
–12 tcyc*
(–tSr )
mode
High-speed
mode
Rev. 3.00, 03/04, page 498 of 830
Time Indication (at Maximum Transfer Rate) [ns]
I2C Bus
tcyc
tSr/tSf
Specifi-
φ=
φ=
φ=
φ=
φ=
Indi-
Influence
cation
φ=
φ=
10
16
20
25
33
Item
cation
(Max.)
(Min.)
5 MHz
8 MHz
MHz
MHz
MHz
MHz
MHz
tSDAHO
3 tcyc
0
0
600
375
300
188
150
120
91
0
0
600
375
300
188
150
120
91
Standard
mode
High-speed
mode
Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the bits TCSS,
IICX5 to IICX0 and CKS0 to CKS2. Depending on the frequency it may not be possible
2
to achieve the maximum transfer rate; therefore, whether or not the I C bus interface
specifications are met must be determined in accordance with the actual setting
conditions.
2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is
(– 6tcyc) (n = 0 to 5).
2
3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
7. Notes on ICDR register read at end of master reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 15.29 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Rev. 3.00, 03/04, page 499 of 830
Stop condition
Start condition
(a)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
ICDR read
disabled period
Execution of instruction
for issuing stop condition
(write 0 to BBSY and SCP)
Confirmation of stop
condition issuance
(read BBSY = 0)
Start condition
issuance
Figure 15.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
8. Notes on start condition issuance for retransmission
Figure 15.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
Rev. 3.00, 03/04, page 500 of 830
No
IRIC = 1?
[1] Wait for end of 1-byte transfer
[1]
Yes
[2] Determine whether SCL is low
Clear IRIC in ICCR
[3] Issue start condition instruction for retransmission
Read SCL pin
No
SCL = Low?
[4] Determine whether start condition is generated or not
[2]
Yes
[5] Set transmit data (slave address + R/W)
Set BBSY = 1,
SCP = 0 (ICCR)
[3]
No
IRIC = 1?
[4]
Note: Program so that processing from [3] to [5]
is executed continuously.
Yes
Write transmit data to ICDR
[5]
Start condition generation
(retransmission)
SCL
9
SDA
ACK
Bit 7
IRIC
[5] ICDR write (transmit data)
[4] IRIC determination
[3] (Retransmission) Start condition instruction issuance
[2] Determination of SCL = Low
[1] IRIC determination
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission and
Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
Rev. 3.00, 03/04, page 501 of 830
9. Note on when I2C bus interface stop condition instruction is issued
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low.
SCL
Secures a high period
9th clock
VIH
SCL is detected as low
because the rise of the
waveform is delayed
SDA
Stop condition generation
IRIC
[1] SCL = low determination
[2] Stop condition instruction issuance
Figure 15.31 Stop Condition Issuance Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
10. Note on IRIC flag clear when the wait function is used
When the wait function is used in I2C bus interface master mode and in a situation where the
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
Secures a high period
SCL
VIH
SCL = low detected
SDA
IRIC
[1] SCL = low determination
[2] IRIC clear
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1
Rev. 3.00, 03/04, page 502 of 830
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
11. Note on ICDR register read and ICCR register access in slave transmit mode
In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 15.33. However, such read and write operations source no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
 Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
 Monitor the BC2 to BC0 counter in ICMR; when the count is B'000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
Waveform at problem occurrence
SDA
R/W
A
SCL
8
9
TRS bit
Bit 7
Address reception
Data transmission
ICDR read and ICCR read/write are disabled
ICDR write
(6 system clock period)
The rise of the 9th clock is detected
Figure 15.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit
Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 3.00, 03/04, page 503 of 830
12. Note on TRS bit setting in slave mode
In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 15.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 15.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 15.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
Restart condition
(a)
(b)
A
SDA
SCL
TRS
8
9
1
Data
transmission
2
3
4
5
6
7
8
9
Address reception
TRS bit setting is suspended in this period
ICDR dummy read
TRS bit setting
The rise of the 9th clock is detected
The rise of the 9th clock is detected
Figure 15.34 TRS Bit Set Timing in Slave Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
13. Note on ICDR read in transmit mode and ICDR write in receive mode
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive
mode or write to the ICDR after setting transmit mode.
Rev. 3.00, 03/04, page 504 of 830
14. Note on ACKE and TRS bits in slave mode
In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition and address are transmitted from the
master device in slave transmit mode (TRS = 1), the ICDRE flag is set, and 1 is received as the
acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source
even when the address does not match.
To use the I2C bus interface module in slave mode, be sure to follow the procedures below.
 When having received 1 as the acknowledge bit value for the last transmit data at the end
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
 Set receive mode (TRS = 0) before the next start condition is input in slave mode.
Complete transmit operation by the procedure shown in figure 15.23, in order to switch
from slave transmit mode to slave receive mode.
15. Notes on Arbitration Lost in Master Mode Operation
The I2C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I2C bus interface erroneously recognizes that the address call has occurred. (See
figure 15.35.)
In multi-master mode, a bus conflict could happen. When the I2C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Rev. 3.00, 03/04, page 505 of 830
• Arbitration is lost
• The AL flag in ICSR is set to 1
I2C bus interface
(Master transmit mode)
S
SLA
R/W
A
DATA1
Transmit data match
Transmit timing match
Other device
(Master transmit mode)
S
SLA
R/W
A
Transmit data does not match
DATA2
A
DATA3
A
Data contention
I2C bus interface
(Slave receive mode)
S
SLA
R/W
A
• Receive address is ignored
SLA
R/W
A
DATA4
A
• Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device.
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost
Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode.
When the MST bit is set to 1 during data transmission or reception in slave mode, the
arbitration decision circuit is enabled and arbitration is lost if conditions are satisfied. In this
case, the transmit/receive data which is not an address may be erroneously recognized as an
address.
In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may
occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order
below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Note: Above restrictions can be released by setting the bits FNC1 and FNC2 in ICXR to B'11.
Rev. 3.00, 03/04, page 506 of 830
Section 16 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. The LPC
interface operates as a slave and supports only I/O read cycle and I/O write cycle transfer.
It is also provided with power-down functions that can control the PCI clock and shut down the
LPC interface.
16.1
Features
• Supports LPC interface I/O read cycles and I/O write cycles
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Has three register sets comprising data and status registers
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
Channels 1 to 3 have fixed I/O addresses of H'0000 to H'FFFF, respectively.
A fast A20 gate function is also provided.
Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set.
• Supports SERIRQ
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
• Power-down functions, interrupts, etc.
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
• Supports version 1.5 of the Intelligent Platform Management Interface (IPMI)
Channel 3 supports the SMIC interface, KCS interface, and BT interface.
IFHSTL1A_010020030700
Rev. 3.00, 03/04, page 507 of 830
Figure 16.1 shows a block diagram of the LPC.
Module data bus
TWR0MW
IDR3
IDR2
IDR1
BTDTR
FIFO TWR1 to 15
(IN)
Parallel → serial conversion
SERIRQ
CLKRUN
SIRQCR0
SIRQCR1
Cycle detection
SIRQCR2
Serial → parallel conversion
LPCPD
Control logic
HISEL
LFRAME
Address match
LRESET
LADR1
LADR2
PD0 I/O
LSCI
PD1 I/O
LSMI
PD2 I/O
PME
LSMIE
LSMIB
LSMI input
LADR3
Serial ← parallel conversion
SYNC output
LCLK
LSCIE
LSCIB
LSCI input
LADR12
LAD0 to
LAD3
PMEE
PMEB
PME input
HICR0
HICR1
TWR0SW
BTDTR
FIFO TWR1 to 15
(OUT)
ODR3
ODR2
ODR1
STR3
STR2
STR1
HICR2
HICR3
Internal interrupt
control
[Legend]
HICR0 to HICR4:
Host interface control register 0 to 4
LADR12H, 12L:
LPC channel 1, 2 address register 12H, 12L
LADR3H, 3L:
LPC channel 3 address register 3H, 3L
IDR1 to IDR3:
Input data register 1 to 3
ODR1 to ODR3:
Output data register 1 to 3
STR1 to STR3:
Status register 1 to 3
TWR0MW:
Bidirectional data register 0MW
TWR0SW:
Bidirectional data register 0SW
TWR1 to TWR15:
Bidirectional data registers 1 to 15
SIRQCR0 to SIRQCR2: SERIRQ control registers 0 to 2
HISEL:
Host interface select register
Figure 16.1 Block Diagram of LPC
Rev. 3.00, 03/04, page 508 of 830
GA20
HICR4
IBFI1
IBFI2
IBFI3
ERRI
16.2
Input/Output Pins
Table 16.1 lists the input and output pins of the LPC.
Table 16.1 Pin Configuration
Name
Abbreviation
LPC address/
data 3 to 0
I/O
Function
LAD3 to LAD0 PE3 to
PE0
I/O
Serial (4-signal-line) transfer cycle
type/address/data signals,
synchronized with LCLK
LPC frame
LFRAME
PE4
Input*1
Transfer cycle start and forced
termination signal
LPC reset
LRESET
PE5
Input*1
LPC interface reset signal
LPC clock
LCLK
PE6
Input
33 MHz PCI clock signal
PE7
1
Serialized
interrupt request
SERIRQ
Port
I/O*
Serialized host interrupt request
signal, synchronized with LCLK
(SMI, HIRQ1, HIRQ6, HIRQ9 to
HIRQ12)
LSCI general
output
LSCI
PD0
Output*1, *2
General output
LSMI general
output
LSMI
PD1
Output*1, *2
General output
PME general
output
PME
PD2
Output*1, *2
General output
GATE A20
GA20
PD3
Output*1, *2
A20 gate control signal output
LPC clock run
CLKRUN
PD4
I/O* *
LCLK restart request signal in case
of serial host interrupt request
LPC power-down
LPCPD
PD5
Input*1
LPC module shutdown signal
1,
2
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
Rev. 3.00, 03/04, page 509 of 830
16.3
Register Descriptions
The LPC registers are listed in the following. Though this LSI accesses these registers as a slave,
some of them can be accessed from the host. For details, see each register description.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Host interface control register 0 (HICR0)
Host interface control register 1 (HICR1)
Host interface control register 2 (HICR2)
Host interface control register 3 (HICR3)
Host interface control register 4 (HICR4)
LPC channel 3 Address register H, L (LADR3H, LADR3L)
LPC channel 1, 2 address register H, L (LADR12H, LADR12L)
Input data register 1 (IDR1)
Input data register 2 (IDR2)
Input data register 3 (IDR3)
Output data register 1 (ODR1)
Output data register 2 (ODR2)
Output data register 3 (ODR3)
Bidirectional data registers 0 to 15 (TWR0 to TWR15)
Status register 1 (STR1)
Status register 2 (STR2)
Status register 3 (STR3)
SERIRQ control register 0 (SIRQCR0)
SERIRQ control register 1 (SIRQCR1)
SERIRQ control register 2 (SIRQCR2)
Host interface select register (HISEL)
SMIC mode:
The following registers are required when SMIC mode is used.
• SMIC flag register (SMICFLG)
• SMIC control status register (SMICCSR)
• SMIC data register (SMICDTR)
• SMIC interrupt register 0 (SMICIR0)
• SMIC interrupt register 1 (SMICIR1)
Rev. 3.00, 03/04, page 510 of 830
BT mode:
The following registers are required when BT mode is used.
• BT status register 0 (BTSR0)
• BT status register 1 (BTSR1)
• BT control status register 0 (BTCSR0)
• BT control status register 1 (BTCSR1)
• BT control register (BTCR)
• BT data buffer (BTDTR)
• BT interrupt mask register (BTIMSR)
• BT FIFO valid size register 0 (BTFVSR0)
• BT FIFO valid size register 1 (BTFVSR1)
Rev. 3.00, 03/04, page 511 of 830
16.3.1
Host Interface Control Registers 0 and 1 (HICR0, HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
HICR0 and HICR1 are initialized to H'00 by a reset or in hardware standby mode.
• HICR0
R/W
Bit
Bit Name Initial Value Slave Host Description
7
6
5
LPC3E
LPC2E
LPC1E
0
0
0
R/W
R/W
R/W



LPC Enable 3 to 1
Enables or disables the LPC interface function.
When the host interface is enabled (at least one of
the three bits is set to 1), processing for data transfer
between the slave processor and the host processor
is performed using pins LAD3 to LAD0, LFRAME,
LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD.
•
LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, TWR0 to TWR15, SMIC, KCS, or BT
1: LPC channel 3 operation is enabled
•
LPC2E
0: LPC channel 2 operation is disabled
No address (LADR2) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
•
LPC1E
0: LPC channel 1 operation is disabled
No address (LADR1) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled
Rev. 3.00, 03/04, page 512 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
4
FGA20E
0
R/W

Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate
can be implemented by firmware operation of the
PD3 output.
When the fast A20 gate function is enabled, the DDR
bit for PD3 must not be set to 1.
0: Fast A20 gate function disabled
•
Other function of the pin is enabled
•
GA20 output internal state is initialized to 1
1: Fast A20 gate function enabled
•
3
SDWNE
0
R/W

GA20 pin output is open-drain (external VCC
pull-up resistor required)
LPC Software Shutdown Enable
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of
initialization by an LPC reset and an LPC shutdown,
see section 16.4.6, LPC Interface Shutdown
Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
•
Writing 0
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown release (rising edge of
LPCPD signal)
1: LPC hardware shutdown state setting enabled
•
Hardware shutdown state when LPCPD signal is
low
[Setting condition]
•
Writing 1 after reading SDWNE = 0
Rev. 3.00, 03/04, page 513 of 830
R/W
Initial
Bit Bit Name Value Slave Host Description
2
PMEE
0
R/W

PME Output Enable
Controls PME output in combination with the PMEB bit in
HICR1. PME pin output is open-drain, and an external pull-up
resistor is needed to pull the output up to VCC
When the PME output function is used, the DDR bit for PD2
must not be set to 1.
PMEE PMEB
1
LSMIE
0
R/W

0
* : PME output disabled, other function of pin is
enabled
1
0 : PME output enabled, PME pin output goes to 0 level
1
1 : PME output enabled, PME pin output is highimpedance
LSMI Output Enable
Controls LSMI output in combination with the LSMIB bit in
HICR1. LSMI pin output is open-drain, and an external pull-up
resistor is needed to pull the output up to VCC
When the LSMI output function is used, the DDR bit for PD1
must not be set to 1.
LSMIE LSMIB
0
LSCIE
0
R/W

0
*
: LSMI output disabled, other function of pin is
enabled
1
0
: LSMI output enabled, LSMI pin output goes to 0
level
1
1
: LSMI output enabled, LSMI pin output is highimpedance
LSCI Output Enable
Controls LSCI output in combination with the LSCIB bit in
HICR1. LSCI pin output is open-drain, and an external pull-up
resistor is needed to pull the output up to VCC
When the LSCI output function is used, the DDR bit for PD0
must not be set to 1.
LSCIE LSCIB
Note:
*
Don't care
Rev. 3.00, 03/04, page 514 of 830
0
*
: LSCI output disabled, other function of pin is
enabled
1
0
: LSCI output enabled, LSCI pin output goes to 0
level
1
1
: LSCI output enabled, LSCI pin output is highimpedance
• HICR1
R/W
Bit
Bit Name Initial Value Slave Host Description
7
LPCBSY
0
R

LPC Busy
Indicates that the LPC interface is processing a
transfer cycle.
0: LPC interface is in transfer cycle wait state
•
•
Bus idle, or transfer cycle not subject to
processing is in progress
Cycle type or address indeterminate during
transfer cycle
[Clearing conditions]
•
•
•
•
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software
shutdown
Forced termination (abort) of transfer cycle
subject to processing
Normal termination of transfer cycle subject to
processing
1: LPC interface is performing transfer cycle
processing
[Setting condition]
•
6
CLKREQ 0
R

Match of cycle type and address
LCLK Request
Indicates that the LPC interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
•
•
•
•
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software
shutdown
SERIRQ is set to continuous mode
There are no further interrupts for transfer to the
host in quiet mode
1: LCLK restart request issued
[Setting condition]
•
In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped
Rev. 3.00, 03/04, page 515 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
5
IRQBSY
0
R

SERIRQ Busy
Indicates that the LPC interface's SERIRQ signal is
engaged in transfer processing.
0: SERIRQ transfer frame wait state
[Clearing conditions]
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown or LPC software
shutdown
•
End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress
[Setting condition]
•
4
LRSTB
0
R/W

Start of SERIRQ transfer frame
LPC Software Reset Bit
Resets the LPC interface. For the scope of
initialization by an LPC reset, see section 16.4.6,
LPC Interface Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
•
Writing 0
•
LPC hardware reset
1: LPC software reset state
[Setting condition]
•
Rev. 3.00, 03/04, page 516 of 830
Writing 1 after reading LRSTB = 0
R/W
Bit
Bit Name Initial Value Slave Host Description
3
SDWNB
0
R/W

LPC Software Shutdown Bit
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of
initialization by an LPC reset and an LPC shutdown,
see section 16.4.6, LPC Interface Shutdown
Function (LPCPD).
0: Normal state
[Clearing conditions]
•
Writing 0
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown
(falling edge of LPCPD signal when SDWNE = 1)
•
LPC hardware shutdown release
(rising edge of LPCPD signal when SDWNE = 0)
1: LPC software shutdown state
[Setting condition]
•
2
PMEB
0
R/W

Writing 1 after reading SDWNB = 0
PME Output Bit
Controls PME output by the combination with the
PMEE bit.
For details, see the PMEE bit in HICR0.
1
LSMIB
0
R/W

LSMI Output Bit
Controls LSMI output by the combination with the
LSMIE bit.
For details, see the LSMIE bit in HICR0.
0
LSCIB
0
R/W

LSCI Output Bit
Controls LSCI output by the combination with the
LSCIE bit.
For details, see the LSCIE bit in HICR0.
Rev. 3.00, 03/04, page 517 of 830
16.3.2
Host Interface Control Registers 2 and 3 (HICR2, HICR3)
The bits 6 to 0 in HICR2 control interrupts from the LPC interface module to the slave processor
(this LSI). HICR3 and the bit 7 of HICR2 monitor the LPC interface pin states.
Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby mode. The states of
the other bits are determined by the pin states.
The pin states can be monitored regardless of the LPC interface operating state or the operating
state of the functions that use pin multiplexing.
• HICR2
R/W
Bit
Bit Name Initial Value Slave Host Description
7
GA20
Undefined
R
6
LRST
0
R/(W)* 

GA20 Pin Monitor
LPC Reset Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware reset occurs.
0: [Clearing condition]
•
Writing 0 after reading LRST = 1
1: [Setting condition]
•
5
SDWN
0
R/(W)* 
LRESET pin falling edge detection
LPC Shutdown Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware shutdown request is generated.
0: [Clearing conditions]
•
Writing 0 after reading SDWN = 1
•
LPC hardware reset
•
LPC software reset
1: [Setting condition]
•
Rev. 3.00, 03/04, page 518 of 830
LPCPD pin falling edge detection
R/W
Bit
Bit Name Initial Value Slave Host Description
4
ABRT
0
R/(W)* 
LPC Abort Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
a forced termination (abort) of an LPC transfer cycle
occurs.
0: [Clearing conditions]
•
Writing 0 after reading ABRT = 1
•
LPC hardware reset
•
LPC software reset
•
LPC hardware shutdown
•
LPC software shutdown
1: [Setting condition]
•
3
IBFIE3
0
R/W

LFRAME pin falling edge detection during LPC
transfer cycle
IBFI3 Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are disabled
1: [When TWRE in LADR3 = 0]
Input data register IDR3 receive completed
interrupt request and SMIC mode and BT mode
interrupt requests are enabled
[When TWRE in LADR3 = 1]
Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are enabled
2
IBFIE2
0
R/W

IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register IDR2 receive completed
interrupt requests disabled
1: Input data register IDR2 receive completed
interrupt requests enabled
Rev. 3.00, 03/04, page 519 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IBFIE1
0
R/W

IDR1 Receive Completion Interrupt Enable
Enables or disables IBFI1 interrupt to the slave
processor (this LSI).
0: Input data register IDR1 receive completed
interrupt requests disabled
1: Input data register IDR1 receive completed
interrupt requests enabled
0
ERRIE
0
R/W

Error Interrupt Enable
Enables or disables ERRI interrupt to the slave
processor (this LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note:
*
Only 0 can be written to clear bits 6 to 4.
• HICR3
R/W
Bit
Bit Name Initial Value Slave Host Description
7
LFRAME Undefined
R

LFRAME Pin Monitor
6
CLKRUN Undefined
R

CLKRUN Pin Monitor
5
SERIRQ
Undefined
R

SERIRQ Pin Monitor
4
LRESET
Undefined
R

LRESET Pin Monitor
3
LPCPD
Undefined
R

LPCPD Pin Monitor
2
PME
Undefined
R

PME Pin Monitor
1
LSMI
Undefined
R

LSMI Pin Monitor
0
LSCI
Undefined
R

LSCI Pin Monitor
Rev. 3.00, 03/04, page 520 of 830
16.3.3
Host Interface Control Register 4 (HICR4)
HICR4 controls the selection of access channel when setting addresses for LPC channels 1 and 2,
and the operation of KCS, SMIC, and BT interfaces included in channel 3.
R/W
Bit
Bit Name
Initial Value Slave Host Description
7
LADR12SEL 0
R/W

Switches the access channel of LADR12H,
LAD12L.
0: LADR1 is selected
1: LADR2 is selected
6 to 4 
All 0
R/W

Reserved
3
0
R/W

In BT mode, H'5 (short wait) or H'6 (long wait) is
returned to the host in the synchronized return
cycle from slave, thus can make the host wait.
The initial value should not be changed.
SWENBL
0: Short wait is issued
1: Long wait is issued
2
KCSENBL
0
R/W

Enables or disables the use of the KCS interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: KCS interface operation is disabled
No address (LADR3) matches for IDR3, ODR3,
or STR3 in KCS mode
1: KCS interface operation is enabled
1
SMICENBL
0
R/W

Enables or disables the use of the SMIC interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: SMIC interface operation is disabled
No address (LADR3) matches for SMICFLG,
SSMICCSR, or SMICDTR
1: SMIC interface operation is enabled
0
BTENBL
0
R/W

Enables or disables the use of the BT interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: BT interface operation is disabled
No address (LADR3) matches for BTIMSR,
BTCR, or BTDTR
1: BT interface operation is enabled
Rev. 3.00, 03/04, page 521 of 830
16.3.4
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
R/W
Bit
Bit Name Initial Value Slave Host
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
All 0
R/W

Description
Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
• LADR3L
R/W
Bit
Bit Name Initial Value Slave Host
7
6
5
4
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
All 0
2

0
R/W

Reserved
1
Bit 1
0
R/W

Channel 3 Address Bit 1
R/W

Description
Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
The initial value should not be changed.
The host address of LPC channel 3 is set.
0
TWRE
0
R/W

Bidirectional data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
TWR-related address (LADR3) match does not
occur.
1: TWR operation is enabled
Rev. 3.00, 03/04, page 522 of 830
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3,
ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address
match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of
bits 3 to 0 are ignored.
Register selection according to the bits ignored in address match determination is as shown in the
following table.
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register
Selection
Bits 15 to5
Bit 4
Bit 3
0
Bit 1
0
I/O write
IDR3 write, C/D3 ← 0
Bits 15 to5
Bit 4
Bit 3
1
Bit 1
0
I/O write
IDR3 write, C/D3 ← 1
Bits 15 to5
Bit 4
Bit 3
0
Bit 1
0
I/O read
ODR3 read
Bits 15 to5
Bit 4
Bit 3
1
Bit 1
0
I/O read
STR3 read
Bits 15 to5
Bit 4
0
0
0
0
I/O write
TWR0MW write
Bits 15 to5
Bit 4
0
0
0
1
I/O write
TWR1 to TWR15
write
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
Bits 15 to5
Bit 4
0
0
0
0
I/O read
TWR0SW read
Bits 15 to5
Bit 4
0
0
0
1
I/O read
TWR1 to TWR15
read
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
Rev. 3.00, 03/04, page 523 of 830
• KCS mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
0
0
1
0
I/O write
IDR3 write, C/D3 ← 0
Bits 15 to5
Bit 4
0
0
1
1
I/O write
IDR3 write, C/D3 ← 1
Bits 15 to5
Bit 4
0
0
1
0
I/O read
ODR3 read
Bits 15 to5
Bit 4
0
0
1
1
I/O read
STR3 read
• BT mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
0
1
0
0
I/O write
BTCR write
Bits 15 to5
Bit 4
0
1
0
1
I/O write
BTDTR write
Bits 15 to5
Bit 4
0
1
1
0
I/O write
BTIMSR write
Bits 15 to5
Bit 4
0
1
0
0
I/O read
BTCR read
Bits 15 to5
Bit 4
0
1
0
1
I/O read
BTDTR read
Bits 15 to5
Bit 4
0
1
1
0
I/O read
BTIMSR read
• SMIC mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
1
0
0
1
I/O write
SMICDTR write
Bits 15 to5
Bit 4
1
0
1
0
I/O write
SMICCSR write
Bits 15 to5
Bit 4
1
0
1
1
I/O write
SMICFLG write
Bits 15 to5
Bit 4
1
0
0
1
I/O read
SMICDTR read
Bits 15 to5
Bit 4
1
0
1
0
I/O read
SMICCSR read
Bits 15 to5
Bit 4
1
0
1
1
I/O read
SMICFLG read
Rev. 3.00, 03/04, page 524 of 830
• Notes on determining address match
The IDR3/ODR3/STR3 addresses depend on mode.
LPC3 SELS KCSE
SMIC BTEN
E
TR3
NBL TWRE ENBL BL
Accessible Mode
IDR3/ODR3/STR3
Host Addresses
STR3:TWR
Related Bit
0
*
*
*
*
*
Channel 3 access Access disabled
disabled
Access disabled
1
0
0
0
0
0
Normal mode
LADR3+0/+4
TWR flag bit
1
0
0
0
0
1
BT mode
Access disabled
Access disabled
1
0
0
0
1
0
SMIC mode
Access disabled
Access disabled
1
0
0
0
1
1
SMIC/BT mode
Access disabled
Access disabled
1
0
0
1
0
0
TWR mode
LADR3+0/+4
TWR flag bit
1
0
0
1
0
1
TWR/BT mode
LADR3+2/+3
TWR flag bit
1
0
0
1
1
0
TWR/SMIC mode LADR3+2/+3
TWR flag bit
1
0
0
1
1
1
TWR/SMIC/BT
mode
TWR flag bit
1
0
1
0
0
0
KCS mode
LADR3+2/+3
TWR flag bit
1
0
1
0
0
1
KCS/BT mode
LADR3+2/+3
TWR flag bit
1
0
1
0
1
0
KCS/SMIC mode LADR3+2/+3
TWR flag bit
1
0
1
0
1
1
KCS/SMIC/BT
mode
LADR3+2/+3
TWR flag bit
1
1
0
0
0
0
Normal mode
LADR3+0/+4
User definition bit
1
1
0
0
0
1
BT mode
Access disabled
Access disabled
1
1
0
0
1
0
SMIC mode
Access disabled
Access disabled
1
1
0
0
1
1
SMIC/BT mode
Access disabled
Access disabled
1
1
0
1
0
0
TWR mode
LADR3+0/+4
TWR flag bit
1
1
0
1
0
1
TWR/BT mode
LADR3+2/+3
TWR flag bit
1
1
0
1
1
0
TWR/SMIC mode LADR3+2/+3
TWR flag bit
1
1
0
1
1
1
TWR/SMIC/BT
mode
TWR flag bit
1
1
1
0
0
0
KCS mode
LADR3+2/+3
User definition bit
1
1
1
0
0
1
KCS/BT mode
LADR3+2/+3
User definition bit
1
1
1
0
1
0
KCS/SMIC mode LADR3+2/+3
User definition bit
1
1
1
0
1
1
KCS/SMIC/BT
mode
User definition bit
1
*
1
1
*
*
Setting prohibited Setting prohibited
Note:
*
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
Setting prohibited
Don't care
Rev. 3.00, 03/04, page 525 of 830
16.3.5
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 16.2 shows the initial value of each register. Table 16.3 shows the host register selection in
address match determination. Table 16.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 16.2 LADR1, LADR2 Initial Values
Register Name
Initial Value
Description
LADR1
H'0060
I/O address of channel 1
LADR2
H'0062
I/O address of channel 2
Table 16.3 Host Register Selection
I/O Address
Bits 15 to 3
Bit 2 Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
LADR1 (bits 15 to 3) 0
LADR1 (bit 1)
LADR1 (bit 0) I/O write
IDR1 write (data),
C/D1 ← 0
LADR1 (bits 15 to 3) 1
LADR1 (bit 1)
LADR1 (bit 0) I/O write
IDR1 write (command),
C/D1 ← 1
LADR1 (bits 15 to 3) 0
LADR1 (bit 1)
LADR1 (bit 0) I/O read
ORD1 read
LADR1 (bits 15 to 3) 1
LADR1 (bit 1)
LADR1 (bit 0) I/O read
STR1 read
LADR2 (bits 15 to 3) 0
LADR2 (bit 1)
LADR2 (bit 0) I/O write
IDR2 write (data),
C/D2 ← 0
LADR2 (bits 15 to 3) 1
LADR2 (bit 1)
LADR2 (bit 0) I/O write
IDR2 write (command),
C/D2 ← 1
LADR2 (bits 15 to 3) 0
LADR2 (bit 1)
LADR2 (bit 0) I/O read
ODR2 read
LADR2 (bits 15 to 3) 1
LADR2 (bit 1)
LADR2 (bit 0) I/O read
STR2 read
Rev. 3.00, 03/04, page 526 of 830
Table 16.4 Slave Selection Internal Registers
Slave (R/W) Bus Width (B/W) LADR12SEL
LADR12
Internal Register
R/W
B
0
LADR12H
LADR1H
R/W
B
1
LADR12H
LADR2H
R/W
B
0
LADR12L
LADR1L
R/W
B
1
LADR12L
LADR2L
R/W
W
0
LADR12H
LADR12L
LADR1H
LADR1L
R/W
W
1
LADR12H
LADR12L
LADR2H
LADR2L
16.3.6
Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit writeonly registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on IDR1 and IDR2 selection, see
section 16.3.5, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on IDR3 selection, see section 16.3.4, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers are undefined.
16.3.7
Output Data Registers 0 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor (this LSI), and 8-bit
read-only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on ODR1 and ODR2 selection, see
section 16.3.5, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on ODR3 selection, see section 16.3.4, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to
the host.
The initial values of the ODR registers are undefined.
Rev. 3.00, 03/04, page 527 of 830
16.3.8
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register to the host processor, and a read-only register to the slave processor, while
TWR0SW is a write-only register to the slave processor and a read-only register to the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 16.3.4, LPC Channel 3 Address Register H, L (LADR3H, LADR3L).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host.
The initial values of TWR0 to TWR15 are undefined.
Rev. 3.00, 03/04, page 528 of 830
16.3.9
Status Registers 1 to 3 (STR1 to STR3)
The STR registers are 8-bit registers that indicate status information during LPC interface
processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the
slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to
bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0. The functions for
bits 7 to 4 in STR3 differ according to the settings of bit SELSTR3 in HISEL and the TWRE bit in
LADR3L. For details, see section 16.3.13, Host Interface Select Register (HISEL). The registers
selected from the host processor according to the I/O address are described in the following
sections. For information on STR1 and STR2 selection, see section 16.3.5, LPC Channel 1,2
Address Register H, L (LADR12H, LADR12L), and information on STR3 selection, see section
16.3.4, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle,
the data in the selected register is transferred to the host processor.
The STR registers are initialized to H'00 by a reset or in hardware standby mode.
• STR1
R/W
Bit
Bit Name Initial Value Slave Host Description
7
6
5
4
DBU17
DBU16
DBU15
DBU14
All 0
3
C/D1
0
R/W
R
Defined by User
The user can use these bits as necessary.
R
R
Command/Data
When the host processor writes to an IDR1 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR1 contains data or a command.
0: Content of input data register (IDR1) is data
1: Content of input data register (IDR1) is a
command
2
DBU12
0
R/W
R
Defined by User
The user can use this bit as necessary.
Rev. 3.00, 03/04, page 529 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IBF1
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR1. This bit is an internal interrupt source to the
slave processor (this LSI).
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 16.7.
0: There is not receive data in IDR1
[Clearing condition]
When the slave processor reads IDR
1: There is receive data in IDR1
[Setting condition]
When the host processor writes to IDR using I/O
write cycle
0
OBF1
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR1.
0: There is not transmit data in ODR1
[Clearing condition]
When the host processor reads ODR1 using I/O
read cycle, or the slave processor writes 0 to the
OBF1 bit
1: There is transmit data in ODR1
[Setting condition]
When the slave processor writes to ODR1
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 530 of 830
• STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU27
DBU26
DBU25
DBU24
All 0
3
C/D2
0
R/W
R
Defined by User
The user can use these bits as necessary.
R
R
Command/Data
When the host processor writes to an IDR2 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR2 contains data or a command.
0: Content of input data register (IDR2) is data
1: Content of input data register (IDR2) is a command
2
DBU22
0
R/W
R
Defined by User
The user can use this bit as necessary.
1
IBF2
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in IDR2.
This bit is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR2
[Clearing condition]
When the slave processor reads IDR2
1: There is receive data in IDR2
[Setting condition]
When the host processor writes to IDR2 using I/O
write cycle
0
OBF2
0
R/(W) R
*
Output Data Register Full
Indicates whether or not there is transmit data in
ODR2.
0: There is not transmit data in ODR2
[Clearing condition]
When the host processor reads ODR2 using I/O read
cycle, or the slave processor writes 0 to the OBF2 bit
1: There is transmit data in ODR2
[Setting condition]
When the slave processor writes to ODR2
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 531 of 830
• STR3
(When TWRE = 1 or SELSTR3 = 0)
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IBF3B
0
R
R
Bidirectional Data Register Input Data Full
Indicates whether or not there is receive data in
TWR0 to TWR15. This is an internal interrupt source
to the slave processor (this LSI).
0: There is not receive data in TWR15
[Clearing condition]
When the slave processor reads TWR15
1: There is receive data in TWR0 to TWR15
[Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
6
OBF3B
0
R/(W)* R
Bidirectional Data Register Output Data Full
Indicates whether or not there is transmit data in
TWR0 to TWR15.
0: There is not transmit data in TWR15
[Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: There is transmit data in TWR0 to TWR15
[Setting condition]
When the slave processor writes to TWR15
5
MWMF
0
R
R
Master Write Mode Flag
Indicates that master write mode is entered by
writing to TWR0 from the host processor.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
Rev. 3.00, 03/04, page 532 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
4
SWMF
0
R/(W)* R
Slave Write Mode Flag
Indicates that slave write mode is entered by writing
to TWR0 from the slave processor (this LSI). In the
event of simultaneous writes by the master and the
slave, the master write has priority.
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
1: [Setting condition]
When the slave processor writes to TWR0 while
MWMF = 0
3
C/D3
0
R
R
Command/Data
When the host processor writes to an IDR3 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR3 contains data or a command.
0: Content of input data register (IDR3) is data
1: Content of input data register (IDR3) is a
command
2
DBU32
0
R/W
R
Defined by User
The user can use this bit as necessary.
1
IBF3A
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave processor reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host processor writes to IDR3 using I/O
write cycle
Rev. 3.00, 03/04, page 533 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
0
OBF3A
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not transmit data in ODR3
[Clearing condition]
When the host processor reads ODR3 using I/O
read cycle, or the slave processor writes 0 to the
OBF3A bit
1: There is transmit data in ODR3
[Setting condition]
When the slave processor writes to ODR3
Note:
*
Only 0 can be written to clear the flag.
• STR3
(When TWRE = 0 and SELSTR3 = 1)
R/W
Bit
Bit Name Initial Value Slave Host Description
7
6
5
4
DBU37
DBU36
DBU35
DBU34
All 0
3
C/D3
0
R/W
R
Defined by User
The user can use these bits as necessary.
R
R
Command/Data
When the host processor writes to an IDR3 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR3 contains data or a command.
0: Content of input data register (IDR3) is data
1: Content of input data register (IDR3) is a command
2
DBU32
0
R/W
R
Defined by User
The user can use this bit as necessary.
Rev. 3.00, 03/04, page 534 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IBF3A
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This bit is an internal interrupt source to the
slave processor (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave processor reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host processor writes to IDR3 using I/O
write cycle
0
OBF3A
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not receive data in ODR3
[Clearing condition]
When the host processor reads ODR3 using I/O
read cycle, or the slave processor writes 0 to the
OBF3A bit
1: There is receive data in ODR3
[Setting condition]
When the slave processor writes to ODR3
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 535 of 830
16.3.10 SERIRQ Control Register 0 (SIRQCR0)
The SIRQCR0 register contains status bits that indicate the SERIRQ operating mode and status
bits that specify SERIRQ0 interrupt sources.
The SIRQCR0 register is initialized to H'00 by a reset or in hardware standby mode.
R/W
Bit
Bit Name Initial Value Slave Host Description
7
Q/C
0
R

Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
•
LPC hardware reset, LPC software reset
•
Specification by the stop frame of the SERIRQ
transfer cycle
1: Quiet mode
[Setting condition]
•
6
SELREQ 0
R/W

Specification by the stop frame of the SERIRQ
transfer cycle
Start Frame Initiation Request Select
Specifies the condition of start frame activation when
the host interrupt request is cleared in quiet mode.
0: When all host interrupt requests are cleared in
quiet mode, start frame initiation is requested
1: When at least one host interrupt request is
cleared in quiet mode, start frame initiation is
requested
5
IEDIR
0
R/W

Interrupt Enable Direct Mode
Specifies whether LPC channel 2 SERIRQ interrupt
source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation
is conditional upon OBF, or is controlled only by the
host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable bit and corresponding OBF are both set to
1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
Rev. 3.00, 03/04, page 536 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
4
SMIE3B
0
R/W

Host SMI Interrupt Enable 3B
Enables or disables a host SMI interrupt request
when OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and
SMIE3B is disabled
[Clearing conditions]
•
Writing 0 to SMIE3B
•
LPC hardware reset, LPC software reset
•
Clearing OBF3B to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting OBF3B to 1
is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
•
3
SMIE3A
0
R/W

Writing 1 after reading SMIE3B = 0
Host SMI Interrupt Enable 3A
Enables or disables a host SMI interrupt request
when OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and
SMIE3A is disabled
[Clearing conditions]
•
Writing 0 to SMIE3A
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE3A = 0
Rev. 3.00, 03/04, page 537 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
2
SMIE2
0
R/W

Host SMI Interrupt Enable 2
Enables or disables a host SMI interrupt request
when OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
•
Writing 0 to SMIE2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
•
1
IRQ12E1 0
R/W

Writing 1 after reading SMIE2 = 0
Host IRQ12 Interrupt Enable 1
Enables or disables a HIRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ12 interrupt request by OBF1 and IRQ12E1
is disabled
[Clearing conditions]
•
Writing 0 to IRQ12E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ12 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
•
Rev. 3.00, 03/04, page 538 of 830
Writing 1 after reading IRQ12E1 = 0
R/W
Bit
Bit Name Initial Value Slave Host Description
0
IRQ1E1
0
R/W

Host IRQ1 Interrupt Enable 1
Enables or disables a HIRQ1 interrupt request when
OBF1 is set by an ODR1 write.
0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ1E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
•
Writing 1 after reading IRQ1E1 = 0
16.3.11 SERIRQ Control Register 1 (SIRQCR1)
The SIRQCR1 register contains status bits that enable or disable an SERIRQ interrupt request.
The SIRQCR1 register is initialized to H'00 by a reset or in hardware standby mode.
Rev. 3.00, 03/04, page 539 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IRQ11E3 0
R/W

Host IRQ11 Interrupt Enable 3
Enables or disables a HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
IRQ11E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested.
[Setting condition]
•
6
IRQ10E3 0
R/W

Writing 1 after reading IRQ11E3 = 0
Host IRQ10 Interrupt Enable 3
Enables or disables a HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
IRQ10E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E3
•
LPC hardware reset, LPC software reset
•
Clearing OB3FA to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested.
[Setting condition]
•
Rev. 3.00, 03/04, page 540 of 830
Writing 1 after reading IRQ10E3 = 0
R/W
Bit
Bit Name Initial Value Slave Host Description
5
IRQ9E3
0
R/W

Host IRQ9 Interrupt Enable 3
Enables or disables a HIRQ9 interrupt request when
OBF3A is set by an ODR3 write.
0: HIRQ9 interrupt request by OBF3A and IRQ9E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ9 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ9 interrupt is requested.
[Setting condition]
•
4
IRQ6E3
0
R/W

Writing 1 after reading IRQ9E3 = 0
Host IRQ6 Interrupt Enable 3
Enables or disables a HIRQ6 interrupt request when
OBF3A is set by an ODR3 write.
0: HIRQ6 interrupt request by OBF3A and IRQ6E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ6 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ6 interrupt is requested.
[Setting condition]
•
Writing 1 after reading IRQ6E3 = 0
Rev. 3.00, 03/04, page 541 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
3
IRQ11E2 0
R/W

Host IRQ11 Interrupt Enable 2
Enables or disables a HIRQ11 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ11 interrupt request by OBF2 and IRQ11E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ11 interrupt is requested.
[Setting condition]
•
2
IRQ10E2 0
R/W

Writing 1 after reading IRQ11E2 = 0
Host IRQ10 Interrupt Enable 2
Enables or disables a HIRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ10 interrupt request by OBF2 and IRQ10E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ10 interrupt is requested.
[Setting condition]
•
Rev. 3.00, 03/04, page 542 of 830
Writing 1 after reading IRQ10E2 = 0
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IRQ9E2
0
R/W

Host IRQ9 Interrupt Enable 2
Enables or disables a HIRQ9 interrupt request when
OBF2 is set by an ODR2 write.
0: HIRQ9 interrupt request by OBF2 and IRQ9E2 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ9E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ9 interrupt is requested.
[Setting condition]
•
0
IRQ6E2
0
R/W

Writing 1 after reading IRQ9E2 = 0
Host IRQ6 Interrupt Enable 2
Enables or disables a HIRQ6 interrupt request when
OBF2 is set by an ODR2 write.
0: HIRQ6 interrupt request by OBF2 and IRQ6E2 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ6E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
HIRQ6 interrupt is requested.
[Setting condition]
•
Writing 1 after reading IRQ6E2 = 0
Rev. 3.00, 03/04, page 543 of 830
16.3.12 SERIRQ Control Register 2 (SIRQCR2)
The SIRQCR2 register contains status bits that specify an SERIRQ interrupt source.
The SIRQCR2 register is initialized to H'00 by a reset or in hardware standby mode.
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IEDIR3
0
R/W

Interrupt Enable Direct Mode 3
Specifies whether SERIRQ interrupt sources (SMI,
HIRQ6, and HIRQ9 to HIRQ11) of LPC channel 3
are generated in relation to OBF or only by the host
interrupt enable bit.
0: The host interrupt is requested when both the
host interrupt enable bit and corresponding OBF
are set to 1
1: The host interrupt is requested when the host
interrupt enable bit is set to 1
6 to 0 
All 0
R/W

Reserved
The initial value should not be changed.
Rev. 3.00, 03/04, page 544 of 830
16.3.13 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in the STR3 register. In addition, this register selects the
output of host interrupt request signal of each frame.
R/W
Bit
Bit Name
Initial Value Slave Host Description
7
SELSTR3 0
R/W

STR3 Register Function Select 3
Sets the functions of bits 7 to 4 in STR3 together
with the TWRE bit in LADR3L. For details see
section 16.3.9, Status Register 1 to 3 (STR1 to
STR3).
0: Bits 7 to 4 in STR3 is the LPC interface status bits
1: [When TWRE = 0]
Bits 7 to 4 in STR3 are defined by user.
[When TWRE = 1]
Bits 7 to 4 in STR3 are the LPC interface status
bits.
6
5
4
3
2
1
0
SELIRQ11 All 0
SELIRQ10
SELIRQ9
SELIRQ6
SELSMI
SELIRQ12
SELIRQ1
R/W

Selects the SERIRQ Output
These bits select the output status for LPC host
interrupt request (HIRQ11, HIRQ10, HIRQ9, HIRQ6,
SMI, HIRQ12, and HIRQ1).
0: [When host interrupt request has been cleared]
The SERIRQ output is high impedance.
[When host interrupt request has been set]
The SERIRQ output is 0 level.
1: [When host interrupt request has been cleared]
The SERIRQ output is 0 level.
[When host interrupt request has been set]
The SERIRQ output is high impedance.
Rev. 3.00, 03/04, page 545 of 830
16.3.14 SMIC Flag Register (SMICFLG)
SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that
indicate whether or not the system is ready to data transfer and those that are used for handshake
of the transfer cycles.
R/W
Bit
Bit Name
Initial Value Slave Host Description
7
RX_DATA_ 0
RDY
R/W
R
Read Transfer Ready
Indicates whether or not the slave is ready for the
host read transfer.
0: Slave waits for ready status
1: Slave is ready for the host read transfer
6
TX_DATA_ 0
RDY
R/W
R
Write Transfer Ready
Indicates whether or not the slave is ready for the
host next write transfer.
0: The slave waits for ready status
1: The slave is ready for the host write transfer.
5

0
R/W
R
Reserved
The initial value should not be changed.
4
SMI
0
R/W
R
SMI Flag
This bit indicates that the SMI is asserted.
0: Indicates waiting for SMI assertion
1: Indicates SMI assertion
Rev. 3.00, 03/04, page 546 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
3
SEVT_
ATN
0
R/W
R
Event Flag
When the slave detects an event for the host, this bit
is set.
0: Indicates waiting for event detection
1: Indicates event detection
2
SMS_
ATN
0
R/W
R
SMS Flag
When there is a message to be transmitted from the
slave to the host, this bit is set.
0: There is not a message
1: There is a message
1

0
R/W
R
Reserved
The initial value should not be changed.
0
BUSY
0
R/(W)* W
SMIC Busy
This bit indicates that the slave is now transferring
data. This bit can be cleared only by the slave and
set only by the host.
The rising edge of this bit is a source of internal
interrupt to the slave.
0: Transfer cycle wait state
[Clearing conditions]
After the slave reads BUSY = 1, writes 0 to this bit.
1: Transfer cycle in progress
[Setting condition]
When the host writes 1 to this bit.
Note: Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 547 of 830
16.3.15 SMIC Control Status Register (SMICCSR)
SMICCSR is one of the registers used to implement SMIC mode. This is an 8-bit
readable/writable register that stores a control code issued from the host and a status code that is
returned from the slave.
The control code is written to this register accompanied by the transfer between the host and slave.
The status code is returned to this register to indicate that the slave has recognized the control
code, and a specified transfer cycle has been completed.
16.3.16 SMIC Data Register (SMICDTR)
SMICDTR is one of the registers used to implement SMIC mode. This is an 8-bit register that is
accessible (readable/writable) from both the slave processor (this LSI) and host processor. This is
used for data transfer between the host and slave.
16.3.17 SMIC Interrupt Register 0 (SMICIR0)
SMICIR0 is one of the registers used to implement SMIC mode. This register includes the bits that
indicate the source of interrupt to the slave.
Rev. 3.00, 03/04, page 548 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
All 0
R/W

Reserved
The initial value should not be changed.
4
HDTWI
0
R/(W)* 
Transfer Data Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the transfer data to SMICDTR.
When the IBFIE3 bit and HDTWIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data transmission wait state
[Clearing condition]
After the slave reads HDTWI = 1, writes 0 to this bit.
1: Transfer data transmission end
[Setting condition]
The transfer cycle is write transfer and the host
writes the transfer data to SMICDTR.
3
HDTRI
0
R/(W)* 
Transfer Data Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the transfer data from SMICDTR.
When the IBFIE3 bit and HDTRIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data receive wait state
[Clearing condition]
After the slave reads HDTRI = 1, writes 0 to this bit.
1: Transfer data receive end
[Setting condition]
The transfer cycle is read transfer and the host
reads the transfer data from SMICDTR.
2
STARI
0
R/(W)* 
Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
Rev. 3.00, 03/04, page 549 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
1
CTLWI
0
R/(W)* 
Control Code Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the control code to SMICCSR.
When the IBFIE3 bit and CTLWIE bit are set to1, the
IBFI3 interrupt is requested to the slave.
0: Control code transmission wait state
[Clearing condition]
After the slave reads CTLWI = 1, writes 0 to this bit.
1: Control code transmission end
[Setting condition]
When the host writes the status code to SMICCSR.
0
BUSYI
R/(W)* 
Transfer Start Interrupt
This is a status flag that indicates that the host starts
transferring. When the IBFIE3 bit and BUSYIE bit
are set to 1, the IBFI3 interrupt is requested to the
slave.
0: Transfer start wait state
[Clearing condition]
After the slave reads BUSYI = 1, writes 0 to this bit.
1: Transfer start
[Setting condition]
When the rising edge of the BUSY bit in SMICFLG is
detected.
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 550 of 830
16.3.18 SMIC Interrupt Register 1 (SMICIR1)
SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that
enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit
in HICR2 to 1.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
4
All 0
HDTWIE 0
R/W

Reserved
The initial value should not be changed.
R/W

Transfer Data Transmission End Interrupt Enable
Enables or disables HDTWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data transmission end interrupt
1: Enables transfer data transmission end interrupt
3
HDTRIE
0
R/W

Transfer Data Receive End Interrupt Enable
Enables or disables HDTRI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data receive end interrupt
1: Enables transfer data receive end interrupt
2
STARIE
0
R/W

Status Code Receive End Interrupt Enable
Enables or disables STARI interrupt that is IBFI3
interrupt source to the slave.
0: Disables status code receive end interrupt
1: Enables status code receive end interrupt
1
CTLWIE
0
R/W

Control Code Transmission End Interrupt Enable
Enables or disables CTLWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables control code transmission end interrupt
1: Enables control code transmission end interrupt
0
BUSYIE
0
R/W

Transfer Start Interrupt Enable
Enables or disables BUSYI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer start interrupt
1: Enables transfer start interrupt
Rev. 3.00, 03/04, page 551 of 830
16.3.19 BT Status Register 0 (BTSR0)
BTSR0 is one of the registers used to implement BT mode. This register includes flags that control
interrupts to the slave (this LSI).
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
All 0
R/W

4
0
R/(W)* 
Reserved
The initial value should not be changed.
FRDI
FIFO Read Request Interrupt
This status flag indicates that host writes the data to
BTDTR buffer with FIFO full state at the host write
transfer. When the IBFIE3 bit and FRDIE bit are set
to 1, IBFI3 interrupt is requested to the slave. The
slave must clear the flag after creating an unused
area by reading the data in FIFO.
0: FIFO read is not requested
[Clearing condition]
After the slave reads FRDI = 1, writes 0 to this bit.
1: FIFO read is requested
[Setting condition]
After the host processor transfers data, the host
writes the data with FIFO Full state.
3
HRDI
0
R/(W)* 
BT Host Read Interrupt
This status flag indicates that the host reads 1 byte
from BTDTR buffer. When the IBFIE3 bit and HRDIE
bit are set to 1, IBFI3 interrupt is requested to the
slave.
0: Host BTDTR read wait state
[Clearing condition]
After the slave reads HRDI = 1, writes 0 to this bit.
1: The host reads from BTDTR
[Setting condition]
The host reads one byte from BTDTR.
Rev. 3.00, 03/04, page 552 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
2
HWRI
0
R/(W)* 
BT Host Write Interrupt
This status flag indicates that the host writes 1byte
to BTDTR buffer. When the IBFIE3 bit and HWRIE
bit are set to 1, IBFI3 interrupt is requested to the
slave.
0: Host BTDTR write wait state
[Clearing condition]
After the slave reads HWRI = 1, writes 0 to this bit.
1: The host writes to BTDTR
[Setting condition]
The host writes one byte to BTDTR.
1
HBTWI
0
R/(W)* 
BTDTR Host Write Start Interrupt
This status flag indicates that the host writes the first
byte of valid data to BTDTR buffer. When the IBFIE3
bit and HBTWIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: BTDTR host write start wait state
[Clearing condition]
After the slave reads HBTWI = 1 and writes 0 to this
bit.
1: BTDTR host write start
[Setting condition]
The host starts writing valid data to BTDTR.
0
HBTRI
0
R/(W)* 
BTDTR Host Read End Interrupt
This status flag indicates that the host reads all valid
data from BTDTR buffer. When the BFIE3 bit and
HBTRIE bit are set to 1, IBFI3 interrupt is requested
to the slave.
0: BTDTR host read end wait state
[Clearing condition]
After the slave reads HBTRI = 1 and writes 0 to this
bit.
1: BTDTR host read end
[Setting condition]
When the host finished reading the valid data from
BTDTR.
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 553 of 830
16.3.20 BT Status Register 1 (BTSR1)
BTSR1 is one of the registers used to implement the BT mode. This register includes a flag that
controls an interrupt to the slave (this LSI).
R/W
Bit
Bit Name Initial Value Slave Host Description
7

0
R/W
6
HRSTI
0
R/(W)* 

Reserved
The initial value should not be changed.
BT Reset Interrupt
This status flag indicates that the BMC_HWRST bit
in BTIMSR is set to 1 by the host. When the IBFIE3
bit and HRSTIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads HRSTI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the rising edge of
BMC_HWRST.
5
IRQCRI
0
R/(W)* 
B2H_IRQ Clear Interrupt
This status flag indicates that the B2H_IRQ bit in
BTIMSR is cleared by the host. When the IBFIE3 bit
and IRQCRIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads IRQCRI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the falling edge of
B2H_IRQ.
Rev. 3.00, 03/04, page 554 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
4
BEVTI
0
R/(W)* 
BEVT_ATN Clear Interrupt
This status flag indicates that the BEVT_ATN bit in
BTCR is cleared by the host. When the IBFIE3 bit
and BEVTIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads BEVTI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the falling edge of
BEVT_ATN.
3
B2HI
0
R/(W)* 
Read End Interrupt
This status flag indicates that the host has finished
reading all data from the BTDTR buffer. When the
IBFIE3 bit and B2HIE bit are set to 1, the IBFI3
interrupt is requested to the slave.
0: [Clearing condition]
When the slave reads B2HI = 1 and writes 0 to
this bit.
1: [Setting conditions]
ATNSW = 0: When the slave detects the falling
edge of B2H_ATN.
ATNSW = 1: When the slave detects the falling
edge of H_BUSY.
2
H2BI
0
R/(W)* 
Write End Interrupt
This status flag indicates that the host has finished
writing all data to the BTDTR buffer. When the
IBFIE3 bit and H2BIE bit are set to 1, the IBFI3
interrupt is requested to the slave.
0: [Clearing condition]
After the slave reads H2BI = 1, writes 0 to this bit.
1: [Setting condition]
When the slave detects the falling edge of
H2B_ATN.
Rev. 3.00, 03/04, page 555 of 830
R/W
Bit
Bit Name Initial Value Slave Host Description
1
CRRPI
0
R/(W)* 
Read Pointer Clear Interrupt
This status flag indicates that the CLR_RD_PTR bit
in BTCR is set to 1 by the host. When the IBFIE3 bit
and CRRPIE bit are set to 1, the IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
After the slave reads CRRPI = 1, writes 0 to this
bit.
1: [Setting condition]
When the slave detects the rising edge of
CLR_RD_PTR.
0
CRWPI
0
R/(W)* 
Write Pointer Clear Interrupt
This status flag indicates that the CLR_WR_PTR bit
in BTCR is set to 1 by the host. When the IBFIE3 bit
and CRWPIE bit are set to 1, the IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
After the slave reads CRWPI = 1, writes 0 to this
bit.
1: [Setting condition]
When the slave detects the rising edge of
CLR_WR_PTR.
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 556 of 830
16.3.21 BT Control Status Register 0 (BTCSR0)
BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains
the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this
LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
R/W
Bit Bit Name Initial Value Slave Host Description
7

0
R/W

Reserved
The initial value should not be changed.
6
5
FSEL1
FSEL0
0
0
R/W
R/W


These bits select either FIFO during BT transfer
FSEL1 FSEL0
0
*
:FIFO disabled
1
*
:FIFO enabled
The FIFO size: 64 bytes (for host write transfer),
additional 64 bytes (for host read transfer).
4
FRDIE
0
R/W

FIFO Read Request Interrupt Enable
Enables or disables the FRDI interrupt which is an
IBFI3 interrupt source to the slave.
0: FIFO read request interrupt is disabled.
1: FIFO read request interrupt is enabled.
3
HRDIE
0
R/W

BT Host Read Interrupt Enable
Enables or disables the HRDI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HRDIE bit must not be set to 1.
0: BT host read interrupt is disabled.
1: BT host read interrupt is enabled.
2
HWRIE
0
R/W

BT Host Write Interrupt Enable
Enables or disables the HWRI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HWRIE bit must not be set to
1.
0: BT host write interrupt is disabled.
1: BT host write interrupt is enabled.
Rev. 3.00, 03/04, page 557 of 830
R/W
Bit Bit Name Initial Value Slave Host Description
1
HBTWIE
0
R/W

BTDTR Host Write Start Interrupt Enable
Enables or disables the HBTWI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host write start interrupt is disabled.
1: BTDTR host write start interrupt is enabled.
0
HBTRIE
0
R/W

BTDTR Host Read End Interrupt Enable
Enables or disables the HBTRI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host read end interrupt is disabled.
1: BTDTR host read end interrupt is enabled.
Note:
*
Don't care.
16.3.22 BT Control Status Register 1 (BTCSR1)
BTCSR1 is one of the registers used to implement the BT mode. The BTCSR1 register contains
the bits used to enable or disable interrupts to the slave (this LSI). The IBFI3 interrupt is enabled
by setting the IBFIE3 bit in HICR2 to 1.
R/W
Bit Bit Name
7
Initial Value Slave Host Description
RSTRENBL 0
R/W

Slave Reset Read Enable
The host reads 0 from the BMC_HWRST bit in
BTIMSR. When this bit is set to 1, the host can read
1 from the BMC_HWRST bit.
0: Host always reads 0 from BMC_HWRST
1: Host can reads 0 from BMC_HWRST
6
HRSTIE
0
R/W

BT Reset Interrupt Enable
Enables or disables the HRSTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BT reset interrupt is disabled.
1: BT reset interrupt is enabled.
5
IRQCRIE
0
R/W

B2H_IRQ Clear Interrupt Enable
Enables or disables the IRQCRI interrupt which is
an IBFI3 interrupt source to the slave.
0: B2H_IRQ clear interrupt is disabled.
1: B2H_IRQ clear interrupt is enabled.
Rev. 3.00, 03/04, page 558 of 830
R/W
Bit Bit Name
Initial Value Slave Host Description
4
0
BEVTIE
R/W

BEVT_ATN Clear Interrupt Enable
Enables or disables the BEVTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BEVT_ATN clear interrupt is disabled.
1: BEVT_ATN clear interrupt is enabled.
3
B2HIE
0
R/W

Read End Interrupt Enable
Enables or disables the B2HI interrupt which is an
IBFI3 interrupt source to the slave.
0: Read end interrupt is disabled.
1: Read end interrupt is enabled.
2
H2BIE
0
R/W

Write End Interrupt Enable
Enables or disables the H2BI interrupt which is an
IBFI3 interrupt source to the slave.
0: Write end interrupt is disabled.
1: Write end interrupt is enabled.
1
CRRPIE
0
R/W

Read Pointer Clear Interrupt Enable
Enables or disables the CRRPI interrupt which is an
IBFI3 interrupt source to the slave.
0: Read pointer clear interrupt is disabled.
1: Read pointer clear interrupt is enabled.
0
CRWPIE
0
R/W

Write Pointer Clear Interrupt Enable
Enables or disables the CRWPI interrupt which is an
IBFI3 interrupt source to the slave.
0: Write pointer clear interrupt is disabled.
1: Write pointer clear interrupt is enabled.
Rev. 3.00, 03/04, page 559 of 830
16.3.23 BT Control Register (BTCR)
BTCR is one of the registers used to implement BT mode. The BTCR register contains bits used
in transfer cycle handshaking, and those indicating the completion of data transfer to the buffer.
R/W
Bit Bit Name
Initial Value Slave Host
7
1
B_BUSY
R/W
R
Description
BT Write Transfer Busy Flag
Read-only bit from the host. Indicates that the
BTDTR buffer is being used for BT write transfer
(write transfer is in progress.)
0: Indicates waiting for BT write transfer
1: Indicates that the BTDTR buffer is being used
6
H_BUSY
0
R
3
(W)*
BT Read Transfer Busy Flag
This is a set/clear bit from the host. Indicates that
the BTDTR buffer is being used for BT read
transfer (read transfer is in progress.)
0: Indicates waiting for BT read transfer
[Clearing condition]
When the host writes a 1 while H_BUSY is set to
1.
1: Indicates that the BTDTR buffer is being used
[Setting condition]
When the host writes a 1 while H_BUSY is set to
0.
5
OEM0
0
R/W
R/(W)*4 User defined bit
This bit is defined by the user, and validated only
when set to 1 by a 0 written from the host.
0: [Clearing condition]
When the slave writes a 0 after a 1 has been
read from OEM0.
1: [Setting condition]
When the slave writes a 1, after a 0 has been
read from OEM0, or when the host writes a 0.
Rev. 3.00, 03/04, page 560 of 830
R/W
Bit Bit Name
4
Initial Value Slave
BEVT_ATN 0
Host
1
Description
5
R/(W)* R/(W)* Event Interrupt
Sets when the slave detects an event to the host.
Setting the B2H_IRQ_EN bit in the BTIMSR
register enables the BEVT_ATN bit to be used as
an interrupt source to the host.
0: No event interrupt request is available
[Clearing condition]
When the host writes a 1 to the bit.
1: An event interrupt request is available
[Setting condition]
When the slave writes a 1 after a 0 has been read
from BEVT_ATN.
3
B2H_ATN
0
R/(W)*1 R/(W)*5 Slave Buffer Write End Indication Flag
This status flag indicates that the slave has finished
writing all data to the BTDTR buffer. Setting the
B2H_IRQ_EN bit in the BTIMSR register enables
the B2H_ATN bit to be used as an interrupt source
to the host.
0: Host has completed reading the BTDTR buffer
[Clearing condition]
When the host writes a 1
1: Slave has completed writing to the BTDTR buffer
[Setting condition]
When the slave writes a 1 after a 0 has been read
from B2N_ATN.
2
H2B_ATN
0
R/(W)*2 R/(W)*1 Host Buffer Write End Indication Flag
This status flag indicates that the host has finished
writing all data to the BTDTR buffer.
0: Slave has completed reading the BTDTR buffer
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from H2B_ATN.
1: Host has completed writing to the BTDTR buffer
[Setting condition]
When the host writes a 1
Rev. 3.00, 03/04, page 561 of 830
R/W
Bit Bit Name
1
Initial Value
CLR_RD_ 0
PTR
Slave
Host Description
2
R/(W)* (W)*1 Read Pointer Clear
This bit is used by the host to clear the read
pointer during read transfer. A host read operation
always yields 0 on readout.
0: Read pointer clear wait
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from CLR_RD_PTR.
1: Read pointer clear
[Setting condition]
When the host writes a 1.
0
CLR_WR_ 0
PTR
2
R/(W)* (W)*
1
Write Pointer Clear
This bit is used by the host to clear the write
pointer during write transfer. A host read
operation always yields 0 on readout.
0: Write pointer clear wait
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from CLR_WR_PTR.
1: Write pointer clear
[Setting condition]
When the host writes a 1.
Notes: 1.
2.
3.
4.
5.
Only 1 can be written to set this flag.
Only 0 can be written to clear this flag.
Only 1 can be written to toggle this flag.
Only 0 can be written to set this flag.
Only 1 can be written to clear this flag.
Rev. 3.00, 03/04, page 562 of 830
16.3.24 BT Data Buffer (BTDTR)
BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer
FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR,
enable FIFO by means of the bits FSEL0 and FSEL1.
R/W
Bit
Bit Name
Initial Value Slave Host
7 to bit7 to bit0 Undefined
0
R/W
R/W
Description
The data written by the host is stored in FIFO (64
bytes) for host write transfer and read out by the
slave in order of host writing. The data written by
the slave is stored in FIFO (64 bytes) for host read
transfer and read out by the host in order of slave
writing.
Rev. 3.00, 03/04, page 563 of 830
16.3.25 BT Interrupt Mask Register (BTIMSR)
BTIMSR is one of the registers used to implement BT mode.
The BTIMSR register contains the bits used to control the interrupts to the host.
R/W
Bit Bit Name
7
BMC_
HWRST
Initial Value Slave
0
Host
2
Description
1
R/(W)* R/(W)* Slave Reset
Performs a reset from the host to the slave. The
host can only write a 1. Writing a 0 to this bit is
invalid. The host will always return a 0 on read
out. Setting the RSTRENBL bit enables a 1 to be
read from the host.
0: The reset is cancelled
[Clearing condition]
When the slave writes a 0, after a 1 has been
read from BMC_HWRST.
1: The reset is in progress.
[Setting condition]
When the host writes a 1.
6
5


0
0
R/W
R/W
R/W
R/W
4
3
2
OEM3
OEM2
OEM1
0
0
0
R/W
R/W
R/W
R/(W)*4 User defined bit
R/(W)*4 These bits are defined by the user and are valid
R/(W)*4 only when set to 1 by a 0 written from the host.
Reserved
0: [Clearing condition]
When the slave writes a 0, after a 1 has been
read from OEM.
1: [Setting condition]
When the slave writes a 1, after a 0 has been
read from OEM, or when the host writes a 0.
Rev. 3.00, 03/04, page 564 of 830
R/W
Bit Bit Name
1
B2H_IRQ
Initial Value Slave
0
Host
1
Description
3
R/(W)* R/(W)* BMC to HOST interrupt
Informs the host that an interrupt has been
requested when the BEVT_ATN or B2H_ATN bit
has been set. The SERIRQ is not issued. To
generate the SERIRQ, it should be issued by the
program.
0: B2H_IRQ interrupt is not requested
[Clearing condition]
When the host writes a 1.
1: B2H_IRQ interrupt is requested
[Setting condition]
When the slave writes a 1, after a 0 has been
read from B2H_IRQ
0
B2H_IRQ_ 0
EN
R
R/W
BMC to HOST interrupt enable
Enables or disables the B2H_IRQ interrupt which
is an the interrupt source from the slave to the
host.
0: B2H_IRQ interrupt is disabled
[Clearing condition]
When a 0 is written by the host.
1: B2H_IRQ interrupt is enabled
[Setting condition]
When a 1 is written by the host.
Notes: 1.
2.
3.
4.
Only 1 can be written to set this flag.
Only 0 can be written to clear this flag.
Only 1 can be written to clear this flag.
Only 0 can be written to set this flag.
Rev. 3.00, 03/04, page 565 of 830
16.3.26 BT FIFO Valid Size Register 0 (BTFVSR0)
BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data
size in the FIFO for host write transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to
0
N7 to N0
All 0
R

These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the slave can read)
for host write transfer. When data is written from the
host, the value in BTFVSR0 is incremented by the
number of bytes that have been written to. Further,
when data is read from the slave, the value is
decremented by only the number of bytes that have
been read.
16.3.27 BT FIFO Valid Size Register 1 (BTFVSR1)
BTFVSR1 is one of the registers used to implement BT mode. BTFVSR1 indicates a valid data
size in the FIFO for host read transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to
0
N7 to N0
All 0
R
Rev. 3.00, 03/04, page 566 of 830

These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the host can read)
for host read transfer. When data is written from the
slave, the value in BTFVSR1 is incremented by the
number of bytes that have been written to. Further,
when data is read from the host, the value is
decremented by only the number of bytes that have
been read.
16.4
Operation
16.4.1
LPC Interface Activation
The LPC interface is activated by setting at least one of bits LPC3E to LPC1E (bits 7 to 5) in
HICR0 to 1. When the LPC interface is activated, the related I/O ports (PE7 to PE0, PD5, and
PD4) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E,
PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports PD3 to PD0) to the LPC
interface's input/output pins.
Use the following procedure to activate the LPC interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. Set the I/O addresses of the channels to be used (LADR1 to LADR3) and whether or not the
bidirectional registers, KCS interface, SMIC interface, and BT interface are to be used.
3. Set the enable bit (LPC3E to LPC1E) for the channel to be used.
4. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
used.
5. Set the selection bits for other functions (SDWNE, IEDIR).
6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, and OBF). Read IDR or
TWR15 to clear IBF.
7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary.
16.4.2
LPC I/O Cycles
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus mastership memory read, bus mastership memory write, bus mastership I/O
read, and bus mastership I/O write. Of these, the chip's LPC supports only I/O read and I/O write
cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle. However, the LPC in this LSI
always returns a value of B'0000 if the BT interface is not used.
Rev. 3.00, 03/04, page 567 of 830
If the received address matches the host address in an LPC register, the LPC interface enters the
busy state; it returns to the idle state by output of a state #12 turnaround. Register (IDR, etc.) and
flag (IBF, etc.) changes are made at this timing, so in the event of a transfer cycle forced
termination (abort) before state #12, registers and flags are not changed.
Table 16.5 I/O Read and Write Cycles
I/O Read Cycle
I/O Write Cycle
State
Count
Contents
Drive
Source
Value
(3 to 0)
Contents
Drive
Source
Value
(3 to 0)
1
Start
Host
B'0000
Start
Host
B'0000
2
Cycle type/direction Host
B'0000
Cycle type/direction Host
B'0010
3
Address 1
Host
Bits 15 to
12
Address 1
Host
Bits 15 to
12
4
Address 2
Host
Bits 11 to 8
Address 2
Host
Bits 11 to 8
5
Address 3
Host
Bits 7 to 4
Address 3
Host
Bits 7 to 4
6
Address 4
Host
Bits 3 to 0
Address 4
Host
Bits 3 to 0
7
Turnaround
(recovery)
Host
B'1111
Data 1
Host
Bits 3 to 0
8
Turnaround
None
B'ZZZZ
Data 2
Host
Bits 7 to 4
9
Synchronization
Slave
B'0000
Turnaround
(recovery)
Host
B'1111
10
Data 1
Slave
Bits 3 to 0
Turnaround
None
B'ZZZZ
11
Data 2
Slave
Bits 7 to 4
Synchronization
Slave
B'0000
12
Turnaround
(recovery)
Slave
B'1111
Turnaround
(recovery)
Slave
B'1111
13
Turnaround
None
B'ZZZZ
Turnaround
None
B'ZZZZ
Rev. 3.00, 03/04, page 568 of 830
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 16.2 and 16.3.
LCLK
LFRAME
LAD3 to LAD0
Start
ADDR
TAR
Sync
Data
TAR
Start
Cycle type,
direction,
and size
Number of clocks
1
1
4
2
1
2
2
1
Figure 16.2 Typical LFRAME Timing
LCLK
LFRAME
LAD3 to LAD0
Start
ADDR
Cycle type,
direction,
and size
TAR
Sync
Slave must stop driving
Master will
drive high
Too many Syncs
cause timeout
Figure 16.3 Abort Mechanism
16.4.3
SMIC Mode Transfer Flow
Figure 16.4 shows the write transfer flow and figure 16.5 shows the read transfer flow in SMIC
mode.
Rev. 3.00, 03/04, page 569 of 830
Slave
Host
Wait for BUSY = 0
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Bit that indicates slave is ready for write transfer.
Issues when slave is ready for the next write transfer.
Wait for
TX_DATA_RDY = 1
Host confirms the TX_DATA_RDY bit in SMICFLG.
The confirmation is unnecessary when Write Start control is issued.
A
Write control code
Host writes the Write control code in SMICCSR.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Slave waits for the BUSY bit in SMICFLG is set.
Generate slave
interrupt
Write transfer data
Slave confirms that valid data is written to SMICDTR
by host.
The HDTWI bit in SMICIR0 is set.
Host writes transfer data in SMICDTR.
Generate slave
interrupt
BUSY = 1
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Generate slave
interrupt
Slave clears the TX_DATA_RDY bit in SMICFLG.
TX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave reads transfer data in SMICDTR according to
Write control code.
Read transfer data
Slave writes the status code to SMICCSR to notify
the processing completion status.
Write status code
Slave clears the BUSY bit in SMICFLG to indicate
transfer completion.
BUSY = 0
Generate host
interrupt
Abnormal
A
Read status code
Normal
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Host sets the BUSY bit in SMICFLG.
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Generate slave
interrupt
Figure 16.4 SMIC Write Transfer Flow
Rev. 3.00, 03/04, page 570 of 830
Slave
Host
Wait for BUSY = 0
Bit that indicates slave is ready for read transfer.
Issues when slave is ready for the next read transfer.
Slave waits for the BUSY bit in SMICFLG is set.
Waits for
RX_DATA_RDY = 1
A
Write control code
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Host confirms the RX_DATA_RDY bit in SMICFLG.
Host writes the Read control code to SMICCSR.
Generate slave
interrupt
BUSY = 1
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Slave clears the RX_DATA_RDY bit in SMICFLG.
Host sets the BUSY bit in SMICFLG.
Generate slave
interrupt
RX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave writes transfer data to SMICDTR according to
Read control code.
Write transfer data
Slave writes the status code to SMICCSR to notify the
processing completion status.
Write status code
Slave clears the BUSY bit in SMICFLG to indicate transfer
completion.
BUSY = 0
Generate host
interrupt
Read transfer data
Slave confirms that valid data is read from SMICDTR
by host.
The HDTRI bit in SMICIR0 is set.
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Host reads transfer data in SMICDTR.
Generate slave
interrupt
Abnormal
A
Read status code
Normal
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Generate slave
interrupt
Figure 16.5 SMIC Read Transfer Flow
Rev. 3.00, 03/04, page 571 of 830
16.4.4
BT Mode Transfer Flow
Figure 16.6 shows the write transfer flow and figure 16.7 shows the read transfer flow in BT
mode.
Slave
Host
Slave waits for the H2B_ATN bit (interrupt from
host) is set.
Wait for
B_BUSY = 0
Host confirms the B_BUSY bit in BTCR.
Wait for
H2B_ATN = 0
Host confirms the H2B_ATN bit in BTCR.
Clear write pointer
Confirms the CLR_WR_PTR bit.
The CRWPI bit in BTSR1 is set to notify write
pointer clearing as an interrupt to slave.
Generate slave
interrupt
Write BTDTR buffer
Confirms host write is started.
The HBTWI bit in BTSR0 is set.
Host clears write pointer by setting the CLR_WR_PTR
bit in BTCR.
Host writes data of 1 to n bytes to the BTDTR buffer.
Generate slave
interrupt
H2B_ATN = 1
Confirms the H2B_ATN bit is set.
The H2BI bit in BTSR1 is set.
Host sets the H2B_ATN bit in BTCR to indicate data write
completion to the buffer for the BT interface.
Generate slave
interrupt
Slave sets the B_BUSY bit in BTCR.
Slave reads data from the BTDTR buffer.
Slave clears the H2B_ATN bit in BTCR.
Slave clears the B_BUSY bit in BTCR to indicate
transfer completion.
B_BUSY = 1
Read BTDTR buffer
H2B_ATN = 0
B_BUSY = 0
Figure 16.6 BT Write Transfer Flow
Rev. 3.00, 03/04, page 572 of 830
Slave
Host
Slave confirms the H_BUSY bit in BTCR.
Slave writes data of 1 to n bytes to the BTDTR
buffer.
Slave sets the B2H_ATN bit in BTCR to indicate
data write completion to the BTDTR buffer.
Wait for
H_BUSY = 0
Write BTDTR buffer
B2H_ATN = 1
Generate host
interrupt
H_BUSY = 1
Clear read pointer
Confirms the CLR_RD_PTR bit.
The CRRPI bit in BTSR1 is set to notify read
pointer clearing as an interrupt source to slave.
Host sets the H_BUSY bit in BTCR.
Host clears read pointer by setting the CLR_RD_PTR
bit in BTCR.
Host reads data from the BTDTR buffer.
Generate slave
interrupt
B2H_ATN = 0
Confirms the B2H_ATN bit.
The B2HI bit in BTSR1 is set to notify host data
read completion as an interrupt source to slave.
Host confirms the B2H_ATN bit in BTCR.
The slave data write completion interrupt is notified to host.
Generate slave
interrupt
Read BTDTR buffer
The HBTRI bit in BTSR0 is set to notify host reads
all data through the BTDTR buffer.
Host waits for the B2H_ATN bit (interrupt from
slave) is set by slave.
Host clears the B2H_ATN bit in BTCR.
Generate slave
interrupt
H_BUSY = 0
Host clears the H_BUSY bit in BTCR to indicate
transfer completion.
Figure 16.7 BT Read Transfer Flow
Rev. 3.00, 03/04, page 573 of 830
16.4.5
A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086-family CPU*. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by the hardware is enabled by
setting the FGA20E bit to 1 in HICR0.
Note: * An Intel microcomputer
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBFI1 interrupt to read IDR1. If the data follows an H'D1
command, firmware copies bit 1 of the data and outputs it at the gate A20 pin.
Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E =
0. When the FGA20E bit is set to 1, PD3/GA20 is used for output of a fast A20 gate signal. The
state of the PD3/GA20 pin can be monitored by reading the GA20 bit in HICR2.
The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host
processor can manipulate the output from this pin by sending commands and data. This function is
only available via the IDR1 register. The LPC interface decodes commands input from the host.
When an H'D1 host command is detected, bit 1 of the data following the host command is output
from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster
than the regular processing using interrupts. Table 16.6 shows the conditions that set and clear
GA20 (PD3). Figure 16.8 shows the GA20 output in flowchart form. Table 16.7 indicates the
GA20 output signal values.
Table 16.6 GA20 (PD3) Set/Clear Conditions
Pin Name
Setting Condition
Clearing Condition
GA20 (PD3)
When bit 1 of the data that follows an
H'D1 host command is 1
When bit 1 of the data follows an H'D1
host command is 0
Rev. 3.00, 03/04, page 574 of 830
Start
Host write
No
H'D1 command
received?
Yes
Wait for next byte
Host write
No
Data byte?
Yes
Write bit 1 of data byte
to DR bit of PD3/GA20
Figure 16.8 GA20 Output
Rev. 3.00, 03/04, page 575 of 830
Table 16.7 Fast A20 Gate Output Signals
Data/Command
Internal CPU
Interrupt Flag
(IBF)
1
H'D1 command
0
1 data*1
1
GA20
(PD3)
Remarks
0
Q
Turn-on sequence
0
1
H'FF command
0
Q (1)
1
H'D1 command
0
Q
0
2
0
0
C/D1
0 data*
Turn-off sequence
1
H'FF command
0
Q (0)
1
H'D1 command
0
Q
Turn-on sequence
0
1 data*
1
0
1
(abbreviated form)
1/0
Command other than H′FF and 1
H'D1
Q (1)
1
H'D1 command
0
Q
Turn-off sequence
0
0 data*2
0
0
(abbreviated form)
1/0
Command other than H′FF and 1
H'D1
Q (0)
1
H'D1 command
0
Q
1
Command other than H'D1
1
Q
1
H'D1 command
0
Q
1
H'D1 command
0
Q
1
H'D1 command
0
Q
Consecutively executed
0
Any data
0
1/0
sequences
1
H'D1 command
0
Q (1/0)
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
Rev. 3.00, 03/04, page 576 of 830
Cancelled sequence
Retriggered sequence
16.4.6
LPC Interface Shutdown Function (LPCPD)
The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin.
There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software
shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC
software shutdown state is controlled by the SDWNB bit. In both states, a part of the LPC
interface enters the reset state by itself, and is no longer affected by external signals other than the
LRESET and LPCPD signals.
Placing the slave processor in sleep mode or software standby mode is effective in reducing
current dissipation in the shutdown state. If software standby mode is set, some means must be
provided for exiting software standby mode before clearing the shutdown state with the LPCPD
signal.
If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the
same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software
shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown
state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into
consideration, the following operating procedure uses a combination of LPC software shutdown
and LPC hardware shutdown.
1. Clear the SDWNE bit to 0.
2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.
3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal
status flags and perform any necessary processing.
4. Set the SDWNB bit to 1 to set LPC software shutdown mode.
5. Set the SDWNE bit to 1 and make a transition to LPC hardware shutdown mode. The SDWNB
bit is cleared automatically.
6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during
steps 3 to 5. If the signal has risen, clear the SDWNE bit to 0 to return to the state in step 1.
7. Place the slave processor in sleep mode or software standby mode as necessary.
8. If software standby mode has been set, exit software standby mode by some means
independent of the LPC.
9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared
to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of
LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
Table 16.8 shows the scope of LPC interface pin shutdown.
Rev. 3.00, 03/04, page 577 of 830
Table 16.8 Scope of LPC Interface Pin Shutdown
Abbreviation
Port
LAD3 to LAD0
Scope of
Shutdown
I/O
Notes
PE3 to PE0 O
I/O
Hi-Z
LFRAME
PE4
O
Input
Hi-Z
LRESET
PE5
X
Input
LPC hardware reset function is active
LCLK
PE6
O
Input
Hi-Z
SERIRQ
PE7
O
I/O
Hi-Z
LSCI
PD0
∆
I/O
Hi-Z, only when LSCIE = 1
LSMI
PD1
∆
I/O
Hi-Z, only when LSMIE = 1
PME
PD2
∆
I/O
Hi-Z, only when PMEE = 1
GA20
PD3
∆
I/O
Hi-Z, only when FGA20E = 1
CLKRUN
PD4
O
I/O
Hi-Z
LPCPD
PD5
X
Input
Needed to clear shutdown state
Notes: O: Pins shut down by the shutdown function
∆: Pins shut down only when the LPC function is selected by register setting
X: Pins not shut down
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by STBY or RES pin input, or WDT0 overflow)
 All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
 LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
 SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
 SDWNB bit is cleared to 0.
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 16.9.
Rev. 3.00, 03/04, page 578 of 830
Table 16.9 Scope of Initialization in Each LPC Interface Mode
System
Reset
LPC Reset
LPC
Shutdown
LPC transfer cycle sequencer (internal state),
LPCBSY and ABRT flags
Initialized
Initialized
Initialized
SERIRQ transfer cycle sequencer (internal state),
CLKREQ and IRQBSY flags
Initialized
Initialized
Initialized
LPC interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2,
C/D3, OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU,
SMICFLG, SMICIR0, BTSR0, BTSR1, BTCR,
BTIMSR, BTFVSR0, BTFVSR1), GA20 (internal
state)
Initialized
Initialized
Retained
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2,
IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3,
IRQ9E3 to IRQ11E3, SELREQ, IEDIR, IEDIR3,
SMICIR1), Q/C flag
Initialized
Initialized
Retained
LRST flag
Initialized
(0)
Can be
set/cleared
Can be
set/cleared
SDWN flag
Initialized
(0)
Initialized
(0)
Can be
set/cleared
LRSTB bit
Initialized
(0)
HR: 0
SR: 1
0 (can be set)
SDWNB bit
Initialized
(0)
Initialized
(0)
HS: 0
SS: 1
SDWNE bit
Initialized
(0)
Initialized
(0)
HS: 1
SS: 0 or 1
LPC interface operation control bits
(LPC3E to LPC1E, FGA20E, LADR12, LADR3,
IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB,
LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1,
SELSMI, SELIRQ6, SELIRQ9, SELIRQ10,
SELIRQ11, SELIRQ12, HICR4, HISEL, BTCSR0,
BTCSR1)
Initialized
Retained
Retained
LRESET signal
Input (port
Input
Input
LPCPD signal
function)
Input
Input
LAD3 to LAD0, LFRAME, LCLK, SERIRQ,
CLKRUN signals
Input
Hi-Z
PME, LSMI, LSCI, GA20 signals (when function
is selected)
Output
Hi-Z
PME, LSMI, LSCI, GA20 signals (when function
is not selected)
Port function
Port function
Items Initialized
Rev. 3.00, 03/04, page 579 of 830
Notes: System reset: Reset by STBY input, RES input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
Figure 16.9 shows the timing of the LPCPD and LRESET signals.
LCLK
LPCPD
LAD3 to LAD0
LFRAME
At least 30 µs
At least 100 µs
At least 60 µs
LRESET
Figure 16.9 Power-Down State Termination Timing
Rev. 3.00, 03/04, page 580 of 830
16.4.7
LPC Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a supporting function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
16.10.
SL
or
H
Start frame
H
R
T
IRQ0 frame
IRQ1 frame
IRQ2 frame
S
S
S
R
T
R
T
R
T
LCLK
START
SERIRQ
IRQ1
Drive source
Host controller
None
IRQ14 frame
IRQ15 frame
S
S
R
T
R
T
IRQ1
IOCHCK frame
S
R
T
None
Stop frame
I
H
R
Next cycle
T
LCLK
STOP
SERIRQ
Drive source
None
IRQ15
None
START
Host controller
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 16.10 SERIRQ Timing
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 3.00, 03/04, page 581 of 830
Table 16.10 Serial Interrupt Transfer Cycle Frame Configuration
Serial Interrupt Transfer Cycle
Frame
Count
Contents
Drive
Source
Number
of States
0
Start
Slave
6
Host
Notes
In quiet mode only, slave drive possible in first
state, then next 3 states 0-driven by host
1
IRQ0
Slave
3
2
IRQ1
Slave
3
Drive possible in LPC channel 1
3
SMI
Slave
3
Drive possible in LPC channels 2 and 3
4
IRQ3
Slave
3
5
IRQ4
Slave
3
6
IRQ5
Slave
3
7
IRQ6
Slave
3
8
IRQ7
Slave
3
9
IRQ8
Slave
3
10
IRQ9
Slave
3
Drive possible in LPC channels 2 and 3
11
IRQ10
Slave
3
Drive possible in LPC channels 2 and 3
12
IRQ11
Slave
3
Drive possible in LPC channels 2 and 3
13
IRQ12
Slave
3
Drive possible in LPC channel 1
14
IRQ13
Slave
3
15
IRQ14
Slave
3
16
IRQ15
Slave
3
17
IOCHCK
Slave
3
18
Stop
Host
Undefined
Drive possible in LPC channels 2 and 3
First, 1 or more idle states, then 2 or 3 states
0-driven by host
2 states: Quiet mode next
3 states: Continuous mode next
There are two modescontinuous mode and quiet modefor serialized interrupts. The mode
initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer
cycle that ended before that cycle.
In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet
mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt
transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate
interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the powerdown state. In order for a slave to transfer an interrupt request in this case, a request to restart the
Rev. 3.00, 03/04, page 582 of 830
clock must first be issued to the host. For details see section 16.4.8, LPC Interface Clock Start
Request.
16.4.8
LPC Interface Clock Start Request
A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN
pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested
since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host
interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is
sent to the host. The timing for this operation is shown in figure 16.11.
CLK
1
2
3
4
5
6
CLKRUN
Pull-up enable
Drive by the host processor
Drive by the slave processor
Figure 16.11 Clock Start or Speed-Up
Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a
different protocol, using the PME signal, etc.
Rev. 3.00, 03/04, page 583 of 830
16.5
Interrupt Sources
16.5.1
IBFI1, IBFI2, IBFI3, ERRI
The LPC interface has four interrupt requests to the slave processor: IBFI1, IBFI2, IBFI3, and
ERRI. IBFI1 and IBFI2 are receive complete interrupts for IDR1 and IDR2 respectively. IBFI3 is
a receive complete interrupt for IDR3 and TWR, and the interrupt in SMIC mode and BT mode.
The ERRI interrupt indicates the occurrence of a special state, such as an LPC reset, LPC
shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding
enable bit.
Table 16.11 Receive Complete Interrupts and Error Interrupt
Interrupt
Description
IBFI1
Requested when IBFIE1 is set to 1 and IDR1 reception is completed
IBFI2
Requested when IBFIE2 is set to 1 and IDR2 reception is completed
IBFI3
Requested when IBFIE3 is set to 1 and IDR3 reception is completed, or when
TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15
Interrupts by HDTWI, HDTRI, STARI, CTLWI, and BUSYI of SMIC mode
Interrupts by FRDI, HRDI, HWRI, HBTWI, HBTRI, HRSTI, IRQCRI, BEVTI, B2HI,
H2BI, CRRPI, and CRWPI of BT mode
ERRI
16.5.2
Requested when ERRIE is set to 1 and LRST, SDWN, or ABRT is set to 1
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12
The LPC interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can
be requested from LPC channel 2 or 3.
There are two ways of clearing a host interrupt request.
When the IEDIR bit in SIRQCR0 and the IEDIR3 bit in SIRQCR2 are cleared to 0s, host interrupt
sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF
flag is cleared to 0 by a read by the host of ODR or TWR15 in the corresponding LPC channel, the
corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request
is cleared.
When the IEDIR bit in SIRQCR0 and the IEDIR3 bit in SIRQCR2 are set to 1s, LPC channel 2
and 3 interrupt requests are dependent only upon the host interrupt enable bits. The host interrupt
enable bit is not cleared when OBF for channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and
SMIE3B, IRQ6E2 and IRQ6E3, IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2
and IRQ11E3 lose their respective functional differences when both bits IEDIR and IEDIR3 are
Rev. 3.00, 03/04, page 584 of 830
set to 1. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable
bit.
Table 16.12 summarizes the methods of setting and clearing these bits, and figure 16.12 shows the
processing flowchart.
Table 16.12 HIRQ Setting and Clearing Conditions
Host Interrupt
Setting Condition
Clearing Condition
HIRQ1
Slave writes to ODR1, then reads 0 from
bit IRQ1E1, and writes 1
Slave writes 0 to bit IRQ1E1, or host
reads ODR1
HIRQ12
Slave writes to ODR1, then reads 0 from
bit IRQ12E1, and writes 1
Slave writes 0 to bit IRQ12E1, or host
reads ODR1
SMI
(IEDIR = 0)
Slave
Slave
SMI
(IEDIR3 = 0)
Slave
•
writes to ODR2, then reads 0 from bit •
SMIE2, and writes 1
writes 0 to bit SMIE2, or host
reads ODR2
Slave
•
writes to ODR3, then reads 0 from bit •
SMIE3A, and writes 1
writes 0 to bit SMIE3A, or host
reads ODR3
•
writes to TWR15, then reads 0 from
bit SMIE3B, and writes 1
•
writes 0 to bit SMIE3B, or host
reads TWR15
SMI
(IEDIR = 1)
Slave
SMI
(IEDIR3 = 1)
Slave
Slave
•
•
writes 0 to bit SMIE3A
•
writes 0 to bit SMIE3B
•
•
reads 0 from bit SMIE2, then writes 1 •
reads 0 from bit SMIE3A, then writes
1
Slave writes 0 to bit SMIE2
reads 0 from bit SMIE3B, then writes
1
HIRQi
Slave
Slave
(i = 6, 9, 10, 11)
• writes to ODR2, then reads 0 from bit • writes 0 to bit IRQiE2, or host
(IEDIR = 0)
IRQiE2, and writes 1
reads ODR2
HIRQi
Slave
Slave
(i = 6, 9, 10, 11)
• writes to ODR3, then reads 0 from bit • writes 0 to bit IRQiE3, or host
(IEDIR3 = 0)
IRQiE3 and writes 1
reads ODR3
HIRQi
Slave
Slave
(i = 6, 9, 10, 11)
• reads 0 from bit IRQiE2, then writes 1 • writes 0 to bit IRQiE2
(IEDIR = 1)
HIRQi
Slave
Slave
(i = 6, 9, 10, 11)
• reads 0 from bit IRQiE3, then writes 1 • writes 0 to bit IRQiE3
(IEDIR3 = 1)
Rev. 3.00, 03/04, page 585 of 830
Slave CPU
Master CPU
ODR1 write
Write 1 to IRQ1E1
No
SERIRQ IRQ1 output
Interrupt initiation
SERIRQ IRQ1
source clearance
ODR1 read
OBF1 = 0?
Yes
No
All bytes
transferred?
Hardware operation
Yes
Software operation
Figure 16.12 HIRQ Flowchart (Example of Channel 1)
Rev. 3.00, 03/04, page 586 of 830
16.6
16.6.1
Usage Notes
Module Stop Setting
The LPC operation stop or enable can be specified by the module stop control register. With the
initial value, LPC operation will stop. Releasing module stop mode enables access to the register.
For details see section 23, Power-Down Modes.
16.6.2
Usage Note of LPC Interface
The LPC interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR is required to avoid data
contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the right to access TWR1 to TWR15
has been obtained.
Table 16.13 shows the host address example of registers LADR3, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Rev. 3.00, 03/04, page 587 of 830
Table 16.13 Host Addresses Example
Register
Host Address When LADR3 = H'A24F
Host Address When LADR3 = H'3FD0
IDR3
H'A24A and H'A24E
H'3FD0 and H'3FD4
ODR3
H'A24A
H'3FD0
STR3
H'A24E
H'3FD4
TWR0MW
H'A250
H'3FC0
TWR0SW
H'A250
H'3FC0
TWR1
H'A251
H'3FC1
TWR2
H'A252
H'3FC2
TWR3
H'A253
H'3FC3
TWR4
H'A254
H'3FC4
TWR5
H'A255
H'3FC5
TWR6
H'A256
H'3FC6
TWR7
H'A257
H'3FC7
TWR8
H'A258
H'3FC8
TWR9
H'A259
H'3FC9
TWR10
H'A25A
H'3FCA
TWR11
H'A25B
H'3FCB
TWR12
H'A25C
H'3FCC
TWR13
H'A25D
H'3FCD
TWR14
H'A25E
H'3FCE
TWR15
H'A25F
H'3FCF
Rev. 3.00, 03/04, page 588 of 830
Section 17 D/A Converter
17.1
•
•
•
•
•
Features
8-bit resolution
Two output channels
Conversion time: Max. 10 µs (when load capacitance is 20 pF)
Output voltage: 0 V to AVref
D/A output retaining function in software standby mode
Internal data bus
Bus interface
Module data bus
AVref
AVCC
DA1
8-bit D/A
D
A
D
R
0
D
A
D
R
1
D
A
C
R
DA0
AVSS
Control circuit
[Legend]
DACR: D/A control register
DADR0: D/A data register 0
DADR1: D/A data register 1
Figure 17.1 Block Diagram of D/A Converter
IFHSTL1A_010020030700
Rev. 3.00, 03/04, page 589 of 830
17.2
Input/Output Pins
Table 17.1 summarizes the input/output pins used by the D/A converter.
Table 17.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground and reference voltage
Analog output pin 0
DA0
Output
Channel 0 analog output
Analog output pin 1
DA1
Output
Channel 1 analog output
Input
Analog block reference voltage
Reference power supply pin AVref
Rev. 3.00, 03/04, page 590 of 830
17.3
Register Descriptions
The D/A converter has the following registers.
• D/A data register 0 (DADR0)
• D/A data register 1 (DADR1)
• D/A control register (DACR)
17.3.1
D/A Data Registers 0 and 1 (DADR0, DADR1)
DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion.
When analog output is permitted, D/A data register contents are converted and output to analog
output pins.
17.3.2
D/A Control Register (DACR)
DACR controls D/A converter operation.
Bit
Bit Name Initial Value
R/W
Description
7
DAOE1
R/W
D/A Output Enable 1
0
Controls D/A conversion and analog output.
0: Analog output DA1 is disabled
1: D/A conversion for channel 1 and analog output DA1
are enabled
6
DAOE0
0
R/W
D/A Output Enable 0
Controls D/A conversion and analog output.
0: Analog output DA0 is disabled
1: D/A conversion for channel 0 and analog output DA0
are enabled
5
DAE
0
R/W
D/A Enable
Controls D/A conversion in conjunction with the DAOE0
and DAOE1 bits. When the DAE bit is cleared to 0, D/A
conversion for channels 0 and 1 are controlled
individually. When the DAE bit is set to 1, D/A conversion
for channels 0 and 1 are controlled as one. Conversion
result output is controlled by the DAOE0 and DAOE1
bits. For details, see table 17.2 below.
4 to 0 
All 1
R
Reserved
The initial value should not be changed.
Rev. 3.00, 03/04, page 591 of 830
Table 17.2 D/A Channel Enable
Bit 7
Bit 6
Bit 5
DAOE1
DAOE0
DAE
Description
0
0
*
Disables D/A conversion
1
0
Enables D/A conversion for channel 0
Disables D/A conversion for channel 1
1
0
1
Enables D/A conversion for channels 0 and 1
0
Disables D/A conversion for channel 0
Enables D/A conversion for channel 1
1
1
Enables D/A conversion for channels 0 and 1
*
Enables D/A conversion for channels 0 and 1
[Legend]
*:
Don't care
Rev. 3.00, 03/04, page 592 of 830
17.4
Operation
The D/A converter incorporates two channels of the D/A circuits and can be converted
individually.
When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are
output.
An example of D/A conversion of channel 0 is shown below. The operation timing is shown in
figure 17.2.
1. Write conversion data to DADR0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV,
conversion results are output from the analog output pin DA0. The conversion results are
output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output
value is calculated by the following formula:
DADR contents/256 x AVref
3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV,
conversion results are output.
4. When the DAOE bit is cleared to 0, analog output is disabled.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
Conversion data (1)
DADR0
Conversion data (2)
DAOE0
Conversion
result (2)
Conversion result (1)
DA0
High impedance state
tDCONV
tDCONV
[Legend]
tDCONV : D/A conversion time
Figure 17.2 D/A Converter Operation Example
Rev. 3.00, 03/04, page 593 of 830
17.5
Usage Note
When this LSI enters software standby mode with D/A conversion enabled, the D/A output is
retained, and the analog power supply current is equal to as during D/A conversion. If the analog
power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0,
and DAE bits all to 0 to disable D/A output.
Rev. 3.00, 03/04, page 594 of 830
Section 18 A/D Converter
This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight
analog input channels to be selected.
18.1
Features
• 10-bit resolution
• Input channels: eight analog input channels
• Analog conversion voltage range can be specified using the reference power supply voltage
pin (AVref) as an analog reference voltage.
• Conversion time: 8.06 µs per channel (at 33-MHz operation)
• Two kinds of operating modes
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
Software, 8-bit timer (TMR) conversion start trigger, or external trigger signal.
• Interrupt request
A/D conversion end interrupt (ADI) request can be generated
• Module stop mode can be set
ADCMS33B_000020021100
Rev. 3.00, 03/04, page 595 of 830
18.1.1
Block Diagram
A block diagram of the A/D converter is shown in figure 18.1.
Module data bus
AVref
10-bit D/A
AVSS
AN0
AN4
AN5
AN6
Multiplexer
AN3
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
+
AN1
AN2
Bus interface
Successive approximations
register
AVCC
Internal data bus
Comparator
φ/8
Control circuit
φ/16
Sample-and-hold
circuit
AN7
ADI interrupt signal
Conversion start trigger from 8-bit timer
ADTRG
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 18.1 Block Diagram of A/D Converter
Rev. 3.00, 03/04, page 596 of 830
18.2
Input/Output Pins
Table 18.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided
into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising
group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
Table 18.1 Pin Configuration
Pin Name
Symbol
Analog power supply AVCC
pin
I/O
Function
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground and reference voltage
Reference power
supply pin
AVref
Input
Reference voltage for A/D conversion
Analog input pin 0
AN0
Input
Group 0 analog input pins
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger
input pin
ADTRG
Input
Group 1 analog input pins
External trigger input pin for starting A/D
conversion
Rev. 3.00, 03/04, page 597 of 830
18.3
Register Descriptions
The A/D converter has the following registers.
•
•
•
•
•
•
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
18.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 18.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read
directly from the CPU, but the lower byte should be read via a temporary register. The temporary
register contents are transferred from the ADDR when the upper byte data is read. When reading
the ADDR, read only the upper byte in byte units or read in word units.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register to Store A/D Conversion
Results
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
Rev. 3.00, 03/04, page 598 of 830
18.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit
Bit Name
Initial Value
R/W
Description
7
ADF
0
R/(W)*
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all channels
specified in scan mode
[Clearing conditions]
6
ADIE
0
R/W
•
When 0 is written after reading ADF = 1
•
When DTC starts by an ADI interrupt and ADDR is
read
A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1
5
ADST
0
R/W
A/D Start
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel ends. In scan
mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to standby mode or
module stop mode.
4
SCAN
0
R/W
Scan Mode
Selects the A/D conversion operating mode.
0: Single mode
1: Scan mode
3
CKS
0
R/W
Clock Select
Sets A/D conversion time.
0: Conversion time is 266 states (max)
1: Conversion time is 134 states (max)
(when the system clock (φ) is 16 MHz or lower)
Switch conversion time while ADST is 0.
Rev. 3.00, 03/04, page 599 of 830
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
CH2
CH1
CH0
All 0
R/W
Channel Select 2 to 0
Note:
*
18.3.3
Select analog input channels.
When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 and AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
100: AN4
100: AN4
101: AN5
101: AN4 and AN5
110: AN6
110: AN4 to AN6
111: AN7
111: AN4 to AN7
Only 0 can be written for clearing the flag.
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name
Initial Value
R/W
Description
7
6
TRGS1
TRGS0
0
0
R/W
R/W
Timer Trigger Select 1 and 0
Enable the start of A/D conversion by a trigger signal.
Only set bits TRGS1 and TRGS0 while A/D
conversion is stopped (ADST = 0).
00: A/D conversion start by external trigger is disabled
01: A/D conversion start by external trigger is disabled
10: A/D conversion start by conversion trigger from
TMR
11: A/D conversion start by ADTRG pin
5 to
0

All 1
Rev. 3.00, 03/04, page 600 of 830
R/W
Reserved
The initial values should not be changed.
18.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
18.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1,
by software or an external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
1 at this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is
automatically cleared to 0, and the A/D converter enters wait state.
18.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four
channels max.). Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
conversion starts on the first channel in the group (AN0 when the CH2 bit in ADCSR is 0, or
AN4 when the CH2 bit in ADCSR is 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
4. The ADST bit is not automatically cleared to 0 so steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Rev. 3.00, 03/04, page 601 of 830
18.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 indicates
the A/D conversion time.
As indicated in figure 18.2, the A/D conversion time (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states
(fixed) when CKS = 1.
Use the conversion time of 134 state only when the system clock (φ) is 16 MHz or lower.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
tD:
A/D conversion start delay
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 18.2 A/D Conversion Timing
Rev. 3.00, 03/04, page 602 of 830
Table 18.3 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1*
Item
Symbol
min
typ
max
min
typ
max
A/D conversion start delay time
tD
10

17
6

9
Input sampling time
tSPL

63


31

A/D conversion time
tCONV
259

266
131

134
Notes: Values in the table indicate the number of states.
* in the table indicates that the system clock (φ) is 16 MHz or lower.
18.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 18.3 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 18.3 External Trigger Input Timing
Rev. 3.00, 03/04, page 603 of 830
18.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1
after A/D conversion ends.
The ADI interrupt can be used as a DTC activation interrupt source.
Table 18.4 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
ADI
A/D conversion end
ADF
Possible
18.6
A/D Conversion Accuracy Definitions
This LSI’s A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'00 0000 0000 (H'000) to
B'00 0000 0001 (H'001) (see figure 18.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'11 1111 1110 (H'3FE) to B'11 1111 1111 (H'3FF) (see
figure 18.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error
(see figure 18.5).
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Rev. 3.00, 03/04, page 604 of 830
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 18.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog
input voltage
Figure 18.5 A/D Conversion Accuracy Definitions
Rev. 3.00, 03/04, page 605 of 830
18.7
Usage Notes
18.7.1
Permissible Signal Source Impedance
This LSI’s analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 5 kΩ or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally in single mode, the input load will essentially comprise only the internal input
resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter
effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., voltage fluctuation ratio of 5 mV/µs or greater) (see figure 18.6).
When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer
should be inserted.
18.7.2
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVSS.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
This LSI
Sensor output
impedance
up to 5 kΩ
A/D converter equivalent circuit
10 kΩ
Sensor input
Low-pass
filter C
up to 0.1 µF
Cin =
15 pF
Figure 18.6 Example of Analog Input Circuit
Rev. 3.00, 03/04, page 606 of 830
20 pF
18.7.3
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of this LSI may be adversely affected.
•
Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVSS ≤ ANn ≤ AVref (n = 0 to 7).
• Relation between AVCC, AVSS and VCC, VSS
For the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS, and AVCC =
VCC is not always necessary. If the A/D converter is not used, the AVCC and AVSS pins
must on no account be left open.
• AVref pin reference voltage specification range
The reference voltage of the AVref pin should be in the range AVref ≤ AVCC.
18.7.4
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply
(AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at
one point to a stable digital ground (VSS) on the board.
18.7.5
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7) should be connected between AVCC and AVSS as
shown in figure 18.7. Also, the bypass capacitors connected to AVCC and AVref, and the filter
capacitors connected to AN0 to AN7 must be connected to AVSS.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding the circuit
constants.
Rev. 3.00, 03/04, page 607 of 830
AVCC
AVref
*1
Rin *2
*1
100 Ω
AN0 to AN7
0.1 µF
AVSS
Notes: Values are reference values.
*1
10 µF
*2
0.01 µF
Rin: Input impedance
Figure 18.7 Example of Analog Input Protection Circuit
10 kΩ
To A/D converter
AN0 to AN7
20 pF
Note: Values are reference values.
Figure 18.8 Analog Input Pin Equivalent Circuit
Rev. 3.00, 03/04, page 608 of 830
Section 19 RAM
This LSI has 40 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a
16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
Rev. 3.00, 03/04, page 609 of 830
Rev. 3.00, 03/04, page 610 of 830
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
The flash memory has the following features. Figure 20.1 shows a block diagram of the flash
memory.
20.1
Features
• Size
Product Classification
ROM Size
ROM Address
H8S/2168
HD64F2168
256 kbytes
H'000000 to H'03FFFF
H8S/2167
HD64F2167
384 kbytes
H'000000 to H'05FFFF
H8S/2166
HD64F2166
512 kbytes
H'000000 to H'07FFFF
• Two flash-memory MATs according to LSI initiation mode
The on-chip flash memory has two memory spaces in the same address space (hereafter
referred to as memory MATs). The mode setting in the initiation determines which memory
MAT is initiated first. The MAT can be switched by using the bank-switching method after
initiation.
 The user memory MAT is initiated at a power-on reset in user mode: 256 kbytes
(H8S/2168), 384 kbytes (H8S/2167), 512 kbytes (H8S/2166)
 The user boot memory MAT is initiated at a power-on reset in user boot mode: 8 kbytes
• Programming/erasing interface by the download of on-chip program
This LSI has a dedicated programming/erasing program. After downloading this program to
the on-chip RAM, programming/erasing can be performed by setting the argument parameter.
• Programming/erasing time
The flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming and
approximately 25 µs per byte. The erasing time is 1000 ms (typ) per 64-kbyte block.
• Number of programming
The number of flash memory programming can be up to 100 times at the minimum. (The value
ranged from 1 to 100 is guaranteed.)
• Three on-board programming modes
 Boot mode
This mode is a program mode that uses an on-chip SCI interface. The user MAT and user
boot MAT can be programmed. This mode can automatically adjust the bit rate between
host and this LSI.
 User program mode
The user MAT can be programmed by using the optional interface.
ROM1250A_000020030700
Rev. 3.00, 03/04, page 611 of 830
 User boot mode
The user boot program of the optional interface can be made and the user MAT can be
programmed.
• Programming/erasing protection
Sets protection against flash memory programming/erasing via hardware, software, or error
protection.
• Programmer mode
This mode uses the PROM programmer. The user MAT and user boot MAT can be
programmed.
Internal address bus
Internal data bus (16 bits)
FCCS
Memory MAT unit
Module bus
FPCS
FECS
FKEY
Control unit
FMATS
FTDAR
User MAT:
256 kbytes (H8S/2168)
384 kbytes (H8S/2167)
512 kbytes (H8S/2166)
User boot MAT: 8 kbytes
Flash memory
FWE pin
Mode pin
[Legend]
FCCS:
FPCS:
FECS:
FKEY:
FMATS:
FTDAR:
Operating
mode
Flash code control status register
Flash program code select register
Flash erase code select register
Flash key code register
Flash MAT select register
Flash transfer destination address register
Note: To read from or write to the registers, the FLSHE bit in the serial timer control
register (STCR) must be set to 1.
Figure 20.1 Block Diagram of Flash Memory
Rev. 3.00, 03/04, page 612 of 830
20.1.1
Operating Mode
When each mode pin and the FWE pin are set in the reset state and reset start is performed, this
LSI enters each operating mode as shown in figure 20.2.
• Flash memory can be read in user mode, but cannot be programmed or erased.
• Flash memory can be read, programmed, or erased on the board only in boot mode, user
program mode, and user boot mode.
• Flash memory can be read, programmed, or erased by means of the PROM programmer in
programmer mode.
RES = 0
Reset state
=0
es
FLSHE = 0
→ FWE = 0
User mode
FWE = 1 →
FLSHE = 1
User program
mode
=0
od
rm
Programmer
mode
RE
g
RES
in
ett
S
RE
e
Us
=0
ot g
bo tin
er set
Us de
mo
S
RE
Programmer mode setting
S=
Bo
ot
0
mo
de
se
ttin
g
User boot
mode
Boot mode
On-board programming mode
Figure 20.2 Mode Transition of Flash Memory
Rev. 3.00, 03/04, page 613 of 830
20.1.2
Mode Comparison
The comparison table of programming and erasing related items about boot mode, user program
mode, user boot mode, and programmer mode is shown in table 20.1.
Table 20.1 Comparison of Programming Modes
Boot mode
User program
mode
User boot mode
Programming/
erasing
environment
On-board
On-board
On-board
Programming/
erasing enable
MAT
User MAT
User boot MAT
User MAT
User MAT
All erasure
Block division
erasure
Programmer
mode
PROM
programmer
User MAT
User boot MAT
(Automatic)
(Automatic)
×
1
*
Program data
transfer
From host via SCI Via optional device Via optional device Via programmer
Reset initiation
MAT
Embedded
program storage
MAT
User MAT
User boot MAT*
2

Transition to user
mode
Changing mode
setting and reset
Changing FLSHE
bit and FWE pin
Changing mode
setting and reset

Notes: 1. All-erasure is performed. After that, the specified block can be erased.
2. Firstly, the reset vector is fetched from the embedded program storage MAT. After the
flash memory related registers are checked, the reset vector is fetched from the user
boot MAT.
• The user boot MAT can be programmed or erased only in boot mode and programmer mode.
• The user MAT and user boot MAT are erased in boot mode. Then, the user MAT and user boot
MAT can be programmed by means of the command method. However, the contents of the
MAT cannot be read until this state.
Only user boot MAT is programmed and the user MAT is programmed in user boot mode or
only user MAT is programmed because user boot mode is not used.
• The boot operation of the optional interface can be performed by the mode pin setting different
from user program mode in user boot mode.
Rev. 3.00, 03/04, page 614 of 830
20.1.3
Flash Memory MAT Configuration
This LSI’s flash memory is configured by the 8-kbyte user boot MAT and 256-kbyte (H8S/2168),
384-kbyte (H8S/2167), or 512-kbytes (H8S/2166) user MAT.
The start address is allocated to the same address in the user MAT and user boot MAT. Therefore,
when the program execution or data access is performed between two MATs, the MAT must be
switched by using FMATS.
The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be
programmed only in boot mode and programmer mode.
Address H'000000
<User MAT>
<User Boot MAT>
Address H'000000
8 kbytes
Address H'001FFF
256 kbytes
(H8S/2168)
384 kbytes
(H8S/2167)
Address H'03FFFF
512 kbytes
(H8S/2166)
Address H'05FFFF
Address H'07FFFF
Figure 20.3 Flash Memory Configuration
The size of the user MAT is different from that of the user boot MAT. An address which exceeds
the size of the 8-kbyte user boot MAT should not be accessed. If the attempt is made, data is read
as undefined value.
Rev. 3.00, 03/04, page 615 of 830
20.1.4
Block Division
The user MAT is divided into 64 kbytes (three blocks for H8S/2168, five blocks for H8S/2167,
seven blocks for H8S/2166), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure
20.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0
to EB15 is specified when erasing.
Rev. 3.00, 03/04, page 616 of 830
EB0
→Programming unit: 128 bytes→
H'00007F
H'000F82
– – – – – – – – – – – – – –
H'000FFF
H'001002
→Programming unit: 128 bytes→
H'00107F
H'001F82
– – – – – – – – – – – – – –
H'001FFF
H'002002
→Programming unit: 128 bytes→
H'00207F
H'002F82
– – – – – – – – – – – – – –
H'002FFF
H'003002
→Programming unit: 128 bytes→
H'00307F
H'003F82
– – – – – – – – – – – – – –
H'003FFF
H'004002
→Programming unit: 128 bytes→
H'00407F
H'00BF82
– – – – – – – – – – – – – –
H'00BFFF
H'00C002
→Programming unit: 128 bytes→
H'00C07F
H'00CF82
– – – – – – – – – – – – – –
H'00CFFF
H'00D002
→Programming unit: 128 bytes→
H'00D07F
H'00DF82
– – – – – – – – – – – – – –
H'00DFFF
H'00E002
→Programming unit: 128 bytes→
H'00E07F
H'00EF82
– – – – – – – – – – – – – –
H'00EFFF
H'00F002
→Programming unit: 128 bytes→
H'00F07F
H'00FF82
– – – – – – – – – – – – – –
H'00FFFF
H'010002
→Programming unit: 128 bytes→
H'01007F
H'01FF82
– – – – – – – – – – – – – –
H'01FFFF
H'020002
→Programming unit: 128 bytes→
H'02007F
H'02FF82
– – – – – – – – – – – – – –
H'02FFFF
H'030002
→Programming unit: 128 bytes→
H'03007F
H'000000
H'000001
H'000002
H'000F80
H'000F81
H'001000
H'001001
H'001F80
H'001F81
H'002000
H'002001
H'002F80
H'002F81
H'003000
H'003001
H'003F80
H'003F81
H'004000
H'004001
H'00BF80
H'00BF81
H'00C000
H'00C001
H'00CF80
H'00CF81
H'00D000
H'00D001
H'00DF80
H'00DF81
H'00E000
H'00E001
H'00EF80
H'00EF81
H'00F000
H'00F001
H'00FF80
H'00FF81
H'010000
H'010001
H'01FF80
H'01FF81
H'020000
H'020001
H'02FF80
H'02FF81
H'030000
H'030001
Erase unit: 4 kbytes
EB1
Erase unit: 4 kbytes
EB2
Erase unit: 4 kbytes
EB3
Erase unit: 4 kbytes
EB4
Erase unit: 32 kbytes
EB5
Erase unit: 4 kbytes
EB6
Erase unit: 4 kbytes
EB7
Erase unit: 4 kbytes
EB8
Erase unit: 4 kbytes
EB9
Erase unit: 64 kbytes
EB10
Erase unit: 64 kbytes
EB11
Erase unit: 64 kbytes
EB12*1
H'03FF80
H'03FF81
H'03FF82
– – – – – – – – – – – – – –
H'03FFFF
H'040000
H'04F001
H'04F002
→Programming unit: 128 bytes→
H'04F07F
H'04FF80
H'04FF81
H'04FF82
– – – – – – – – – – – – – –
H'04FFFF
H'050000
H'050001
H'050002
→Programming unit: 128 bytes→
H'05007F
H'05FF80
H'05FF81
H'05FF82
– – – – – – – – – – – – – –
H'05FFFF
H'060000
H'060001
H'060002
→Programming unit: 128 bytes→
H'06007F
H'06FF80
H'06FF81
H'06FF82
– – – – – – – – – – – – – –
H'06FFFF
H'070000
H'070001
H'070002
→Programming unit: 128 bytes→
H'07007F
H'07FF80
H'07FF81
H'07FF82
– – – – – – – – – – – – – –
H'07FFFF
Erase unit: 64 kbytes
EB13*1
Erase unit: 64 kbytes
EB14*1*2
Erase unit: 64 kbytes
EB15*1*2
Erase unit: 64 kbytes
Notes: 1. EB12 to EB15 are not available in the H8S/2168.
2. EB14 and EB15 are not available in the H8S/2167.
Figure 20.4 Block Division of User MAT
Rev. 3.00, 03/04, page 617 of 830
20.1.5
Programming/Erasing Interface
Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and
specifying the program address/data and erase block by using the interface register/parameter.
The procedure program is made by the user in user program mode and user boot mode. An
overview of the procedure is given as follows. For details, see section 20.4.2, User Program Mode.
Start user procedure
program for programming/erasing.
Select on-chip program to be
downloaded and
specify the destination.
Download on-chip program
by setting FKEY and SCO bits.
Initialization execution
(downloaded program execution)
Programming (in 128-byte units)
or erasing (in one-block units)
(downloaded program execution)
No
Programming/erasing
completed?
Yes
End user procedure
program
Figure 20.5 Overview of User Procedure Program
1. Selection of on-chip program to be downloaded
For programming/erasing execution, the FLSHE bit in STCR must be set to 1 to transition to
user program mode.
This LSI has programming/erasing programs which can be downloaded to the on-chip RAM.
The on-chip program to be downloaded is selected by setting the corresponding bits in the
programming/erasing interface register. The address of the programming destination is
specified by the flash transfer destination address register (FTDAR).
Rev. 3.00, 03/04, page 618 of 830
2. Download of on-chip program
The on-chip program is automatically downloaded by setting the flash key code register
(FKEY) and the SCO bit in the flash code control status register (FCCS), which are
programming/erasing interface registers.
The flash memory is replaced to the embedded program storage area when downloading. Since
the flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in the space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameter,
whether the normal download is executed or not can be confirmed.
3. Initialization of programming/erasing
The operating frequency is set before execution of programming/erasing. This setting is
performed by using the programming/erasing interface parameter.
4. Programming/erasing execution
For programming/erasing execution, the FLSHE bit in STCR and the FWE pin must be set to 1
to transition to user program mode.
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameter and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction and performing the subroutine call of the specified address in the on-chip RAM.
The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory.
All interrupts are prohibited during programming and erasing. Interrupts must be masked
within the user system.
5. When programming/erasing is executed consecutively
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.
Rev. 3.00, 03/04, page 619 of 830
20.2
Input/Output Pins
Table 20.2 shows the flash memory pin configuration.
Table 20.2 Pin Configuration
Pin Name
Input/Output
Function
RES
Input
Reset
FWE
Input
Flash memory programming/erasing enable pin
MD2
Input
Sets operating mode of this LSI
MD1
Input
Sets operating mode of this LSI
MD0
Input
Sets operating mode of this LSI
TxD1
Output
Serial transmit data output (used in boot mode)
RxD1
Input
Serial receive data input (used in boot mode)
20.3
Register Descriptions
The registers/parameters which control flash memory are shown in the following. To read from or
write to these registers/parameters, the FLSHE bit in the serial timer control register (STCR) must
be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
•
•
•
•
•
•
•
•
•
•
•
•
Flash code control status register (FCCS)
Flash program code select register (FPCS)
Flash erase code select register (FECS)
Flash key code register (FKEY)
Flash MAT select register (FMATS)
Flash transfer destination address register (FTDAR)
Download pass/fail result (DPFR)
Flash pass/fail result (FPFR)
Flash multipurpose address area (FMPAR)
Flash multipurpose data destination area (FMPDR)
Flash erase Block select (FEBS)
Flash programming/erasing frequency control (FPEFEQ)
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 20.3.
Rev. 3.00, 03/04, page 620 of 830
Table 20.3 Register/Parameter and Target Mode
Download
Programming/
FCCS
Erasing Interface FPCS
Register
FECS

FTDAR
Programming/
DPFR
Erasing Interface FPFR
Parameter
FPEFEQ
Programming
Erasure
Read













FKEY
FMATS
Initialization


*1
*1
*2














FMPAR




FMPDR




FEBS




Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
20.3.1
Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. These registers are initialized at a reset or in hardware standby mode.
Rev. 3.00, 03/04, page 621 of 830
• Flash Code Control Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of on-chip program.
Bit
Initial
Bit Name Value
R/W
Description
7
FWE
R
Flash Program Enable
1/0
Monitors the signal level input to the FWE pin and
enables or disables programming/erasing flash memory.
0: Programming/erasing disabled
1: Programming/erasing enabled
6, 5

All 0
R/W
4
FLER
0
R
Reserved
The initial value should not be changed.
Flash Memory Error
Indicates an error occurs during programming and
erasing flash memory. When FLER is set to 1, flash
memory enters the error protection state.
When FLER is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to flash
memory, the reset must be released after the reset
period of 100 µs which is longer than normal.
0: Flash memory operates normally.
Programming/erasing protection for flash memory
(error protection) is invalid.
[Clearing condition]
•
At a reset or in hardware standby mode
1: An error occurs during programming/erasing flash
memory.
Programming/erasing protection for flash memory
(error protection) is valid.
[Setting conditions]
Rev. 3.00, 03/04, page 622 of 830
•
When an interrupt, such as NMI, occurs during
programming/erasing flash memory.
•
When the flash memory is read during
programming/erasing flash memory (including a
vector read or an instruction fetch).
•
When the SLEEP instruction is executed during
programming/erasing flash memory (including
software-standby mode)
•
When a bus master other than the CPU, such as the
DTC, gets bus mastership during
programming/erasing flash memory.
Bit
Initial
Bit Name Value
R/W
Description
3
WEINTE
R/W
Program/Erase Enable
0
Modifies the space for the interrupt vector table, when
interrupt vector data is not read successfully during
programming/erasing flash memory or switching between
a user MAT and a user boot MAT. When this bit is set to
1, interrupt vector data is read from address spaces
H'FFE080 to H'FFE0FF (on-chip RAM space), instead of
from address spaces H'000000 to H'00007F (up to vector
number 31). Therefore, make sure to set the vector table
in the on-chip RAM space before setting this bit to 1.
The interrupt exception handling on and after vector
number 32 should not be used because the correct
vector is not read, resulting in the CPU runaway.
0: The space for the interrupt vector table is not
modified.
When interrupt vector data is not read successfully,
the operation for the interrupt exception handling
cannot be guaranteed. An occurrence of any
interrupts should be masked.
1: The space for the interrupt vector table is modified.
Even when interrupt vector data is not read
successfully, the interrupt exception handling up to
vector number 31 is enabled.
2, 1

All 0
R/W
Reserved
The initial value should not be changed.
0
SCO
0
(R)/W*
Source Program Copy Operation
Requests the on-chip programming/erasing program to
be downloaded to the on-chip RAM.
When this bit is set to 1, the on-chip program which is
selected by FPCS/FECS is automatically downloaded in
the on-chip RAM specified by FTDAR.
In order to set this bit to 1, H′A5 must be written to FKEY
and this operation must be executed in the on-chip RAM.
Four NOP instructions must be executed immediately
after setting this bit to 1.
Since this bit is cleared to 0 when download is
completed, this bit cannot be read as 1.
All interrupts must be disabled. This should be made in
the user system.
0: Download of the on-chip programming/erasing
program to the on-chip RAM is not executed.
Rev. 3.00, 03/04, page 623 of 830
Bit
Initial
Bit Name Value
R/W
Description
0
SCO
(R)/W*
[Clearing condition]
When download is completed
0
1: Request that the on-chip programming/erasing
program is downloaded to the on-chip RAM is
occurred.
[Setting conditions]
When all of the following conditions are satisfied and 1 is
set to this bit
• H'A5 is written to FKEY
•
Note:
*
During execution in the on-chip RAM
This bit is a write only bit. This bit is always read as 0.
• Flash Program Code Select Register (FPCS)
FPCS selects the on-chip programming program to be downloaded.
Bit
Initial
Bit Name Value
R/W
Description
7 to 1

R/W
Reserved
All 0
The initial value should not be changed.
0
PPVS
0
R/W
Program Pulse Verify
Selects the programming program.
0: On-chip programming program is not selected.
[Clearing condition] When transfer is completed
1: On-chip programming program is selected.
• Flash Erase Code Select Register (FECS)
FECS selects download of the on-chip erasing program.
Bit
Initial
Bit Name Value
R/W
Description
7 to 1

R/W
Reserved
All 0
The initial value should not be changed.
0
EPVB
0
R/W
Erase Pulse Verify Block
Selects the erasing program.
0: On-chip erasing program is not selected.
[Clearing condition] When transfer is completed
1: On-chip erasing program is selected.
Rev. 3.00, 03/04, page 624 of 830
• Flash Key Code Register (FKEY)
FKEY is a register for software protection that enables download of on-chip program and
programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing
cannot be executed if the key code is not written.
Bit
Initial
Bit Name Value
R/W
Description
7
6
5
4
3
2
1
0
K7
K6
K5
K4
K3
K2
K1
K0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Key Code
0
0
0
0
0
0
0
0
Only when H'A5 is written, writing to the SCO bit is valid.
When the value other than H'A5 is written to FKEY, 1
cannot be set to the SCO bit. Therefore downloading to
the on-chip RAM cannot be executed.
Only when H'5A is written, programming/erasing can be
executed. Even if the on-chip programming/erasing
program is executed, the flash memory cannot be
programmed or erased when the value other than H'5A
is written to FKEY.
H'A5: Writing to the SCO bit is enabled. (The SCO bit
cannot be set by the value other than H'A5.)
H'5A: Programming/erasing is enabled. (The value other
than H'A5 is in software protection state.)
H'00: Initial value
Rev. 3.00, 03/04, page 625 of 830
• Flash MAT Select Register (FMATS)
FMATS specifies whether user MAT or user boot MAT is selected.
Bit
Initial
Bit Name Value
R/W
Description
7
6
5
4
3
2
1
0
MS7
MS6
MS5
MS4
MS3
MS2
MS1
MS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MAT Select
0/1*
0
0/1*
0
0/1*
0
0/1*
0
These bits are in user-MAT selection state when the
value other than H'AA is written and in user-boot-MAT
selection state when H'AA is written.
The MAT is switched by writing the value in FMATS.
When the MAT is switched, follow section 20.6,
Switching between User MAT and User Boot MAT. (The
user boot MAT cannot be programmed in user program
mode if user boot MAT is selected by FMATS. The user
boot MAT must be programmed in boot mode or in
programmer mode.)
H'AA: The user boot MAT is selected (in user-MAT
selection state when the value of these bits are
other than H'AA)
Initial value when these bits are initiated in user
boot mode.
H'00: Initial value when these bits are initiated in a mode
except for user boot mode (in user-MAT selection
state)
[Programmable condition]
These bits are in the execution state in the on-chip RAM.
Note:
*
Set to 1 when in user boot mode, otherwise set to 0.
Rev. 3.00, 03/04, page 626 of 830
• Flash Transfer Destination Address Register (FTDAR)
FTDAR is a register that specifies the address to download an on-chip program. This register must
be specified before setting the SCO bit in FCCS to 1.
Bit
Initial
Bit Name Value
R/W
Description
7
TDER
R/W
Transfer Destination Address Setting Error
0
This bit is set to 1 when the address specified by bits
TDA6 to TDA0, which is the start address to download an
on-chip program, is over the range. Whether or not the
range specified by bits TDA6 to TDA0 is within the range
of H'00 to H'03 is determined when an on-chip program is
downloaded by setting the SCO bit in FCCS to 1. Make
sure that this bit is cleared to 0 before setting the SCO bit
to 1 and the value specified by TDA6 to TDA0 is within
the range of H'00 to H'03.
0: The value specified by bits TDA6 to TDA0 is within the
range.
1: The value specified by is TDA6 to TDA0 is over the
range (H'04 to H'FF) and the download is stopped.
6
5
4
3
2
1
0
TDA6
TDA5
TDA4
TDA3
TDA2
TDA1
TDA0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transfer Destination Address
Specifies the start address to download an on-chip
program. H'00 to H'03 can be specified as the start
address in the on-chip RAM space.
H'00: H'FFE080 is specified as a start address to
download an on-chip program.
H'01: H'FF0800 is specified as a start address to
download an on-chip program.
H'02: H'FF1800 is specified as a start address to
download an on-chip program.
H'03: H'FF8800 is specified as a start address to
download an on-chip program.
H'04 to H'FF: Setting prohibited. Specifying this value
sets the TDER bit to 1 and stops the
download.
Rev. 3.00, 03/04, page 627 of 830
20.3.2
Programming/Erasing Interface Parameter
The programming/erasing interface parameter specifies the operating frequency, storage place for
program data, programming destination address, and erase block and exchanges the processing
result for the downloaded on-chip program. This parameter uses the general registers of the CPU
(ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware
standby mode.
When download, initialization, or on-chip program is executed, registers of the CPU except for
R0L are stored. The return value of the processing result is written in R0L. Since the stack area is
used for storing the registers except for R0L, the stack area must be saved at the processing start.
(A maximum size of a stack area to be used is 128 bytes.)
The programming/erasing interface parameter is used in the following four items.
1.
2.
3.
4.
Download control
Initialization before programming or erasing
Programming
Erasing
These items use different parameters. The correspondence table is shown in table 20.4. The
meaning of the bits in FPFR varies in each processing program: initialization, programming, or
erasure. For details, see descriptions of FPFR for each process.
Rev. 3.00, 03/04, page 628 of 830
Table 20.4 Parameters and Target Modes
Name of
Parameter
Abbreviation
Down
Load
Download pass/fail DPFR
result
Flash pass/fail
result
FPFR

Flash
programming/
erasing frequency
control
FPEFEQ

Initialization
Programming
Erasure
R/W
Initial
Value
Allocation



R/W
Undefined
On-chip
RAM*
R/W
Undefined
R0L of
CPU

R/W
Undefined
ER0 of
CPU

Flash multipurpose FMPAR
address area



R/W
Undefined
ER1 of
CPU
Flash multipurpose FMPDR
data destination
area



R/W
Undefined
ER0 of
CPU
Flash erase block
select


R/W
Undefined
R0L of
CPU
Note:
*
FEBS

A single byte of the start address to download an on-chip program, which is specified by
FTDAR
Rev. 3.00, 03/04, page 629 of 830
(1)
Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the 2-kbyte area starting from the address specified by FTDAR.
Download control is set by the program/erase interface registers, and the DPFR parameter
indicates the return value.
(a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by writing the single byte of
the start address specified by FTDAR to the value other than the return value of download (for
example, H'FF) before the download start (before setting the SCO bit to 1).
Bit
Initial
Bit Name Value
R/W
7 to 3



Description
Unused
Return 0
2
SS

R/W
Source Select Error Detect
Only one type for the on-chip program which can be
downloaded can be specified. When more than two
types of the program are selected, the program is not
selected, or the program is selected without mapping,
error is occurred.
0: Download program can be selected normally
1: Download error is occurred (multi-selection or
program which is not mapped is selected)
1
FK

R/W
Flash Key Register Error Detect
Returns the check result whether the value of FKEY is
set to H′A5.
0: KEY setting is normal (FKEY = H'A5)
1: Setting value of FKEY becomes error (FKEY = value
other than H'A5)
0
SF

R/W
Success/Fail
Returns the result whether download is ended normally
or not. The determination result whether program that is
downloaded to the on-chip RAM is read back and then
transferred to the on-chip RAM is returned.
0: Downloading on-chip program is ended normally (no
error)
1: Downloading on-chip program is ended abnormally
(error occurs)
Rev. 3.00, 03/04, page 630 of 830
(2)
Programming/Erasing Initialization
The on-chip programming/erasing program to be downloaded includes the initialization program.
The specified period pulse must be applied when programming or erasing. The specified pulse
width is made by the method in which wait loop is configured by the CPU instruction. The
operating frequency of the CPU must be set.
The initial program is set as a parameter of the programming/erasing program which has
downloaded these settings.
(a) Flash programming/erasing frequency parameter (FPEFEQ: general register ER0 of CPU)
This parameter sets the operating frequency of the CPU. The settable range of the operating
frequency in this LSI is 5 to 33 MHz.
Bit
Initial
Bit Name Value
31 to 16 

R/W
Description

Unused
This bit should be cleared to 0.
15 to 0
F15 to F0 
R/W
Frequency Set
Set the operating frequency of the CPU. With the PLL
multiplication function, set the frequency multiplied. The
setting value must be calculated as the following
methods.
1. The operating frequency which is shown in MHz units
must be rounded in a number to three decimal places
and be shown in a number of two decimal places.
2. The value multiplied by 100 is converted to the binary
digit and is written to the FPEFEQ parameter
(general register ER0).
For example, when the operating frequency of the CPU
is 33.000 MHz, the value is as follows.
1. The number to three decimal places of 33.000 is
rounded and the value is thus 33.00.
2. The formula that 33.00 × 100 = 3300 is converted to
the binary digit and B'0000,1100,1110,0100
(H'0CE4) is set to ER0.
Rev. 3.00, 03/04, page 631 of 830
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the initialization result.
Bit
Initial
Bit Name Value
R/W
Description
7 to 2


Unused

Return 0
1
FQ

R/W
Frequency Error Detect
Returns the check result whether the specified operating
frequency of the CPU is in the range of the supported
operating frequency.
0: Setting of operating frequency is normal
1: Setting of operating frequency is abnormal
0
SF

R/W
Success/Fail
Indicates whether initialization is completed normally.
0: Initialization is ended normally (no error)
1: Initialization is ended abnormally (error occurs)
(3)
Programming Execution
When flash memory is programmed, the programming destination address on the user MAT must
be passed to the programming program in which the program data is downloaded.
1. The start address of the programming destination on the user MAT must be stored in a general
register ER1. This parameter is called as flash multipurpose address area parameter (FMPAR).
Since the program data is always in units of 128 bytes, the lower eight bits (A7 to A0) must be
H'00 or H'80 as the boundary of the programming start address on the user MAT.
2. The program data for the user MAT must be prepared in the consecutive area. The program
data must be in the consecutive space which can be accessed by using the MOV.B instruction
of the CPU and in other than the flash memory space.
When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be
prepared by filling with the dummy code H'FF.
The start address of the area in which the prepared program data is stored must be stored in a
general register ER0. This parameter is called as flash multipurpose data destination area
parameter (FMPDR).
For details on the program processing procedure, see section 20.4.2, User Program Mode.
Rev. 3.00, 03/04, page 632 of 830
(a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU)
This parameter stores the start address of the programming destination on the user MAT.
When the address in the area other than flash memory space is set, an error occurs.
The start address of the programming destination must be at the 128-byte boundary. If this
boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA
bit (bit 1) in FPFR.
Bit
31 to 0
Initial
Bit Name Value
MOA31 to 
MOA0
R/W
Description
R/W
Store the start address of the programming destination
on the user MAT. The consecutive 128-byte
programming is executed starting from the specified start
address of the user MAT. Therefore, the specified
programming start address becomes a 128-byte
boundary and MOA6 to MOA0 are always 0.
(b) Flash multipurpose data destination parameter (FMPDR: general register ER0 of CPU):
This parameter stores the start address in the area which stores the data to be programmed in the
user MAT. When the storage destination of the program data is in flash memory, an error occurs.
The error occurrence is indicated by the WD bit in FPFR.
Bit
31 to 0
Initial
Bit Name Value
MOD31 to 
MOD0
R/W
Description
R/W
Store the start address of the area which stores the
program data for the user MAT. The consecutive 128byte data is programmed to the user MAT starting from
the specified start address.
(c) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the program processing result.
Bit
Initial
Bit Name Value
R/W
Description
7


Unused

Return 0.
Rev. 3.00, 03/04, page 633 of 830
Bit
Initial
Bit Name Value
6
MD

R/W
Description
R/W
Programming Mode Related Setting Error Detect
Returns the check result that a high level signal is input
to the FWE pin and the error protection state is not
entered. When the low level signal is input to the FWE
pin or the error protection state is entered, 1 is written to
this bit. The state can be confirmed with the FWE and
FLER bits in FCCS. For conditions to enter the error
protection state, see section 20.5.3, Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: Programming cannot be performed (FWE = 0 or
FLER = 1)
5
EE

R/W
Programming Execution Error Detect
1 is returned to this bit when the specified data could not
be written because the user MAT was not erased. If this
bit is set to 1, there is a high possibility that the user MAT
is partially rewritten. In this case, after removing the error
factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is
selected, an error occurs when programming is
performed. In this case, both the user MAT and user boot
MAT are not rewritten. Programming of the user boot
MAT should be performed in boot mode or programmer
mode.
0: Programming has ended normally
1: Programming has ended abnormally (programming
result is not guaranteed)
4
FK

R/W
Flash Key Register Error Detect
Returns the check result of the value of FKEY before the
start of the programming processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H′5A)
3



Unused
Returns 0.
2
WD

R/W
Write Data Address Detect
When the address in the flash memory area is specified
as the start address of the storage destination of the
program data, an error occurs.
0: Setting of write data address is normal
1: Setting of write data address is abnormal
Rev. 3.00, 03/04, page 634 of 830
Bit
Initial
Bit Name Value
1
WA

R/W
Description
R/W
Write Address Error Detect
When the following items are specified as the start
address of the programming destination, an error occurs.
•
When the programming destination address in the
area other than flash memory is specified
•
When the specified address is not in a 128-byte
boundary. (The lower eight bits of the address are
other than H'00 and H'80.)
0: Setting of programming destination address is normal
1: Setting of programming destination address is
abnormal
0
SF

R/W
Success/Fail
Indicates whether the program processing is ended
normally or not.
0: Programming is ended normally (no error)
1: Programming is ended abnormally (error occurs)
Rev. 3.00, 03/04, page 635 of 830
(4)
Erasure Execution
When flash memory is erased, the erase-block number on the user MAT must be passed to the
erasing program which is downloaded. This is set to the FEBS parameter (general register ER0).
One block is specified from the block number 0 to 15.
For details on the erasing processing procedure, see section 20.4.2, User Program Mode.
(a) Flash erase block select parameter (FEBS: general register ER0 of CPU)
This parameter specifies the erase-block number. The several block numbers cannot be specified.
Bit
Initial
Bit Name Value
R/W
Description
31 to 8


Unused

These bits should be cleared to H′0.
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0








R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.00, 03/04, page 636 of 830
Erase Block
Set the erase-block number in the range from 0 to 15. 0
corresponds to the EB0 block and 15 corresponds to the
EB15 block. The number other than 0 to 11, 0 to 13, and
0 to 15 should not be set in the H8S/2168, H8S/2167,
and H8S/2166, respectively.
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter returns value of the erasing processing result.
Bit
Initial
Bit Name Value
R/W
Description
7



Unused
6
MD

R/W
Programming Mode Related Setting Error Detect
Return 0.
Returns the check result that a high level signal is input
to the FWE pin and the error protection state is not
entered. When the low level signal is input to the FWE
pin or the error protection state is entered, 1 is written to
this bit. The state can be confirmed with the FWE and
FLER bits in FCCS. For conditions to enter the error
protection state, see section 20.5.3, Error Protection.
0: FWE and FLER settings are normal (FWE = 1,
FLER = 0)
1: Programming cannot be performed (FWE = 0 or
FLER = 1)
5
EE

R/W
Erasure Execution Error Detect
1 is returned to this bit when the user MAT could not be
erased or when flash-memory related register settings
are partially changed. If this bit is set to 1, there is a high
possibility that the user MAT is partially erased. In this
case, after removing the error factor, erase the user
MAT. If FMATS is set to H'AA and the user boot MAT is
selected, an error occurs when erasure is performed. In
this case, both the user MAT and user boot MAT are not
erased. Erasing of the user boot MAT should be
performed in boot mode or programmer mode.
0: Erasure has ended normally
1: Erasure has ended abnormally (erasure result is not
guaranteed)
4
FK

R/W
Flash Key Register Error Detect
Returns the check result of FKEY value before start of
the erasing processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H′5A)
3
EB

R/W
Erase Block Select Error Detect
Returns the check result whether the specified eraseblock number is in the block range of the user MAT.
0: Setting of erase-block number is normal
1: Setting of erase-block number is abnormal
Rev. 3.00, 03/04, page 637 of 830
Bit
Initial
Bit Name Value
R/W
Description
2, 1


Unused

Return 0.
0
SF

R/W
Success/Fail
Indicates whether the erasing processing is ended
normally or not.
0: Erasure is ended normally (no error)
1: Erasure is ended abnormally (error occurs)
20.4
On-Board Programming Mode
When the pin is set in on-board programming mode and the reset start is executed, the on-board
programming state that can program/erase the on-chip flash memory is entered. On-board
programming mode has three operating modes: boot mode, user program mode, and user boot
mode.
For details of the pin setting for entering each mode, see table 20.5. For details of the state
transition of each mode for flash memory, see figure 20.2.
Table 20.5 Setting On-Board Programming Mode
Mode Setting
FWE
MD2
MD1
MD0
NMI
Boot mode
1
0
0
0
1
User program mode
1*
1
1
0
0/1
User boot mode
1
0
0
0
0
Note:
20.4.1
*
Before downloading the programming/erasing programs, the FLSHE bit must be set to
1 to transition to user program mode.
Boot Mode
Boot mode executes programming/erasing user MAT and user boot MAT by means of the control
command and program data transmitted from the host using the on-chip SCI. The tool for
transmitting the control command and program data must be prepared in the host. The SCI
communication mode is set to asynchronous mode. When reset start is executed after this LSI’s
pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate
is automatically adjusted, the communication with the host is executed by means of the control
command method.
Rev. 3.00, 03/04, page 638 of 830
The system configuration diagram in boot mode is shown in figure 20.6. For details on the pin
setting in boot mode, see table 20.5. The NMI and other interrupts are ignored in boot mode.
However, the NMI and other interrupts should be disabled in the user system.
This LSI
Host
Boot
Control command, program data
programming
tool and program
data
Reply response
Control command,
analysis execution
software (on-chip)
Flash
memory
RxD1
On-chip SCI_1
TxD1
On-chip RAM
Figure 20.6 System Configuration in Boot Mode
(1)
SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format
is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the
host by means of the measured low period and transmits the bit adjustment end sign (1 byte of
H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received
normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot
mode is initiated again (reset) and the operation described above must be executed. The bit rate
between the host and this LSI is not matched by the bit rate of transmission by the host and system
clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be
set to 4,800 bps, 9,600 bps, or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 20.6. Boot mode must be initiated in the range of this
system clock.
Start
bit
D0
D1
D2
D3
D4
D5
Measure low period (9 bits) (data is H'00)
D6
D7
Stop bit
High period of
at least 1 bit
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI
Rev. 3.00, 03/04, page 639 of 830
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
Bit Rate of Host
System Clock Frequency
4,800 bps
5 to 33 MHz
9,600 bps
5 to 33 MHz
19,200 bps
8 to 33 MHz
(2)
State Transition Diagram
The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
1. Bit rate adjustment
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
2. Waiting for inquiry set command
For inquiries about user-MAT size and configuration, MAT start address, and support state, the
required information is transmitted to the host.
3. Automatic erasure of all user MAT and user boot MAT
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
4. Waiting for programming/erasing command
 When the program preparation notice is received, the state for waiting program data is
entered. The programming start address and program data must be transmitted following
the programming command. When programming is finished, the programming start address
must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is
returned to the state of programming/erasing command wait.
 When the erasure preparation notice is received, the state for waiting erase-block data is
entered. The erase-block number must be transmitted following the erasing command.
When the erasure is finished, the erase-block number must be set to H'FF and transmitted.
Then the state for waiting erase-block data is returned to the state for waiting
programming/erasing command. The erasure must be used when the specified block is
programmed without a reset start after programming is executed in boot mode. When
programming can be executed by only one operation, all blocks are erased before the state
for waiting programming/erasing/other command is entered. The erasing operation is not
required.
 There are many commands other than programming/erasing. Examples are sum check,
blank check (erasure check), and memory read of the user MAT/user boot MAT and
acquisition of current status information.
Note that memory read of the user MAT/user boot MAT can only read the programmed data after
all user MAT/user boot MAT has automatically been erased.
Rev. 3.00, 03/04, page 640 of 830
(Bit rate adjustment)
H'00.......H'00 reception
H'00 transmission
(adjustment completed)
Boot mode initiation
(reset by boot mode)
Bit rate adjustment
H'55
2.
ption
rece
Inquiry command reception
Wait for inquiry
setting command
Inquiry command response
3.
4.
1.
Processing of
inquiry setting
command
All user MAT and
user boot MAT erasure
Wait for
programming/erasing
command
Read/check command
reception
Processing of
read/check command
Command response
(Erasure selection command reception)
(Erasure end notice)
(Program end notice)
(Program command reception)
(Erase-block specification)
Wait for erase-block
data
(Program data transmission)
Wait for program data
Figure 20.8 Overview of Boot Mode State Transition Diagram
Rev. 3.00, 03/04, page 641 of 830
20.4.2
User Program Mode
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be
programmed/erased.)
Programming/erasing is executed by downloading the program in the microcomputer.
The overview flow is shown in figure 20.9.
High voltage is applied to internal flash memory during the programming/erasing processing.
Therefore, transition to reset or hardware standby must not be executed. Doing so may damage or
destroy flash memory. If reset is executed accidentally, reset must be released after the reset input
period of 100 µs which is longer than normal.
Programming/erasing
start
When programming,
program data is prepared
1. Make sure that the program data will not overlap the download
destination specified by FTDAR.
2. The FWE bit is set to 1 by inputting a high level signal to the FWE
pin.
Programming/erasing
procedure program is
transferred to the on-chip
RAM and executed
3. Programming/erasing is executed only in the on-chip RAM.
However, if program data is in a consecutive area and can be
accessed by the MOV.B instruction of the CPU like RAM or
ROM, the program data can be in an external space.
Programming/erasing
end
4. After programming/erasing is finished, input a low level signal to
the FWE pin and transfer to the hardware protection state.
Figure 20.9 Programming/Erasing Overview Flow
Rev. 3.00, 03/04, page 642 of 830
(1)
On-chip RAM Address Map when Programming/Erasing is Executed
Parts of the procedure program that are made by the user, like download request,
programming/erasing procedure, and determination of the result, must be executed in the on-chip
RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in
the on-chip RAM must be controlled so that these parts do not overlap.
Figure 20.10 shows the program area to be downloaded.
Address
<On-chip RAM>
RAMTOP
Area that can be used by user*
DPFR
(Return value: 1 byte)
Area to be
downloaded
(Size : 2 kbytes)
Unusable area in
programming/erasing
processing period
FTDAR setting
System use area
(15 bytes)
Programming/erasing program entry
FTDAR setting + 16
Initialization program entry
FTDAR setting + 32
Initialization + programming program
or
Initialization + erasing program
Area that can be used by user*
FTDAR setting + 2 kbytes
RAMEND
Note: * The on-chip RAM area in this LSI is split into H'FF0800 to H'FF97FF,
H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F.
The area that can be used by the user is specified by FTDAR.
Figure 20.10 RAM Map When Programming/Erasing is Executed
Rev. 3.00, 03/04, page 643 of 830
(2)
Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 20.11.
1.
Disable interrupts and bus
master operation
other than CPU
Set FKEY to H'A5
2.
Set FKEY to H'5A
10.
Set SCO to 1 and
execute download
3.
Set parameters to ER1
and ER0
(FMPAR and FMPDR)
11.
Clear FKEY to 0
4.
Programming
JSR FTDAR setting + 16
12.
5.
DPFR = 0?
No
Yes
Initialization
1
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
6.
Initialization
JSR FTDAR setting + 32
7.
Yes
FPFR = 0?
Download error processing
Set the FPEFEQ
parameter
FPFR = 0?
Programming
Download
Start programming
procedure program
8.
No
Initialization error processing
1
Yes
No
Required data
programming is
completed?
9.
13.
No
Clear FKEY and
programming
error processing
14.
Yes
Clear FKEY to 0
15.
End programming
procedure program
Figure 20.11 Programming Procedure
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
Rev. 3.00, 03/04, page 644 of 830
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the dummy data to be added is H'FF, the program processing period can be
shortened.
1. Select the on-chip program to be downloaded and specify a download destination
When the PPVS bit of FPCS is set to 1, the programming program is selected. Several
programming/erasing programs cannot be selected at one time. If several programs are set,
download is not performed and a download error is returned to the SS bit in DPFR. The start
address of a download destination is specified by FTDAR.
2. Program H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for download
request.
3. 1 is set to the SCO bit of FCCS and then download is executed.
To set 1 to the SCO bit, the following conditions must be satisfied.
 H'A5 is written to FKEY.
 The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned
to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of DPFR. Before the SCO bit is
set to 1, incorrect determination must be prevented by setting the one byte of the start address
(to be used as DPFR) specified by FTDAR to a value other than the return value (e.g. H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
 The user-MAT space is switched to the on-chip program storage area.
 After the selection condition of the download program and the FTDAR setting are checked,
the transfer processing to the on-chip RAM specified by FTDAR is executed.
 The SCO bit in FCCS is cleared to 0.
 The return value is set to the DPFR parameter.
 After the on-chip program storage area is returned to the user-MAT space, the user
procedure program is returned.
 In the download processing, the values of general registers of the CPU are held.
Rev. 3.00, 03/04, page 645 of 830
 In the download processing, any interrupts are not accepted. However, interrupt requests
are held. Therefore, when the user procedure program is returned, the interrupts occur.
 When the level-detection interrupt requests are to be held, interrupts must be input until the
download is ended.
 When hardware standby mode is entered during download processing, the normal
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
 Since a stack area of 128 bytes at the maximum is used, the area must be allocated before
setting the SCO bit to 1.
 If a flash memory access by the DTC signal is requested during downloading, the operation
cannot be guaranteed. Therefore, an access request by the DTC signal must not be
generated.
4. FKEY is cleared to H'00 for protection.
5. The value of the DPFR parameter must be checked and the download result must be
confirmed.
 Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
 If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
 If the value of the DPFR parameter is different from before downloading, check the SS bit
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
6. The operating frequency are set to the FPEFEQ parameters for initialization.
 The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
ER0).
The settable range of the FPEFEQ parameter is 5 to 33 MHz. When the frequency is set to
out of this range, an error is returned to the FPFR parameter of the initialization program
and initialization is not performed. For details on the frequency setting, see the description
in 20.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ).
7. Initialization
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the start
address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and
initialization is executed by using the following steps.
Rev. 3.00, 03/04, page 646 of 830
MOV.L
#DLTOP+32,ER2
; Set entry address to ER2
JSR
NOP
@ER2
; Call initialization routine
 The general registers other than R0L are held in the initialization program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the initialization program, 128-byte stack area at the
maximum must be allocated in RAM.
 Interrupts can be accepted during the execution of the initialization program. The program
storage area and stack area in the on-chip RAM and register values must not be destroyed.
8. The return value in the initialization program, FPFR (general register R0L) is determined.
9. All interrupts and the use of a bus master other than the CPU are prohibited.
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, the
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts and bus mastership to other than the CPU, such as to the DTC, are
prohibited.
To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to
B'1 in interrupt control mode 0 or bits 7 and 6 (I and UI) should be set to B'11 in interrupt
control mode 1. Interrupts other than NMI are held and not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to other than the CPU, such as to the DTC, the error
protection state is entered. Therefore, taking bus mastership by the DTC is prohibited.
10. FKEY must be set to H′5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
 Example of the FMPAR setting
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits of the address must be H'00 or H'80 as the
boundary of 128 bytes.
Rev. 3.00, 03/04, page 647 of 830
 Example of the FMPDR setting
When the storage destination of the program data is flash memory, even if the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM
and then programming must be executed.
12. Programming
There is an entry point of the programming program in the area from the start address specified
by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
MOV.L
#DLTOP+16,ER2
; Set entry address to ER2
JSR
NOP
@ER2
; Call programming routine
 The general registers other than R0L are held in the programming program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the programming program, a stack area of 128 bytes at the
maximum must be allocated in RAM.
13. The return value in the programming program, FPFR (general register R0L) is determined.
14. Determine whether programming of the necessary data has finished.
If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps 12 to 14. Increment the programming destination address by 128
bytes and update the programming data pointer correctly. If an address which has already been
programmed is written to again, not only will a programming error occur, but also flash
memory will be damaged.
15. After programming finishes, clear FKEY and specify software protection.
If this LSI is restarted by a reset immediately after user MAT programming has finished,
secure the reset period (period of RES = 0) of 100 µs which is longer than normal.
Rev. 3.00, 03/04, page 648 of 830
(3)
Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 20.12.
Start erasing procedure
program
1
Set FKEY to H'A5
Set FKEY to H'5A
Set SCO to 1 and
execute download
Set FEBS parameter
2.
Erasing
JSR FTDAR setting + 16
3.
Clear FKEY to 0
DPFR = 0?
Yes
4.
FPFR = 0 ?
No
Yes
Download error processing
Set the FPEFEQ
parameter
Initialization
Disable interrupts and
bus master operation
other than CPU
1.
Erasing
Download
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
No
No
Clear FKEY and erasing
error processing
Required block
erasing is
completed?
Initialization
JSR FTDAR setting + 32
5.
Yes
Clear FKEY to 0
6.
FPFR = 0 ?
No
Yes Initialization error processing
End erasing
procedure program
1
Figure 20.12 Erasing Procedure
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in
figure 20.10.
A single divided block is erased by one erasing processing. For block divisions, refer to figure
20.4. To erase two or more blocks, update the erase block number and perform the erasing
processing for each block.
Rev. 3.00, 03/04, page 649 of 830
1. Select the on-chip program to be downloaded
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is reported to the SS bit in the DPFR
parameter.
Specify the start address of a download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, refer to Programming Procedure in
User Program Mode in section 20.4.2, sub-section (2).
The procedures after setting parameters for erasing programs are as follows:
2. Set the FEBS parameter necessary for erasure
Set the erase block number of the user MAT in the flash erase block select parameter FEBS
(general register ER0). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
3. Erasure
Similar to as in programming, there is an entry point of the erasing program in the area from
the start address of a download destination specified by FTDAR + 16 bytes of on-chip RAM.
The subroutine is called and erasing is executed by using the following steps.
MOV.L
#DLTOP+16,ER2
; Set entry address to ER2
JSR
NOP
@ER2
; Call erasing routine
•
•
•
The general registers other than R0L are held in the erasing program.
R0L is a return value of the FPFR parameter.
Since the stack area is used in the erasing program, a stack area of 128 bytes at the
maximum must be allocated in RAM.
4. The return value in the erasing program, FPFR (general register R0L) is determined.
5. Determine whether erasure of the necessary blocks has completed.
If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5.
Blocks that have already been erased can be erased again.
6. After erasure completes, clear FKEY and specify software protection.
If this LSI is restarted by a reset immediately after user MAT erasure has completed, secure
the reset period (period of RES = 0) of 100 µs which is longer than normal.
Rev. 3.00, 03/04, page 650 of 830
(4)
Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing
program and programming program can be downloaded to separate on-chip RAM areas.
Figure 20.13 shows a repeating procedure of erasing and programming.
Specify a download
destination of erasing
program by FTDAR
1
Download erasing program
Erase relevant block
(execute erasing program)
Initialize erasing program
Programming program
download
Specify a download
destination of programming
program by FTDAR
Download programming
program
Initialize programming
program
Erasing/ Programming
Erasing program
download
Start procedure program
Set FMPDR to
program relevant block
(execute programming
program)
Confirm operation
End ?
No
Yes
End procedure program
1
Figure 20.13 Repeating Procedure of Erasing and Programming
In the above procedure, download and initialization are performed only once at the beginning.
In this kind of operation, note the following:
• Be careful not to damage on-chip RAM with overlapped settings.
In addition to the erasing program area and programming program area, areas for the user
procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make
settings that will overwrite data in these areas.
• Be sure to initialize both the erasing program and programming program.
Initialization by setting the FPEFEQ parameter must be performed for both the erasing
program and the programming program. Initialization must be executed for both entry
addresses: (download start address for erasing program) + 32 bytes and (download start
address for programming program) + 32 bytes.
Rev. 3.00, 03/04, page 651 of 830
20.4.3
User Boot Mode
This LSI has user boot mode which is initiated with different mode pin settings than those in boot
mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that
uses the on-chip SCI.
Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the
user boot MAT is only enabled in boot mode or programmer mode.
(1)
User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 20.5.
When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT
and user boot MAT states are checked by this check routine.
While the check routine is running, NMI and all other interrupts cannot be accepted.
Next, processing starts from the execution start address of the reset vector in the user boot MAT.
At this point, H′AA is set to FMATS because the execution MAT is the user boot MAT.
(2)
User MAT Programming in User Boot Mode
For programming the user MAT in user boot mode, additional processing made by setting FMATS
are required: switching from user-boot-MAT selection state to user-MAT selection state, and
switching back to user-boot-MAT selection state after programming completes.
Figure 20.14 shows the procedure for programming the user MAT in user boot mode.
Rev. 3.00, 03/04, page 652 of 830
Start programming
procedure program
1
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
Set FMATS to value other than
H'AA to select user MAT
MAT
switchover
Yes
No
Download error processing
Set the FPEFEQ
parameters
Initialization
JSR FTDAR setting + 32
FPFR = 0 ?
Set parameter to ER0 and
ER1 (FMPAR and FMPDR)
Programming
Clear FKEY to 0
User-MAT selection state
Download
Set FKEY to H'A5
Set SCO to 1 and
execute download
DPFR = 0 ?
Initialization
User-boot-MAT selection state
Set FKEY to H'A5
Programming
JSR FTDAR setting + 16
FPFR = 0 ?
No
Yes Clear FKEY and programming
error processing
No
Required data
programming is
completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
Set FMATS to H'AA to
select user boot MAT
Disable interrupts
and bus master operation
other than CPU
1
User-boot-MAT
selection state
MAT
switchover
End programming
procedure program
Note: The MAT must be switched by FMATS
to perform the programming error
processing in the user boot MAT.
Figure 20.14 Procedure for Programming User MAT in User Boot Mode
The difference between the programming procedures in user program mode and user boot mode is
whether the MAT is switched or not as shown in figure 20.14.
In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT
hidden in the background. The user MAT and user boot MAT are switched only while the user
MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being
programmed, the procedure program must be located in an area other than flash memory. After
programming completes, switch the MATs again to return to the first state.
MAT switching is enabled by writing a specific value to FMATS. However note that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
read is undetermined. Perform MAT switching in accordance with the description in section 20.6,
Switching between User MAT and User Boot MAT.
Rev. 3.00, 03/04, page 653 of 830
Except for MAT switching, the programming procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
(3)
User MAT Erasing in User Boot Mode
For erasing the user MAT in user boot mode, additional processing made by setting FMATS are
required: switching from user-boot-MAT selection state to user-MAT selection state, and
switching back to user-boot-MAT selection state after erasing completes.
Figure 20.15 shows the procedure for erasing the user MAT in user boot mode.
Start erasing
procedure program
1
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
Set FMATS to value other
than H'AA to select user MAT
MAT
switchover
Yes
No
Download error processing
Set the FPEFEQ
parameters
Initialization
JSR FTDAR setting + 32
Set FEBS parameter
Erasing
Clear FKEY to 0
User-MAT selection state
Download
Set FKEY to H'A5
Set SCO to 1 and
execute download
DPFR = 0 ?
Initialization
User-boot-MAT selection state
Set FKEY to H'A5
Programming
JSR FTDAR setting + 16
FPFR = 0 ?
Yes
No
No
Clear FKEY and erasing
error processing
Required
block erasing is
completed?
Yes
FPFR = 0 ?
No
Clear FKEY to 0
Yes Initialization error processing
Set FMATS to H'AA to
select user boot MAT
Disable interrupts
and bus master operation
other than CPU
1
User-boot-MAT
selection state
MAT
switchover
End erasing
procedure program
Note: The MAT must be switched by FMATS to perform
the erasing error processing in the user boot MAT.
Figure 20.15 Procedure for Erasing User MAT in User Boot Mode
Rev. 3.00, 03/04, page 654 of 830
The difference between the erasing procedures in user program mode and user boot mode depends
on whether the MAT is switched or not as shown in figure 20.15.
MAT switching is enabled by writing a specific value to FMATS. However note that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is
read is undetermined. Perform MAT switching in accordance with the description in section 20.6,
Switching between User MAT and User Boot MAT.
Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
20.4.4
Procedure Program and Storable Area for Programming Data
In the descriptions in the previous section, the programming/erasing procedure programs and
storable areas for program data are assumed to be in the on-chip RAM. However, the program and
the data can be stored in and executed from other areas, such as part of flash memory which is not
to be programmed or erased, or somewhere in the external address space.
(1)
Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip
RAM specified by FTDAR, therefore, this area is not available for use.
2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So,
make sure that this area is secured.
3. Download by setting the SCO bit to 1 will lead to switching of the MAT. If, therefore, this
operation is used, it should be executed from the on-chip RAM.
4. The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been determined. When in a mode in which the external address
space is not accessible, such as single-chip mode, the required procedure programs, NMI
handling vector and NMI handler should be transferred to the on-chip RAM before
programming/erasing of the flash memory starts.
5. The flash memory is not accessible during programming/erasing operations, therefore, the
operation program is downloaded to the on-chip RAM to be executed. The NMI-handling
vector and programs such as that which activate the operation program, and NMI handler
should thus be stored in on-chip memory other than flash memory or the external address
space.
6. After programming/erasing, the flash memory should be inhibited until FKEY is cleared.
The reset state (RES = 0) must be in place for more than 100 µs when the LSI mode is changed
to reset on completion of a programming/erasing operation.
Rev. 3.00, 03/04, page 655 of 830
Transitions to the reset state, and hardware standby mode are inhibited during
programming/erasing. When the reset signal is accidentally input to the chip, a longer period in
the reset state than usual (100 µs) is needed before the reset signal is released.
7. Switching of the MATs by FMATS should be needed when programming/erasing of the user
boot MAT is operated in user-boot mode. The program which switches the MATs should be
executed from the on-chip RAM. See section 20.6, Switching between User MAT and User
Boot MAT. Please make sure you know which MAT is selected when switching between
them.
8. When the data storable area indicated by programming parameter FMPDR is within the flash
memory area, an error will occur even when the data stored is normal. Therefore, the data
should be transferred to the on-chip RAM to place the address that FMPDR indicates in an
area other than the flash memory.
In consideration of these conditions, there are three factors; operating mode, the bank structure of
the user MAT, and operations.
The areas in which the programming data can be stored for execution are shown in tables.
Table 20.7 Executable MAT
Initiated Mode
Operation
User Program Mode
User Boot Mode*
Programming
Table 20.8 (1)
Table 20.8 (3)
Erasing
Table 20.8 (2)
Table 20.8 (4)
Note:
*
Programming/Erasing is possible to user MATs.
Rev. 3.00, 03/04, page 656 of 830
Table 20.8 (1)
Useable Area for Programming in User Program Mode
Storable /Executable Area
Item
Storage Area for
Program Data
On-chip
RAM
Selected MAT
Embedded
External Space
Program
(Expanded Mode) User MAT Storage Area
User
MAT
×*


Operation for
Selection of On-chip
Program to be
Downloaded
Operation for Writing
H'A5 to FKEY
Execution of Writing
SCO = 1 to FCCS
(Download)
×
×
×
×
Operation for FKEY
Clear
Determination of
Download Result
Operation for
Download Error
Operation for Settings
of Initial Parameter
Execution of
Initialization
Determination of
Initialization Result
Operation for
Initialization Error
NMI Handling Routine
×
Operation for Inhibit of
Interrupt
Operation for Writing
H'5A to FKEY
Operation for Settings
of Program Parameter
×
Rev. 3.00, 03/04, page 657 of 830
Storable /Executable Area
On-chip
RAM
Item
Embedded
External Space
Program
(Expanded Mode) User MAT Storage Area
User
MAT
Execution of
Programming
×
Determination of
Program Result
×
Operation for Program
Error
×
Operation for FKEY
Clear
×
Note:
*
Selected MAT
×
Transferring the data to the on-chip RAM enables this area to be used.
Rev. 3.00, 03/04, page 658 of 830
Table 20.8 (2)
Useable Area for Erasure in User Program Mode
Storable /Executable Area
Item
On-chip
RAM
Selected MAT
Embedded
External Space
Program
(Expanded Mode) User MAT Storage Area
User
MAT
Operation for
Selection of On-chip
Program to be
Downloaded
Operation for Writing
H'A5 to FKEY
Execution of Writing
SCO = 1 to FCCS
(Download)
×
×
×
×
Operation for FKEY
Clear
Determination of
Download Result
Operation for
Download Error
Operation for Settings
of Initial Parameter
Execution of
Initialization
Determination of
Initialization Result
Operation for
Initialization Error
NMI Handling Routine
×
Operation for Inhibit of
Interrupt
Operation for Writing
H'5A to FKEY
Operation for Settings
of Erasure Parameter
×
Execution of Erasure
×
Determination of
Erasure Result
×
×
Rev. 3.00, 03/04, page 659 of 830
Storable /Executable Area
Item
On-chip
RAM
Embedded
External Space
Program
(Expanded Mode) User MAT Storage Area
User
MAT
Operation for Erasure
Error
×
Operation for FKEY
Clear
×
Rev. 3.00, 03/04, page 660 of 830
Selected MAT
Table 20.8 (3)
Useable Area for Programming in User Boot Mode
Storable/Executable Area
Item
Storage Area for
Program Data
On-chip
RAM
Selected MAT
User Boot External Space
User
MAT
(Expanded Mode) MAT
×*1

User
Boot
MAT

Embedded
Program
Storage Area

Operation for
Selection of On-chip
Program to be
Downloaded
Operation for Writing
H'A5 to FKEY
Execution of Writing
SCO = 1 to FCCS
(Download)
×
×
×
×
Operation for FKEY
Clear
Determination of
Download Result
Operation for
Download Error
Operation for
Settings of Initial
Parameter
Execution of
Initialization
Determination of
Initialization Result
Operation for
Initialization Error
NMI Handling
Routine
×
Operation for
Interrupt Inhibit
Switching MATs by
FMATS
×
Operation for Writing
H'5A to FKEY
×
×
Rev. 3.00, 03/04, page 661 of 830
Storable/Executable Area
Item
On-chip
RAM
User Boot External Space
User
MAT
(Expanded Mode) MAT
Operation for
Settings of Program
Parameter
×
Execution of
Programming
×
Determination of
Program Result
×
Operation for
Program Error
Selected MAT
User
Boot
MAT
Embedded
Program
Storage Area
×
×*2
Operation for FKEY
Clear
×
Switching MATs by
FMATS
×
×
Notes: 1. Transferring the data to the on-chip RAM enables this area to be used.
2. Switching FMATS by a program in the on-chip RAM enables this area to be used.
Rev. 3.00, 03/04, page 662 of 830
Table 20.8 (4)
Useable Area for Erasure in User Boot Mode
Storable/Executable Area
Item
On-chip
RAM
Selected MAT
User Boot External Space
User
MAT
(Expanded Mode) MAT
User
Boot
MAT
Embedded
Program
Storage Area
Operation for
Selection of On-chip
Program to be
Downloaded
Operation for Writing
H'A5 to FKEY
Execution of Writing
SCO = 1 to FCCS
(Download)
×
×
×
×
Operation for FKEY
Clear
Determination of
Download Result
Operation for
Download Error
Operation for
Settings of Initial
Parameter
Execution of
Initialization
Determination of
Initialization Result
Operation for
Initialization Error
NMI Handling
Routine
×
Operation for
Interrupt Inhibit
Switching MATs by
FMATS
×
Operation for Writing
H'5A to FKEY
×
Operation for
Settings of Erasure
Parameter
×
×
Rev. 3.00, 03/04, page 663 of 830
Storable/Executable Area
On-chip
RAM
Item
User Boot External Space
User
MAT
(Expanded Mode) MAT
Execution of Erasure
×
Determination of
Erasure Result
×
Operation for
Erasure Error
×*
Operation for FKEY
Clear
×
Switching MATs by
FMATS
×
Note:
*
Selected MAT
User
Boot
MAT
Embedded
Program
Storage Area
×
×
Switching FMATS by a program in the on-chip RAM enables this area to be used.
Rev. 3.00, 03/04, page 664 of 830
20.5
Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error
protection.
20.5.1
Hardware Protection
Programming and erasing of flash memory is forcibly disabled or suspended by hardware
protection. In this state, the downloading of an on-chip program and initialization are possible.
However, an activated program for programming or erasure cannot program or erase locations in a
user MAT, and the error in programming/erasing is reported in the parameter FPFR.
Table 20.9 Hardware Protection
Function to be Protected
Item
Description
Download
FWE pin protection
•
When a low level signal is input to the 
FWE pin, the FWE bit in FCCS is
cleared and the program/eraseprotected state is entered.
Reset/standby
protection
•
The program/erase interface registers
are initialized in the reset state
(including a reset by the WDT) and
standby mode and the program/eraseprotected state is entered.
•
The reset state will not be entered by
a reset using the RES pin unless the
RES pin is held low until oscillation
has stabilized after power is initially
supplied. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width that is specified in
the section on AC characteristics
section. If a reset is input during
programming or erasure, data values
in the flash memory are not
guaranteed. In this case, execute
erasure and then execute program
again.
Program/Erase
Rev. 3.00, 03/04, page 665 of 830
20.5.2
Software Protection
Software protection is set up in any of two ways: by disabling the downloading of on-chip
programs for programming and erasing and by means of a key code.
Table 20.10 Software Protection
Function to be Protected
Item
Description
Protection by the
SCO bit
•
The program/erase-protected state is
entered by clearing the SCO bit in
FCCS which disables the downloading
of the programming/erasing programs.
Protection by the
FKEY register
•
Downloading and
programming/erasing are disabled
unless the required key code is written
in FKEY. Different key codes are used
for downloading and for
programming/erasing.
20.5.3
Download
Program/Erase
Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer entering runaway during programming/erasing of the flash memory or
operations that are not according to the established procedures for programming/erasing. Aborting
programming or erasure in such cases prevents damage to the flash memory due to excessive
programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in the FCCS register is set to 1 and the error-protection state is entered, and this aborts the
programming or erasure.
The FLER bit is set in the following conditions:
1. When an interrupt such as NMI occurs during programming/erasing.
2. When the flash memory is read during programming/erasing (including a vector read or an
instruction fetch).
3. When a SLEEP instruction (including software-standby mode) is executed during
programming/erasing.
4. When a bus master other than the CPU, such as the DTC, gets bus mastership during
programming/erasing.
Rev. 3.00, 03/04, page 666 of 830
Error protection is cancelled only by a reset or by hardware-standby mode. Note that the reset
should be released after the reset period of 100 µs which is longer than normal. Since high
voltages are applied during programming/erasing of the flash memory, some voltage may remain
after the error-protection state has been entered. For this reason, it is necessary to reduce the risk
of damage to the flash memory by extending the reset period so that the charge is released.
The state-transition diagram in figure 20.16 shows transitions to and from the error-protection
state.
Program mode
Erase mode
Read disabled
Programming/erasing
enabled FLER = 0
RES = 0 or STBY = 0
Er
Error occurrence
Error protection mode
Read enabled
Programming/erasing disabled
FLER = 1
Reset or hardware
standby
(Hardware protection)
Read disabled
Programming/erasing disabled
FLER = 0
or
=0
c
S
=0
u
(S
E
oft rred R
BY
T
wa
S
RES = 0 or
re
sta
STBY = 0
nd
by
)
ror
oc
Software-standby mode
Program/erase interface
register is in its initial state.
Error-protection mode
(Software standby)
Read disabled
Cancel
programming/erasing disabled
software-standby mode
FLER = 1
Program/erase interface
register is in its initial state.
Figure 20.16 Transitions to Error-Protection State
Rev. 3.00, 03/04, page 667 of 830
20.6
Switching between User MAT and User Boot MAT
It is possible to alternate between the user MAT and user boot MAT. However, the following
procedure is required because these MATs are allocated to address 0.
(Switching to the user boot MAT disables programming and erasing. Programming of the user
boot MAT should take place in boot mode or programmer mode.)
1. MAT switching by FMATS should always be executed from the on-chip RAM.
2. To ensure that the MAT that has been switched to is accessible, execute four NOP instructions
in the on-chip RAM immediately after writing to FMATS of the on-chip RAM (this prevents
access to the flash memory during MAT switching).
3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is
being accessed. Always mask the maskable interrupts before switching between MATs. In
addition, configure the system so that NMI interrupts do not occur during MAT switching.
4. After the MATs have been switched, take care because the interrupt vector table will also have
been switched. If interrupt processing is to be the same before and after MAT switching,
transfer the interrupt-processing routines to the on-chip RAM and set the WEINTE bit in
FCCS to place the interrupt-vector table in the on-chip RAM.
5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user
boot MAT, do not access addresses above the top of its 8-kbyte memory space. If access goes
beyond the 8-kbyte space, the values read are undefined.
<User MAT>
<On-chip RAM>
<User boot MAT>
Procedure for
switching to the
user boot MAT
Procedure for
switching to
the user MAT
Procedure for switching to the user boot MAT
(1) Mask interrupts
(2) Write H'AA to FMATS.
(3) Execute four NOP instructions before
accessing the user boot MAT.
Procedure for switching to the user MAT
(1) Mask interrupts
(2) Write a value other than H'AA to FMATS.
(3) Execute four NOP instructions before accessing
the user MAT.
Figure 20.17 Switching between the User MAT and User Boot MAT
Rev. 3.00, 03/04, page 668 of 830
20.7
Programmer Mode
Along with its on-board programming mode, this LSI also has a programmer mode as a further
mode for the programming and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can freely be used to write programs to the on-chip ROM.
Program/erase is possible on the user MAT and user boot MAT*1. The PROM programmer must
support microcomputers with 256 or 512-kbyte flash memory as a device type*2. Figure 20.18
shows a memory map in programmer mode.
A status-polling system is adopted for operation in automatic program, automatic erase, and
status-read modes. In the status-read mode, details of the system’s internal signals are output after
execution of automatic programming or automatic erasure. In programmer mode, provide a 12MHz input-clock signal.
Notes: 1. For the PROM programmer and the version of its program, see the instruction manuals
for socket adapter.
2. In this LSI, set the programming voltage of the PROM programmer to 3.3 V.
MCU mode
H8S/2168*1 Programmer mode
H'000000
H'00000
MCU mode
On-chip
ROM area
H'03FFFF
H8S/2167*2 Programmer mode
H'000000
H'00000
MCU mode
On-chip
ROM area
H'00000
On-chip
ROM area
H'3FFFF
H'05FFFF
H8S/2166*3 Programmer mode
H'000000
H'5FFFF
H'FF output*3
H'07FFFF
H'7FFFF
H'07FFFF
H'7FFFF
Notes: 1. Use the PROM programmer which supports microcomputers with 256-kbyte flash memory as a device type.
2. Use the PROM programmer which supports microcomputers with 512-kbyte flash memory as a device type.
3. When programming, fill with H'FF.
Figure 20.18 Memory Map in Programmer Mode
Rev. 3.00, 03/04, page 669 of 830
20.8
Serial Communication Interface Specification for Boot Mode
Initiating boot mode enables the boot program to communicate with the host by using the internal
SCI. The serial communication interface specification is shown below.
(1)
Status
The boot program has three states.
1. Bit-Rate-Adjustment State
In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot
mode enables starting of the boot program and entry to the bit-rate-adjustment state. The
program receives the command from the host to adjust the bit rate. After adjusting the bit rate,
the program enters the inquiry/selection state.
2. Inquiry/Selection State
In this state, the boot program responds to inquiry commands from the host. The device name,
clock mode, and bit rate are selected. After selection of these settings, the program is made to
enter the programming/erasing state by the command for a transition to the
programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs and user boot MATs before the transition.
3. Programming/erasing state
Programming and erasure by the boot program take place in this state. The boot program is
made to transfer the programming/erasing programs to the RAM by commands from the host.
Sum checks and blank checks are executed by sending these commands from the host.
These boot program states are shown in figure 20.19.
Rev. 3.00, 03/04, page 670 of 830
Reset
Bit-rate-adjustment
state
Inquiry/response
wait
Response
Inquiry
Operations for
inquiry and selection
Transition to
programming/erasing
Operations for
response
Operations for erasing
user MATs and user
boot MATs
Programming/erasing
wait
Checking
Erasing
Programming
Operations for
programming
Operations for
erasing
Operations for
checking
Figure 20.19 Boot Program States
Rev. 3.00, 03/04, page 671 of 830
(2)
Bit-Rate-Adjustment State
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 20.20.
Host
Boot Program
H'00 (30 times maximum)
Measuring the
1-bit length
H'00 (Completion of adjustment)
H'55
H'E6 (Boot response)
(H'FF (error))
Figure 20.20 Bit-Rate-Adjustment Sequence
(3)
Communications Protocol
After adjustment of the bit rate, the protocol for communications between the host and the boot
program is as shown below.
1. 1-byte commands and 1-byte responses
These commands and responses are comprised of a single byte. These are consists of the
inquiries and the ACK for successful completion.
2. n-byte commands or n-byte responses
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The amount of programming data is not included under this heading because it is determined
in another command.
3. Error response
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
4. Programming of 128 bytes
The size is not specified in commands. The size of n is indicated in response to the
programming unit inquiry.
5. Memory read response
Rev. 3.00, 03/04, page 672 of 830
This response consists of 4 bytes of data.
1-byte command
or 1-byte response
Command or response
n-byte Command or
n-byte response
Data
Size
Checksum
Command or response
Error response
Error code
Error response
128-byte programming
Address
Data (n bytes)
Command
Memory read
response
Size
Checksum
Data
Response
Checksum
Figure 20.21 Communication Protocol Format
• Command (1 byte): Commands including inquiries, selection, programming, erasing, and
checking
• Response (1 byte): Response to an inquiry
• Size (1 byte): The amount of data for transmission excluding the command, amount of data,
and checksum
• Checksum (1 byte): The checksum is calculated so that the total of all values from the
command byte to the SUM byte becomes H′00.
• Data (n bytes): Detailed data of a command or response
• Error response (1 byte): Error response to a command
• Error code (1 byte): Type of the error
• Address (4 bytes): Address for programming
• Data (n bytes): Data to be programmed (the size is indicated in the response to the
programming unit inquiry.)
• Size (4 bytes): 4-byte response to a memory read
Rev. 3.00, 03/04, page 673 of 830
(4)
Inquiry and Selection States
The boot program returns information from the flash memory in response to the host’s inquiry
commands and sets the device code, clock mode, and bit rate in response to the host’s selection
command.
Inquiry and selection commands are listed below.
Table 20.11 Inquiry and Selection Commands
Command
Command Name
Description
H'20
Supported Device Inquiry
Inquiry regarding device codes
H'10
Device Selection
Selection of device code
H'21
Clock Mode Inquiry
Inquiry regarding numbers of clock modes and
values of each mode
H'11
Clock Mode Selection
Indication of the selected clock mode
H'22
Multiplication Ratio Inquiry
Inquiry regarding the number of frequencymultiplied clock types, the number of
multiplication ratios, and the values of each
multiple
H'23
Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum
values of the main clock and peripheral clocks
H'24
User Boot MAT Information Inquiry Inquiry regarding the number of user boot
MATs and the start and last addresses of
each MAT
H'25
User MAT Information Inquiry
Inquiry regarding the a number of user MATs
and the start and last addresses of each MAT
H'26
Block for Erasing Information
Inquiry
Inquiry regarding the number of blocks and
the start and last addresses of each block
H'27
Programming Unit Inquiry
Inquiry regarding the unit of programming data
H'3F
New Bit Rate Selection
Selection of new bit rate
H'40
Transition to Programming/Erasing Erasing of user MAT and user boot MAT, and
State
entry to programming/erasing state
H'4F
Boot Program Status Inquiry
Inquiry into the operated status of the boot
program
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new
bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly
be needed. When two or more selection commands are sent at once, the last command will be
valid.
All of these commands, except for the boot program status inquiry command (H'4F), will be valid
until the boot program receives the programming/erasing transition (H'40). The host can choose
Rev. 3.00, 03/04, page 674 of 830
the needed commands out of the commands and inquiries listed above. The boot program status
inquiry command (H'4F) is valid after the boot program has received the programming/erasing
transition command (H'40).
(a) Supported Device Inquiry
The boot program will return the device codes of supported devices and the product code in
response to the supported device inquiry.
Command
H'20
• Command, H'20, (1 byte): Inquiry regarding supported devices
Response
H'30
Size
Number of devices
Number of
characters
Device code
Product name
···
SUM
• Response, H'30, (1 byte): Response to the supported device inquiry
• Size (1 byte): Number of bytes to be transmitted, excluding the command, size, and checksum,
that is, the amount of data contributes by the number of devices, characters, device codes and
product names
• Number of devices (1 byte): The number of device types supported by the boot program
• Number of characters (1 byte): The number of characters in the device codes and boot
program’s name
• Device code (4 bytes): ASCII code of the supporting product
• Product name (n bytes): Type name of the boot program in ASCII-coded characters
• SUM (1 byte): Checksum
The checksum is calculated so that the total number of all values from the command byte to
the SUM byte becomes H'00.
(b) Device Selection
The boot program will set the supported device to the specified device code. The program will
return the selected device code in response to the inquiry after this setting has been made.
Command
H'10
Size
Device code
SUM
• Command, H'10, (1 byte): Device selection
• Size (1 byte): Amount of device-code data
This is fixed at 2
• Device code (4 bytes): Device code (ASCII code) returned in response to the supported device
inquiry
• SUM (1 byte): Checksum
Rev. 3.00, 03/04, page 675 of 830
Response
H'06
• Response, H'06, (1 byte): Response to the device selection command
ACK will be returned when the device code matches.
Error response
H'90
ERROR
• Error response, H'90, (1 byte): Error response to the device selection command
ERROR
: (1 byte): Error code
H'11: Sum check error
H'21: Device code error, that is, the device code does not match
(c) Clock Mode Inquiry
The boot program will return the supported clock modes in response to the clock mode inquiry.
Command
H'21
• Command, H'21, (1 byte): Inquiry regarding clock mode
Response
H'31
Size
Number of modes
Mode
···
SUM
• Response, H'31, (1 byte): Response to the clock-mode inquiry
• Size (1 byte): Amount of data that represents the number of modes and modes
• Number of clock modes (1 byte): The number of supported clock modes
H'00 indicates no clock mode or the device allows to read the clock mode.
• Mode (1 byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.)
• SUM (1 byte): Checksum
(d) Clock Mode Selection
The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made.
The clock-mode selection command should be sent after the device-selection commands.
Command
•
•
•
•
H'11
Size
Mode
SUM
Command, H'11, (1 byte): Selection of clock mode
Size (1 byte): Amount of data that represents the modes
Mode (1 byte): A clock mode returned in reply to the supported clock mode inquiry.
SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to the clock mode selection command
ACK will be returned when the clock mode matches.
Rev. 3.00, 03/04, page 676 of 830
Error Response
H'91
ERROR
• Error response, H'91, (1 byte) : Error response to the clock mode selection command
• ERROR
: (1 byte): Error code
H'11: Checksum error
H'22: Clock mode error, that is, the clock mode does not match.
Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must
be selected using these respective values.
(e) Multiplication Ratio Inquiry
The boot program will return the supported multiplication and division ratios.
Command
H'22
• Command, H'22, (1 byte): Inquiry regarding multiplication ratio
Response
H'32
Size
Number
of types
Number of
multiplication ratios
Multiplication ratio
···
···
SUM
• Response, H'32, (1 byte): Response to the multiplication ratio inquiry
• Size (1 byte): The amount of data that represents the number of clock sources and
multiplication ratios and the multiplication ratios
• Number of types (1 byte): The number of supported multiplied clock types
(e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the
number of types will be H'02.)
• Number of multiplication ratios (1 byte): The number of multiplication ratios for each type
(e.g. the number of multiplication ratios to which the main clock can be set and the peripheral
clock can be set.)
• Multiplication ratio (1 byte)
Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency
multiplier is four, the value of multiplication ratio will be H'04.)
Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is
divided by two, the value of division ratio will be H'FE. H'FE = D'-2)
The number of multiplication ratios returned is the same as the number of multiplication ratios
and as many groups of data are returned as there are types.
• SUM (1 byte): Checksum
Rev. 3.00, 03/04, page 677 of 830
(f) Operating Clock Frequency Inquiry
The boot program will return the number of operating clock frequencies, and the maximum and
minimum values.
Command
H'23
• Command, H'23, (1 byte): Inquiry regarding operating clock frequencies
Response
H'33
Size
Number of operating clock
frequencies
Minimum value of operating Maximum value of operating clock
clock frequency
frequency
···
SUM
• Response, H'33, (1 byte): Response to operating clock frequency inquiry
• Size (1 byte): The number of bytes that represents the minimum values, maximum values, and
the number of frequencies.
• Number of operating clock frequencies (1 byte): The number of supported operating clock
frequency types
(e.g. when there are two operating clock frequency types, which are the main and peripheral
clocks, the number of types will be H'02.)
• Minimum value of operating clock frequency (2 bytes): The minimum value of the multiplied
or divided clock frequency.
The minimum and maximum values represent the values in MHz, valid to the hundredths place
of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is
H'07D0.)
• Maximum value (2 bytes): Maximum value among the multiplied or divided clock frequencies.
There are as many pairs of minimum and maximum values as there are operating clock
frequencies.
• SUM (1 byte): Checksum
Rev. 3.00, 03/04, page 678 of 830
(g) User Boot MAT Information Inquiry
The boot program will return the number of user boot MATs and their addresses.
Command
H'24
• Command, H'24, (1 byte): Inquiry regarding user boot MAT information
Response
H'34
Size
Number of areas
Area-start address
Area-last address
···
SUM
• Response, H'34, (1 byte): Response to user boot MAT information inquiry
• Size (1 byte): The number of bytes that represents the number of areas, area-start addresses,
and area-last address
• Number of Areas (1 byte): The number of consecutive user boot MAT areas
When user boot MAT areas are consecutive, the number of areas returned is H'01.
• Area-start address (4 byte): Start address of the area
• Area-last address (4 byte): Last address of the area
There are as many groups of data representing the start and last addresses as there are areas.
• SUM (1 byte): Checksum
(h) User MAT Information Inquiry
The boot program will return the number of user MATs and their addresses.
Command
H'25
• Command, H'25, (1 byte): Inquiry regarding user MAT information
Response
H'35
Size
Number of areas
Start address area
Last address area
···
SUM
• Response, H'35, (1 byte): Response to the user MAT information inquiry
• Size (1 byte): The number of bytes that represents the number of areas, area-start address and
area-last address
• Number of areas (1 byte): The number of consecutive user MAT areas
When the user MAT areas are consecutive, the number of areas is H'01.
• Area-start address (4 bytes): Start address of the area
• Area-last address (4 bytes): Last address of the area
There are as many groups of data representing the start and last addresses as there are areas.
• SUM (1 byte): Checksum
Rev. 3.00, 03/04, page 679 of 830
(i) Erased Block Information Inquiry
The boot program will return the number of erased blocks and their addresses.
Command
H'26
• Command, H'26, (1 byte): Inquiry regarding erased block information
Response
H'36
Size
Number of blocks
Block start address
Block last address
···
SUM
• Response, H'36, (1 byte): Response to the number of erased blocks and addresses
• Size (three bytes): The number of bytes that represents the number of blocks, block-start
addresses, and block-last addresses.
• Number of blocks (1 byte): The number of erased blocks
• Block start address (4 bytes): Start address of a block
• Block last Address (4 bytes): Last address of a block
There are as many groups of data representing the start and last addresses as there are areas.
• SUM (1 byte): Checksum
(j) Programming Unit Inquiry
The boot program will return the programming unit used to program data.
Command
H'27
• Command, H'27, (1 byte): Inquiry regarding programming unit
Response
H'37
Size
Programming unit
SUM
• Response, H'37, (1 byte): Response to programming unit inquiry
• Size (1 byte): The number of bytes that indicate the programming unit, which is fixed to 2
• Programming unit (2 bytes): A unit for programming
This is the unit for reception of programming.
• SUM (1 byte): Checksum
Rev. 3.00, 03/04, page 680 of 830
(k) New Bit-Rate Selection
The boot program will set a new bit rate and return the new bit rate.
This selection should be sent after sending the clock mode selection command.
Command
H'3F
Size
Bit rate
Input frequency
Number of
multiplication ratios
Multiplication
ratio 1
Multiplication
ratio 2
SUM
• Command, H'3F, (1 byte): Selection of new bit rate
• Size (1 byte): The number of bytes that represents the bit rate, input frequency, number of
multiplication ratios, and multiplication ratio
• Bit rate (2 bytes): New bit rate
One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is
H′00C0.)
• Input frequency (2 bytes): Frequency of the clock input to the boot program
This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g.
when the value is 20.00 MHz, it will be 2000, which is H'07D0.)
• Number of multiplication ratios (1 byte): The number of multiplication ratios to which the
device can be set.
• Multiplication ratio 1 (1 byte) : The value of multiplication or division ratios for the main
operating frequency
Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock
frequency is multiplied by four, the multiplication ratio will be H'04.)
Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock
frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2)
• Multiplication ratio 2 (1 byte): The value of multiplication or division ratios for the peripheral
frequency
Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock
frequency is multiplied by four, the multiplication ratio will be H'04.)
(Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is
divided by two, the value of division ratio will be H'FE. H'FE = D'-2)
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to selection of a new bit rate
When it is possible to set the bit rate, the response will be ACK.
Error Response
H'BF
ERROR
• Error response, H'BF, (1 byte): Error response to selection of new bit rate
Rev. 3.00, 03/04, page 681 of 830
• ERROR: (1 byte): Error code
H'11:
Sum checking error
H'24:
Bit-rate selection error
The rate is not available.
H'25:
Error in input frequency
This input frequency is not within the specified range.
H'26:
Multiplication-ratio error
The ratio does not match an available ratio.
H'27:
Operating frequency error
The frequency is not within the specified range.
(5)
Received Data Check
The methods for checking of received data are listed below.
1. Input frequency
The received value of the input frequency is checked to ensure that it is within the range of
minimum to maximum frequencies which matches the clock modes of the specified device. When
the value is out of this range, an input-frequency error is generated.
2. Multiplication ratio
The received value of the multiplication ratio or division ratio is checked to ensure that it matches
the clock modes of the specified device. When the value is out of this range, an multiplicationratio error is generated.
3. Operating frequency
Operating frequency is calculated from the received value of the input frequency and the
multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at
the operating frequency. The expression is given below.
Operating frequency = Input frequency × Multiplication ratio, or
Operating frequency = Input frequency ÷ Division ratio
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
4. Bit rate
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR),
and the value (N) in the bit rate register (BRR), which are found from the peripheral operating
clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than
Rev. 3.00, 03/04, page 682 of 830
4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the
following expression:
Error (%) = {[
φ × 106
(N + 1) × B × 64 × 2(2×n − 1)
] − 1} × 100
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation
H'06
• Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response
H'06
• Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 20.22.
Boot program
Host
Setting a new bit rate
Waiting for one-bit period
at the specified bit rate
H'06 (ACK)
Setting a new bit rate
Setting a new bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Figure 20.22 New Bit-Rate Selection Sequence
Rev. 3.00, 03/04, page 683 of 830
(6)
Transition to Programming/Erasing State
The boot program will transfer the erasing program, and erase the user MATs and user boot MATs
in that order. On completion of this erasure, ACK will be returned and will enter the
programming/erasing state.
The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the
transition to programming/erasing state. These procedures should be carried out before sending of
the programming selection command or program data.
Command
H'40
• Command, H'40, (1 byte): Transition to programming/erasing state
Response
H'06
• Response, H'06, (1 byte): Response to transition to programming/erasing state
The boot program will send ACK when the user MAT and user boot MAT have been erased
by the transferred erasing program.
Error Response
H'C0
H'51
• Error response, H'C0, (1 byte): Error response for user boot MAT blank check
• Error code, H'51, (1 byte): Erasing error
An error occurred and erasure was not completed.
(7)
Command Error
A command error will occur when a command is undefined, the order of commands is incorrect,
or a command is unacceptable. Issuing a clock-mode selection command before a device selection
or an inquiry command after the transition to programming/erasing state command, are examples.
Error Response
H'80
H'xx
• Error response, H'80, (1 byte): Command error
• Command, H'xx, (1 byte): Received command
(8)
Command Order
The order for commands in the inquiry selection state is shown below.
1. A supported device inquiry (H'20) should be made to inquire about the supported devices.
2. The device should be selected from among those described by the returned information and set
with a device-selection (H'10) command.
3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes.
4. The clock mode should be selected from among those described by the returned information
and set.
Rev. 3.00, 03/04, page 684 of 830
5. After selection of the device and clock mode, inquiries for other required information should
be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23),
which are needed for a new bit-rate selection.
6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according
to the returned information on multiplication ratios and operating frequencies.
7. After selection of the device and clock mode, the information of the user boot MAT and user
MAT should be made to inquire about the user boot MATs information inquiry (H'24), user
MATs information inquiry (H'25), erased block information inquiry (H'26), and programming
unit inquiry (H'27).
8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing
state command (H'40). The boot program will then enter the programming/erasing state.
(9)
Programming/Erasing State
A programming selection command makes the boot program select the programming method, a
128-byte programming command makes it program the memory with data, and an erasing
selection command and block erasing command make it erase the block. The
programming/erasing commands are listed below.
Table 20.12 Programming/Erasing Command
Command
Command Name
Description
H'42
User boot MAT programming selection Transfers the user boot MAT programming
program
H'43
User MAT programming selection
Transfers the user MAT programming
program
H'50
128-byte programming
Programs 128 bytes of data
H'48
Erasing selection
Transfers the erasing program
H'58
Block erasing
Erases a block of data
H'52
Memory read
Reads the contents of memory
H'4A
User boot MAT sum check
Checks the checksum of the user boot MAT
H'4B
User MAT sum check
Checks the checksum of the user MAT
H'4C
User boot MAT blank check
Checks whether the contents of the user
boot MAT are blank
H'4D
User MAT blank check
Checks whether the contents of the user
MAT are blank
H'4F
Boot program status inquiry
Inquires into the boot program’s status
Rev. 3.00, 03/04, page 685 of 830
• Programming
Programming is executed by a programming-selection command and a 128-byte programming
command.
Firstly, the host should send the programming-selection command and select the programming
method and programming MATs. There are two programming selection commands, and
selection is according to the area and method for programming.
1. User boot MAT programming selection
2. User MAT programming selection
After issuing the programming selection command, the host should send the 128-byte
programming command. The 128-byte programming command that follows the selection
command represents the data programmed according to the method specified by the selection
command. When more than 128-byte data is programmed, 128-byte commands should
repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the
address will stop the programming. On completion of programming, the boot program will
wait for selection of programming or erasing.
Where the sequence of programming operations that is executed includes programming with
another method or of another MAT, the procedure must be repeated from the programming
selection command.
The sequence for programming-selection and 128-byte programming commands is shown in
figure 20.23.
Host
Boot program
Programming selection (H'42, H'43)
Transfer of the
programming
program
ACK
128-byte programming (address, data)
Programming
Repeat
ACK
128-byte programming (H'FFFFFFFF)
ACK
Figure 20.23 Programming Sequence
Rev. 3.00, 03/04, page 686 of 830
(a) User boot MAT programming selection
The boot program will transfer a programming program. The data is programmed to the user boot
MATs by the transferred programming program.
Command
H'42
• Command, H'42, (1 byte): User boot MAT programming selection
Response
H'06
• Response, H'06, (1 byte): Response to user boot MAT programming selection
When the programming program has been transferred, the boot program will return ACK.
Error Response
H'C2
ERROR
• Error response : H'C2 (1 byte): Error response to user boot MAT programming selection
• ERROR : (1 byte): Error code
H'54: Selection processing error (transfer error occurs and processing is not completed)
• User MAT programming selection
The boot program will transfer a program for programming. The data is programmed to the
user MATs by the transferred program for programming.
Command
H'43
• Command, H'43, (1 byte): User MAT programming selection
Response
H'06
• Response, H'06, (1 byte): Response to user MAT programming selection
When the programming program has been transferred, the boot program will return ACK.
Error Response
H'C3
ERROR
• Error response : H'C3 (1 byte): Error response to user MAT programming selection
• ERROR : (1 byte): Error code
H'54: Selection processing error (transfer error occurs and processing is not completed)
(b) 128-byte programming
The boot program will use the programming program transferred by the programming selection to
program the user boot MATs or user MATs in response to 128-byte programming.
Command
H'50
Address
Data
···
···
SUM
Rev. 3.00, 03/04, page 687 of 830
• Command, H'50, (1 byte): 128-byte programming
• Programming Address (4 bytes): Start address for programming
Multiple of the size specified in response to the programming unit inquiry
(i.e. H'00, H'01, H'00, H'00 : H'010000)
• Programming Data (128 bytes): Data to be programmed
The size is specified in the response to the programming unit inquiry.
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to 128-byte programming
On completion of programming, the boot program will return ACK.
Error Response
H'D0
ERROR
• Error response, H'D0, (1 byte): Error response for 128-byte programming
• ERROR: (1 byte): Error code
H'11: Checksum Error
H'2A: Address Error
H'53: Programming error
A programming error has occurred and programming cannot be continued.
The specified address should match the unit for programming of data. For example, when the
programming is in 128-byte units, the lower 8 bits of the address should be H'00 or H'80.
When there are less than 128 bytes of data to be programmed, the host should fill the rest with
H'FF.
Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the
programming operation. The boot program will interpret this as the end of the programming and
wait for selection of programming or erasing.
Command
H'50
Address
SUM
• Command, H'50, (1 byte): 128-byte programming
• Programming Address (4 bytes): End code is H'FF, H'FF, H'FF, H'FF.
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to 128-byte programming
On completion of programming, the boot program will return ACK.
Error Response
H'D0
ERROR
• Error Response, H'D0, (1 byte): Error response for 128-byte programming
Rev. 3.00, 03/04, page 688 of 830
• ERROR: (1 byte): Error code
H'11: Checksum error
H'2A: Address error
H'53: Programming error
An error has occurred in programming and programming cannot be continued.
(10) Erasure
Erasure is performed with the erasure selection and block erasure command.
Firstly, erasure is selected by the erasure selection command and the boot program then erases the
specified block. The command should be repeatedly executed if two or more blocks are to be
erased. Sending a block-erasure command from the host with the block number H'FF will stop the
erasure operating. On completion of erasing, the boot program will wait for selection of
programming or erasing.
The sequences of issuing the erasure selection command and block-erasure command are shown in
figure 20.24.
Host
Boot program
Preparation for erasure (H'48)
Transfer of erasure
program
ACK
Repeat
Erasure (Erasure block number)
Erasure
ACK
Erasure (H'FF)
ACK
Figure 20.24 Erasure Sequence
Rev. 3.00, 03/04, page 689 of 830
(a) Erasure Selection
The boot program will transfer the erasure program. User MAT data is erased by the transferred
erasure program.
Command
H'48
• Command, H'48, (1 byte): Erasure selection
Response
H'06
• Response, H'06, (1 byte): Response for erasure selection
After the erasure program has been transferred, the boot program will return ACK.
Error Response
H'C8
ERROR
• Error Response, H'C8, (1 byte): Error response to erasure selection
• ERROR: (1 byte): Error code
H'54: Selection processing error (transfer error occurs and processing is not completed)
(b) Block Erasure
The boot program will erase the contents of the specified block.
Command
H'58
Size
Block number
SUM
• Command, H'58, (1 byte): Erasure
• Size (1 byte): The number of bytes that represents the erasure block number
This is fixed to 1.
• Block number (1 byte): Number of the block to be erased
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to Erasure
After erasure has been completed, the boot program will return ACK.
Error Response
H'D8
ERROR
• Error Response, H'D8, (1 byte): Response to Erasure
• ERROR (1 byte): Error code
H'11:
Sum check error
H'29:
Block number error
Block number is incorrect.
H'51:
Erasure error
An error has occurred during erasure.
On receiving block number H'FF, the boot program will stop erasure and wait for a selection
command.
Rev. 3.00, 03/04, page 690 of 830
Command
H'58
Size
Block number
SUM
• Command, H'58, (1 byte): Erasure
• Size, (1 byte): The number of bytes that represents the block number
This is fixed to 1.
• Block number (1 byte): H'FF
Stop code for erasure
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to end of erasure (ACK)
When erasure is to be performed after the block number H'FF has been sent, the procedure
should be executed from the erasure selection command.
(11) Memory read
The boot program will return the data in the specified address.
Command
H'52
Size
Area
Read size
Read address
SUM
• Command: H'52 (1 byte): Memory read
• Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9)
• Area (1 byte)
H'00: User boot MAT
H'01: User MAT
An address error occurs when the area setting is incorrect.
• Read address (4 bytes): Start address to be read from
• Read size (4 bytes): Size of data to be read
• SUM (1 byte): Checksum
Response
H'52
Read size
Data
···
SUM
•
•
•
•
Response: H'52 (1 byte): Response to memory read
Read size (4 bytes): Size of data to be read
Data (n bytes): Data for the read size from the read address
SUM (1 byte): Checksum
Error Response
H'D2
ERROR
• Error response: H'D2 (1 byte): Error response to memory read
Rev. 3.00, 03/04, page 691 of 830
• ERROR: (1 byte): Error code
H'11: Sum check error
H'2A: Address error
The read address is not in the MAT.
H'2B: Size error
The read size exceeds the MAT.
(12) User Boot MAT Sum Check
The boot program will return the byte-by-byte total of the contents of the bytes of the user boot
MAT, as a 4-byte value.
Command
H'4A
• Command, H'4A, (1 byte): Sum check for user-boot MAT
Response
H'5A
Size
Checksum of user boot program
SUM
• Response, H'5A, (1 byte): Response to the sum check of user-boot MAT
• Size (1 byte): The number of bytes that represents the checksum
This is fixed to 4.
• Checksum of user boot program (4 bytes): Checksum of user boot MATs
The total of the data is obtained in byte units.
• SUM (1 byte): Sum check for data being transmitted
(13) User MAT Sum Check
The boot program will return the byte-by-byte total of the contents of the bytes of the user MAT.
Command
H'4B
• Command, H'4B, (1 byte): Sum check for user MAT
Response
H'5B
Size
Checksum of user program
SUM
• Response, H'5B, (1 byte): Response to the sum check of the user MAT
• Size (1 byte): The number of bytes that represents the checksum
This is fixed to 4.
• Checksum of user boot program (4 bytes): Checksum of user MATs
The total of the data is obtained in byte units.
• SUM (1 byte): Sum check for data being transmitted
(14) User Boot MAT Blank Check
The boot program will check whether or not all user boot MATs are blank and return the result.
Rev. 3.00, 03/04, page 692 of 830
Command
H'4C
• Command, H'4C, (1 byte): Blank check for user boot MAT
Response
H'06
• Response, H'06, (1 byte): Response to the blank check of user boot MAT
If all user MATs are blank (H'FF), the boot program will return ACK.
Error Response
H'CC
H'52
• Error Response, H'CC, (1 byte): Response to blank check for user boot MAT
• Error Code, H'52, (1 byte): Erasure has not been completed.
(15) User MAT Blank Check
The boot program will check whether or not all user MATs are blank and return the result.
Command
H'4D
• Command, H'4D, (1 byte): Blank check for user MATs
Response
H'06
• Response, H'06, (1 byte): Response to the blank check for user boot MATs
If the contents of all user MATs are blank (H'FF), the boot program will return ACK.
Error Response
H'CD
H'52
• Error Response, H'CD, (1 byte): Error response to the blank check of user MATs.
• Error code, H'52, (1 byte): Erasure has not been completed.
(16) Boot Program State Inquiry
The boot program will return indications of its present state and error condition. This inquiry can
be made in the inquiry/selection state or the programming/erasing state.
Command
H'4F
• Command, H'4F, (1 byte):
Response
•
•
•
•
H'5F
Size
Inquiry regarding boot program’s state
Status
ERROR
SUM
Response, H'5F, (1 byte): Response to boot program state inquiry
Size (1 byte): The number of bytes. This is fixed to 2.
Status (1 byte): State of the boot program
ERROR (1 byte): Error status
ERROR = 0 indicates normal operation.
ERROR = 1 indicates error has occurred.
• SUM (1 byte): Sum check
Rev. 3.00, 03/04, page 693 of 830
Table 20.13 Status Code
Code
Description
H'11
Device Selection Wait
H'12
Clock Mode Selection Wait
H'13
Bit Rate Selection Wait
H'1F
Programming/Erasing State Transition Wait (Bit rate selection is completed)
H'31
Programming State for Erasure
H'3F
Programming/Erasing Selection Wait (Erasure is completed)
H'4F
Programming Data Receive Wait (Programming is completed)
H'5F
Erasure Block Specification Wait (Erasure is completed)
Table 20.14 Error Code
Code
Description
H'00
No Error
H'11
Sum Check Error
H'12
Program Size Error
H'21
Device Code Mismatch Error
H'22
Clock Mode Mismatch Error
H'24
Bit Rate Selection Error
H'25
Input Frequency Error
H'26
Multiplication Ratio Error
H'27
Operating Frequency Error
H'29
Block Number Error
H'2A
Address Error
H'2B
Data Length Error
H'51
Erasure Error
H'52
Erasure Incomplete Error
H'53
Programming Error
H'54
Selection Processing Error
H'80
Command Error
H'FF
Bit-Rate-Adjustment Confirmation Error
Rev. 3.00, 03/04, page 694 of 830
20.9
Usage Notes
1. The initial state of the product at its shipment is in the erased state. For the product whose
revision of erasing is undefined, we recommend to execute automatic erasure for checking the
initial state (erased state) and compensating.
2. For the PROM programmer suitable for programmer mode in this LSI and its program version,
refer to the instruction manual of the socket adapter.
3. If the socket, socket adapter, or product index does not match the specifications, too much
current flows and the product may be damaged.
4. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a
PROM programmer that supports the 256 or 512-kbyte flash memory on-chip MCU device at
3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. Use
only the specified socket adapter. If other adapters are used, the product may be damaged.
5. Do not remove the chip from the PROM programmer nor input a reset signal during
programming/erasing. As a high voltage is applied to the flash memory during
programming/erasing, doing so may damage or destroy flash memory permanently. If reset is
executed accidentally, reset must be released after the reset input period of 100 µs which is
longer than normal.
6. The flash memory is not accessible until FKEY is cleared after programming/erasing
completes. If this LSI is restarted by a reset immediately after programming/erasing has
finished, secure the reset period (period of RES = 0) of more than 100 µs. Though transition to
the reset state or hardware standby state during programming/erasing is prohibited, if reset is
executed accidentally, reset must be released after the reset input period of 100 µs which is
longer than normal.
7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory
to hardware protection state. This power on/off timing must also be satisfied at a power-off and
power-on caused by a power failure and other factors.
8. Program the area with 128-byte programming-unit blocks in on-board programming or
programmer mode only once. Perform programming in the state where the programming-unit
block is fully erased.
9. When the chip is to be reprogrammed with the programmer after execution of programming or
erasure in on-board programming mode, it is recommend that automatic programming is
performed after execution of automatic erasure.
10. To write data or programs to the flash memory, data or programs must be allocated to
addresses higher than that of the external interrupt vector table (H'000040) and H'FF must be
written to the areas that are reserved for the system in the exception handling vector table.
11. If data other than H'FFFFFFFF is written to the key code area (H'00003C to H'00003F) of
flash memory, only H'00 can be read in programmer mode. (In this case, data is read as H'00.
Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to
write H'FFFFFFFF to the entire key code area. If data other than H'FF is to be written to the
Rev. 3.00, 03/04, page 695 of 830
key code area in programmer mode, a verification error will occur unless a software
countermeasure is taken for the PROM programmer and the version of its program.
12. The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock
frequency is 33 MHz, the download for each program takes approximately 120 µs at the
maximum.
13. While an instruction in on-chip RAM is being executed, the DTC can write to the SCO bit in
FCCS that is used for a download request or FMATS that is used for MAT switching. Make
sure that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and damage RAM or a MAT switchover may occur and the CPU get out of
control. Do not use DTC to program flash related registers.
14. A programming/erasing program for flash memory used in the conventional H8S F-ZTAT
microcomputer which does not support download of the on-chip program by a SCO transfer
request cannot run in this LSI. Be sure to download the on-chip program to execute
programming/erasing of flash memory in this LSI.
15. Unlike the conventional H8S F-ZTAT microcomputer, no countermeasures are available for a
runaway by WDT during programming/erasing. Prepare countermeasures (e.g. use of the
periodic timer interrupts) for WDT with taking the programming/erasing time into
consideration as required.
Rev. 3.00, 03/04, page 696 of 830
Section 21 Boundary Scan (JTAG)
The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard
1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan
Architecture. Although the name of the function is boundary scan and the name of the group who
worked on standardization is the JTAG, the JTAG is commonly used as the name of a boundary
scan architecture and a serial interface to access the devices having the architecture.
This LSI has a boundary scan function (JTAG). Using this function along with other LSIs
facilitates testing a printed-circuit board.
21.1
Features
• Five test pins (ETCK, ETDI, ETDO, ETMS, and ETRST)
• TAP controller
• Six instructions
BYPASS mode
EXTEST mode
SAMPLE/PRELOAD mode
CLAMP mode
HIGHZ mode
IDCODE mode
(These instructions are test modes corresponding to IEEE 1149.1.)
HUDS000A_000120020900
Rev. 3.00, 03/04, page 697 of 830
ETCK
ETMS
TAP
controller
Decoder
ETRST
ETDI
Shift register
SDBSR
SDBPR
SDIR
SDIDR
ETDO
Mux
[Legend]
SDIR:
SDBPR:
SDBSR:
SDIDR:
Instruction register
Bypass register
Boundary scan register
ID code register
Figure 21.1 JTAG Block Diagram
Rev. 3.00, 03/04, page 698 of 830
21.2
Input/Output Pins
Table 21.1 shows the JTAG pin configuration.
Table 21.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Test clock
ETCK
Input
Test clock input
Provides an independent clock supply to the
JTAG. As the clock input to the ETCK pin is
supplied directly to the JTAG, a clock waveform
with a duty cycle close to 50% should be input.
For details, see section 25, Electrical
Characteristics. If there is no input, the ETCK pin
is fixed to 1 by an internal pull-up.
Test mode select
ETMS
Input
Test mode select input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP
controller. If there is no input, the ETMS pin is
fixed to 1 by an internal pull-up.
Test data input
ETDI
Input
Serial data input
Performs serial input of instructions and data for
JTAG registers. ETDI is sampled on the rise of
the ETCK pin. If there is no input, the ETDI pin is
fixed to 1 by an internal pull-up.
Test data output
ETDO
Output
Serial data output
Performs serial output of instructions and data
from JTAG registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the highimpedance state.
Test reset
ETRST
Input
Test reset input signal
Initializes the JTAG asynchronously. If there is
no input, the ETRST pin is fixed to 1 by an
internal pull-up.
Rev. 3.00, 03/04, page 699 of 830
21.3
Register Descriptions
The JTAG has the following registers.
•
•
•
•
Instruction register (SDIR)
Bypass register (SDBPR)
Boundary scan register (SDBSR)
ID code register (SDIDR)
Instructions can be input to the instruction register (SDIR) by serial transfer from the test data
input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass
register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS,
CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 334-bit register to which the
ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code
register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE
mode. All registers cannot be accessed directly by the CPU.
Table 21.2 shows the kinds of serial transfer possible with each JTAG register.
Table 21.2 JTAG Register Serial Transfer
Register
Serial Input
Serial Output
SDIR
Possible
Possible
SDBPR
Possible
Possible
SDBSR
Possible
Possible
SDIDR
Impossible
Possible
Rev. 3.00, 03/04, page 700 of 830
21.3.1
Instruction Register (SDIR)
SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the
ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the
Test-Logic-Reset state, but is not initialized by a reset or in standby mode.
Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the
last 4 bits of the serial data will be stored in SDIR.
• H8S/2168
Bit
Bit Name
Initial Value
R/W
Description
31
30
29
28
TS3
TS2
TS1
TS0
1
1
1
0
R/W
R/W
R/W
R/W
Test Set Bits
0000: EXTEST mode
0001: Setting prohibited
0010: CLAMP mode
0011: HIGHZ mode
0100: SAMPLE/PRELOAD mode
0101: Setting prohibited
:
:
1101: Setting prohibited
1110: IDCODE mode (Initial value)
1111: BYPASS mode
27 to 14 
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
13

1
R
Reserved
This bit is always read as 1 and cannot be modified.
12

0
R
Reserved
This bit is always read as 0 and cannot be modified.
11

1
R
Reserved
This bit is always read as 1 and cannot be modified.
10 to 1

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
0

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 3.00, 03/04, page 701 of 830
• H8S/2167, H8S/2166
Bit
Bit Name
Initial Value
R/W
Description
31
30
29
28
TS3
TS2
TS1
TS0
1
1
1
0
R/W
R/W
R/W
R/W
Test Set Bits
0000: EXTEST mode
0001: Setting prohibited
0010: CLAMP mode
0011: HIGHZ mode
0100: SAMPLE/PRELOAD mode
0101: Setting prohibited
:
:
1101: Setting prohibited
1110: IDCODE mode (Initial value)
1111: BYPASS mode
27 to 14 
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
13

1
R
Reserved
This bit is always read as 1 and cannot be modified.
12

0
R
Reserved
This bit is always read as 0 and cannot be modified.
11, 10

All 1
R
Reserved
These bits are always read as 1 and cannot be
modified.
9

0
R
Reserved
This bit is always read as 0 and cannot be modified.
8

1
R
Reserved
This bit is always read as 1 and cannot be modified.
7 to 1

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
0

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 3.00, 03/04, page 702 of 830
21.3.2
Bypass Register (SDBPR)
SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected
between the ETDI and ETDO pins.
21.3.3
Boundary Scan Register (SDBSR)
SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI.
Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the
IEEE1149.1 standard can be performed.
Table 21.3 shows the relationship between the terminals of this LSI and the boundary scan
register.
Rev. 3.00, 03/04, page 703 of 830
Table 21.3 Correspondence between Pins and Boundary Scan Register
Pin No.
Pin Name
Input/Output
Bit No.
from ETDI
2
P45
Input
Enable
Output
333
332
331
3
P46
Input
Enable
Output
330
329
328
4
P47
Input
Enable
Output
327
326
325
5
P56
Input
Enable
Output
324
323
322
6
P57
Input
Enable
Output
321
320
319
9
MD1
Input
318
10
MD0
Input
317
11
NMI
Input
316
14
MD2
Input
315
15
P51
Input
Enable
Output
314
313
312
16
P50
Input
Enable
Output
311
310
309
17
P97
Input
Enable
Output
308
307
306
18
P96
Input
Enable
Output
305
304
303
Rev. 3.00, 03/04, page 704 of 830
Pin No.
Pin Name
Input/Output
Bit No.
19
P95
Input
Enable
Output
302
301
300
20
P94
Input
Enable
Output
299
298
297
21
P93
Input
Enable
Output
296
295
294
22
P92
Input
Enable
Output
293
292
291
23
P91
Input
Enable
Output
290
289
288
24
P90
Input
Enable
Output
287
286
285
25
PC7
Input
Enable
Output
284
283
282
26
PC6
Input
Enable
Output
281
280
279
27
PC5
Input
Enable
Output
278
277
276
28
PC4
Input
Enable
Output
275
274
273
29
PC3
Input
Enable
Output
272
271
270
30
PC2
Input
Enable
Output
269
268
267
31
PC1
Input
Enable
Output
266
265
264
Rev. 3.00, 03/04, page 705 of 830
Pin No.
Pin Name
Input/Output
Bit No.
32
PC0
Input
Enable
Output
263
262
261
33
PA7
Input
Enable
Output
260
259
258
34
PA6
Input
Enable
Output
257
256
255
35
PA5
Input
Enable
Output
254
253
252
37
PA4
Input
Enable
Output
251
250
249
38
PA3
Input
Enable
Output
248
247
246
39
PA2
Input
Enable
Output
245
244
243
40
PA1
Input
Enable
Output
242
241
240
41
PA0
Input
Enable
Output
239
238
237
43
P87
Input
Enable
Output
236
235
234
44
P86
Input
Enable
Output
233
232
231
45
P85
Input
Enable
Output
230
229
228
46
P84
Input
Enable
Output
227
226
225
Rev. 3.00, 03/04, page 706 of 830
Pin No.
Pin Name
Input/Output
Bit No.
47
P83
Input
Enable
Output
224
223
222
48
P82
Input
Enable
Output
221
220
219
49
P81
Input
Enable
Output
218
217
216
50
P80
Input
Enable
Output
215
214
213
51
PE7
Input
Enable
Output
212
211
210
52
PE6
Input
Enable
Output
209
208
207
53
PE5
Input
Enable
Output
206
205
204
54
PE4
Input
Enable
Output
203
202
201
55
PE3
Input
Enable
Output
200
199
198
56
PE2
Input
Enable
Output
197
196
195
57
PE1
Input
Enable
Output
194
193
192
58
PE0
Input
Enable
Output
191
190
189
59
PD7
Input
Enable
Output
188
187
186
Rev. 3.00, 03/04, page 707 of 830
Pin No.
Pin Name
Input/Output
Bit No.
60
PD6
Input
Enable
Output
185
184
183
61
PD5
Input
Enable
Output
182
181
180
62
PD4
Input
Enable
Output
179
178
177
63
PD3
Input
Enable
Output
176
175
174
64
PD2
Input
Enable
Output
173
172
171
65
PD1
Input
Enable
Output
170
169
168
66
PD0
Input
Enable
Output
167
166
165
68
P70
Input
164
69
P71
Input
163
70
P72
Input
162
71
P73
Input
161
72
P74
Input
160
73
P75
Input
159
74
P76
Input
158
75
P77
Input
157
78
P60
Input
Enable
Output
156
155
154
79
P61
Input
Enable
Output
153
152
151
80
P62
Input
Enable
Output
150
149
148
Rev. 3.00, 03/04, page 708 of 830
Pin No.
Pin Name
Input/Output
Bit No.
81
P63
Input
Enable
Output
147
146
145
82
P64
Input
Enable
Output
144
143
142
83
P65
Input
Enable
Output
141
140
139
84
P66
Input
Enable
Output
138
137
136
85
P67
Input
Enable
Output
135
134
133
92
PF2
Input
Enable
Output
132
131
130
93
PF1
Input
Enable
Output
129
128
127
94
PF0
Input
Enable
Output
126
125
124
96
P27
Input
Enable
Output
123
122
121
97
P26
Input
Enable
Output
120
119
118
98
P25
Input
Enable
Output
117
116
115
99
P24
Input
Enable
Output
114
113
112
100
P23
Input
Enable
Output
111
110
109
Rev. 3.00, 03/04, page 709 of 830
Pin No.
Pin Name
Input/Output
Bit No.
101
P22
Input
Enable
Output
108
107
106
102
P21
Input
Enable
Output
105
104
103
103
P20
Input
Enable
Output
102
101
100
104
P17
Input
Enable
Output
99
98
97
105
P16
Input
Enable
Output
96
95
94
106
P15
Input
Enable
Output
93
92
91
107
P14
Input
Enable
Output
90
89
88
108
P13
Input
Enable
Output
87
86
85
109
P12
Input
Enable
Output
84
83
82
110
P11
Input
Enable
Output
81
80
79
112
P10
Input
Enable
Output
78
77
76
113
PB7
Input
Enable
Output
75
74
73
114
PB6
Input
Enable
Output
72
71
70
Rev. 3.00, 03/04, page 710 of 830
Pin No.
Pin Name
Input/Output
Bit No.
115
PB5
Input
Enable
Output
69
68
67
116
PB4
Input
Enable
Output
66
65
64
117
PB3
Input
Enable
Output
63
62
61
118
PB2
Input
Enable
Output
60
59
58
119
PB1
Input
Enable
Output
57
56
55
120
PB0
Input
Enable
Output
54
53
52
121
P30
Input
Enable
Output
51
50
49
122
P31
Input
Enable
Output
48
47
46
123
P32
Input
Enable
Output
45
44
43
124
P33
Input
Enable
Output
42
41
40
125
P34
Input
Enable
Output
39
38
37
126
P35
Input
Enable
Output
36
35
34
127
P36
Input
Enable
Output
33
32
31
Rev. 3.00, 03/04, page 711 of 830
Pin No.
Pin Name
Input/Output
Bit No.
128
P37
Input
Enable
Output
30
29
28
129
P40
Input
Enable
Output
27
26
25
130
P41
Input
Enable
Output
24
23
22
131
P42
Input
Enable
Output
21
20
19
132
P43
Input
Enable
Output
18
17
16
133
P52
Input
Enable
Output
15
14
13
134
P53
Input
Enable
Output
12
11
10
135
FWE
Input
9
136
P54
Input
Enable
Output
8
7
6
137
P55
Input
Enable
Output
5
4
3
138
P44
Input
Enable
Output
2
1
0
to ETDO
Note: The enable signals are active-high. When an enable signal is driven high, the
corresponding pin is driven with the output value.
Rev. 3.00, 03/04, page 712 of 830
21.3.4
ID Code Register (SDIDR)
SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output H'0026200F (H8S/2168) or
H'0030200F (H8S/2167 or H8S/2166), that are fixed codes, from ETDO. However, no serial data
can be written to SDIDR via ETDI.
• H8S/2168
31 28
27
0000
0000
Version
(4 bits)
12
0010
0110
0010
Part Number
(16 bits)
11
0000
0000
1
0
111
1
Manufacture Identify
(11 bits)
Fixed Code
(1 bit)
• H8S/2167, H8S/2166
31 28
27
0000
0000
Version
(4 bits)
12
0011
0000
Part Numbe