ATMEL ATSAM9708 Sound synthesis Datasheet

Features
• Up to 128-voice Top-quality Wavetable Synthesis Chip
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– Two 64-voice RISC DSP Cores
– Two High-speed CISC Control Processors
– Versatile Programmable Digital Audio Routing Between the Two DSPs
Voices Can Be Allocated for Synthesis and/or Effects and/or Audio Processing
Maximum Single-shot PCM Wavesize of 4M Samples (93 Seconds @ 44.1 kHz)
Samples Can Be Stored in 16-bit Floating Point Format (20-bit Dynamic), 16-bit Linear,
8-bit Linear
Standard Audio Processing Firmware Includes Equalizer, Surround, MPEG Audio
Decoder (Level 2)
Sophisticated Built-in Cache Memories
– Allows Use of Standard 90 ns 16-bit ROMs/RAMs
– Guarantees Crisp Response Even Under Heavy Traffic Conditions
GS® Sound Set(1) under License from Roland® Corporation, Other Sound Sets
Available
16-channel Audio-in, 16-channel Audio-out @ 22 Bits Audio/Channel
28-bit Internal Audio Path
Two Serial MIDI-In, Two Serial MIDI-Out
Firmware/Wavetable Data Can Reside in ROM, DRAM, SDRAM
Up to 256M Bytes of External Memory with Support of SIMM (DRAM) and DIMM
(SDRAM)
High-speed 16-bit Burst Transfer for Firmware Download or Streaming Audio
Compatible with ATSAM9707, Uses Proven Design and Development Tools
– Sound Editor, Sound Bank Editor
– Algorithm Compiler, Assembler, Source Debugger
– Direct Development from PC Environment, No Special Emulator Required
Top Technology
– Single Low-frequency Crystal and Built-in PLL
– 3.3V Supply, 5V-tolerant I/Os
– Space-saving 144-lead TQFP Package
– Power-down Mode
Typical Applications: Karaokes, High-range Multimedia, Classical Organs, Digital
Pianos, Professional Keyboards, Musical Samplers
Note:
Sound
Synthesis
ATSAM9708
128-voice
Integrated
Sound
Synthesizer
1. The GS Sound Set is subject to special licensing conditions. Not to be used for
musical instruments.
Description
The ATSAM9708 is a 128-voice integrated synthesizer, integrating two PDSP blocks
and a memory management unit (MMU). One PDSP block is a combination of a specialized 64-slot RISC-based digital signal processor (DSP), a general-purpose 16-bit
CISC-based control processor (P16), a cache memory and an “intelligent” peripheral
I/O interface. Both PDSPs are fully independent and share the same external memory
through the MMU.
1772D–DRMSD–01/04
Block Diagrams
16-bit Bus
Figure 1. ATSAM9708 Block Diagram
PDSP 1
MMU
MIDI and Audio
Memory
PDSP 2
Figure 2. PDSP Block Diagram
I/O Functions
16-bit Bus
MIDI
Control/Status
MIDI UART
Timers
Host I/F
P16 Processor
16-bit CISC
Processor Core
Includes
256 x 16 Data RAM
256 x 16 Boot ROM
MMU
Synthesis/DSP
Audio
2
RISC DSP Core
Includes
512 x 38 Alg RAM
128 x 28 MA1 RAM
256 x 32 MA2 RAM
256 x 32 MB RAM
128 x 16 MX RAM
256 x 16 MY RAM
64 x 13 ML RAM
Cache Memory
128 x 16
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Pin Description by Function
Table 1. Power Group
Name
Pin Count
Type
Function
GND
19
PWR
Power Ground. All GND pins should be returned to digital ground.
VC3
8
PWR
Core Power, +3.3V nominal (3V to 4.5V). All VC3 pins should be returned to
+3.3V.
VCC1
5
PWR
Pad (except Memory Pad) Power, +3.0V to +5.5V. All VCC pins should be
returned to +5V (or 3.3V in case of single 3.3V supply).
VCC2
5
PWR
Memory Pad Power, +3.0V to +5.5V. All VCC pins should be returned to +5V (for
RAM or DRAM) or 3.3V (for SDRAM or 3.3V ROM).
Pin Count
Type
Function
16
I/O
16-bit data bus to host processor.
Information on these pins is:
- 2 x parallel MIDI (MPU-401 type applications)
- 2 x high-speed burst data transfers to/from external memory
PC_A[2:0]
3
IN
Selects one of 8 internal registers:
0, 1: MPU-401 register processor #1
2, 3: Burst data (16-bit) processor #1
4 - 5: MPU-401 register processor #2
6 - 7: Burst data (16-bit) processor #2
PC_CS(4)
1
IN
Chip select from host, active low.
PC_WR
1
IN
Write from host, active low.
PC_RD
1
IN
Read from host, active low.
PC_READY
1
TSout
Open drain output buffer. Driven low during 16-bit burst mode transfers to
synchronize host to the ATSAM9708 memory.
PC_IO16
1
TSout
Open drain output buffer; driven low during 16-bit burst mode transfers.
Indicates to host that a 16-bit I/O is in progress.
PC_IRQ
1
TSout
Tri-state output pin, active high. Can be connected directly to host PC_IRQ line.
Table 2. ISA Bus Group(1)
Name
PC_D[15:0]
Notes:
(2, 3)
1. ISA bus group pins are powered by VCC1 power rail.
2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities.
3. To interface with PC ISA bus, VCC1 should be connected to 5V power and PC_D bus should be buffered. Direction is given by
PC_RD signal.
4. Pin Names in this document exhibiting an overbar (PC_CS for example) indicates that the signal is active low.
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1772D–DRMSD–01/04
Table 3. MIDI and Audio Group(1)
Name
Pin Count
Type
MIDI1_IN
1
IN
Main MIDI input. Routed to PDSP#1, can also be routed to PDSP#2.
MIDI2_IN
1
I/O
Auxiliary MIDI input. Routed to PDSP#2(2)
MIDI1_OUT
1
OUT
Main MIDI output. Outputs from PDSP#1.
MIDI2_OUT
1
OUT
Auxiliary MIDI output. Outputs from PDSP#2(2)
OVCK_OUT
1
OUT
Buffered X2 output. Typically used to drive external sigma/delta DAC/ADC at
fS x 256.
BCK_OUT
1
OUT
Audio data bit clock. Provides timing to SD_OUT.
WS_OUT
1
OUT
Audio data word select. WS_OUT timing can be selected to be I2S- or
Japanese-compatible.
SD_OUT[7:0]
8
OUT
8 stereo serial audio data output (16 audio channels). Each output holds 64 bits
(2 x 32) of serial data per frame. Audio data has 22-bit precision(2).
SD_IN[7:0]
8
I/O
Notes:
Function
8 stereo serial audio data input (16 audio channels). Each input holds 64 bits
(2 x 32) of serial data per frame. Audio data in is received with 20-bit
precision(2).
1. MIDI and Audio group pins are powered by VCC1 power rail.
2. These pins have alternate functions as GPIO pins (general-purpose input/output pins). See “General-purpose Input/Output
Routing” on page 24 for more details.
Table 4. Memory Group(1)
Name
4
Pin Count
Type
Function
CK_OUT
1
OUT
Master clock for SDRAM operation. Frequency is 4 times the X1 frequency
(typ 45.1584 MHz).
WA[26:0]
27
OUT
External memory address (ROM/SRAM/DRAM/SDRAM), up to 128M words
(256M bytes).
DRAM/SDRAM addresses are time-multiplexed on these pins as follows:
WA0 - WA8: DRA0 - DRA8
WA18: DRA9
WA20: DRA10
WA22: DRA11
RBS
1
OUT
SRAM byte select. Should be connected to the lower RAM address when 8-bit
wide SRAM is used. The type of RAM (16-bit/8-bit) can be selected by
program.
WD[15:0]
16
I/O
WCS0
1
OUT
PCM ROM chip select, active low
WCS1
1
OUT
SRAM chip select, active low
WWE
1
OUT
SRAM/DRAM/SDRAM write enable, active low. Timing compatible with SIMM
DRAM early write feature.
WOE
1
OUT
PCM ROM/SRAM output enable, active low
PCM ROM/SRAM/DRAM/SDRAM data
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Table 4. Memory Group(1) (Continued)
Name
Pin Count
Type
RAS
1
I/O
DRAM/SDRAM row address strobe. At the end of reset RAS is tested to
determine memory type configuration (pulled high to select SDRAM type). RAS
should be pulled to VCC or GND through an external 10K resistor.
CAS
1
I/O
DRAM/SDRAM column address strobe. At the end of reset CAS is tested to
determine memory type configuration (pulled high to select DRAM type). CAS
should be pulled to VCC or GND through an external 10K resistor.
REFRESH
1
I/O
Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be
used with multiple SIMM/DIMM modules to force refresh simultaneously on all
modules. At the end of reset REFRESH is tested to select bootstrap state
(pulled high to start built-in CPU bootstrap in case of ROMless applications).
Note:
Function
1. Memory group pins are powered by VCC2 power rail.
Table 5. Miscellaneous Group
Name
Pin Count
Type
Function
LFT
1
ANA
PLL low pass filter. Should be connected to an external RC network.
TEST
1
IN
Test pin. Should be returned to GND.
LDTEST
1
IN
Test pin. Should be returned to GND.
PDWN
1
IN
Power down, active low
RESET
1
IN
Master reset input, active low. Schmidt trigger input.
X1, X2(1)
2
–
Crystal connection. Crystal frequency should be fS x 256 (typ 11.2896 MHz).
Crystal frequency is internally multiplied by 4 to provide the IC master clock. X1
can also be used as external clock input (3.3V input).
Note:
1. X2 cannot be used to drive external circuitry.
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1772D–DRMSD–01/04
Pinout by Pin Number
Table 6. Pinout by Pin Number
Pin Number
Name
Pin Number
Name
Pin Number
Name
Pin Number
Name
1
PC_D[10]
37
SD_IN[2]
73
WD[9]
109
VCC2
2
PC_D[9]
38
SD_IN[3]
74
WD[8]
110
GND
3
PC_D[8]
39
SD_OUT[0]
75
WD[7]
111
WA[9]
4
PC_IO16
40
SD_OUT[1]
76
WD[6]
112
VC3
5
VCC1
41
VC3
77
WD[5]
113
GND
6
GND
42
GND
78
WD[4]
114
WA[10]
7
PC_READY
43
SD_OUT[2]
79
WD[3]
115
WA[11]
8
VC3
44
SD_OUT[3]
80
VC3
116
WA[12]
9
GND
45
WS_OUT
81
VCC2
117
WA[13]
10
PC_RD
46
BCK_OUT
82
GND
118
WA[14]
11
PC_WR
47
OVCK_OUT
83
GND
119
WA[15]
12
PC_A[0]
48
SD_IN[4]
84
WD[2]
120
WA[16]
13
PC_A[1]
49
SD_IN[5]
85
WD[1]
121
WA[17]
14
PC_IRQ
50
SD_IN[6]
86
WD[0]
122
WA[18]
15
PC_A[2]
51
GND
87
WWE
123
WA[19]
16
PC_CS
52
VCC1
88
WOE
124
VCC2
17
VC3
53
SD_IN[7]
89
WCS0
125
GND
18
GND
54
SD_OUT[4]
90
WCS1
126
WA[20]
19
PC_D[0]
55
SD_OUT[5]
91
CK_OUT
127
WA[21]
20
VCC1
56
SD_OUT[6]
92
RBS
128
WA[22]
21
GND
57
SD_OUT[7]
93
WA[0]
129
WA[23]
22
PC_D[1]
58
VC3
94
WA[1]
130
WA[24]
23
PC_D[2]
59
GND
95
WA[2]
131
WA[25]
24
PC_D[3]
60
LFT
96
WA[3]
132
WA[26]
25
PC_D[4]
61
X1
97
VCC2
133
GND
26
PC_D[5]
62
X2
98
GND
134
RESET
27
PC_D[6]
63
VC3
99
VC3
135
TEST
28
PC_D[7]
64
GND
100
GND
136
LDTEST
29
MIDI1_IN
65
WD[15]
101
WA[4]
137
PDWN
30
MIDI2_IN
66
WD[14]
102
WA[5]
138
PC_D[15]
31
MIDI1_OUT
67
WD[13]
103
RAS
139
PC_D[14]
32
MIDI2_OUT
68
WD[12]
104
CAS
140
PC_D[13]
33
SD_IN[0]
69
VCC2
105
REFRESH
141
PC_D[12]
34
SD_IN[1]
70
GND
106
WA[6]
142
VCC1
35
VCC1
71
WD[11]
107
WA[7]
143
GND
36
GND
72
WD[10]
108
WA[8]
144
PC_D[11]
6
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Absolute Maximum
Ratings
Table 7. Absolute Maximum Ratings
Ambient Temperature (Power Applied)...............-40°C to + 85°C
*NOTICE:
Storage Temperature........................................-65°C to + 150°C
Voltage on any pin (except X1)......................-0.5V to VCC + 0.5V
Voltage on X1 pin ..........................................-0.5V to VC3 + 0.5V
VCC Supply Voltage...............................................-0.5V to + 6.5V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
condtions for extended periods may affect device
reliability.
VC3 Supply Voltage................................................-0.5V t0 +4.5V
Maximum IOL per I/O pin....................................................4.4mA
(except PC_IRQ, PC_READY)
Maximum IOL PC_IRQ, PC_READY...............................16.16mA
Note:
All voltages with respect to 0V, GND = 0V
Recommended
Operating Conditions
Table 8. Recommended Operating Conditions
Symbol
Parameter
(1)
Min
Typ
Max
Unit
VCC
Supply voltage
3
3.3/5.0
5.5
V
VC3
Supply voltage
3
3.3
4.5
V
tA
Operating ambient temperature
0
70
°C
Note:
1. When using 3.3V supply, care must be taken that voltage applied on pin does not exceed VCC + 0.5V.
DC Characteristics
Table 9. DC Characteristics (tA = 25°C, VC3 = 3.3V ± 10%)
Symbol
Parameter
VCC
Min
VIL
Low-level input voltage
3.3
5.0
-0.5
-0.5
VIH
High-level input voltage
3.3
5.0
2.3
3.3
VOL
Low-level output voltage
PC_D[15:0], PC_IRQ, PC_READY: IOL = -24
mA
Others except LFT: IOL = -3.2 mA
3.3
5.0
0
Typ
3
Max
Unit
1.0
1.7
V
3.8
5.5
V
0.45
0.45
V
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1772D–DRMSD–01/04
Table 9. DC Characteristics (tA = 25°C, VC3 = 3.3V ± 10%) (Continued)
Symbol
Parameter
VCC
Min
VOL
High-level output voltage
PC_D[15:0], PC_IRQ, PC_READY: IOH = 10
mA
Others except LFT: IOH = 0.8 mA
3.3
5.0
2.8
4.5
ICC
Power supply current
(crystal frequency = 12 MHz)
3.3
5.0
Power down supply current
8
Typ
Max
Unit
V
100
25
140
35
mA
TBD
TBD
µA
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
DSP RISC Signal
Processor
Each of the two DSP engines operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions
known as “algorithms”. Up to 32 different DSP algorithms can be stored on-chip in each
DSP private Alg RAM memory, allowing the device to be programmed for a number of
audio signal generation/processing applications. Each DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with
interpolation, alternate loop and 24 dB resonant filtering for each voice, for a total
polyphony of 128 voices. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms.
Each DSP also includes a 20 x 16 pipelined two’s complement multiplier, a 28-bit pipelined adder and eight 24-bit final accumulators.
A typical application uses around 75% of the capacity of the DSP engines for synthesis,
thus providing a minimum of 96-voice wavetable polyphony. The remaining processing
power is used for typical function like reverberation, chorus, direct sound, surround
effect, equalizer, etc.
Frequently-accessed DSP parameter data are stored in 5 banks of on-chip RAM memory for each DSP. Sample data or delay lines, which are accessed relatively
infrequently, are stored in external ROM, SRAM, DRAM or SDRAM memory. The combination of localized micro-program memory and localized parameter data allows microinstructions to execute in 20 ns (50 MIPS) on each DSP. Separate buses from each of
the on-chip parameter RAM memory banks allow highly parallel data movement to
increase the effectiveness of each micro-instruction. With this architecture, a single
micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load,
store, etc.), providing a total potential throughput of 600 million operations per second
(MOPS).
P16 Control
Processor and I/O
Functions
Each of the two P16 control processors is a general-purpose 16-bit CISC processor
core, that runs from external memory. A boot/macro ROM is included on-chip to accelerate commonly executed routines and to allow the use of RAM only devices for the
external memory. Each P16 also includes 256 words of local RAM data memory.
Each P16 control processor writes to the parameter RAM blocks within its associated
DSP in order to control the synthesis process. In a typical application, the P16 control
processor parses and interprets incoming commands from the MIDI UART or from the
parallel 16-bit interface and then controls the DSP by writing into the parameter RAM
banks of its associated DSP core. Slowly-changing synthesis functions, such as LFOs,
are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables.
Each P16 control processor interfaces with other private peripheral devices, such as the
system control and status registers, the on-chip MIDI UART, the on-chip timers and the
ISA PC 16-bit interface through specialized “intelligent” peripheral I/O logic. This I/O
logic automates many of the system I/O transfers to minimize the amount of overhead
processing required from the P16.
The parallel interface is implemented using three address lines (A2, A1, A0), a chip
select signal, read and write strobes from the host and a 16-bit data bus (PC_D0 PC_D15).
This data bus cannot drive the PC bus directly. External buffers and an external decoder
(PAL) or plug and play IC are required to map the 16-bit I/O addresses and AEN from
the PC into the three address lines and chip select from the ATSAM9708.
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1772D–DRMSD–01/04
The PDSP#1 responds on addresses 0 to 3 (A2A1A0 = 0XX), while PDSP#2 responds
on addresses 4 to 7 (A2A1A0 = 1XX).
Each PDSP parallel interface supports a byte-wide I/O interface and a 16-bit port dedicated to burst transfers.
The byte-wide I/O interface is normally used to implement a MPU-401 UART-mode
compatible interface. It is specified by address A1A0 = 0X, address 00 being the data
register, address 01 being the status/control registers. Besides the standard two status
bits of the MPU-401, two additional bits are provided to expand the MPU-401 protocol.
Address A1A0 = 10 specifies a 16-bit I/O port. It is mainly used for burst audio transfers
to/from the PC using very efficient PC instructions like REP OUTSW or REP INSW
which operate at maximum ISA bus bandwidth. This port may also be used for fast program or sound bank uploads.
DSP Cache RAM
The memory management unit (MMU) allows external ROM and/or RAM memory
resources to be shared between the two DSPs and the two P16 control processors. This
allows a single device (i.e., DRAM) to serve as sample memory storage/delay lines for
the DSPs and as program storage/data memory for the P16 control processors.
The DSP cache RAM allows a dramatic reduction in the traffic with the external
ROM/RAM, allowing use of standard 90 ns ROM parts with sampling frequencies up to
48 kHz. Average access request rate to external memory is only one for every two
frames for each slot, which gives 64 accesses per synthesis frame. The MMU can provide up to 169 memory accesses per frame, which leaves over 100 accesses free per
frame to be used by the P16 processors. This means that under full 128-voice polyphony traffic conditions, each P16 instruction average execution time is around 400 ns at
48 kHz sampling frequency.
128-voice polyphony can be assured only when all samples are played at nominal frequency or down-transposed. Simultaneously playing a large number of up-transposed
samples can adversely affect polyphony. For more details of possible polyphony for a
given application, please refer to the application note “ATSAM9708 Memory Management Unit”.
10
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Timing Diagrams
All timing conditions: VCC = 5V, VC3 = 3.3V, tA = 25°C; signals PC_READY, I/O CS16,
D0 - D15 with 220 ohms pull-up, 30 pF capacitance; signal PC_IRQ with 470 ohms pulldown, 30 pF capacitance; all other outputs except X2 and LFT load capacitance = 30
pF. All timings refer to tCK, which is the internal master clock period. The internal master
clock frequency is 4 times the frequency at pin X1; therefore, tCK = tXTAL/4. The sampling
rate is given by 1/(tCK * 1024). The maximum crystal frequency/clock frequency at X1 is
12.288 MHz (48 kHz sampling rate).
PC Host Interface
Figure 3. Host Interface Read Cycle
PC_A[2:0]
tAVCS
PC_CS
tCSLRDL
tPRD
tRDHCSB
PC_RD
tRDLIORL
tPIOR
PC_ READY
tCSLIOCS
tCSHIOCS
tIORHDV
PC_IO16
tRDLDV
tRDH
PC_D[15:0]
Note:
PC_D[15:8] valid only if PC_A[2:1] = 10.
Figure 4. Host Interface Write Cycle
PC_A[2:0]
tAVCS
PC_CS
tCSLWRL
tPWR
tWRHCSB
PC_WR
tWRLIORL
tPIOR
PC_ READY
tCSLIOCS
tCSHIOCS
tIORHWRH
PC_IO16
tDWS
tDWB
PC_D[15:0]
Note:
PC_D[15:8] valid only if PC_A[2:1] = 10.
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1772D–DRMSD–01/04
.
Table 10. PC Host Interface Timing Parameters
Symbol
Parameter
Min
tAVCS
Address valid to chip select low
0
ns
tCSLDRL
Chip select low to PC_RD low
5
ns
tRDHCSH
PC_RD high to PC_CS high
5
ns
tPRD
PC_RD pulse width
50
ns
(1)
tRDLDV
Data out valid from PC_RD
tDRH
Data out hold from PC_RD
tRDLIORL
PC_READY low from PC_RD (2)
tPIRO
PC_READY pulse width
tIORHDV
Unit
ns
5
10
ns
0
10
ns
128
tck
0
ns
0
20
ns
20
ns
(2)
(3)
Max
20
(2)
PC_READY rising to data out valid
Typ
tCSLIOCS
PC_IO16 low from PC_CS low
tCSHIOCS
PC_IO16 high from PC_CS high (3)
0
tCSLWRL
PC_CS low to PC_WR low
5
ns
tWRHCSH
PC_WR high to PC_CS high
5
ns
tPWR
PC_WR pulse width
50
ns
tWRLIORL
PC_READY low from PC_WR low (2)
0
tIORHWRH
PC_READY high to PC_WR high (2)
5
ns
tDWS
Write data setup time
10
ns
tDWH
Write data hold time
0
ns
Notes:
12
10
ns
1. When data is already loaded into internal ATSAM9708 output register. In this case PC_READY stays high during the read
cycle.
2. PC_READY goes into low only if the data is not ready to be loaded into/read from internal ATSAM9708 register. 128 tck corresponds to a single worst-case situation. At fCK = 12.288 MHz, PC_READY is likely to never go low when using standard
ISA bus timing.
3. PC_IO16 is asserted low by ATSAM9708 if A2A1 = 10 to indicate fast 16-bit ISA bus transfer to the PC.
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
External Memory Timing
External Memory
Overview
The following memories can be connected to the ATSAM9708:
•
ROM or Flash memories, 16 bits wide
•
Static RAMs, 8 bits or 16 bits wide
•
DRAMs, 16 bits wide
•
SDRAMs, 16 bits wide
DRAMs and SDRAMs cannot be connected at the same time. The type of dynamic RAM
connection is determined at power-up by sensing the level of pins RAS and CAS (see
Table 4 on page 4 and “Memory Type Configuration and Boot Configuration” on page
26).
Eight-bit wide static RAM can be connected using the additional Ram Byte Select (RBS)
address signal. RBS allows access to two bytes of SRAM within one regular memory
cycle, thereby providing 16 bits of data. Eight-bit wide SRAM can be connected only
under control of WCS1. The selection 8 bits/16 bits is done by firmware.
ROM and static RAMs use linear addressing (address lines WA0 to WA26). DRAM and
SDRAMs use time-multiplexed addressing with a ROW/COL scheme (address lines
DRA0 to DRA11). Additionally, SDRAMs use the DRA0/DRA11 lines for configuration
and the DRA10 line for auto precharge.
ROM/SRAMs and DRAM/SDRAM address line share the same pins of the ATSAM9708.
The timing is determined by the input signal DRAM. If DRAM is high at the beginning of
a memory cycle, this indicates DRAM/SDRAM access.
If only one type of memory is connected (i.e., SDRAM), then the DRAM signal can be
hardwired. Otherwise, it should be derived from an external decoding of high-order
address lines.
13
1772D–DRMSD–01/04
External Memory Timing
Overview
One memory cycle consists of six internal master clock cycles (6 x tCK). The internal
master clock period is one-fourth of the clock period at X1. The internal master clock is
provided at pin CK_OUT when external SDRAM is connected (RAS sensed high during
RESET).
Basic notes on SDRAM timing:
•
RESET should be held low at least 100 µs (SDRAM timing requirement on idle
cycles)
•
SDRAM mode is fixed to sequential, burst length = 1, CAS latency 2, standard
operation, programmed write burst length.
•
SDRAM cycles for read: NOP - ACTIVE - NOP - READ AUTO PRECHARGE - NOP
- NOP.
•
SDRAM cycles for write: NOP - ACTIVE - NOP - WRITE AUTO PRECHARGE NOP - NOP
•
SDRAM cycles for refresh: NOP - AUTO REFRESH - NOP - NOP - NOP - NOP
Figure 5. ROM and SRAM Basic Timing, DRAM = Low
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
CK_OUT
WA[26:0]
WOE
WWE
RBS
WD[15:0]
ROM/SRAM16 READ
14
SRAM16 WRITE
SRAM8 WRITE
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Figure 6. DRAM Basic Timing, DRAM = High
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
4
5
0
1
CK_OUT
(1)
DRAxx
row
col
RAS
CAS
WWE
REFRESH
WD[15:0]
DRAM READ
Note:
DRAM WRITE
DRAM REFRESH
1. See Table 11 on page 16.
Figure 7. SDRAM Basic Timing, DRAM = High
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
CK_OUT
(1)
DRAxx
row
col
RAS
CAS
WWE
REFRESH
WD[15:0]
SDRAM READ
Note:
SDRAM WRITE
SDRAM AUTO REFRESH
1. See Table 11 on page 16.
15
1772D–DRMSD–01/04
Figure 8. SDRAM Init Sequence, DRAM = High
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
CK_OUT
(1)
DRAxx
row
col
RAS
CAS
WWE
REFRESH
PRECHARGE A10 = 1
Note:
AUTO REFRESH
(TWO CYCLES)
LOAD MODE REG
DRA = 020H
1. See Table 11 below.
Table 11. RAS/CAS Correspondence to Physical Address(1)
Note:
16
Signal
Value at RAS Time
Value at CAS Time
WA0/DRA0
WA0
WA9
WA1/DRA1
WA1
WA10
WA2/DRA2
WA2
WA11
WA3/DRA3
WA3
WA12
WA4/DRA4
WA4
WA13
WA5/DRA5
WA5
WA14
WA6/DRA6
WA6
WA15
WA7/DRA7
WA7
WA16
WA8/DRA8
WA8
WA17
WA18/DRA9
WA18
WA19 (DRAM)
Don’t care (SDRAM)
WA20/DRA10
WA20
WA21 (DRAM)
High (SDRAM)
WA22/DRA11
WA22
WA23 (DRAM)
Don’t care (SDRAM)
Valid for DRAM and SDRAM unless otherwise stated.
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Detailed External DRAM Timing
Figure 9. Read Cycle
tRC
tRAS
tRP
RAS
tRCD
tCAS
tCRP
CAS
tASR
tRAH
tASC
tCAH
D[11:0] (1)
WOE
tCAC
tOFF
tRAC
WD[15:0]
Note:
1. See Table 11 on page 16.
Figure 10. Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
tRCD
tCAS
tCRP
CAS
tASR
tRAH
tASC
tCAH
(1)
DRA[11:0]
tWCS
tWCH
WWE
tDS
tDH
WD[15:0]
Note:
1. See Table 11 on page 16.
17
1772D–DRMSD–01/04
Figure 11. Refresh Cycle (RAS Only)
tRC
tRAS
tRP
RAS
tASR
tRAH
(1)
DRA[11:0]
Note:
counter
1. See Table 11 on page 16.
Table 12. External DRAM Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
tRC
Read/Write/Refresh cycle
tRAC
Access time from RAS
5 x tCK - 5
ns
tCAC
Access time from CAS
3 x tCK - 5
ns
tOFF
CAS high to output Hi-Z
2 x tCK - 5
ns
tRP
RAS precharge time
tRAS
6 x tCK
ns
2 x tCK
ns
RAS pulse width
4 x tCK - 5
ns
tCAS
CAS pulse width
3 x tCK - 5
ns
tRCD
RAS to CAS delay time
tCRP
CAS to RAS precharge time
tASR
2 x tCK
ns
2 x tCK - 5
ns
Row address setup time
tCK - 5
ns
tRAH
Row address hold time
tCK - 5
ns
tASC
Column address setup time
tCK - 5
ns
tCAH
Column address hold time
3 x tCK - 5
ns
tWCS
Write command set-up time
2 x tCK
ns
tWCH
Write command hold time
3 x tCK
ns
tDS
Write data set-up time
2 x tCK
ns
tDH
Write data hold time
3 x tCK
ns
512 x tCK
ns
Refresh counter average period
(12-bit counter)
The following points should be noted:
•
The multiplexed CAS, RAS addressing can support memory DRAM chips up to 16 Mbits x N as long as the number of
row address lines and column address lines are identical. For example, device type 416C1200 is supported because it
is a 1M x 16 organization with 10-bit row and 10-bit column. Device type 416C1000 is not supported because it is a 1M
x 16 organization with 12-bit row and 8-bit column.
•
The signal WOE is normally not used for DRAM connection. It is represented only for reference purposes.
18
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
•
As RAS only counter refresh method is employed, several banks of DRAMs can be connected using simple external
CAS decoding. Linear address lines (WAx) can be used to select between DRAM banks. For example, a 1M x 32 SIMM
module may be connected as two 1M x 16 banks, with CAS0 and CAS1 selections issued from CAS and WA20.
•
During a whole DRAM cycle (from RAS low to CAS rising), WCS0 is asserted low.
•
The equivalence between multiplexed DRAM address lines (DRA0 to DRA11) and the corresponding linear addressing
(WA0 to WA23) is as follows:
DRA11
DRA10
DRA9
DRA8
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
RAS time
WA22
WA20
WA18
WA8
WA7
WA6
WA5
WA4
WA3
WA2
WA1
WA0
CAS time
WA23
WA21
WA19
WA17
WA16
WA15
WA14
WA13
WA12
WA11
WA10
WA9
•
To save DRAM power consumption, CAS and RAS are cycled only when necessary. Therefore, depending on firmware
loaded, total board power consumption may increase with synthesis processing traffic.
Detailed External ROM Timing
Figure 12. ROM Read Cycle
tRC
WCS0
tAOE
WA[26:0]
tPOE
WOE
tDF
tOE
WD[15:0]
tAD
Table 13. External ROM Timing Parameters
Symbol
Parameter
tRC
Read cycle time
tAOE
Min
Typ
Max
Unit
6 x tCK
ns
Address valid to WOE low
tCK
ns
tPOE
Output enable pulse width
5 x tck
ns
tAD
Address access time
6 x tCK - 5
ns
tOE
Output enable access time
5 x tCK - 5
ns
tDF
Chip select or WOE high to input data
High Z
0
tCK - 5
ns
19
1772D–DRMSD–01/04
External RAM Timing
Figure 13. 16-bit SRAM Read Cycle
tRC
WCS1
tAOE
WA[26:0]
tPOE
WOE
WWE
tOE
tDF
WD[15:0]
tAD
Figure 14. 16-bit SRAM Write Cycle
tWC
WCS1
tCSWE
WA[26:0]
tOEWE
WOE
tWP
WWE
tDW
tDH
WD[15:0]
Table 14. External 16-bit SRAM Timing Parameters
Symbol
Parameter
tRC
Read cycle time
tAOE
Min
Typ
Max
Unit
6 x tCK
ns
Address valid to WOE low
tCK
ns
tPOE
Output enable pulse width
5 x tCK
ns
tAD
Address access time
6 x tCK - 5
ns
tOE
Output enable access time
5 x tCK - 5
ns
tDF
Chip select or WOE high to input data High Z
20
0
tCK - 5
ns
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Table 14. External 16-bit SRAM Timing Parameters (Continued)
Symbol
Parameter
Min
Typ
Max
tWC
Write cycle time
tCSWE
Write enable low from CS
tCK - 10
ns
tOEWE
Write enable low from Address or WOE
2tCK - 10
ns
tWP
Write pulse-width
tDW
Data out setup time
3.5 x tCK - 10
ns
tDH
Data out hold time
0.5 x tCK
ns
6 x tCK
Unit
ns
3.5 x tCK
ns
Figure 15. 8-bit SRAM Read Cycle
tRC
WCS1
tCSOE
WA[26:0]
tPOE
WOE
WWE
RBS
tORB
tACE
tOE
WD[7:0]
tACH
LOW
tDF
HIGH
21
1772D–DRMSD–01/04
Figure 16. 8-bit SRAM Write Cycle
tWC
WCS1
tCSWE
WA[26:0]
WOE
tWP
tWP
WWE
tAS
RBS
tDW1 tDH1
WD[7:0]
LOW
tDW2
tDH2
HIGH
Table 15. External 8-bit SRAM Timing Parameters
Symbol
Parameter
tRC
Word (2 x bytes) read cycle time
tCSOE
Chip select low/address valid to WOE low
tPOE
Output enable pulse width
tACE
Chip select/address low byte access time
3 x tCK - 5
ns
tOE
Output enable low byte access time
2 x tCK - 5
ns
tORB
Output enable low to byte select high
tACH
Byte select high byte access time
tDF
Chip select or WOE high to input data
High Z
tWC
Word (2 x bytes) write cycle time
tCSWE
1st WWE low from CS or Address or WOE
tWP
Write (low and high byte) pulse width
tDW1
Data out low byte setup time
1.5 x tCK - 10
ns
tDH1
Data out low byte hold time
10
ns
tAS
RBS high to second write pulse
tCK - 5
ns
tDW2
Data out high byte setup time
2.5 x tCK - 10
ns
tDH2
Data out high byte hold time
10
ns
22
Min
Typ
Max
Unit
6 x tCK
ns
tCK
ns
5 x tCK
ns
2 x tCK
ns
3 x tCK - 5
ns
0
tCK - 5
6 x tCK
tck - 10
ns
ns
ns
1.5 x tCK
ns
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Digital Audio Timing
Figure 17. Digital Audio Timing Diagram
tCW
tCW
tCLBD
WS_OUT
BCK_OUT
tSOD
tSOD
SD_IN[7:0]
SD_OUT[7:0]
Table 16. Digital Audio Timing Parameters
Symbol
Parameter
Min
Typ
Max
tCW
BCK_OUT rising to WS_OUT change
8 x tCK- 10
ns
tSOD
SD_IN[7:0]/SD_OUT[7:0] valid prior/after BCK_OUT rising
8 x tCK - 10
ns
tCLBD
BCK_OUT cycle time
16 x tCK
Unit
ns
Figure 18. Digital Audio Frame Format
WS_OUT
(I2S)
BCK_OUT
SD_IN[7:0]
SD_OUT[7:0]
MSB
LSB
(16 bits)
LSB
(20 bits)
MSB
LSB
(18 bits)
Note:
SD_IN[7:0] is always 20 bits.
23
1772D–DRMSD–01/04
Audio Routing
Each PDSP can process eight digital audio inputs and generate eight digital audio outputs for a total of 16 digital audio-in and 16 digital audio-out.
The eight outputs from DSP#2 can be individually routed on DSP#1 inputs.
Figure 19. Audio Routing
SD_IN[7:4]
SD_IN[3:0]
MIDI Routing
PDSP#1
SD_OUT[3:0]
PDSP#2
SD_OUT[7:4]
Th e de f au l t c o n fi g u r a ti o n as s i g n s MI D I1 _ IN /M I DI 1 _O UT t o P D S P # 1 a n d
MIDI2_IN/MIDI2_OUT to PDSP#2.
Alternatively, MIDI1_IN can be routed as the same MIDI input to both PDSPs. In this
case, the MIDI2_IN is available as a general-purpose input.
Also, if the MIDI2_OUT is not necessary, it can be defined as a general-purpose output.
General-purpose
Input/Output Routing
MIDI2_IN, MIDI2_OUT, SD_IN[7, 6, 5, 3, 2, 1, 0] and SD_OUT[7:1] pins can be individually routed as general-purpose inputs or outputs as identified in Table 17.
Table 17. General-purpose Input/Output Routing
GPIO
Pin
GPIO_OUT[0] DSP#1
MIDI2_OUT
GPIO_OUT[1] DSP#1
SD_OUT[1]
GPIO_OUT[2] DSP#1
SD_OUT[2]
GPIO_OUT[3] DSP#1
SD_OUT[3]
GPIO_OUT[4] DSP#1
SD_IN[0]
GPIO_OUT[5] DSP#1
SD_IN[1]
GPIO_OUT[6] DSP#1
SD_IN[2]
GPIO_OUT[7] DSP#1
SD_IN[3]
GPIO_OUT[0] DSP#2
SD_OUT[4]
GPIO_OUT[1] DSP#2
SD_OUT[5]
GPIO_OUT[2] DSP#2
SD_OUT[6]
GPIO_OUT[3] DSP#2
SD_OUT[7]
GPIO_OUT[4] DSP#2
MIDI2_IN
GPIO_OUT[5] DSP#2
SD_IN[5]
GPIO_OUT[6] DSP#2
SD_IN[6]
24
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Table 17. General-purpose Input/Output Routing (Continued)
GPIO
Pin
GPIO_OUT[7] DSP#2
SD_IN[7]
GPIO_IN[0] DSP#1
SD_IN[0]
GPIO_IN[1] DSP#1
SD_IN[1]
GPIO_IN[2] DSP#1
SD_IN[2]
GPIO_IN[3] DSP#1
SD_IN[3]
GPIO_IN[0] DSP#2
MIDI2_IN
GPIO_IN[1] DSP#2
SD_IN[5]
GPIO_IN[2] DSP#2
SD_IN[6]
GPIO_IN[3] DSP#2
SD_IN[7]
Bi-processor
Operation
Each PDSP has access to the same memory space. Sample data, buffers and programs can therefore be shared between the two PDSPs, thus minimizing memory
requirements.
Each P16 has the possibility to test a read-only bit that identifies the PDSP number it
belongs to (PDSPID). This allows the firmware to make decisions according to the processor currently executing the code.
As an example, consider implementation of a 128-voice synthesizer. An easy way to
share traffic between the two PDSPs would be to have PDSP#1 process even MIDInumbered notes, while the PDSP#2 would process odd MIDI-numbered notes.
In this case, there would only be a single firmware processed by both P16s, with some
coding as follows:
If (PDSPID == 0 && noteeven) then ProcessNote();
If (PDSPID == 1 && noteodd) then ProcessNote();
The two PDSPs may also execute completely different firmware. In this case, as both
types of firmware start from address 100H, a test on PDSPID should be done at the
beginning of the program to jump to the correct firmware.
Reset and Powerdown
During power-up, the RESET input should be held low until the crystal oscillator and
PLL are stabilized. This may take about 20 ms. The RESET signal is normally derived
from the PC master reset. However, a typical RC/diode power-up network can also be
used for some applications.
After the low-to-high transition of RESET, the following occurs:
•
If REFRESH is sampled high at the low to high transition of RESET then the
external SDRAM init cycles are executed (see “Memory Type Configuration and
Boot Configuration” on page 26).
•
Both Synthesis/DSP enter an idle state.
•
If REFRESH is low, then both P16 program execution starts from address 0100H in
ROM space (WCS0 low).
•
If REFRESH is high, then both P16 program execution starts from address 0000H in
internal bootstrap ROM space. Each internal bootstrap expects to receive 256
words from its respective 16-bit burst transfer port, which will be stored from 0100H
25
1772D–DRMSD–01/04
to 01FFH into the external DRAM space. The bootstrap then resumes control at
address 0100H.
•
Memory Type
Configuration and
Boot Configuration
If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal
oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode.
To exit power down, PDWN has to be asserted high, then RESET applied.
At the end of power-up, when RESET input goes from low to high, RAS, CAS and
REFRESH pins are sampled by the ATSAM9708 to determine memory type configuration and boot type. RAS, CAS and REFRESH must be pulled to VCC or GND through an
external 10K resistor to select these different power-up configurations.
One memory type can be used for low pages (addresses [0-8000000h], AD[27] = 0) and
a different type for high pages (addresses [8000000h-10000000h]).
Memory types allowed are Flash/ROM, SRAM, DRAM or SDRAM.
When using RAM (SRAM, DRAM or SDRAM) in low page, P16 must start in bootstrap
state. When in bootstrap state, P16 program execution starts at address 0. If not in bootstrap, program execution starts at address 100h. Bootstrap is selected via the
REFRESH pin.
Table 18. Memory Type and Boot Configuration
Pin Level Detected at Reset
REFRESH
RAS
Low Page
High Page
CAS
Stand-alone Mode
Memory Type
Selected by
Memory Type
Selected by
Low
Low
Low
Flash/ROM
WCS0
SRAM
WCS1
Low
Low
High
Flash/ROM
WCS0
DRAM
RAS, CAS
Low
High
Low
Flash/ROM
WCS0
SDRAM
RAS, CAS
Low
High
High
Flash/ROM
WCS0
Selected by firmware
Bootstrap Mode
Note:
26
High
Low
Low
SRAM
WCS0
Flash/ROM
WCS1
High
Low
High
DRAM
RAS, CAS
Flash/ROM
WCS1
High
High
X
SDRAM
RAS, CAS
Flash/ROM
WCS1
1. When accessing DRAM or SDRAM, DRAM/SDRAM is selected by signals RAS and CAS (WCS0 and WCS1 are inactive)
and addresses are time-multiplexed on WA[..] pins as follows:
• WA0 - WA8: DRA0 - DRA8
• WA18: DRA9
• WA20: DRA10
• WA22: DRA11
When accessing SRAM, Flash or ROM, SRAM/Flash/ROM are selected by signals WCS0, WCS1 (RAS and CAS are inactive) and WA[26:0] address pins:
• if low pages: WCS0 = 0, WCS1 = 1
• if high pages: WCS0 = 1, WCS1 = 0
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Recommended Board
Layout
Like all HCMOS high-integration ICs, some rules of board layout should be followed for
reliable device operation:
GND, VCC, VC3
Distribution,
Decouplings
All GND, VCC, VC3 pins should be connected. GND and VCC planes are strongly recommended below the ATSAM9708. The board GND and VCC distribution should be in grid
form. If 3.3V is not available, then VC3 can be connected to VCC by two 1N4148 diodes in
series.
Recommended decoupling is 0.1 µF at each corner of the IC with an additional 10 µF
decoupling close to the crystal. VC3 requires a single 0.1µF decoupling close to the IC.
Crystal, LFT
The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the ATSAM9708 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM9708.
Buses
Parallel layout from PC_D[15:0] and DRA[11:0]/WD[15:0] should be avoided. The
PC_D[15:0] bus is an asynchronous high-transient current-type bus. Even on short distances, it can induce pulses on DRA[11:0]/WD[15:0] which can corrupt addresses
and/or data on these buses.
A ground plane should be implemented below the PC_D[15:0] bus, which connects both
to the PC-ISA connector and to the ATSAM9708 GND.
A ground plane should be implemented below the DRA[11:0]/WD[15:0] bus, which connects both to the DRAM SIMM grounds and to the ATSAM9708.
Analog Section
A specific AGND ground plane should be provided, which connects to the GND ground
by a single trace. No digital signals should cross the AGND plane. Refer to the Codec
vendor recommended layout for correct implementation of the analog section.
27
1772D–DRMSD–01/04
Recommended
Crystal
Compensation and
LFT Filter
Figure 20. Recommended Crystal Compensation and LFT Filter
134
61
X1
C4
22 pF
C1
22 pF
X1
62
X2
60
LFT
R1
137
100 Ω
C2
2.2 nF
RESET
PDWN
C3
10 nF
28
ATSAM9708
1772D–DRMSD–01/04
ATSAM9708
Mechanical Dimensions
Figure 21. 144-lead TQFP Package Drawing
Table 19. 144-lead TQFP Package Dimensions (in millimeters)
Min
Nom
Max
A
1.40
1.50
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
D
21.90
22.00
22.10
D1
19.90
20.00
20.10
E
21.90
22.00
22.10
E1
19.90
20.00
20.10
L
0.45
0.60
0.75
P
B
0.50
0.17
0.22
0.27
29
1772D–DRMSD–01/04
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