Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package 350 MHz–150 MHz 1.8 V VDD 1.8 V I/O cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register. Byte Write and Global Write Functional Description Applications The GS8160V18/32/36AT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS8160V18/32/36AT operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.00a 6/2003 -350 -333 -300 -250 -200 -150 Unit tKQ tCycle 1.8 2.85 2.0 3.0 2.2 3.3 2.3 4.0 2.7 5.0 3.3 6.7 ns ns Curr (x18) Curr (x32/x36) tKQ tCycle 395 455 370 430 335 390 280 330 230 270 185 210 mA mA 4.5 4.5 4.7 4.7 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 270 305 250 285 230 270 210 240 185 205 170 190 mA mA 1/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160V18A 100-Pin TQFP Pinout NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB6 VDD VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00a 6/2003 2/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160V32A 100-Pin TQFP Pinout NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00a 6/2003 3/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS8160V36A 100-Pin TQFP Pinout DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.00a 6/2003 4/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BW I Byte Write—Writes all enabled bytes; active low BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC — No Connect Rev: 1.00a 6/2003 5/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 GS8160V18/32/36A Block Diagram A0–An Register D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ 1 Power Down Control DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.00a 6/2003 6/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.00a 6/2003 7/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.00a 6/2003 8/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D ADSP ADSC Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00a 6/2003 9/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.00a 6/2003 10/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00a 6/2003 11/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 3.6 V VDDQ Voltage in VDDQ Pins –0.5 to 3.6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 3.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 3.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o –55 to 125 o TBIAS Temperature Under Bias C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.00a 6/2003 12/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 1.8 V Supply Voltage VDD1 1.6 1.8 2.0 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.6 1.8 2.0 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00a 6/2003 13/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.00a 6/2003 14/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 100 uA FTInput Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V — Output Low Voltage VOL IOL = 4 mA, VDD = 1.6 V — 0.4 V Rev: 1.00a 6/2003 15/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Rev: 1.00a 6/2003 — Device Deselected; All other inputs ≥ VIH or ≤ VIL Standby Current Flow Through IDD 70 90 IDD 40 ISB Pipeline Pipeline 250 20 IDD IDDQ Flow Through 40 360 35 IDD IDDQ Pipeline ISB 270 35 IDD IDDQ Flow Through Flow Through 400 55 0 to 70°C IDD IDDQ Symbol Pipeline Mode 75 95 50 50 260 20 370 35 280 35 410 55 –40 to 85°C -350 70 90 40 40 235 15 340 30 255 30 380 50 75 95 50 50 245 15 350 30 265 30 390 50 –40 to 85°C -333 0 to 70°C Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Deselect Current — ZZ ≥ VDD – 0.2 V Operating Current (x18) Device Selected; All other inputs ≥VIH or ≤ VIL Output open (x32/ x36) Test Conditions Parameter Operating Currents 60 85 40 40 215 15 310 25 240 30 345 45 0 to 70°C 65 90 50 50 225 15 320 25 250 30 355 45 –40 to 85°C -300 60 85 40 40 200 10 260 20 220 20 290 40 0 to 70°C 65 90 50 50 210 10 270 20 230 20 300 40 –40 to 85°C -250 50 75 40 40 175 10 215 15 190 15 240 30 0 to 70°C 55 80 50 50 185 10 225 15 200 15 250 30 –40 to 85°C -200 50 60 40 40 160 10 170 15 175 15 190 20 0 to 70°C 55 65 50 50 170 10 180 15 185 15 200 20 –40 to 85°C -150 mA mA mA mA mA mA mA mA Unit Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/24 © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time tKC -350 -333 -300 -250 -200 -150 Unit Min Max Min Max Min Max Min Max Min Max Min Max 2.85 — 3.0 — 3.3 — 4.0 — 5.0 — 6.7 — ns Clock to Output Valid tKQ — 1.8 — 2.0 — 2.2 — 2.3 — 2.7 — 3.3 ns Clock to Output Invalid tKQX 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns Clock to Output in Low-Z tLZ1 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns Setup time tS 1.0 — 1.0 — 1.0 — 1.2 — 1.4 — 1.5 — ns Hold time tH 0.1 — 0.1 — 0.1 — 0.2 — 0.4 — 0.5 — ns Clock Cycle Time tKC 4.5 — 4.7 — 5.0 — 5.5 — 6.5 — 7.5 — ns Clock to Output Valid tKQ — 4.5 — 4.7 — 5.0 — 5.5 — 6.5 — 7.5 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Setup time tS 1.3 — 1.4 — 1.4 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.3 — 0.4 — 0.4 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.0 — 1.0 — 1.3 — 1.3 — 1.3 — 1.5 — ns Clock LOW Time tKL 1.2 — 1.2 — 1.5 — 1.5 — 1.5 — 1.7 — ns Clock to Output in High-Z tHZ1 1.0 1.8 1.0 2.0 1.0 2.2 1.0 2.3 1.0 2.7 1.0 3.0 ns G to Output Valid tOE — 1.8 — 2.0 — 2.2 — 2.3 — 2.7 — 3.3 ns 1 G to output in Low-Z tOLZ 0 — 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 1.8 — 2.0 — 2.2 — 2.3 — 2.7 — 3.0 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00a 6/2003 17/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Rev: 1.00a 6/2003 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 18/24 DQa–DQd G E3 E2 E1 Ba–Bd BW GW A0–An ADV ADSC ADSP CK Begin Pipeline Mode Timing tS tS tS tS tS A tS tS tH tH tH tH Cont tS tOE Single Read Read A Write B tS B tH tH Single Write tKL tKH tKC Deselect C Q(A) tOHZ D(B) tS tH tLZ tKQ Q(C) Q(C+1) E1 masks ADSP Burst Read Q(C+2) Read C+1 Read C+2 Read C+3 Cont ADSC initiated read Read C E2 and E3 only sampled with ADSP and ADSC tH tH Cont Q(C+3) tKQX Deselected with E1 Deselect Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 © 2003, Giga Semiconductor, Inc. Rev: 1.00a 6/2003 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 19/24 DQa–DQd G E3 E2 E1 Ba–Bd BW GW A0–An ADV ADSC ADSP CK Begin tS tS tS A tS tS tOE tH tH tH tH Read A Flow Through Mode Timing tS tS tH tH tKH tKL tH tKC Cont1 tS tS B tS tH tH C Q(A) tS D(B) tOHZ tH tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Read C+1 Read C+2 Read C+3 Read C Fixed High Read C tHADSC initiated read Write B E2 and E3 only sampled with ADSC Cont Deselect Q(C) tHZ tKQX Deselected with E1 Cont2 Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ tKC ~ ~ tS tH tZZH ~ ~~ ~ CK ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ Sleep Mode Timing Diagram tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.00a 6/2003 20/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 TQFP Package Drawing L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle L1 c e D D1 Description Pin 1 Symbol θ b A1 A2 0.10 Y 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.00a 6/2003 21/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8160V18AT-350 Pipeline/Flow Through TQFP 350/4.5 C 1M x 18 GS8160V18AT-333 Pipeline/Flow Through TQFP 333/4.7 C 1M x 18 GS8160V18AT-300 Pipeline/Flow Through TQFP 300/5 C 1M x 18 GS8160V18AT-250 Pipeline/Flow Through TQFP 250/5.5 C 1M x 18 GS8160V18AT-200 Pipeline/Flow Through TQFP 200/6.5 C 1M x 18 GS8160V18AT-150 Pipeline/Flow Through TQFP 150/7.5 C 512K x 32 GS8160V32AT-350 Pipeline/Flow Through TQFP 350/4.5 C 512K x 32 GS8160V32AT-333 Pipeline/Flow Through TQFP 333/4.7 C 512K x 32 GS8160V32AT-300 Pipeline/Flow Through TQFP 300/5 C 512K x 32 GS8160V32AT-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 32 GS8160V32AT-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 32 GS8160V32AT-150 Pipeline/Flow Through TQFP 150/7.5 C 512K x 36 GS8160V36AT-350 Pipeline/Flow Through TQFP 350/4.5 C 512K x 36 GS8160V36AT-333 Pipeline/Flow Through TQFP 333/4.7 C 512K x 36 GS8160V36AT-300 Pipeline/Flow Through TQFP 300/5 C 512K x 36 GS8160V36AT-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 36 GS8160V36AT-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 36 GS8160V36AT-150 Pipeline/Flow Through TQFP 150/7.5 C 1M x 18 GS8160V18AT-350I Pipeline/Flow Through TQFP 350/4.5 I 1M x 18 GS8160V18AT-333I Pipeline/Flow Through TQFP 333/4.7 I 1M x 18 GS8160V18AT-300I Pipeline/Flow Through TQFP 300/5 I 1M x 18 GS8160V18AT-250I Pipeline/Flow Through TQFP 250/5.5 I 1M x 18 GS8160V18AT-200I Pipeline/Flow Through TQFP 200/6.5 I 1M x 18 GS8160V18AT-150I Pipeline/Flow Through TQFP 150/7.5 I 512K x 32 GS8160V32AT-350I Pipeline/Flow Through TQFP 350/4.5 I 512K x 32 GS8160V32AT-333I Pipeline/Flow Through TQFP 333/4.7 I 512K x 32 GS8160V32AT-300I Pipeline/Flow Through TQFP 300/5 I 512K x 32 GS8160V32AT-250I Pipeline/Flow Through TQFP 250/5.5 I 512K x 32 GS8160V32AT-200I Pipeline/Flow Through TQFP 200/6.5 I 512K x 32 GS8160V32AT-150I Pipeline/Flow Through TQFP 150/7.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160V18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 6/2003 22/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 36 GS8160V36AT-350I Pipeline/Flow Through TQFP 350/4.5 I 512K x 36 GS8160V36AT-333I Pipeline/Flow Through TQFP 333/4.7 I 512K x 36 GS8160V36AT-300I Pipeline/Flow Through TQFP 300/5 I 512K x 36 GS8160V36AT-250I Pipeline/Flow Through TQFP 250/5.5 I 512K x 36 GS8160V36AT-200I Pipeline/Flow Through TQFP 200/6.5 I 512K x 36 GS8160V36AT-150I Pipeline/Flow Through TQFP 150/7.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160V18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 6/2003 23/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc. Preliminary GS8160V18/32/36AT-350/333/300/250/200/150 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS8160VxxA_r1 Rev: 1.00a 6/2003 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet 24/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, Giga Semiconductor, Inc.