Cypress CY7C53150 Neuron chip network processor Datasheet

CY7C53150
CY7C53120
Neuron® Chip Network Processor
Features
Functional Description
• Three eight-bit pipelined processors for concurrent
processing of application code and network traffic
• 11-pin I/O port programmable in 34 modes for fast application program development
• Two 16-bit timer/counters for measuring and generating I/O device waveforms
• Five-pin communication port that supports direct
connect and network transceiver interfaces
• Programmable pull-ups on IO4–IO7 and 20-mA sink
current on IO0–IO3
• Unique 48-bit ID number in every device to facilitate
network installation and management
• Low operating current; sleep mode operation for
reduced current consumption[1]
• 0.35-µm Flash process technology
• 5.0V operation
• On-chip LVD circuit to prevent nonvolatile memory
corruption during voltage drops
• 2,048 bytes of SRAM for buffering network data,
system, and application data storage
• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),
4096 bytes (CY7C53120E4) of Flash memory with
on-chip charge pump for flexible storage of configuration data and application code
• Addresses up to 58 KB of external memory
(CY7C53150)
• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
• Maximum input clock operation of 20 MHz
(CY7C53150), 10 MHz (CY7C53120E2), 40 MHz
(CY7C53120E4) over a –40°C to 85°C[2] temperature
range
• 64-pin TQFP package (CY7C53150)
• 32-pin SOIC or 44-pin TQFP package (CY7C53120)
The CY7C531x0 Neuron chip implements a node for
LonWorks distributed intelligent control networks. It incorporates, on a single chip, the necessary communication and
control functions, both in hardware and firmware, that facilitate
the design of a LonWorks node.
The CY7C531x0 contains a very flexible five-pin communication port that can be configured to interface with a wide
variety of media transceivers at a wide range of data rates. The
most common transceiver types are twisted-pair, powerline,
RF, IR, fiber-optics, and coaxial.
The CY7C531x0 is manufactured using state-of-the-art
0.35-µm Flash technology, providing to designers the most
cost-effective Neuron chip solution.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in 10-KB ROM (CY7C53120E2), 12-KB ROM
(CY7C53120E4), or off-chip memory (CY7C53150). The
firmware also contains 34 preprogrammed I/O drivers, greatly
simplifying application programming. The application program
is stored in the Flash memory (CY7C53120) and/or off-chip
memory (CY7C53150), and may be updated by downloading
over the network.
The CY7C53150 incorporates an external memory interface
that can address up to 64 KB with 6 KB of the address space
mapped internally. LonWorks nodes that require large application programs can take advantage of this external memory
capability.
The CY7C53150 Neuron chip is an exact replacement for the
Motorola MC143150Bx and Toshiba TMPN3150B1 devices.
The CY7C53120E2 Neuron chip is an exact replacement for
the Motorola MC143120E2 device since it contains the same
firmware in ROM.
Logic Block Diagram
Media Access
Control Processor
Network
Processor
Internal
Data Bus
(0:7)
Application
Processor
CP4
CP0
I/O Block
IO10
IO0
2 Timer/
Counters
Internal
Address Bus
(0:15)
2 KB RAM
Communications
Port
Oscillator,
Clock, and
Control
Flash
CLK1
CLK2
SERVICE
RESET
External
Address/Data Bus
(CY7C53150)
ROM
(CY7C53120)
Notes:
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details please refer to Cypress’s
Neuron Metastability Description application note.
2. Maximum Junction Temperature is 105°C. TJunction = TAmbient + V•I•θJA. 32-pin SOIC θJA = 51C/W. 44-pin TQFP θJA = 43C/W. 64-pin TQFP θJA = 44C/W.
Cypress Semiconductor Corporation
Document #: 38-10001 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 24, 2003
CY7C53150
CY7C53120
.
Pin Configurations
Pin 1
Indicator [3]
D2
D3
D4
D5
D6
VDD
VSS
D0
D1
VDD
D7
CP4
CP3
CP2
CP1
CP0
NC[4]
VDD
VSS
CLK1
CLK2
VDD
VSS
VDD
VSS
NC[4]
SERVICE
IO10
A1
A0
Vss
Vpp
IO4
IO5
IO6
IO7
IO8
IO9
A4
A3
A2
IO2
IO3
RESET
VDD
A8
A7
A6
A5
IO0
IO1
A13
A12
A11
A10
A9
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
31
50
30
51
29
52
28
53
27
54
26
55
25
56
24
57
CY7C53150-20AI
23
58
22
59
21
60
20
61
19
62
18
63
17
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NC[4]
NC[4]
A14
A15
E
R/W
VDD
NC[4]
CY7C53150
64-lead Thin Quad Flat Pack
Notes:
3. The smaller dimple at the bottom left of the marking indicates pin 1.
4. No Connect (NC) — Should not be used. (These pins may be used for internal testing.)
Document #: 38-10001 Rev. *D
Page 2 of 12
CY7C53150
CY7C53120
Pin Configurations (continued)
IO8
IO9
VDD
NC[4]
IO10
VSS
CP4
31
30
29
28
27
26
25
NC[4]
IO7
32
CP3
NC[4]
33
44-lead QFP
23
34
22
NC[4]
IO6
35
21
CP1
IO5
36
20
CP0
VSS
37
19
VDD
VDD
38
18
CP2
NC[4]
39
17
NC[4]
RESET
40
16
VSS
VDD
41
15
CLK1
IO4
42
14
CLK2
IO3
43
13
VSS
[4 ]
44
12
NC[4]
6
7
8
9
10
NC[4]
VSS
Vpp
VDD
VDD
11
5
SERVICE
NC
4
IO0
[4 ]
3
CY7C53120Ex-yyAI
2
NC
PIN 1
INDICATOR
Document #: 38-10001 Rev. *D
24
NC[4]
IO1
VDD
VSS
IO5
IO6
IO7
IO8
IO9
VDD
IO10
VSS
CP4
CP3
CP1
CP0
VDD
CP2
IO2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC[4]
RESET
VDD
IO4
IO3
IO2
IO1
IO0
SERVICE
VSS
Vpp
VDD
VDD
VSS
CLK2
CLK1
VSS
CY7C53120Ex-yySI
32-lead SOIC
Page 3 of 12
CY7C53150
CY7C53120
Pin Descriptions
Pin Name
CY7C53150
CY7C53120xx
CY7C53120xx
TQFP-64 Pin No. SOIC-32 Pin No. TQFP-44 Pin No.
I/O
Pin Function
CLK1
Input
Oscillator connection or external clock
input.
24
15
15
CLK2
Output
Oscillator connection. Leave open when
external clock is input to CLK1. Maximum
of one external load.
23
14
14
I/O (Built-In
Pull-up)
Reset pin (active LOW). Note. The
allowable external capacitance connected
to the RESET pin is 100 –1000 pF.
6
1
40
SERVICE
I/O (Built-In
Configurable
Pull-up)
Service pin (active LOW). Alternates
between input and output at a 76-Hz rate.
17
8
5
IO0–IO3
I/O
Large current-sink capacity (20 mA).
General I/O port. The output of timer/
counter 1 may be routed to IO0. The output
of timer/counter 2 may be routed to IO1.
2, 3, 4, 5
7, 6, 5, 4
4, 3, 2, 43
IO4–IO7
I/O (Built-In
Configurable
Pull-ups)
General I/O port. The input to
timer/counter 1 may be derived from one of
IO4–IO7. The input to timer/counter 2 may
be derived from IO4.
10, 11, 12, 13
3, 30, 29, 28
42, 36, 35, 32
IO8–IO10
I/O
General I/O port. May be used for serial
communication under firmware control.
14, 15, 16
27, 26, 24
31, 30, 27
D0–D7
I/O
Bidirectional memory data bus.
43, 42, 38, 37,
36, 35, 34, 33
N/A
N/A
RESET
R/W
Output
Read/write control output for external
memory.
45
N/A
N/A
E
Output
Enable clock control output for external
memory.
46
N/A
N/A
A0–A15
Output
Memory address output port.
64, 63, 62, 61, 60,
59, 58, 57, 56, 55,
54, 53, 52, 51, 50,
47
N/A
N/A
VDD
Input
Power input (5V nom). All VDD pins must
be connected together externally.
7, 20, 22, 26,
40, 41, 44
2, 11, 12,
18, 25, 32
9, 10, 19,
29, 38, 41
VSS
Input
Power input (0V, GND). All VSS pins must
be connected together externally.
8,19, 21, 25, 39
9, 13, 16, 23, 31
7,13, 16, 26, 37
Vpp
Input
In-circuit test mode control. If Vpp is high
when RESET is asserted, the I/O, address
and data buses become Hi-Z.
9
10
8
CP0–CP4 Communication Bidirectional port supporting communi- 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24, 25
Network
cations in three modes.
Interface
NC
—
No connect. Must not be connected on the 1, 18, 27, 48, 49
user’s PC board, since they may be
connected internal to the chip.
N/A
1, 6, 11, 12, 17,
22, 23, 28, 33, 34,
39, 44
Memory Usage
All Neuron chips require system firmware to be present when
they are powered up. In the case of the CY7C53120 family,
this firmware is preprogrammed in the factory in an on-chip
ROM. In the case of the CY7C53150, the system firmware
must be present in the first 16 KB of an off-chip nonvolatile
memory such as Flash, EPROM, EEPROM, or NVRAM.
These devices must be programmed in a device programmer
Document #: 38-10001 Rev. *D
before board assembly. Because the system firmware implements the network protocol, it cannot itself be downloaded
over the network.
For the CY7C53120 family, the user application program is
stored in on-chip Flash memory. It may be programmed using
a device programmer before board assembly, or may be
Page 4 of 12
CY7C53150
CY7C53120
downloaded and updated over the LonTalk network from an
external network management tool.
transceiver is responsible for encoding and decoding the data
stream.
For the CY7C53150, the user application program is stored in
on-chip Flash Memory and also in off-chip memory. The user
program may initially be programmed into the off-chip memory
device using a device programmer.
In Differential Mode, pins CP0 and CP1 form a differential
receiver with built-in programmable hysteresis and low-pass
filtering. Pins CP2 and CP3 form a differential driver. Serial
data is communicated using Differential Manchester encoding.
The following tables describe the communications port when
used in Differential Mode.
Flash Memory Retention and Endurance
CP0 – CP1 ≥
Data and code stored in Flash Memory is guaranteed to be
retained for at least 10 years for programming temperature
range of –25°C to 85°C.
The Flash Memory can typically be written 100,000 times
without any data loss.[5] An erase/write cycle takes 20 ms. The
system firmware extends the effective endurance of Flash
memory in two ways. If the data being written to a byte of Flash
memory is the same as the data already present in that byte,
the firmware does not perform the physical write. So for
example, an application that sets its own address in Flash
memory after every reset will not use up any write cycles if the
address has not changed. In addition, system firmware
version 13.1 or higher is able to aggregate writes to eight
successive address locations into a single write for
CY7C53120E4 devices. For example, if 4 KB of code is
downloaded over the network, the firmware would execute
only 512 writes rather than 4,096.
Vhys + 200 mV
CP0
VDD/2
CP1
Figure 1. Receiver Input Waveform
Programmable Hysteresis Values
(Expressed as differential peak-to-peak voltages in terms of VDD)
Hysteresis[6]
Vhys Min.
Vhys Typ.
Vhys Max.
0
0.019 VDD
0.027 VDD
0.035 VDD
1
0.040 VDD
0.054 VDD
0.068 VDD
2
0.061 VDD
0.081 VDD
0.101 VDD
3
0.081 VDD
0.108 VDD
0.135 VDD
4
0.101 VDD
0.135 VDD
0.169 VDD
5
0.121 VDD
0.162 VDD
0.203 VDD
6
0.142 VDD
0.189 VDD
0.236 VDD
7
0.162 VDD
0.216 VDD
0.270 VDD
40-MHz 3120 Operation
The CY7C53120E4-40 device was designed to run at
frequencies up to 40 MHz using an external clock oscillator. It
is important to note that external oscillators may typically take
on the order of 5 ms to stabilize after power-up. The Neuron
chip should be held in reset until the CLK1 input is stable. With
some oscillators, this may require the use of a reset-stretching
Low-Voltage Detection chip/circuit. Check the oscillator
vendor’s specification for more information about start-up
stabilization times.
Low-Voltage Inhibit Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip
whenever the VDD input is less than 4.1 ± 0.3V. This feature
prevents the corruption of nonvolatile memory during voltage
drops.
Communications Port
Values[7]
Programmable Glitch Filter
(Receiver (end-to-end) filter values expressed as transient
pulse suppression times)
Filter (F)
Min.
Typ.
Max.
Unit
0
10
75
140
ns
1
120
410
700
ns
2
240
800
1350
ns
3
480
1500
2600
ns
Receiver[8] (End-to-End) Absolute Asymmetry
(Worst case across hysteresis)
Filter (F)
Max ( tPLH – tPHL)
Unit
0
35
ns
1
150
ns
2
250
ns
3
400
ns
The Neuron chip includes a versatile 5-pin communications
port that can be configured in three different ways. In
Single-Ended Mode, pin CP0 is used for receiving serial data,
pin CP1 for transmitting serial data, and pin CP2 enables an
external transceiver. Data is communicated using Differential
Manchester encoding.
In Special Purpose Mode, pin CP0 is used for receiving serial
data, pin CP1 for transmitting serial data, pin CP2 transmits a
bit clock, and pin CP4 transmits a frame clock for use by an
external intelligent transceiver. In this mode, the external
≤ 3 ns
Differential Receiver (End-to-End) Absolute Symmetry[9, 10]
Filter (F)
Hysteresis (H)
0
0
Max ( tPLH – tPHL) Unit
24
ns
Notes:
5. For detailed information about data retention after 100K cycles, please see Cypress qualification report.
6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.
7. Must be disabled if data rate is 1.25 Mbps or greater.
8. Receiver input, VD = VCP0 – VCP1, at least 200 mV greater than hysteresis levels. See Figure 1.
9. CP0 and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in Figure 8. VDD = 5.00 V ± 5%.
10. tPLH: Time from input switching states from low to high to output switching states. tPHL: Time from input switching states from high to low to output switching states.
Document #: 38-10001 Rev. *D
Page 5 of 12
CY7C53150
CY7C53120
Electrical Characteristics (VDD = 4.5V–5.5V)
Min.
Typ.
Max.
VIL
Parameter
Input Low Voltage
IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET
CP0, CP1 (Differential)
Description
—
—
—
—
0.8
Programmable
VIH
Input High Voltage
IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7,RESET
CP0, CP1 (Differential)
2.0
Programmable
—
—
—
—
VOL
Low-Level Output Voltage
Iout < 20 µA
Standard Outputs (IOL = 1.4 mA)[11]
High Sink (IO0–IO3), SERVICE, RESET (IOL = 20 mA)
High Sink (IO0–IO3), SERVICE, RESET (IOL = 10 mA)
Maximum Sink (CP2, CP3) (IOL = 40 mA)
Maximum Sink (CP2, CP3) (IOL = 15 mA)
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.4
0.8
0.4
1.0
0.4
VOH
High-Level Output Voltage
Iout < 20 µA
Standard Outputs (IOH = –1.4 mA)[11]
High Sink (IO0 – IO3), SERVICE (IOH = –1.4 mA)
Maximum Source (CP2, CP3) (IOH = –40 mA)
Maximum Source (CP2, CP3) (IOH = –15 mA)
VDD – 0.1
VDD – 0.4
VDD – 0.4
VDD – 1.0
VDD – 0.4
—
—
—
—
—
—
—
—
—
—
Vhys
Hysteresis (Excluding CLK1)
175
—
—
mV
)[12]
Iin
Input Current (Excluding Pull-Ups) (VSS to VDD
Ipu
Pull-Up Source Current (Vout = 0 V, Output = High-Z)[12]
Current[13]40-MHz
IDD
Operating Mode Supply
20-MHz Clock
10-MHz Clock
5-MHz Clock
2.5-MHz Clock
1.25-MHz Clock
0.625-MHz Clock[14]
IDDsleep
Sleep Mode Supply Current[1, 13]
Clock[14]
Unit
V
V
V
V
—
—
±10
µA
60
—
260
µA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55
32
20
12
8
7
3
mA
—
—
100
µA
LVI Trip Point (VDD)
Part Number
CY7C53120E2, CY7C53120E4, and CY7C53150
Min.
Typ.
Max.
Unit
3.8
4.1
4.4
V
Notes:
11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150, standard
outputs also include A0–A15, D0–D7, E, and R/W.
12. IO4–IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up.
13. Supply current measurement conditions: VDD = 5V, all outputs under no-load conditions, all inputs < 0.2V or > (VDD – 0.2V), configurable pull-ups off, crystal
oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 µA typical and 600 µA maximum when enabled. It is
enabled on either of the following conditions:
• Neuron chip in Operating mode and Comm Port in Differential mode.
• Neuron chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake-up not masked.
14. Supported through an external oscillator only.
Document #: 38-10001 Rev. *D
Page 6 of 12
CY7C53150
CY7C53120
External Memory Interface Timing — CY7C53150, VDD ± 10% (VDD = 4.5V to 5.5 V, TA = –40°C to+ 85°C [2])
Parameter
tcyc
PWEH
PWEL
Description
Min.
Max.
Unit
100
3200
ns
tcyc/2 – 5
tcyc/2 + 5
ns
tcyc/2 – 5
tcyc/2 + 5
ns
Memory Cycle Time (System Clock Period)[15]
Pulse Width, E High
Pulse Width, E
[16]
Low[16]
Valid[20]
tAD
Delay, E High to Address
tAH
Address Hold Time After E High[20]
—
35
ns
10
—
ns
—
25
ns
Read[20]
tRD
Delay, E High to R/W Valid
tRH
R/W Hold Time Read After E High
5
—
ns
tWR
Delay, E High to R/W Valid Write
—
25
ns
tWH
R/W Hold Time Write After E High
5
—
ns
tDSR
Read Data Setup Time to E High
15
—
ns
tDHR
Data Hold Time Read After E High
0
—
ns
10
—
ns
—
12
ns
0
—
ns
—
42
ns
50
—
ns
tDHW
Data Hold Time Write After E
tDDW
Delay, E Low to Data Valid
tDHZ
High[17, 18]
Data Three State Hold Time After E
Low[19]
Three-State[18]
tDDZ
Delay, E High to Data
tacc
External Memory Access Time (tacc = tcyc – tAD – tDSR) at
20-MHz input clock
Differential Transceiver Electrical Characteristics
Min.
Max.
Unit
Receiver Common Mode Voltage Range to maintain hysteresis[21]
Characteristic
1.2
VDD – 2.2
V
Receiver Common Mode Range to operate with unspecified hysteresis
0.9
VDD – 1.75
V
–0.05Vhys – 35
0.05Vhys + 35
mV
Propagation Delay (F = 0, VID = Vhys/2 + 200 mV)
—
230 ns
ns
Input Resistance
5
—
MΩ
—
10
µs
35
Ω
Input Offset Voltage
Wake-up Time
Differential Output Impedance for CP2 and
CP3[22]
TEST SIGNAL
CL = 20 pF for E
CL = 30 pF for A0–A15, D0–D7, and R/W
CL
CL = 50 pF for all other signals
Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified
PWEH
PWEL
2.0V
0.8V
2.0V
Figure 3. Test Point Levels for E Pulse Width Measurements
Notes:
15. tcyc = 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz).
16. Refer to Figure 3 for detailed measurement information.
17. The data hold parameter, tDHW, is measured to the disable levels shown in Figure 5, rather than to the traditional data invalid levels.
18. Refer to Figure 6 and Figure 5 for detailed measurement information.
19. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information.
20. To meet the timing above for 20-MHz operation, the loading on A0–A15, D0–D7, and R/W is 30 pF. Loading on E is 20 pF.
21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs.
22. Z0 = |V[CP2]-V[CP3] |/40mA for 4.75 < VDD < 5.25V.
Document #: 38-10001 Rev. *D
Page 7 of 12
CY7C53150
CY7C53120
DRIVE TO 2.4V
2.0V
0.8V
DRIVE TO 0.4V
A
B
2.0V
0.8V
A — Signal valid-to-signal valid specification (maximum or minimum)
B — Signal valid-to-signal invalid specification (maximum or minimum)
Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified
VOH – 0.5 V
VOL + 0.5 V
VOH – Measured high output drive level
VOL – Measured low output drive level
Figure 5. Test Point Levels for Driven-to-Three-State Time Measurements
VDD/2
TEST SIGNAL
ILOAD = 1.4 mA
CL = 30 pF
Figure 6. Signal Loading for Driven-to-Three-State Time Measurements
tcyc
E
20 pF Load
Address
(A0 – A15)
30 pF Load
PWEH
PWEL
tAD
tAD
tAD
Address
tAD
Address
tAH
Address
Address
tAH
tAH
tAH
tWR
tRD
R/W
30 pF Load
tRH
tDSR
tDSR
Data (In)
(D0 – D7)
tWH
Data In
Data In
tDHR
Data (Out)
(D0 – D7)
30 pF Load
tDHR
tDDZ
tDDW
tDHZ
tDDW
tDHW
tDHW
Data Out
Memory READ
Memory READ
Memory WRITE
tDDZ
tDHZ
Data Out
Memory WRITE
Figure 7. External Memory Interface Timing Diagram
Document #: 38-10001 Rev. *D
Page 8 of 12
CY7C53150
CY7C53120
5
4
V (C P 0 )
3
V cm
V (C P 1 )
2
V (C P 0 )-V (C P 1 )
1
T im e
V trip +
Vh
V trip -1
5V
N e u ro n C h ip ’s
In te rn a l
C o m p a ra to r
0V
C o m m o n -M o d e v o lta g e : V c m = ( V (C P 0 ) + V (C P 1 ) ) / 2
H y s te re s is V o lta g e : V h = [V trip + ] - [V trip -]
Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms
Ordering Information[23]
Flash
(KB)
ROM
(KB)
Firmware
Version
Max. Input
Clock
(MHz)
Package
Name
Package Type
0.5
0
N/A
20[25]
A65
64-lead Thin Plastic Quad Flat Pack
CY7C53120E2-10SI[24]
2
10
6
10
S34
32-lead (450 mil) Molded SOIC
CY7C53120E4-40SI[26]
4
12
12
40
S34
32-lead (450 mil) Molded SOIC
CY7C53120E2-10AI[24]
2
10
6
10
A44
44-lead Thin Plastic Quad Flat Pack
CY7C53120E4-40AI[26]
4
12
12
40
A44
44-lead Thin Plastic Quad Flat Pack
Part Number
CY7C53150-20AI
Notes:
23. All parts contain 2KB of SRAM.
24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware.
25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later.
26. CY7C53120E4 requires upgraded LonBuilder and NodeBuilder software.
Document #: 38-10001 Rev. *D
Page 9 of 12
CY7C53150
CY7C53120
Package Diagrams
44-lead Thin Plastic Quad Flat Pack A44
51-85064-B
64-lead Thin Plastic Quad Flat Pack (14 × 14 × 1.4 mm) A65
51-85046-B
Document #: 38-10001 Rev. *D
Page 10 of 12
CY7C53150
CY7C53120
Package Diagrams (continued)
32-lead (450-mil) Molded SOIC S34
51-85081-A
Echelon, LonWorks, LonTalk, and Neuron are registered trademarks of Echelon Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-10001 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C53150
CY7C53120
Document History Page
Document Title: CY7C53150/CY7C53120 Neuron® Chip Network Processor
Document Number: 38-10001
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
111472
11/28/01
DSG
Change from Spec number: 38-00891 to 38-10001
*A
111990
02/06/02
CFB
Changed the max. cur rent values
Specified the Flash endurance of “100K typical” with reference to qual report
Fixed some incorrect footnotes and figure numbering
*B
114465
04/24/02
KBO
Added Sleep Metastability footnote
Added Junction Temperature footnote
Added maximum sleep current footnote
Changed “EEPROM” references to “Flash Memory”
*C
115269
04/26/02
KBO
Repositioned Note 3
*D
124450
03/25/03
KBO
Removed Note 2 regarding data retention
Removed Note 16 regarding max sleep current
Changed the system image firmware version from V12 to V13.1
Document #: 38-10001 Rev. *D
Page 12 of 12