Cypress CY62187EV30LL-55BAXI 64-mbit (4 m ã 16) static ram Datasheet

CY62187EV30 MoBL®
64-Mbit (4 M × 16) Static RAM
shy64-Mbit (4 M × 16) Static RAM
Features
Functional Description
■
Very high speed
❐ 55 ns
■
Wide voltage range
❐ 2.2 V to 3.7 V
■
Ultra low standby power
❐ Typical standby current: 8 A
❐ Maximum standby current: 48 A
■
Ultra low active power
❐ Typical active current: 7.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
The CY62187EV30 is a high performance CMOS static RAM
organized as 4 M words by 16-bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The
input and output pins (I/O0 through I/O15) are placed in a high
impedance state when: deselected (CE1HIGH or CE2 LOW),
outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH and WE LOW).
■
CMOS for optimum speed and power
■
Available in Pb-free 48-ball FBGA package
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A21). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A21).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
9 for a complete description of read and write modes.
Cypress Semiconductor Corporation
Document Number: 001-48998 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 18, 2012
CY62187EV30 MoBL®
Logic Block Diagram
4096K × 16
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA-IN DRIVERS
I/O0–I/O7
I/O8–I/O15
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
COLUMN DECODER
BHE
WE
OE
CE2
CE1
BLE
Power down
Circuit
Document Number: 001-48998 Rev. *G
Page 2 of 15
CY62187EV30 MoBL®
Contents
Pin Configuration ............................................................. 4
Product Portfolio .............................................................. 4
Maximum Ratings............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 6
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-48998 Rev. *G
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 3 of 15
CY62187EV30 MoBL®
Pin Configuration
Figure 1. 48-ball FBGA
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12
A21
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
A20
H
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62187EV30LL
Min
Typ[1]
Max
2.2
3.0
3.7
55
Standby ISB2 (A)
f = fMax
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
7.5
9
45
55
8
48
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-48998 Rev. *G
Page 4 of 15
CY62187EV30 MoBL®
DC Input Voltage [2, 3] .................. –0.3 V to VCC (max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Operating Range
Supply Voltage to Ground
Potential........................................ –0.3 V to VCC(max) + 0.3 V
Device
DC Voltage Applied to Outputs
in High Z State [2, 3] ....................... –0.3 V to VCC(max) + 0.3 V
CY62187EV30LL
Range
Ambient
Temperature
VCC[4]
Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH
Output HIGH voltage
VOL
Output LOW voltage
VIH
Input HIGH voltage
VIL
Input LOW voltage
Test Conditions
55 ns
Min
Typ[5]
Max
–
Unit
2.2 V < VCC < 2.7 V
IOH = –0.1 mA
2.0
–
2.7 V < VCC < 3.7 V
IOH = –1.0 mA
2.4
–
–
V
2.2 V < VCC < 2.7 V
IOL = 0.1 mA
–
–
0.4
V
2.7 V < VCC < 3.7 V
IOL = 2.1 mA
2.2 V < VCC < 2.7 V
V
–
–
0.4
V
1.8
–
VCC + 0.3 V
V
2.7 V < VCC < 3.7 V
2.2
–
VCC + 0.3 V
V
2.2 V< VCC < 2.7 V
–0.3
–
0.6
V
–0.3
–
0.8[6]
V
–1
–
+1
A
2.7 V < VCC < 3.7 V
IIX
Input leakage current
GND < VI < VCC
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fMax = 1/tRC
–
45
55
mA
–
7.5
9
mA
Automatic CE
power down
current—CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0,
VCC = 3.7 V
–
8
48
A
ISB2 [7]
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
Capacitance
Parameter[8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
25
pF
35
pF
Notes
2. VIL(min) = –2.0V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
4. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions input LOW Voltage applied to the device must not be higher than 0.7 V.
7. Chip enables (CE1 and CE2) and Byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-48998 Rev. *G
Page 5 of 15
CY62187EV30 MoBL®
Thermal Resistance
Parameter[9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
2-layer printed circuit board
FBGA
59.06
Unit
C/W
14.08
C/W
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
90%
90%
10%
VCC
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Table 1. AC Test Loads
Parameter
R1
R2
RTH
VTH
2.5 V
16667
15385
8000
1.20
3.3 V
1103
1554
645
1.75
Unit



V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR [11]
Data retention current
Conditions
VCC = 1.5 V, CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or
VIN < 0.2 V
Min
1.5
–
Typ[10]
–
–
Max
–
48
Unit
V
A
tCDR[9]
Chip deselect to data
retention time
0
–
–
ns
tR[12]
Operation recovery time
55
–
–
ns
Figure 3. Data Retention Waveform [13]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enables (CE1 and CE2) and Byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
13. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-48998 Rev. *G
Page 6 of 15
CY62187EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[14]
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
6
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
Z[15]
5
–
ns
–
20
ns
10
–
ns
–
20
ns
0
–
ns
tLZOE
OE LOW to LOW
tHZOE
OE HIGH to high Z[15, 16]
tLZCE
CE1 LOW and CE2 HIGH to low Z[15]
Z[15, 16]
tHZCE
CE1 HIGH and CE2 LOW to high
tPU
CE1 LOW and CE2 HIGH to power up
tPD
CE1 HIGH and CE2 LOW to power down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
tLZBE
BLE/BHE LOW to low Z [15]
10
–
ns
–
20
ns
55
–
ns
tHZBE
BLE/BHE HIGH to high Z
[15, 16]
Write Cycle[17]
tWC
Write cycle time
tSCE
CE1 LOW and CE2 HIGH to write end
45
–
ns
tAW
Address setup to write end
45
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
45
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
20
ns
10
–
ns
Z[15, 16]
tHZWE
WE LOW to high
tLZWE
WE HIGH to low Z[15]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VTH, input pulse levels of 0 to
VCC(typ), and output loading of the specified IOL/IOH as shown in Table 1 on page 6.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
17. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
Document Number: 001-48998 Rev. *G
Page 7 of 15
CY62187EV30 MoBL®
Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled)[18, 19]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 5. Read Cycle 2 (OE Controlled)[19, 20]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
tDOE
DATA I/O
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA OUT VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes
18. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-48998 Rev. *G
Page 8 of 15
CY62187EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle 1 (WE Controlled) [21, 22, 23, 24]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 24
tHZOE
Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [21, 22, 23, 24]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 24
tHZOE
Notes
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. Data I/O is high impedance if OE = VIH.
23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
24. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-48998 Rev. *G
Page 9 of 15
CY62187EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 3 (WE Controlled, OE LOW)[25, 26]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 26
tHD
DATA IN VALID
tLZWE
tHZWE
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[25,26]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 26
tHD
DATA IN VALID
Notes
25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-48998 Rev. *G
Page 10 of 15
CY62187EV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
[27]
X
[27]
Mode
Power
X
High Z
Deselect/Power Down
Standby (ISB)
X
X[27]
X[27]
High Z
Deselect/Power Down
Standby (ISB)
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
[27]
X
X
L
X
[27]
L
H
X
X[27]
[27]
X
X
Inputs Outputs
Note
27. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-48998 Rev. *G
Page 11 of 15
CY62187EV30 MoBL®
Ordering Information
Speed
(ns)
55
Ordering Code
CY62187EV30LL-55BAXI
Package
Diagram
Package Type
001-50044 48-ball fine pitch ball grid array (8 × 9.5 × 1.4 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY 621 8
7
E V30 LL - 55 BA X
I
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
BA = 48-ball FBGA
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 64-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-48998 Rev. *G
Page 12 of 15
CY62187EV30 MoBL®
Package Diagram
Figure 10. 48-ball FBGA (8 × 9.5 × 1.4 mm)
001-50044 *D
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
CMOS
complementary metal oxide semiconductor
CE
chip enable
I/O
input/output
mA
milliampere
OE
output enable
ms
millisecond
SRAM
static random access memory
ns
nanosecond
FBGA
fine-pitch ball grid array

ohms
WE
write enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-48998 Rev. *G
Symbol
Unit of Measure
°C
degree Celsius
MHz
mega hertz
µA
microampere
Page 13 of 15
CY62187EV30 MoBL®
Document History Page
Document Title: CY62187EV30 MoBL® 64-Mbit (4 M × 16) Static RAM
Document Number: 001-48998
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2595932
VKN/PYRS
10/24/08
New Datasheet
*A
2644442
VKN/PYRS
01/23/09
Updated the Package diagram on page 10
*B
2672650
VKN/PYRS
03/12/09
Extended the VCC range to 3.7V
Added 55 ns speed bin and it’s related information
Changed ICC (typ) from 2.5 mA to 3.5 mA at f = 1 MHz
Changed ICC (max) from 4 mA to 6 mA at f = 1 MHz
For 70 ns speed, changed ICC (typ) form 33 mA to 28 mA at f = fMAX
For 70 ns speed, changed ICC (max) from 40 mA to 45 mA at f = fMAX
For 70 ns speed, changed tPWE from 45 to 50 ns, tSD from 30 to 35 ns
Modified footnote #6
Changed 48-Ball FBGA package dimensions from 8 x 9.5 x 1.6 mm to
8 x 9.5 x 1.4 mm and updated package diagram on page 10
*C
2737164
VKN/AESA
07/13/09
Converted from preliminary to final
Changed ICC(typ) from 3.5 mA to 4 mA at f = 1 MHz
Changed ICC(typ) from 35 mA to 45 mA and from 28 mA to 35 mA for the speeds
50 ns and 70 ns respectively at f = fmax
Included VCC range in the test condition of the “Electrical Characteristics” table
for the specs VOH, VOL, VIH, VIL
Changed VIL(max) from 0.8V to 0.7V for VCC = 2.7V to 3.7V
Changed CIN spec from 20 pF to 25 pF and COUT spec from 20 pF to 35 pF
Included thermal specs for 48-FBGA
Included VCC range for VTH spec in the AC test load table
Changed tLZBE spec from 5 ns to 10 ns
Added footnote #20 related to chip enable
*D
2765892
VKN
09/18/09
Removed 70 ns speed
For 55 ns speed, at f = 1 MHz, changed ICC (max) spec from 6 mA to 9 mA
Changed ICC(typ) from 4 mA to 7.5 mA at f = 1 MHz
*E
3177000
AJU
02/18/2011
Updated Features (Corrected ICC(typ) from 4 mA to 7.5 mA).
Updated Pin Configuration (Renamed Figure 1 as “48-ball FBGA”).
Updated Product Portfolio (Corrected ICC(typ) from 4 mA to 7.5 mA).
Updated Electrical Characteristics (Included BHE and BLE in ISB2 test
conditions to reflect Byte power down feature).
Updated Table 1 on page 6 (AC Test Loads).
Updated Data Retention Characteristics (Included BHE and BLE in ICCDR test
conditions to reflect Byte power down feature, corrected tR(min) from tRC to
55 ns).
Added Ordering Code Definitions.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Changed all instances of IO to I/O.
Updated in new template.
*F
3282088
RAME
06/14/2011
Updated template as per current Cypress standards.
Removed reference to AN1064 SRAM system guidelines.
Changed the VIL parameter max value to 0.8 V for test condition 2.7 V < VCC
< 3.7 V and referenced to footnote # 6.
*G
3785005
TAVA
10/18/2012
Minor Text Modifications. Updated Package Diagram (from Rev *C to *D).
Document Number: 001-48998 Rev. *G
Page 14 of 15
CY62187EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-48998 Rev. *G
Revised October 18, 2012
Page 15 of 15
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.